CEP830G

N-Channel Enhancement Mode Field Effect Transistor FEATURES Type CEP830G CEB830G CEF830G VDSS 500V 500V 500V RDS(ON) 1.5Ω 1.5Ω 1.5Ω ID 5A 5A 5A e @VGS 10V 10V 10V CEP830G/CEB830G CEF830G PRELIMINARY Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. D D G S CEB SERIES TO-263(DD-PAK) G G D S G CEP SERIES TO-220 D S CEF SERIES TO-220F S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Limit Symbol TO-220/263 VDS VGS ID IDM PD TJ,Tstg f TO-220F Units V V 500 ±30 5 20 83 0.66 -55 to 150 5 e e A A W W/ C C 20 42 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range 0.33 Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA 1.5 62.5 Limit 3.6 65 Units C/W C/W This is preliminary information on a new product in development now . Details are subject to change without notice . 1 Rev 1. 2009.Nov. http://www.cetsemi.com CEP830G/CEB830G CEF830G Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b c Tc = 25 C unless otherwise noted Symbol BVDSS IDSS IGSSF IGSSR VGS(th) RDS(on) gFS Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd IS f VSD VGS = 0V, IS = 3.1A VDS = 400V, ID = 5A, VGS = 10V Test Condition VGS = 0V, ID = 250µA VDS = 500V, VGS = 0V VGS = 30V, VDS = 0V VGS = -30V, VDS = 0V VGS = VDS, ID = 250µA VGS = 10V, ID = 2.5A VDS = 50V, ID = 4.8A 2.5 1.2 7 595 90 20 15 8 30 7 13 2.5 5 5 1.6 30 16 60 14 17 Min 500 1 100 -100 4 1.5 Typ Max Units V µA nA nA V Ω S pF pF pF ns ns ns ns nC nC nC A V VDS = 25V, VGS = 0V, f = 1.0 MHz VDD = 250V, ID = 5A, VGS = 10V, RGEN = 14Ω Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature . b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2% . c.Guaranteed by design, not subject to production testing. d.Limited only by maximum temperature allowed . e.Pulse width limited by safe operating area . f.Full package IS(max) = 4A . 2 CEP830G/CEB830G CEF830G 12 10 8 6 4 2 0 VGS=10,9,8,7V 12 10 8 6 4 25 C 2 0 TJ=125C -55 C 4 5 6 ID, Drain Current (A) VGS=6V VGS=4V 0 2 4 6 8 10 12 ID, Drain Current (A) 1 2 3 VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 900 750 600 450 300 150 0 Crss 0 5 10 15 20 25 Coss Ciss 2.2 1.9 1.6 1.3 1.0 0.7 0.4 -100 VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics ID=2.5A VGS=10V RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) C, Capacitance (pF) -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 VDS=VGS TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature 10 0 VTH, Normalized Gate-Source Threshold Voltage IS, Source-drain current (A) ID=250µA VGS=0V 10 -1 10 -25 0 25 50 75 100 125 150 -2 0.4 0.6 0.8 1.0 1.2 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 3 CEP830G/CEB830G CEF830G VGS, Gate to Source Voltage (V) 10 8 6 4 2 0 VDS=400V ID=5A RDS(ON)Limit ID, Drain Current (A) 10 1 100ms 1ms 10ms DC 10 0 0 3 6 9 12 15 10 -1 TC=25 C TJ=150 C Single Pulse 10 0 10 1 10 2 10 3 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDD t on V IN VGS RGEN G RL D VOUT td(on) VOUT 10% VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area toff tr 90% td(off) 90% 10% tf INVERTED 90% S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms 10 0 r(t),Normalized Effective Transient Thermal Impedance D=0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 10 -1 10 -2 Single Pulse 10 -3 1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2 -5 10 10 -4 10 -3 10 -2 10 -1 10 0 10 1 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve 4