CEPF640_08

N-Channel Enhancement Mode Field Effect Transistor FEATURES Type CEPF640 CEBF640 CEFF640 VDSS 200V 200V 200V RDS(ON) 0.15Ω 0.15Ω 0.15Ω ID 19A 19A 19A d @VGS 10V 10V 10V CEPF640/CEBF640 CEFF640 Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-220 & TO-263 & TO-220F full-pak for through hole. G G D S G CEP SERIES TO-220 D D S CEB SERIES TO-263(DD-PAK) G D S CEF SERIES TO-220F S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Limit Symbol TO-220/263 VDS VGS ID IDM PD TJ,Tstg e TO-220F Units V V 200 ±20 19 76 125 1.0 -55 to 150 19 76 40 0.32 d d A A W W/ C C Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA 1.0 62.5 Limit 3.1 65 Units C/W C/W Details are subject to change without notice . 1 Rev 3. 2008.Oct. http://www.cetsemi.com CEPF640/CEBF640 CEFF640 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Dynamic Characteristics c Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b Tc = 25 C unless otherwise noted Symbol BVDSS IDSS IGSSF IGSSR VGS(th) RDS(on) Test Condition VGS = 0V, ID = 250µA VDS = 160V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V VGS = VDS, ID = 250µA VGS = 10V, ID = 10A 2 0.125 Min 200 25 100 -100 4 0.150 Typ Max Units V µA 4 nA nA V Ω gFS Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd IS f VSD VDS = 10V, ID = 9A VDS = 25V, VGS = 0V, f = 1.0 MHz 9 1955 355 55 21 5 66 11 44 8 14 19 42 10 132 22 57 S pF pF pF ns ns ns ns nC nC nC A V VDD = 100V, ID = 11A, VGS = 10V, RGEN = 9.1Ω VDS = 160V, ID = 19A, VGS = 10V Drain-Source Diode Characteristics and Maximun Ratings VGS = 0V, IS = 19A g 1.5 Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature . b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2% . c.Guaranteed by design, not subject to production testing. d.Limited only by maximum temperature allowed . e .Pulse width limited by safe operating area . f .Full package IS(max) = 10.5A . g.Full package VSD test condition IS = 10.5A . i.L = 1mH, IAS = 25A, VDD = 25V, RG = 25Ω, Starting TJ = 25 C 2 CEPF640/CEBF640 CEFF640 12 10 8 6 4 2 0 0.0 VGS=10,9,8,7V 40 25 C ID, Drain Current (A) ID, Drain Current (A) 30 -55 C 20 TJ=125 C VGS=6V 10 0.5 1.0 1.5 2.0 2.5 3.0 0 3 4 5 6 7 8 VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 3000 2500 2000 1500 1000 500 0 Coss Crss 0 5 10 15 20 25 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -100 VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics ID=10A VGS=10V Ciss RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) C, Capacitance (pF) -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 VDS=VGS TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature VGS=0V VTH, Normalized Gate-Source Threshold Voltage IS, Source-drain current (A) ID=250µA 10 1 10 0 -25 0 25 50 75 100 125 150 10 -1 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 3 CEPF640/CEBF640 CEFF640 VGS, Gate to Source Voltage (V) 10 8 6 4 2 0 VDS=160V ID=19A 10 2 RDS(ON)Limit 10ms 100ms 1ms ID, Drain Current (A) 4 10 1 10ms DC 10 0 8 16 24 32 40 48 56 64 0 TC=25 C TJ=150 C Single Pulse 10 0 10 1 10 2 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDD t on V IN VGS RGEN G RL D VOUT td(on) VOUT 10% VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area toff tr 90% td(off) 90% 10% tf INVERTED 90% S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 Single Pulse PDM t1 t2 10 -2 1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve 4