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CES2309

CES2309

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CES2309 - P-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CES2309 数据手册
CES2309 P-Channel Enhancement Mode Field Effect Transistor FEATURES -20V, -2.2A, RDS(ON) = 165mΩ @VGS = -4.5V. RDS(ON) = 300mΩ @VGS = -2.5V. High dense cell design for extremely low RDS(ON). Rugged and reliable. Lead free product is acquired. SOT-23 package. D PRELIMINARY G D G SOT-23 S S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a TA = 25 C unless otherwise noted Symbol VDS VGS ID IDM PD TJ,Tstg Limit -20 Units V V A A W C ±12 -2.2 -8 1.25 -55 to 150 Maximum Power Dissipation Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Ambient b Symbol RθJA Limit 100 Units C/W This is preliminary information on a new product in development now . Details are subject to change without notice . 7-6 Rev 1. 2006.April http://www.cetsemi.com CES2309 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics c Gate Threshold Voltage Static Drain-Source On-Resistance Dynamic Characteristics d Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics d Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current b Drain-Source Diode Forward Voltage c td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = -2.2A VDS = -6V, ID = -2.2A, VGS = -4.5V VDD = -6V, ID = -1A, VGS = -4.5V, RGEN = 6Ω 10 4 19 5 6.2 0.5 0.8 -2.2 -1.2 20 10 40 10 10 ns ns ns ns nC nC nC A V gFS Ciss Coss Crss VDS = -5V, ID = -2.2A VDS = -6V, VGS = 0V, f = 1.0 MHz 3 275 105 70 S pF pF pF VGS(th) RDS(on) VGS = VDS, ID = -250µA VGS = -4.5V, ID = -2.2A VGS = -2.5V, ID = -2.0A -0.5 135 230 -1.5 165 300 V mΩ mΩ BVDSS IDSS IGSSF IGSSR VGS = 0V, ID = -250µA VDS = -20V, VGS = 0V VGS = 12V, VDS = 0V VGS = -12V, VDS = 0V -20 -1 100 -100 V µA TA = 25 C unless otherwise noted Symbol Test Condition Min Typ Max Units nA nA 7 Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Surface Mounted on FR4 Board, t < 5 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing. 7-7 CES2309 5 -VGS=4.5,4,3,V 5 -ID, Drain Current (A) 4 -VGS=2.5V 3 -ID, Drain Current (A) 4 3 2 -VGS=2.0V 2 TJ=125 C 1 25 C 0 -55 C 1 -VGS=1.5V 0 0 1 2 3 4 5 0 0.5 1.0 1.5 2.0 2.5 3.0 -VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 360 300 240 180 120 60 0 0 2 4 6 8 10 Coss Crss Ciss 2.2 1.9 1.6 1.3 1.0 0.7 0.4 -100 -VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) ID=-2.2A VGS=-4.5V C, Capacitance (pF) -50 0 50 100 150 200 -VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature -IS, Source-drain current (A) VGS=0V 1 VTH, Normalized Gate-Source Threshold Voltage VDS=VGS ID=-250µA 10 10 0 10 -25 0 25 50 75 100 125 150 -1 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature -VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 7-8 CES2309 -VGS, Gate to Source Voltage (V) 5 V =-6V DS ID=-2.2A 4 10 2 RDS(ON)Limit -ID, Drain Current (A) 10 1 3 10 0 2 1ms 10ms 100ms 1s DC 10 -1 1 0 0 1.6 3.2 4.8 6.4 10 -2 TA=25 C TJ=150 C Single Pulse -1 10 10 0 10 1 10 2 7 Qg, Total Gate Charge (nC) Figure 7. Gate Charge -VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area VDD t on V IN D VGS RGEN G 90% toff tr 90% RL VOUT td(on) VOUT td(off) 90% 10% tf 10% INVERTED S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms 10 0 r(t),Normalized Effective Transient Thermal Impedance D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 PDM t1 t2 1. RθJA (t)=r (t) * RθJA 2. RθJA=See Datasheet 3. TJM-TA = P* RθJA (t) 4. Duty Cycle, D=t1/t2 10 -2 Single Pulse -3 10 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve 7-9
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