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CEU10P10

CEU10P10

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CEU10P10 - P-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CEU10P10 数据手册
P-Channel Enhancement Mode Field Effect Transistor FEATURES -100V, -8A, RDS(ON) = 350mΩ @VGS = -10V. CED10P10/CEU10P10 Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-251 & TO-252 package. D D G S CEU SERIES TO-252(D-PAK) G D G S CED SERIES TO-251(I-PAK) S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD TJ,Tstg -100 Units V V A A W W/ C C ±30 -8 -32 50 0.4 -55 to 150 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA Limit 2.5 50 Units C/W C/W 2009.Aug 1 http://www.cetsemi.com CED10P10/CEU10P10 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics c Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics d Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current b Drain-Source Diode Forward Voltage c td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = -8A VDS = -80V, ID = -8A, VGS = -10V VDD = -50V, ID = -8A, VGS = -10V, RGEN = 25Ω 16 7 36 14 14 4 6.0 -8 -1.5 32 14 72 28 20 ns ns ns ns nC nC nC A V d TA = 25 C unless otherwise noted Symbol BVDSS IDSS IGSSF IGSSR VGS(th) RDS(on) gFS Ciss Coss Crss Test Condition VGS = 0V, ID = -250µA VDS = -100V, VGS = 0V VGS = 30V, VDS = 0V VGS = -30V, VDS = 0V VGS = VDS, ID = -250µA VGS = -10V, ID = -4A VDS = -40V, ID = -4A -2 300 3.5 575 120 30 Min -100 -1 100 -100 -4 350 Typ Max Units V µA nA nA V mΩ S pF pF pF VDS = -25V, VGS = 0V, f = 1.0 MHz Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Surface Mounted on FR4 Board, t < 10 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing. 2 CED10P10/CEU10P10 10 15 -ID, Drain Current (A) -ID, Drain Current (A) 8 6 4 2 0 -VGS=10,8,6,5V 25 C 12 9 6 3 0 TJ=125 C -55 C -VGS=4V 5 -VGS=3V 0 2 4 6 8 10 0 1 2 3 4 5 6 -VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 900 750 600 450 300 150 0 Coss Crss 0 5 10 15 20 25 Ciss 2.2 1.9 1.6 1.3 1.0 0.7 0.4 -100 -VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics ID=-4A VGS=-10V RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) C, Capacitance (pF) -50 0 50 100 150 200 -VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 VDS=VGS TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature -IS, Source-drain current (A) VGS=0V 10 1 VTH, Normalized Gate-Source Threshold Voltage ID=-250µA 10 0 -25 0 25 50 75 100 125 150 10 -1 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature -VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 3 CED10P10/CEU10P10 -VGS, Gate to Source Voltage (V) 10 V =-80V DS ID=-8A 10 2 RDS(ON)Limit 1ms -ID, Drain Current (A) 8 6 4 2 0 10 1 10ms 100ms DC 10 0 0 4 8 12 16 10 -1 TC=25 C TJ=150 C Single Pulse 0 10 10 1 10 2 10 3 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDD t on V IN VGS RGEN G RL D VOUT td(on) VOUT -VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area toff tr 90% td(off) 90% 10% tf 10% INVERTED 90% S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 Single Pulse PDM t1 t2 10 -2 1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve 4
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