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CEU1710

CEU1710

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CEU1710 - N-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CEU1710 数据手册
CED1710/CEU1710 N-Channel Enhancement Mode Field Effect Transistor FEATURES 100V, 17A, RDS(ON) = 85mΩ @VGS = 10V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-251 & TO-252 package. D PRELIMINARY G D G S CEU SERIES TO-252(D-PAK) G D S CED SERIES TO-251(I-PAK) S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD TJ,Tstg 100 Units V V A A W W/ C C ±20 17 68 50 0.4 -55 to 150 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA Limit 2.5 50 Units C/W C/W This is preliminary information on a new product in development now . Details are subject to change without notice . 1 2005.May http://www.cetsemi.com CED1710/CEU1710 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = 15A VDS = 80V, ID = 19A, VGS = 10V VDD = 50V, ID = 19A, VGS = 10V, RGEN = 25Ω 17 51 16 71 26 3.3 16.2 15 1.5 34 100 32 140 34 ns ns ns ns nC nC nC A V c Tc = 25 C unless otherwise noted Symbol BVDSS IDSS IGSSF IGSSR VGS(th) RDS(on) gFS Ciss Coss Crss Test Condition VGS = 0V, ID = 250µA VDS = 100, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V VGS = VDS, ID = 250µA VGS = 10V, ID = 15A VDS = 2.5V, ID = 15A 2 65 11 702 200 88 Min 100 1 100 -100 4 85 Typ Max Units V µA 4 nA nA V mΩ S pF pF pF VDS = 25V, VGS = 0V, f = 1.0 MHz Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. c.Guaranteed by design, not subject to production testing. 2 CED1710/CEU1710 6 VGS=10,8,6V 5 4 3 2 1 50 25 C ID, Drain Current (A) ID, Drain Current (A) 40 30 VGS=5V 20 TJ=125 C -55 C 10 VGS=4V 0 0.0 0 0.5 1.0 1.5 2.0 2.5 3.0 1 2 3 4 5 6 7 VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 1200 1000 800 600 400 Coss 200 0 0 5 10 15 20 25 Crss Ciss 2.2 1.9 1.6 1.3 1.0 0.7 0.4 -100 VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) ID=15A VGS=10V C, Capacitance (pF) -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature VGS=0V 2 VTH, Normalized Gate-Source Threshold Voltage VDS=VGS ID=250µA IS, Source-drain current (A) 25 50 75 100 125 150 10 10 1 10 -25 0 0 0.2 0.6 1.0 1.4 1.8 2.2 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 3 CED1710/CEU1710 VGS, Gate to Source Voltage (V) 10 VDS=80V ID=19A 10 2 RDS(ON)Limit ID, Drain Current (A) 8 4 100µs 1ms 10ms DC 10 1 6 4 10 0 2 0 0 5 10 15 20 25 30 10 -1 TC=25 C TJ=150 C Single Pulse 10 -1 10 0 10 1 10 2 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area VDD t on V IN D VGS RGEN G 90% toff tr 90% RL VOUT td(on) VOUT td(off) 90% 10% tf 10% INVERTED S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 Single Pulse PDM t1 t2 1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -2 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 Square Wave Pulse Duration (msec) Figure 11. Normalized Thermal Transient Impedance Curve 4
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