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CEU40N10

CEU40N10

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CEU40N10 - N-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CEU40N10 数据手册
N-Channel Enhancement Mode Field Effect Transistor FEATURES 100V, 37A, RDS(ON) = 32mΩ @VGS = 10V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-251 & TO-252 package. CED40N10/CEU40N10 D D G S CEU SERIES TO-252(D-PAK) G D G S CED SERIES TO-251(I-PAK) S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD TJ,Tstg 100 Units V V A A W W/ C C ±20 37 148 93.8 0.75 -55 to 150 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA Limit 1.6 50 Units C/W C/W Details are subject to change without notice . 1 Rev 1. 2009.Nov. http://www.cetsemi.com CED40N10/CEU40N10 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Dynamic Characteristics c Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = 20A VDS = 80V, ID = 37A, VGS = 10V VDD = 50V, ID = 37A, VGS = 10V, RGEN = 25Ω 35 30 138 29 50.8 12 19 37 1.5 70 60 276 58 67.5 ns ns ns ns nC nC nC A V VGS(th) RDS(on) gFS Ciss Coss Crss VGS = VDS, ID = 250µA VGS = 10V, ID = 20A 2 26 4 32 V mΩ BVDSS IDSS IGSSF IGSSR VGS = 0V, ID = 250µA VDS = 100V, VGS = 0V VGS = 25V, VDS = 0V VGS = -25V, VDS = 0V 100 1 100 -100 V µA Tc = 25 C unless otherwise noted Symbol Test Condition Min Typ Max Units nA nA VDS = 40V, ID = 20A VDS = 25V, VGS = 0V, f = 1.0 MHz 24 2060 330 40 S pF pF pF Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. c.Guaranteed by design, not subject to production testing. d.L = 0.42mH, IAS = 43.5A, VDD = 25V, RG = 25Ω, Starting TJ = 25 C 2 CED40N10/CEU40N10 36 30 24 18 12 6 0 VGS=10,9V 100 80 60 40 20 TJ=125 C 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0 2 4 25 C -55 C 6 8 ID, Drain Current (A) VGS=6V VGS=5V ID, Drain Current (A) VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 6000 5000 4000 3000 2000 1000 0 Crss 0 5 10 15 20 25 Ciss Coss 2.6 2.2 1.8 1.4 1.0 0.6 0.2 -100 VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics ID=20A VGS=10V RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) C, Capacitance (pF) -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 VDS=VGS TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature IS, Source-drain current (A) VGS=0V 10 2 VTH, Normalized Gate-Source Threshold Voltage ID=250µA 10 1 -25 0 25 50 75 100 125 150 10 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 3 CED40N10/CEU40N10 VGS, Gate to Source Voltage (V) 10 8 6 4 2 VDS=80V ID=37A 10 3 RDS(ON)Limit ID, Drain Current (A) 10 2 10ms 100ms 1ms DC 10 1 0 0 9 18 27 36 45 54 10 0 TC=25 C TJ=175 C Single Pulse 10 0 10 1 10 2 10 3 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDD t on V IN VGS RGEN G RL D VOUT td(on) VOUT 10% VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area toff tr 90% td(off) 90% 10% tf INVERTED 90% S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 Single Pulse PDM t1 t2 10 -2 1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 Square Wave Pulse Duration (msec) Figure 11. Normalized Thermal Transient Impedance Curve 4
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