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CEU41A2

CEU41A2

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CEU41A2 - N-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CEU41A2 数据手册
CED41A2/CEU41A2 N-Channel Enhancement Mode Field Effect Transistor FEATURES 20V, 36A, RDS(ON) = 20mΩ @VGS = 4.5V. RDS(ON) = 30mΩ @VGS = 2.5V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-251 & TO-252 package. D D G S CEU SERIES TO-252(D-PAK) G D G S CED SERIES TO-251(I-PAK) S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD TJ,Tstg 20 Units V V A A W W/ C C ±12 36 100 43 0.29 -55 to 175 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA Limit 3.5 50 Units C/W C/W Rev 1. 2005.May 6 - 62 http://www.cetsemi.com CED41A2/CEU41A2 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Forwand Transconductance Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = 10.7A VDS = 10V, ID = 10.7A, VGS = 4.5V VDD = 10 V, ID = 1A, VGS = 4.5V, RGEN =6Ω 20 20 72 20 15 2 3 36 1.3 40 40 130 40 20 ns ns ns ns nC nC nC A V c Tc = 25 C unless otherwise noted Symbol BVDSS IDSS IGSSF IGSSR VGS(th) RDS(on) gFS Ciss Coss Crss Test Condition VGS = 0V, ID = 250µA VDS = 20V, VGS = 0V VGS = 12V, VDS = 0V VGS = -12V, VDS = 0V VGS = VDS, ID = 250µA VGS = 4.5V, ID = 10.7A VGS = 2.5V, ID = 9.1A VDS = 5V, ID = 10.7A 0.5 16 21 15 950 450 135 Min 20 1 100 -100 1.5 20 30 Typ Max Units V µA nA nA V mΩ mΩ S pF pF pF 6 VDS = 8V, VGS = 0V, f = 1.0 MHz Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. c.Guaranteed by design, not subject to production testing. 6 - 63 CED41A2/CEU41A2 30 VGS=4.5,3.5,3.0,2.5V 25 20 VGS=2.0V 15 10 5 0 0 1 2 3 30 25 C ID, Drain Current (A) ID, Drain Current (A) 24 18 12 TJ=125 C 6 -55 C 0 0 1 2 3 VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 1800 1500 1200 Ciss 900 600 Coss 300 0 0 2 4 6 8 10 Crss 1.8 1.6 1.4 1.2 1.0 0.8 0.6 -100 VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) ID=10.7A VGS=4.5V C, Capacitance (pF) -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature VGS=0V 10 2 VTH, Normalized Gate-Source Threshold Voltage VDS=VGS ID=250µA IS, Source-drain current (A) 25 50 75 100 125 150 10 1 10 -25 0 0 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 6 - 64 CED41A2/CEU41A2 VGS, Gate to Source Voltage (V) 5 VDS=10V ID=10.7A 10 3 ID, Drain Current (A) 4 10 2 RDS(ON)Limit 3 100µs 1ms 10ms DC 2 10 1 1 0 0 4 8 12 16 10 0 TC=25 C TJ=175 C Single Pulse 10 -1 6 10 0 10 1 10 2 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area VDD t on V IN D VGS RGEN G 90% toff tr 90% RL VOUT td(on) VOUT td(off) 90% 10% tf 10% INVERTED S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 Single Pulse PDM t1 t2 1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -2 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 Square Wave Pulse Duration (msec) Figure 11. Normalized Thermal Transient Impedance Curve 6 - 65
CEU41A2 价格&库存

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