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CEU540A

CEU540A

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CEU540A - N-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CEU540A 数据手册
CED540A/CEU540A N-Channel Enhancement Mode Field Effect Transistor FEATURES 100V, 25A, RDS(ON) = 49mΩ @VGS = 10V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-251 & TO-252 package. D D G S CEU SERIES TO-252(D-PAK) G D G S CED SERIES TO-251(I-PAK) S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD TJ,Tstg 100 Units V V A A W W/ C C ±20 25 100 68 0.45 -55 to 175 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA Limit 2.2 50 Units C/W C/W Specification and data are subject to change without notice . 6 - 74 Rev .1 2006.March http://www.cetsemi.com CED540A/CEU540A Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Dynamic Characteristics c Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = 18A VDS = 80V, ID = 18A, VGS = 10V VDD = 50V, ID = 18A, VGS = 10V, RGEN = 5.1Ω 13 11 32 15 37.5 6 18 25 1.3 40 35 65 45 48 ns ns ns ns nC nC nC A V gFS Ciss Coss Crss VDS = 25V, ID = 18A VDS = 25V, VGS = 0V, f = 1.0 MHz 14 832 240 105 S pF pF pF VGS(th) RDS(on) VGS = VDS, ID = 250µA VGS = 10V, ID = 18A 2 42 4 49 V mΩ BVDSS IDSS IGSSF IGSSR VGS = 0V, ID = 250µA VDS = 100V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V 100 25 100 -100 V µA Tc = 25 C unless otherwise noted Symbol Test Condition Min Typ Max Units nA nA 6 Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. c.Guaranteed by design, not subject to production testing. 6 - 75 CED540A/CEU540A 80 VGS=10,9V 60 50 40 30 20 25 C 10 TJ=125 C 0 0 1 2 3 4 5 6 2 4 6 8 -55 C ID, Drain Current (A) 60 VGS=8V 40 VGS=7V 20 VGS=6V VGS=5V 0 ID, Drain Current (A) VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 1200 1000 Ciss 800 600 400 Coss 200 0 0 5 10 15 20 25 Crss 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -100 VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) ID=18A VGS=10V C, Capacitance (pF) -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature VGS=0V 2 VTH, Normalized Gate-Source Threshold Voltage VDS=VGS ID=250µA IS, Source-drain current (A) 25 50 75 100 125 150 10 10 1 10 -25 0 0 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 6 - 76 CED540A/CEU540A VGS, Gate to Source Voltage (V) 10 VDS=80V ID=18A 10 3 RDS(ON)Limit 2 ID, Drain Current (A) 8 10 10µs 100µs 6 10 1 4 1ms 10 0 2 0 0 10 20 30 40 10 -1 TC=25 C TJ=175 C Single Pulse 10 0 10ms 100ms DC 6 10 3 10 1 10 2 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area VDD t on V IN D VGS RGEN G 90% toff tr 90% RL VOUT td(on) VOUT td(off) 90% 10% tf 10% INVERTED S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 Single Pulse PDM t1 t2 1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -2 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 Square Wave Pulse Duration (msec) Figure 11. Normalized Thermal Transient Impedance Curve 6 - 77
CEU540A 价格&库存

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