CEU6060R

CED6060R/CEU6060R Feb. 2003 N-Channel Logic Level Enhancement Mode Field Effect Transistor FEATURES 6 60V , 30A , RDS(ON)=25m Ω @VGS=10V. Super high dense cell design for extremely low RDS(ON). High power and current handling capability. TO-251 & TO-252 package. D G S G D S D G CEU SERIES TO-252AA(D-PAK) CED SERIES TO-251(l-PAK) S ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous @TJ=125 C -Pulsed Drain-Source Diode Forward Current Maximum Power Dissipation @Tc=25 C Derate above 25 C Operating and Storage Temperature Range Symbol VDS VGS ID IDM IS PD TJ, TSTG Limit 60 20 30 120 30 50 0.3 -55 to 175 Unit V V A A A W W/ C C THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient R JC R JA 6-42 3 50 C/W C/W CED6060R/CEU6060R ELECTRICAL CHARACTERISTICS (TC=25 C unless otherwise noted) Parameter Single Pulse Drain-Source Avalanche Energy Maximum Drain-Source Avalanche Current Symbol a Condition VDD =25V, L = 25µH RG =25 Ω Min Typ Max Unit DRAIN-SOURCE AVALANCHE RATING EAS IAS 200 30 mJ A 6 OFF CHARACTERISTICS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate-Body Leakage BVDSS IDSS IGSS VGS(th) RDS(ON) ID(ON) gFS b VGS = 0V, ID = 250µA VDS = 60V, VGS = 0V VGS = 20V, VDS = 0V VDS = VGS, ID = 250µA VGS = 10V, ID = 24A VGS = 10V, VDS = 10V VDS = 10V, ID = 24A VDD = 30V, ID = 30A, VGS = 10V, RGEN= 7.5Ω 60 25 V µA 100 nA ON CHARACTERISTICS a Gate Threshold Voltage Drain-Source On-State Resistance On-State Drain Current Forward Transconductance 2 4 25 60 20 15 45 36 VDS =48V, ID = 30A, VGS =10V 6-43 V mΩ A S SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge tD(ON) tr tD(OFF) tf Qg Qgs Qgd 20 60 43 ns ns ns ns nC nC nC 250 300 130 150 9 19 CED6060R/CEU6060R ELECTRICAL CHARACTERISTICS (TC=25 C unless otherwise noted) Parameter DYNAMIC CHARACTERISTICSb Input Capacitance CISS COSS CRSS Symbol Condition Min Typ Max Unit 1178 428 95 PF PF PF 6 Output Capacitance Reverse Transfer Capacitance VDS =25V, VGS = 0V f =1.0MHZ DRAIN-SOURCE DIODE CHARACTERISTICS b Diode Forward Voltage VSD VGS = 0V, Is =24A 0.9 1.3 V Notes a.Pulse Test:Pulse Width 300 s, Duty Cycle 2%. b.Guaranteed by design, not subject to production testing. 40 VGS=10,8,7V 35 6V 40 TJ=125 C 25 C 30 ID, Drain Current(A) 25 VGS=5V 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 4V ID, Drain Current (A) 30 20 10 -55 C 0 2 3 4 5 6 7 8 VDS, Drain-to-Source Voltage (V) VGS, Gate-to-Source Voltage (V) Figure 1. Output Characteristics Figure 2. Transfer Characteristics 6-44 CED6060R/CEU6060R 1800 3.0 RDS(ON), Normalized Drain-Source On-Resistance VGS=10V 2.5 2.0 Tj=125 C 1.5 25 C 1.0 0.5 0 -55 C 1500 C, Capacitance (pF) 1200 900 600 Ciss Coss 300 Crss 0 0 10 15 20 25 30 0 10 20 30 40 50 6 VDS, Drain-to Source Voltage (V) ID, Drain Current(A) Figure 3. Capacitance Figure 4. On-Resistance Variation with Drain Current and Temperature BVDSS, Normalized Drain-Source Breakdown Voltage 1.15 1.10 1.05 1.00 0.95 0.90 0.85 -50 -25 ID=250 A Vth, Normalized Gate-Source Threshold Voltage 1.15 1.10 1.05 1.0 0.95 0.90 0.85 0.80 -50 -25 0 25 50 75 100 125 150 VDS=VGS ID=250 A 0 25 50 75 100 125 150 Tj, Junction Temperature ( C) Tj, Junction Temperature ( C) Figure 5. Gate Threshold Variation with Temperature 50 Figure 6. Breakdown Voltage Variation with Temperature 100 gFS, Transconductance (S) 30 20 10 VDS=10V 0 0 10 20 30 40 Is, Source-drain current (A) 40 10 1 0.4 0.6 0.8 1.0 1.2 1.4 IDS, Drain-Source Current (A) VSD, Body Diode Forward Voltage (V) Figure 7. Transconductance Variation with Drain Current 6-45 Figure 8. Body Diode Forward Voltage Variation with Source Current CED6060R/CEU6060R 15 VGS, Gate to Source Voltage (V) 300 ID, Drain Current (A) 12 9 6 3 0 0 VDS=48V ID=30A 100 R D S( ) ON Lim it 10 1m 10 0 10 s s s 10 VGS=10V Single Pulse Tc=25 C ms 10 0m DC s 6 1 6 12 18 24 30 36 42 48 1 10 60 100 Qg, Total Gate Charge (nC) VDS, Drain-Source Voltage (V) Figure 9. Gate Charge Figure 10. Maximum Safe Operating Area VDD t on V IN D VGS RGEN G 90% toff tr 90% RL VOUT td(on) VOUT td(off) 90% 10% tf 10% INVERTED S VIN 50% 10% 50% PULSE WIDTH Figure 11. Switching Test Circuit Figure 12. Switching Waveforms 2 r(t),Normalized Effective Transient Thermal Impedance 1 D=0.5 0.2 0.1 0.1 0.05 0.02 0.01 Single Pulse 0.01 0.01 PDM t1 t2 1. R JA (t)=r (t) * R JA 2. R JA=See Datasheet 3. TJM-TA = PDM* R JA (t) 4. Duty Cycle, D=t1/t2 1 10 100 1000 10000 0.1 Square Wave Pulse Duration (msec) Figure 13. Normalized Thermal Transient Impedance Curve 6-46