CS5158GDR16

CS5158 CS5158 CPU 5-Bit Synchronous Buck Controller Description The CS5158 is a 5-Bit synchronous dual N-Channel buck controller. It is designed to provide unprecedented transient response for today’s demanding high-density, high-speed logic. The regulator operates using a proprietary control method, which allows a 100ns response time to load transients. The CS5158 is designed to operate over a 4.25-16V range (VCC) using 12V to power the IC and 5V as the main supply for conversion. The CS5158 is specifically designed to power Pentium® II processors and other high performance core logic. It includes the following features: on board, 5-Bit DAC, short circuit protection, 0.8% output tolerance for the 01111 DAC code (1.3V) and 1% for the remaining DAC codes, VCC monitor, and programmable soft start capability. The CS5158 is available in 16 pin surface mount. Features s Dual N-Channel Design s Excess of 1MHz Operation s 100ns Transient Response s 5-Bit DAC s Backward Compatible with Adjustable CS5157 s 30ns Gate Rise/Fall Times s 0.8% Accuracy for the 01111 DAC Code and 1% for the Remaining DAC Codes s 5V & 12V Operation s Remote Sense s Programmable Soft Start s Lossless Short Circuit Protection s VCC Monitor s 25ns FET Nonoverlap Time s V2TM Control Topology 1200µF/10V x 3 AlEl Application Diagram Switching Power Supply for core logic - Pentium® II processor 12V 5V 0.1µF s Current Sharing s Overvoltage Protection VCC1 VCC2 VID0 VID1 VID2 VID3 VID4 330pF SS 0.1µF 0.33µF COMP LGnd VID0 VID1 VID2 VID3 VID4 COFF VGATE(H) IRL3103 2µH 1.3V to 3.5V @ 13A Package Options CS5158 VGATE(L) IRL3103 1200µF/10V x 5 AlEl PGnd VFB VFFB 3.3k 16 Lead SO Narrow VID0 VID1 VID2 VID3 SS VID4 COFF VFFB 1 VFB COMP LGnd VCC1 VGATE(L) PGnd VGATE(H) VCC2 100pF V2 is a trademark of Switch Power, Inc. Pentium is a registered trademark of Intel Corporation. Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com Rev. 2/16/99 1 A ® Company CS5158 Absolute Maximum Ratings Pin Name Max Operating Voltage Max Current VCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC/1.5A peak VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA DC/1.5A peak SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-100µA COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200µA VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2µA COFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2µA VFFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2µA VID0 - VID4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-50µA VGATE(H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak VGATE(L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak LGnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA PGnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0° to 150°C Lead Temperature Soldering Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183°C, 230°C peak Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−65° to 150°C ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Electrical Characteristics: 0°C < TA < +70°C; 0°C < TJ < +85°C; 8V < VCC1 < 14V; 5V < VCC2 < 14V; DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1nF; COFF = 330pF; CSS = 0.1µF, unless otherwise specified. TEST CONDITIONS MIN TYP MAX PARAMETER UNIT s Error Amplifier VFB Bias Current Open Loop Gain Unity Gain Bandwidth COMP SINK Current COMP SOURCE Current COMP CLAMP Current COMP High Voltage COMP Low Voltage PSRR s VCC1 Monitor Start Threshold Stop Threshold Hysteresis s DAC Input Threshold Input Pull Up Resistance Pull Up Voltage Accuracy (all codes except 01111 at 0.8%) VID4 VID3 VID2 VID1 VID0 0 1 1 1 1 0 1 1 1 0 0 1 1 0 1 0 1 1 0 0 0 1 0 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 1 1 0 VFB = 0V 1.25V < VCOMP < 4V; Note 1 Note 1 VCOMP = 1.5V; VFB = 3V; VSS > 2V VCOMP = 1.2V; VFB = 2.7V; VSS = 5V VCOMP = 0V; VFB = 2.7V VFB = 2.7V; VSS = 5V VFB =3V 8V < VCC1 < 14V @ 1kHz; Note 1 50 500 0.4 30 0.4 4.0 60 0.3 60 3000 2.5 50 1.0 4.3 160 85 1.0 8.0 70 1.6 5.0 600 µA dB kHz mA µA mA V mV dB Output switching Output not switching Start-Stop 3.75 3.70 3.90 3.85 50 4.05 4.00 V V mV VID0, VID1, VID2, VID3, VID4 VID0, VID1, VID2, VID3, VID4 Measure VFB = VCOMP, 25°C ≤ TJ ≤ 85°C 1.00 25 4.85 1.25 50 5.00 2.40 100 5.15 1.0 V kΩ V % 1.2896 1.3365 1.3860 1.4355 1.4850 1.5345 1.5840 1.6335 1.6830 1.7325 2 1.3000 1.3500 1.4000 1.4500 1.5000 1.5500 1.6000 1.6500 1.7000 1.7500 1.3104 1.3635 1.4140 1.4645 1.5150 1.5655 1.6160 1.6665 1.7170 1.7675 V V V V V V V V V V CS5158 Electrical Characteristics: 0°C < TA < +70°C; 0°C < TJ < +85°C; 8V < VCC1 < 14V; 5V < VCC2 < 14V; DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1nF; COFF = 330pF; CSS = 0.1µF, unless otherwise specified. TEST CONDITIONS MIN TYP MAX PARAMETER UNIT s DAC: continued VID4 VID3 VID2 VID1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1.7820 1.8315 1.8810 1.9305 1.9800 2.0295 1.2315 2.0790 2.1780 2.2770 2.3760 2.4750 2.5740 2.6730 2.7720 2.8710 2.9700 3.0690 3.1680 3.2670 3.3660 3.4650 1.8000 1.8500 1.9000 1.9500 2.0000 2.0500 1.2440 2.1000 2.2000 2.3000 2.4000 2.5000 2.6000 2.7000 2.8000 2.9000 3.0000 3.1000 3.2000 3.3000 3.4000 3.5000 1.8180 1.8685 1.9190 1.9695 2.0200 2.0705 1.2564 2.1210 2.2220 2.3230 2.4240 2.5250 2.6260 2.7270 2.8280 2.9290 3.0300 3.1310 3.2320 3.3330 3.4340 3.5350 V V V V V V V V V V V V V V V V V V V V V V s VGATE(H) and VGATE(L) Out SOURCE Sat at 100mA Out SINK Sat at 100mA Out Rise Time Out Fall Time Delay VGATE(H) to VGATE(L) Delay VGATE(L) to VGATE(H) VGATE(H), VGATE(L) Resistance VGATE(H), VGATE(L) Schottky Measure VCC1 – VGATE(L),;VCC2 – VGATE(H) Measure VGATE(H) – VPGnd; VGATE(L) – VPGnd 1V < VGATE(H) < 9V; 1V < VGATE(L) < 9V VCC1 = VCC2 = 12V 9V > VGATE(H) > 1V; 9V > VGATE(L) > 1V VCC1 = VCC2 = 12V VGATE(H) falling to 2V; VCC1 = VCC2 = 8V VGATE(L) rising to 2V VGATE(L) falling to 2V; VCC1 = VCC2 = 8V VGATE(H) rising to 2V Resistor to LGnd LGnd to VGATE(H) @ 10mA LGnd to VGATE(L) @ 10mA 1.2 1.0 30 30 25 25 20 50 600 2.0 1.5 50 50 50 50 100 800 V V ns ns ns ns kΩ mV s Soft Start (SS) Charge Time Pulse Period Duty Cycle COMP Clamp Voltage VFFB SS Fault Disable High Threshold (Charge Time/Pulse Period) × 100 VFB = 0V; VSS = 0 VGATE(H) = Low; VGATE(L) = Low 1.6 25 1.0 0.50 0.9 3.3 100 3.3 0.95 1.0 2.5 5.0 200 6.0 1.10 1.1 3.0 ms ms % V V V 3 CS5158 Electrical Characteristics: 0°C < TA < +70°C; 0°C < TJ < +85°C; 8V < VCC1 < 14V; 5V < VCC2 < 14V; DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1nF; COFF = 330pF; CSS = 0.1µF, unless otherwise specified. TEST CONDITIONS MIN TYP MAX PARAMETER UNIT s PWM Comparator Transient Response VFFB Bias Current s Supply Current ICC1 No Switching ICC2 No Switching Operating ICC1 Operating ICC2 VFFB = 0 to 5V to VGATE(H) = 9V to 1V; VCC1 = VCC2 = 12V VFFB = 0V 100 0.3 125 ns µA VFB = COMP = VFFB VFB = COMP = VFFB 8.5 1.6 8 2 13.5 3.0 13 5 mA mA mA mA s COFF Normal Charge Time Extension Charge Time Discharge Current s Time Out Timer Time Out Time Fault Mode Duty Cycle VFFB = 1.5V; VSS = 5V VSS = VFFB = 0 COFF to 5V; VFB >1V 1.0 5.0 5.0 1.6 8.0 2.2 11.0 µs µs mA VFB = VCOMP; VFFB = 2V; Record VGATE(H) Pulse High Duration VFFB = 0V 10 35 30 50 50 65 µs % Note 1: Guaranteed by design, not 100% tested in production. Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION 16L SO Narrow 1,2,3,4,6 VID0 – VID4 Voltage ID DAC input pins. These pins are internally pulled up to 5V providing logic ones if left open. VID4 selects the DAC range. When VID4 is High (logic one), the DAC range is 2.10V to 3.50V with 100mV increments. When VID4 is Low (logic zero), the DAC range is 1.30V to 2.05V with 50mV increments. VID0 - VID4 select the desired DAC output voltage. Leaving all 5 DAC input pins open results in a DAC output voltage of 1.2440V, allowing for adjustable output voltage, using a traditional resistor divider. Soft Start Pin. A capacitor from this pin to LGnd in conjunction with internal 60µA current source provides soft start function for the controller. This pin disables fault detect function during Soft Start. When a fault is detected, the soft start capacitor is slowly discharged by internal 2µA current source setting the time out before trying to restart the IC. Charge/discharge current ratio of 30 sets the duty cycle for the IC when the regulator output is shorted. A capacitor from this pin to ground sets the time duration for the on board one shot, which is used for the constant off time architecture. Fast feedback connection to the PWM comparator. This pin is connected to the regulator output. The inner feedback loop terminates on time. Boosted power for the high side gate driver. High FET driver pin capable of 1.5A peak switching current. Internal circuit prevents VGATE(H) and VGATE(L) from being in high state simultaneously. 4 5 SS 7 8 9 10 COFF VFFB VCC2 VGATE(H) CS5158 Package Pin Description: continued PACKAGE PIN # PIN SYMBOL FUNCTION 16L SO Narrow 11 PGnd High current ground for the IC. The MOSFET drivers are referenced to this pin. Input capacitor ground and the source of lower FET should be tied to this pin. Low FET driver pin capable of 1.5A peak switching current. Input power for the IC and low side gate driver. Signal ground for the IC. All control circuits are referenced to this pin. Error amplifier compensation pin. A capacitor to ground should be provided externally to compensate the amplifier. Error amplifier DC feedback input. This is the master voltage feedback which sets the output voltage. This pin can be connected directly to the output or a remote sense trace. 12 13 14 15 16 VGATE(L) VCC1 LGnd COMP VFB Block Diagram VCC2 VCC1 + 3.90V 3.85V VCC1 Monitor Comparator 5V 60µA 0.7V + SS Low Comparator R S Q Q VGATE(H) FAULT FAULT PGnd SS 2µA + SS High Comparator FAULT Latch VCC1 VID0 VID1 VID2 VID3 VID4 5 BIT DAC + PWM Comparator Slow Feedback + Error Amplifier 2.5V VGATE(L) PGnd VFB COMP VFFB Maximum On-Time Timeout Normal Off-Time Timeout R S Q Q PWM Latch GATE(H) = ON GATE(H) = OFF COFF One Shot R S Q Fast Feedback + Extended Off-Time Timeout VFFB Low Comparator Off-Time Timeout COFF LGnd 1V PWM COMP Time Out Timer (30µs) Edge Triggered 5 CS5158 Applications Information Theory of Operation V2TM Control Method The V2TM method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. PWM Comparator + VGATE(H) C – VGATE(L) change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2TM method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. Constant Off Time To maximize transient response, the CS5158 uses a constant off time method to control the rate of output pulses. During normal operation, the off time of the high side switch is terminated after a fixed period, set by the COFF capacitor. To maintain regulation, the V2TM control loop varies switch on time. The PWM comparator monitors the output voltage ramp, and terminates the switch on time. Constant off time provides a number of advantages. Switch duty cycle can be adjusted from 0 to 100% on a pulse by pulse basis when responding to transient conditions. Both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. PWM slope compensation to avoid sub-harmonic oscillations at high duty cycles is avoided. Switch on time is limited by an internal 30µs timer, minimizing stress to the power components. Programmable Output The CS5158 is designed to provide two methods for programming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.10V to 3.50V in 100mV steps, the second is 1.30V to 2.05V in 50mV steps, depending on the digital input code. If all five bits are left open, the CS5158 enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB and VFFB pins, as in traditional controllers. Start Up Until the voltage on the VCC1 supply pin exceeds the 3.9V monitor threshold, the soft start and gate pins are held low. The FAULT latch is reset (no Fault condition). The output of the error amplifier (COMP) is pulled up to 1V by the comparator clamp. When the VCC1 pin exceeds the monitor threshold, the GateH output is activated, and the soft start capacitor begins charging. The GateH output will remain on, enabling the NFET switch, until terminated by either the PWM comparator, or the maximum on time timer. If the maximum on time is exceeded before the regulator output voltage achieves the 1V level, the pulse is terminated. The GateH pin drives low, and the GateL pin drives high for the duration of the extended off time. This time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. The GateL pin will then drive low, the GateH pin will drive high, and the cycle repeats. When regulator output voltage achieves the 1V level present at the COMP pin, regulation has been achieved and normal off time will ensue. The PWM comparator termi6 Ramp Signal VFFB Output Voltage Feedback VFB – Error Amplifier COMP Error Signal E + Reference Voltage Figure 1: V2TM Control Diagram The V2TM control method is illustrated in Figure 1. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2TM control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V2TM control scheme has the same advantages in line transient response. A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This CS5158 Applications Information: continued nates the switch on time, with off time set by the COFF capacitor. The V2TM control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. The soft start and COMP capacitors will charge to their final levels, providing a controlled turn on of the regulator output. Regulator turn on time is determined by the COMP capacitor charging to its final value. Its voltage is limited by the soft start COMP clamp and the voltage on the soft start pin (see Figures 2 and 3). Trace 1 - Regulator Output Voltage (5V/div.) Trace 2 - Inductor Switching Node (5V/div.) Figure 4: CS5158 demonstration board enable startup waveforms. Trace 1 - Regulator Output Voltage (1V/div.) Trace 2 - Inductor Switching Node (2V/div.) Trace 3 - 12V input (VCC1 and VCC2) (5V/div.) Trace 4 - 5V Input (1V/div.) Figure 2: CS5158 demonstration board startup in response to increasing 12V and 5V input voltages. Extended off time is followed by normal off time operation when output voltage achieves regulation to the error amplifier output. Normal Operation During normal operation, switch off time is constant and set by the COFF capacitor. Switch on time is adjusted by the V2TM control loop to maintain regulation. This results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. Output voltage ripple will be determined by inductor ripple current working into the ESR of the output capacitors (see Figures 5 and 6). Ch1 High 2.80V Trace 1 - Regulator Output Voltage (10mV/div.) Trace 2 - Inductor Switching Node (5V/div.) Trace 1 - Regulator Output Voltage (1V/div.) Trace 3 - COMP Pin (error amplifier output) (1V/div.) Trace 4 - Soft Start Pin (2V/div.) Figure 5: Peak-to-peak ripple on VOUT = 2.8V, IOUT = 0.5A (light load). Figure 3: CS5158 demonstration board startup waveforms. If the input voltage rises quickly, or the regulator output is enabled externally, output voltage will increase to the level set by the error amplifier output more rapidly, usually within a couple of cycles (see Figure 4). 7 CS5158 Applications Information: continued Trace1 - Regulator Output Voltage (10mV/div.) Trace 2 - Inductor Switching Node (5V/div.) Trace 1 - Regulator Output Voltage (100mV/div.) Trace 2 - Inductor Switching Node (5V/div.) Trace 3 - Output Current (0.5 to 13 Amps) (10A/div.) Figure 6: Peak-to-peak ripple on VOUT = 2.8V, IOUT = 13A (heavy load). Transient Response The CS5158 V2TM control loop’s 100ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. For best transient response, a combination of a number of high frequency and bulk output capacitors are usually used. If the maximum on time is exceeded while responding to a sudden increase in load current, a normal off time occurs to prevent saturation of the output inductor. Figure 8: CS5158 demonstration board response to 13A load turn on (output set for 2.8V). Upon completing a normal off time, the V2TM control loop immediately connects the inductor to the input voltage, providing 100% duty cycle. Regulation is achieved in less than 20µs. Trace1 - Regulator Output Voltage (100mV/div.) Trace 2 - Inductor Switching Node (5V/div.) Trace 3 - Output Current (13 to 0.5 Amps) (10A/div.) Figure 9: CS5158 demonstration board response to 13A load turn off (output set for 2.8V). V2TM control topology immediately connects inductor to ground, providing 0% duty cycle. Regulation is achieved in less than 10µs. Protection and Monitoring Features VCC1 Monitor To maintain predictable startup and shutdown characteristics an internal VCC1 monitor circuit is used to prevent the part from operating below 3.75V minimum startup. The VCC1 monitor comparator provides hysteresis and guarantees a 3.70V minimum shutdown threshold. Trace 1 - Regulator Output Voltage (100mV/div.) Trace 3 - Regulator Output Current (10A/div.) Figure 7: CS5158 demonstration board response to a 0.5 to 13A load pulse (output set for 2.8V). 8 CS5158 Applications Information: continued Short Circuit Protection A lossless hiccup mode short circuit protection feature is provided, requiring only the soft start capacitor to implement. If a short circuit condition occurs (VFFB < 1V), the VFFB low comparator sets the FAULT latch. This causes the top MOSFET to shut off, disconnecting the regulator from it’s input voltage. The soft start capacitor is then slowly discharged by a 2µA current source until it reaches it’s lower 0.7V threshold. The regulator will then attempt to restart normally, operating in it’s extended off time mode with a 50% duty cycle, while the soft start capacitor is charged with a 60µA charge current. If the short circuit condition persists, the regulator output will not achieve the 1V low VFFB comparator threshold before the soft start capacitor is charged to it’s upper 2.5V threshold. If this happens the cycle will repeat itself until the short is removed. The soft start charge/discharge current ratio sets the duty cycle for the pulses (2µA/60µA = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%). This protection feature results in less stress to the regulator components, input power supply, and PC board traces than occurs with constant current limit protection (see Figures 10 and 11). If the short circuit condition is removed, output voltage will rise above the 1V level, preventing the FAULT latch from being set, allowing normal operation to resume. Trace 4 = 5V from PC Power Supply (2V/div.) Trace 2 = Inductor Switching Node (2V/div.) Figure 11: Startup with regulator output shorted. Overvoltage Protection Overvoltage protection (OVP) is provided as result of the normal operation of the V2TM control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100ns, causing the top MOSFET to shut off, disconnecting the regulator from it’s input voltage. The bottom MOSFET is then activated, resulting in a “crowbar” action to clamp the output voltage and prevent damage to the load (see Figures 12 and 13). The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. The bottom FET and board trace must be properly designed to implement the OVP function. Trace 4 - 5V Supply Voltage (2V/div.) Trace 3 - Soft Start Timing Capacitor (1V/div.) Trace 2 - Inductor Switching Node (2V/div.) Figure 10: CS5158 demonstration board hiccup mode short circuit protection. Gate pulses are delivered while the soft start capacitor charges, and cease during discharge. Trace 4 = 5V from PC Power Supply (5V/div.) Trace1 = Regulator Output Voltage (1V/div.) Trace 2 = Inductor Switching Node (5V/div.) Figure 12: OVP response to an input-to-output short circuit by immediately providing 0% duty cycle, crow-barring the input voltage to ground. 9 CS5158 Applications Information: continued 5V R3 10k R1 10k VOUT Power Good PN3904 R2 6.2k PN3904 CS5158 Figure 15: Implementing Power Good with the CS5158. Trace 4 = 5V from PC Power Supply (2V/div.) Trace 1 = Regulator Output Voltage (1V/div.) Figure 13: OVP response to an input-to-output short circuit by pulling the input voltage to ground. External Output Enable Circuit On/off control of the regulator can be implemented through the addition of two additional discrete components (see Figure 14). This circuit operates by pulling the soft start pin high, and the VFFB pin low, emulating a short circuit condition. 5V Ch 1 High 2.80V MMUN2111T1 (SOT-23) Trace 3 = 12V Input (VCC1) and VCC2) (10V/div.) Trace 4 = 5V Input (2V/div.) Trace 1 = Regulator Output Voltage (1V/div.) Trace 2 = Power Good Signal (2V/div.) 5 SS CS5158 8V FFB IN4148 Figure 16: CS5158 demonstration board during power up. Power Good signal is activated when output voltage reaches 1.70V. Shutdown Input Selecting External Components The CS5158 can be used with a wide range of external power components to optimize the cost and performance of a particular design. The following information can be used as general guidelines to assist in their selection. NFET Power Transistors Both logic level and standard MOSFETs can be used. The reference designs derive gate drive from the 12V supply which is generally available in most computer systems and utilize logic level MOSFETs. Multiple MOSFETs may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the MOSFET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5V of ground when in the low state and to within 2V of their respective bias supplies when in the high state. In practice, the MOSFET gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller IC. For the typical application where VCC1 = VCC2 = 12V and 5V is 10 Figure 14: Implementing shutdown with the CS5158. External Power Good Circuit An optional Power Good signal can be generated through the use of four additional external components (see Figure 15). The threshold voltage of the Power Good signal can be adjusted per the following equation: VPower Good = (R1 + R2) × 0.65V R2 This circuit provides an open collector output that drives the Power Good output to ground for regulator voltages less than VPower Good. CS5158 Applications Information: continued used as the source for the regulator output current, the following gate drive is provided; VGATE(H) = 12V - 5V = 7V, VGATE(L) = 12V (see Figure 17). where: Period = 1 switching frequency COFF = Period × (1 - duty cycle) , 4848.5 Schottky Diode for Synchronous MOSFET A Schottky diode may be placed in parallel with the synchronous MOSFET to conduct the inductor current upon turn off of the switching MOSFET to improve efficiency. The CS5158 reference circuit does not use this device due to it’s excellent design. Instead, the body diode of the synchronous MOSFET is utilized to reduce cost and conducts the inductor current. For a design operating at 200kHz or so, the low non-overlap time combined with Schottky forward recovery time may make the benefits of this device not worth the additional expense (see Figure 6, channel 2). The power dissipation in the synchronous MOSFET due to body diode conduction can be estimated by the following equation: Trace 3 = VGATE(H) (10V/div.) Math 1= VGATE(H) - 5VIN Trace 4 = VGATE(L) (10V/div.) Trace 2 = Inductor Switching Node (5V/div.) Power = Vbd × ILOAD × conduction time × switching frequency Where Vbd = the forward drop of the MOSFET body diode. For the CS5158 demonstration board as shown in Figure 6; Power = 1.6V × 13A × 100ns × 233kHz = 0.48W This is only 1.3% of the 36.4W being delivered to the load. Input and Output Capacitors These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the input supply lines and regulator output voltage. Key specifications for input capacitors are their ripple rating, while ESR is important for output capacitors. For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. Output Inductor The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. Thermal Management Thermal Considerations for Power MOSFETs and Diodes In order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a maximum of 150°C or lower. The thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows: Thermal Impedance = TJUNCTION(MAX) - TAMBIENT Power Figure 17: CS5158 gate drive waveforms depicting rail to rail swing. The most important aspect of MOSFET performance is RDSON, which effects regulator efficiency and MOSFET thermal management requirements. The power dissipated by the MOSFETs may be estimated as follows; Switching MOSFET: Power = ILOAD2 × RDSON × duty cycle Synchronous MOSFET: Power = ILOAD2 × RDSON × (1 - duty cycle) Duty Cycle = VOUT + (ILOAD × RDSON OF SYNCH FET) VIN + (ILOAD × RDSON OF SYNCH FET) - (ILOAD × RDSON OF SWITCH FET) Off Time Capacitor (COFF) The COFF timing capacitor sets the regulator off time: TOFF = COFF × 4848.5 When the VFFB pin is less than 1V, the current charging the COFF capacitor is reduced. The extended off time can be calculated as follows: TOFF = COFF × 24,242.5. Off time will be determined by either the TOFF time, or the time out timer, whichever is longer. The preceding equations for duty cycle can also be used to calculate the regulator switching frequency and select the COFF timing capacitor: 11 CS5158 Applications Information: continued A heatsink may be added to TO-220 components to reduce their thermal impedance. A number of PC board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. EMI Management As a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. When designing for compliance with EMI/EMC regulations, additional components may be added to reduce noise emissions. These components are not required for regulator operation and experimental results may allow them to be eliminated. The input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of the power component to minimize routing distance will also help to reduce emissions. 5. Place the output filter capacitor(s) as close to the load as possible and connect the ground terminal to pin 14 (LGnd). 6. Connect the VFB pin directly to the load with a separate trace (remote sense). 7. Place 5V input capacitors close to the switching MOSFET and synchronous MOSFET. Route gate drive signals VGATE(H) (pin 10) and VGATE(L) (pin 12 when used) with traces that are a minimum of 0.025 inches wide. VCC 0.1µF 15 To the negative terminal of the input capacitors 11 1.0µF VCOMP 100pF VFFB 8 5 SOFTSTART OFF TIME To the negative terminal of the output capacitors Figure 20: Layout Guidelines 2µH 2µH + 33Ω 1000pF 1200µF x 3/16V Figure 18: Filter components Figure 19: Input Filter Layout Guidelines 1. Place 12V filter capacitor next to the IC and connect capacitor ground to pin 11 (PGnd). 2. Connect pin 11 (PGnd) with a separate trace to the ground terminals of the 5V input capacitors. 3. Place fast feedback filter capacitor next to pin 8 (VFFB) and connect it’s ground terminal with a separate, wide trace directly to pin 14 (LGnd). 4. Connect the ground terminals of the Compensation capacitor directly to the ground of the fast feedback filter capacitor to prevent common mode noise from effecting the PWM comparator. 12 CS5158 Additional Application Circuits 5V 12V MBRS 120 0.1µF MBRS120 1µ F VCC1 VID0 VID1 VID2 VID3 VID4 COFF 330pF SS 0.1µF 0.33µF COMP LGnd VFB VFFB 3.3k + VCC2 VGATE(H) MBRS120 1µF Si4410DY 3µH 3.3V/10A + 1200µF/10V x 3 AIEI 3.3V + Si9410 1µF 1200µF/10V x 3 AIEI VCC1 VID0 VID1 VID2 Si9410DY VCC2 VGATE(H) 5µ H 2.5V/7A CS5158 VGATE(L) PGnd CS5158 VFB + Si9410 VID3 VID4 COFF 330pF SS 0.1µF 0.33µF COMP LGnd 1200µF/10V x 5 AIEI 1200µF/10V x 5 AIEI VGATE(L) PGnd VFFB 3.3k 100pF 100pF Figure 21: 5V to 3.3V/10A converter. Figure 23: 3.3V to 2.5V/7A converter with 12V bias. 5V MBRS 120 0.1µF MBRS120 1µF MBRS120 1µF Si4410 VCC1 VID0 VID1 VID2 VID3 VID4 COFF VGATE(L) VCC2 VGATE(H) 3µH + 1200µF/10V x 3 AIEI Remote Sense 3.3V/10A CS5158 VFB 10Ω Si9410 + 1200µF/10V x 5 AIEI 330pF SS 0.1µF 0.33µF COMP LGnd PGnd VFFB 3.3k Connect to other circuits for current sharing 100pF Figure 22: 5V to 3.3V/10A converter with current sharing. 13 CS5158 Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA D Lead Count 16L SO Narrow Metric Max Min 10.00 9.80 English Max Min .394 .386 Thermal Data RΘJC RΘJA typ typ 16L SO Narrow 28 115 ˚C/W ˚C/W Surface Mount Narrow Body (D); 150 mil wide 4.00 (.157) 3.80 (.150) 6.20 (.244) 5.80 (.228) 0.51 (.020) 0.33 (.013) 1.27 (.050) BSC 1.75 (.069) MAX 1.57 (.062) 1.37 (.054) 1.27 (.050) 0.40 (.016) 0.25 (.010) 0.19 (.008) D REF: JEDEC MS-012 0.25 (0.10) 0.10 (.004) Ordering Information Part Number CS5158GD16 CS5158GDR16 Description 16L SO Narrow 16L SO Narrow (tape & reel) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Rev. 2/16/99 14 © 1999 Cherry Semiconductor Corporation