CDB4225

CS4225 Digital Audio Conversion System Features Description The CS4225 is a single-chip, stereo analog-to-digital and quad digital-to-analog converter using delta-sigma conversion techniques. Applications include CD-quality music, FM radio quality music, telephone-quality speech. Four D/A converters make the CS4225 ideal for surround sound and automotive applications. The CS4225 is supplied in a 44-pin plastic package with J-leads (PLCC) or as a die. ORDERING INFORMATION CS4225-KL 0° to 70° C CS4225-BL -40° to 85° C CS4225-YU -40° to 85° C CDB4225 44-pin PLCC 44-pin PLCC die Evaluation Board l Stereo 16-bit A/D Converters l Quad 16-bit D/A Converters l Sample Rates From 4 kHz to 50 kHz l >100 dB DAC Signal-to-Noise Ratio l Variable Bandwidth Auxiliary 12-bit A/D l Programmable Input Gain & Output Attenuation l +5V Power Supply l On-chip Anti-aliasing and Output Smoothing Filters l Error Correction and De-Emphasis I AD2/CDIN/CKF1 AD3/CS/IF1 SCL/CCLK/IF0 SDA/CDOUT/CKF0 VREF CMOUT VD+ VA+ Control Port DEM RST-PDN Digital Filters with De-Emphasis LRCK Serial Audio Data Interface SCLK SDIN1 SDIN2 SDOUT1 SDOUT2 DIF/HOLD DAC#1 DAC#2 DAC#3 DAC#4 Volume Control Volume Control Volume Control Volume Control Voltage Reference H/S Analog Low Pass and Output Stage AOUT1 AOUT2 AOUT3 AOUT4 2 MUX Left ADC Right ADC PLL IS0/AD0, IS1/AD1 AIN1L AIN1R AIN2L AIN2R AIN3L AIN3R AGND2 Digital Filters Input Gain AINAUX 12-Bit ADC Clock Osc/ Divider OVL CLKOUT XTI XTO Auxiliary Digital Input FILT CL CR DATAUX SCLKAUX LRCKAUX AGND1 DGND Preliminary Product Information Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 1997 (All Rights Reserved) Input MUX NOV ‘93 DS86PP8 1 CS4225 ANALOG CHARACTERISTICS( TA = 25°C; VA+, VD+ = +5V; Full Scale Input Sine wave, 1 kHz; Word Clock = 48 kHz (PLL in use); Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in "Recommended Connection Diagram"; SPI mode, Format 0, unless otherwise specified.) Parameter * Symbol Min Typ Max Units Analog Input Characteristics - Minimum gain setting (0 dB); unless otherwise specified. ADC Resolution ADC Differential Nonlinearity Dynamic Range Audio channels(A weighted): THD+N Audio channels Auxiliary channel 16 12 82 Audio channels(0 to 0.454 Fs): -3.0 -0.2 1.3 2.66 (Note 1) 10 1.9 85 -85 85 1.5 10 2.8 100 2.1 ±0.9 -82 .1 +0.2 46.7 1.7 2.94 15 2.3 Bits Bits LSB dB dB dB dB dB dB dB LSB Vpp ppm/°C kΩ pF V Total Harmonic Distortion + Noise (A weighted) Interchannel Isolation Interchannel Gain Mismatch Frequency Response Programmable Input Gain Gain Step Offset Error Full Scale Input Voltage (Auxiliary and Audio channels): Gain Drift Input Resistance Input Capacitance CMOUT Output Voltage Notes: 1. Input resistance is for the input selected. Non-selected inputs have a very high (>1MΩ) input resistance. The input resistance will vary with gain value selected, but will always be greater than the min. value specified. * Parameter definitions are given at the end of this data sheet. Specifications are subject to change without notice. 2 DS86PP8 CS4225 ANALOG CHARACTERISTICS Parameter * (Continued) Symbol Min Typ Max Units Analog Output Characteristics - Minimum Attenuation; Unless Otherwise Specified. DAC Resolution DAC Differential Nonlinearity Total Dynamic Range Total Harmonic Distortion (DAC muted,A weighted) (Note 2) THD 16 100 85 (0 to 0.476 Fs) (All Outputs) -3.0 0.2 0.88 (Note 2) 2.66 (Fs/2 to 2Fs) Resistance: Capacitance: 8 88 85 1.0 10 2.8 100 -60 ±0.9 0.01 0.2 +0.2 -117 1.12 2.94 5 100 Bits LSB dB % dB dB dB dB dB dB mV Vpp ppm/°C Degrees dB kΩ pF Instantaneous Dynamic Range (DAC not muted, Note 2, A weighted) Interchannel Isolation Interchannel Gain Mismatch Frequency Response Programmable Attenuation Attenuation Step Offset Voltage Full Scale Output Voltage Gain Drift Deviation from Linear Phase Out of Band Energy Analog Output Load (Note 2) Power Supply Power Supply Current Power Supply Rejection Notes: 2. 10 kΩ, 100 pF load. Operating Power Down (1 kHz) 120 1 40 TBD TBD mA mA dB DS86PP8 3 CS4225 16-Bit Audio A/D Decimation Filter Characteristics Parameter Passband ( to -3 dB corner) Passband Ripple Transition Band Stop Band Stop Band Rejection Group Delay Group Delay Variation vs. Frequency (Fs is conversion freq.) Symbol Min 0 0.40Fs (See graphs towards the end of this data sheet) Typ 10/Fs Max 0.454Fs ±0.1 0.60Fs 0.0 Units Hz dB Hz Hz dB s µs ≥ 0.60Fs 75 - D/A Interpolation Filter Characteristics (See graphs toward the end of this data sheet) Parameter Passband (to -3 dB corner) Passband Ripple Transition Band Stop Band Stop Band Rejection Stop Band Rejection with Ext. 2Fs RC filter Group Delay Group Delay Variation vs. Frequency (Fs is conversion freq.) Symbol Min 0 0.442Fs ≥0.567Fs 50 57 Typ 12/Fs Max 0.476Fs ±0.1 0.567Fs TBD Units Hz dB Hz Hz dB dB s µs 4 DS86PP8 CS4225 SWITCHING CHARACTERISTICS (TA = 25°C; VA+, VD+ = +5V, outputs loaded with 30pF) Parameter SCLK period SCLK high time SCLK low time Input Transition Time Input Clock Frequency Input Clock (XTI) low time Input Clock (XTI) high time Input clock jitter tolerance PLL clock recovery frequency CLKOUT duty cycle Audio ADC’s & DAC’s sample rate RST-PDN low time MSB output from LRCK edge (Format 1 and 3) SDOUT output from SCLK edge SDIN setup time before SCLK edge SDIN hold time after SCLK edge LRCK to SCLK delay (slave mode) LRCK to SCLK setup (slave mode) LRCK to SCLK alignment (master mode) Note: (Note 5) tlrpd tdpd tds tdh tlrckd tlrcks tmslr Fs LRCK, LRCKAUX SCLK, SCLKAUX 10% to 90% points Crystals XTI Symbol tsckw tsckh tsckl Min 80 25 25 32 32 30 30 32 2.048 45 4 500 35 35 -20 Typ 500 50 Max 10 26000 26000 50 3.200 55 50 50 50 35 35 20 Units ns ns ns ns kHz kHz ns ns ps kHz MHz % kHz ns ns ns ns ns ns ns ns 5. After Powering up the CS4225, RST-PDN should be held low for 50 ms to allow the voltage reference to settle. LRCK LRCKAUX (input) t lrckd t lrcks t sckh t sckl SCLK* SCLKAUX* (output) t mslr LRCK LRCKAUX (output) SCLK* SCLKAUX* (input) SDIN1 SDIN2 DATAUX t lrpd SDOUT1 SDOUT2 t ds t dh MSB t sckw t dpd MSB-1 *Active edge of SCLK, SCLKAUX depends on selected format. Audio Ports Master Mode Timing DS86PP8 Audio Ports Slave Mode and Data I/O timing 5 CS4225 SWITCHING CHARACTERISTICS - CONTROL PORT Parameter SPI Mode (H/S=0) CCLK Clock Frequency CS High Time Between Transmissions CS Falling to SCK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN CDIN (Note 9) fsck tcsh tcss tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2 Symbol (TA = 25oC VD+, VA+ = 5V±10%; Inputs: logic 0 = DGND, logic 1 = VD+, CL = 30pF) Min Max Units 0 1.0 20 500 500 250 50 1 MHz µs ns ns ns ns ns 250 25 25 100 100 ns ns ns ns ns Notes: 9. Data must be held for sufficient time to bridge the transition time of CCLK. CS t css CCLK t r2 CDIN t dsu CDOUT t f2 t scl t sch t csh t dh t pd 6 DS86PP8 CS4225 SWITCHING CHARACTERISTICS - CONTROL PORT Parameter I C Mode (H/S = floating) SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup Time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition 2® 2® (TA = 25oC; VD+, VA+ = 5V±10%;Inputs: logic 0 = DGND, logic 1 = VD+, CL = 20pF) Symbol Note 10 fscl tbuf thdst tlow thigh tsust Note 11 thdd tsud tr tf tsusp 4.7 0 4.7 4.0 4.7 4.0 4.7 0 250 1 300 100 kHz µs µs µs µs µs µs ns µs ns µs Min Max Units Notes: 10. Use of the I C bus interface requires a license from Philips. I2C® is a registered trademark of Philips Semiconductors. 11. Data must be held for sufficient time to bridge the 300ns transition time of SCL. Stop SDA t buf Start Repeated Start Stop t hdst t high t hdst tf t susp SCL t low t hdd t sud t sust tr DS86PP8 7 CS4225 ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.) Parameter Power Supplies: Input Current Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Warning: (Power Applied) Digital Analog (Except Supply Pins) Symbol VD VA Min -0.3 -0.3 -0.3 -0.3 -55 -65 Typ Max 6.0 6.0 ±10.0 (VA+)+0.3 (VD+)+0.3 +125 +150 Units V V mA V V °C °C Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS respect to 0V.) Parameter Power Supplies: Operating Ambient Temperature Digital Analog CS4225-KL CS4225-BL CS4225-YU (AGND, DGND = 0V, all voltages with Min 4.6 4.6 0 -40 -40 Typ 5.0 5.0 25 25 25 Max 5.4 5.4 70 +85 +85 Units V V °C °C °C Symbol VD VA TA DIGITAL CHARACTERISTICS (TA = 25°C; VA+, VD+ = 5V) Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage at I0 = -2.0 mA Low-level Output Voltage at I0 = 2.0 mA Input Leakage Current Output Leakage Current (Digital Inputs) (High-Z Digital Outputs) Symbol VIH VIL VOH VOL Min (VD+)-1.0 -0.3 (VD+)-0.3 Typ Max (VD+)+0.3 1.0 0.1 10 10 Units V V V V µA µA 8 DS86PP8 CS4225 F e rrite B ea d + 5V S u pp ly 2.0 + 1 µF 0 .1 µ F + 1 µF 0 .1 µ F 3 T o O p tio na l Inp u t B uffers 23 CMOUT 0.4 7 µ F 19 A IN 1L 1.0 µ F VD 26 VA AOUT1 + 5V A n alo g (o p tio na l) If a se p arate + 5V an alog su pp ly is a va ila ble , atta ch here an d re m ove th e 2.0 re sisto r 27 600 0 .00 22 µ F NPO 600 0 .00 22 µ F NPO + > 1 .8 µ F + 47 k 28 AOUT2 18 A IN 1R 1.0 µ F > 1 .8 µ F 47k 16 A IN 2L 29 AOUT3 600 0 .00 22 µ F NPO 600 0 .00 22 µ F NPO 0 .1 µ F + 1.0 µ F 17 A IN 2R > 1 .8 µ F + 47 k 30 AOUT4 1.0 µ F 15 A IN 3L CS4225 VREF > 1 .8 µ F + 1 0 µF 47 k 24 1.0 µ F 14 A IN 3 R 1.0 µ F 21 CR CL 22 0.01 µ F NPO S C L/C C LK /IF0 S D A /C D O U T/C K F 0 A D 3/C S /IF 1 7 0.0 1 µ F N PO 150 20 A IN A U X 9 10 8 M icroC o ntroller A D 2/C D IN /C K F 1 0 .47 µ F 0 .01 µ F NPO 4 D ig ita l A udio S ource 5 S D IN 1 D A TA U X LRCKAUX SCLKAUX S D IN 2 SDOUT1 SDOUT2 LRCK 43 42 1 6 38 33 44 41 A u dio DSP DIF/HOLD M o de S e ttin g and Hardware C on trols SCLK R S T -P D N C LK O U T 40 36 11 39 37 13 H /S DEM IS 0/A D O IS 1 /A D 1 A G N D 1 ,2 OVL 12 DGND 2 FILT 32 XTO X TI 25 31 35 34 E x tern a l C lo c k Input A ll u n us ed in p uts C1 C2 s h ou ld b e tied to 0 V . A ll N C p in s sh ou ld 0.2 µ F b e le ft floating. Figure 1 - Recommended Connection Diagram DS86PP8 9 CS4225 FUNCTIONAL DESCRIPTION Overview The CS4225 has 2 channels of 16-bit analog-todigital conversion and 4 channels of 16-bit digital-to-analog conversion. An auxiliary 12-bit ADC is also provided. The ADCs and the DACs are delta-sigma type converters. The ADC inputs have adjustable input gain, while the DAC outputs have adjustable output attenuation. Digital audio data for the DACs and from the ADCs is communicated over a serial port. Separate pins for input and output data are provided, allowing concurrent writing to and reading from the device. Control for the functions available on the CS4225 are communicated over a serial microcontroller style interface, or may be set via dedicated mode pins. Figure 1 shows the recommended connection diagram for the CS4225. Analog Inputs Line Level Inputs AIN1R, AIN1L, AIN2R, AIN2L, AIN3R, AIN3L and AINAUX are the line level input pins (See Figure 1). These pins are internally biased to the CMOUT voltage (nominally 2.1V). A 1µF DC blocking capacitor allows signals centered around 0V to be input. Figure 2 shows an optional dual op amp buffer which combines level shifting with a gain of 0.5 to attenuate the standard line level of 2Vrms to 1Vrms. The CMOUT reference level is used to bias the op amps to approximately one half the supply voltage. Series DC blocking capacitors eliminate the contribution of signal offset to the A/D converters. The CS4225 offset calibration scheme yields minimum DC offset values assuming that the inputs are AC coupled (DC blocking capacitor present). If a DC blocking capacitor is not used, a greater DC offset will occur. This offset could be as high as + 70 codes, with no gain. 10 Line In Right 1.0 uF 20 k 56 pF 10 k _ + 1.0 uF AINxR Example Op-Amps are MC34074 5k CMOUT 0.47 uF 0.47 uF 1.0 uF AINxL 10 k Line In Left 1.0 uF 20 k + _ Op-amps are run from VA+ (+5V) and AGND. 56 pF Figure 2 - Optional Line Input Buffer The input pair for the 16-bit ADCs is selected by IS0 and IS1, which are accessible in the Input Selection Byte in software mode or dedicated pins in the hardware mode. Antialiasing filters follow the input mux, providing antialiasing for the input channels. These filters consist of internal resistors and external capacitors attached to the CR and CL pins. The CR and CL capacitors must be low voltage coefficient type, such as NPO. The analog signal is input to the 12-bit ADC via the AINAUX pin. An antialiasing filter of 150Ω with 0.01µF to ground is required (See Figure 1) along with a series DC blocking capacitor. The AINAUX signal is normally routed to the 12-bit ADC. This signal may also be routed to the Left 16-bit ADC (replacing the selected left input), under control of the AIM bit in the 12-bit ADC Mode Byte. In this mode, the input antialiasing filters and gain adjustment operates on the AINAUX signal. Adjustable Input Gain The signals from the line inputs are routed to a programmable gain circuit which provides up to DS86PP8 CS4225 46.5dB of gain in 1.5dB steps. The gain is adjustable only by software control. Level changes only take effect on zero crossings to minimize audible artifacts. If there is no zero crossing, then the requested level change will occur after a time-out of 511 frames (10.6ms at 48kHz frame rate). There is a separate zero crossing detector for each channel. Analog Outputs Line Level Outputs AOUT1, AOUT2, AOUT3 and AOUT4 output a 1Vrms l evel for full scale, centered around +2.1V. Figure 1 shows the recommended 1.0µF dc blocking capacitor with a 40kΩ resistor to ground. When driving impedances greater than 10kΩ, this provides a high pass corner of 20Hz. These outputs may be muted. Output Level Attenuator The DAC outputs are each routed through an attenuator, which is adjustable in 1dB steps. Output attenuation is available via software control only. Level changes are implemented such that the noise is attenuated by the same amount as the signal (equivalent to using an analog attenuator after the signal source), until the residual output noise is equal to the noise floor in the mute state. Level changes only take effect on zero crossings to minimize audible artifacts. If there is no zero crossing, then the requested level change will occur after a time-out of 511 frames (10.6ms at 48kHz frame rate). There is a separate zero crossing detector for each channel. Each output can be independently muted via mute control bits. In addition, the CS4225 has an optional mute on consecutive zeros feature, where each DAC output will mute if it receives 512 consecutive zeros. A single non-zero value will unmute the DAC output. ADC and DAC Coding The CS4225 converters use 2’s complement coding. Table 1 shows the ADC and DAC transfer functions. 16-bit ADC/DAC Input/ Output Voltage* +1.400000 +1.399957 +0.000064 +0.000021 -0.000021 -0.000064 -1.399957 -1.400000 2’s Complement Code 7FFF 7FFE 0001 0000 FFFF FFFE 8001 8000 12-bit ADC 2’s Input Complement Voltage* Code 7FF 7FE 001 000 FFF FFE 801 800 +1.40000 +139864 +0.00204 +0.00068 -0.00068 -0.00204 -1.39864 -1.40000 *Nominal voltage relative to CMOUT (Typ 2.1V), no gain or attenuation. Actual measured voltage will be modified by the gain error and offset error specifications. Table 1 - ADC/DAC Input and Output Coding Table Calibration Both output offset voltage and input offset error are minimized by an internal calibration cycle. At least one calibration cycle must be invoked after power up. A calibration will occur any time the part comes out of reset, including the powerup reset. For the most accurate calibration, some time must be allowed between powering up the CS4225, or exiting the power-down state, and initiating a calibration cycle, to allow the voltage reference to settle. This is achieved by holding RST/PDN low for at least 50ms after power up or exiting power-down mode. Input offset error will be calibrated for all inputs and outputs. A calibration takes 192 frames to complete, based on the frequency of the VCO of the inter11 DS86PP8 CS4225 nal PLL. The calibration that occurs following a reset will proceed at a rate determined by the free running VCO in software mode (which will be at a Fs of about 40kHz), or the selected clock input in hardware mode. The CS4225 can be calibrated whenever desired. A control bit, CAL, in the Control Byte, is provided to initiate a calibration. The sequence is: 1) Set CAL to 1, the CS4225 sets CALD to 1 and begins to calibrate. 2) Wait for CALD to go to 0. CALD will go to 0 when the calibration is done. 3) Set CAL to 0 for normal operation. Clock Generation The master clock to operate the CS4225 may be generated by using the on-chip crystal oscillator, by using the on-chip PLL, or by using an external clock source. If the active clock source stops for 5µs, the CS4225 will enter a power down state to prevent overheating. In all modes it is desirable to have SCLK & LRCK synchronous to the selected master clock. Clock Source The CS4225 requires a high frequency (256 Fs) clock to run the internal logic. The Clock Source bits, CS0/1/2, in the Clock Mode Byte determine the source of the clock. A high frequency crystal can be attached to XTI and XTO, or a high frequency clock can be input into XTI. In both these cases, the internal PLL is disabled, with the VCO shut off. The externally supplied high frequency clock can be 256 Fs, 384 Fs or 512 Fs. The CI0/1 bits in the Clock Mode Byte must be set accordingly. When using the on-chip crystal oscillator, external loading capacitors are required (see Figure 1). High frequency crystals (> 8 MHz) should be parallel resonant, fundamental mode and designed for 20pF loading (equivalent to 40pF to ground on each leg). An example crystal supplier is CAL crystal (714) 991-1580. 12 Alternatively, the on-chip PLL may be used to generate the required high frequency clock. The PLL input clock is either 1 Fs, 32 Fs or 64 Fs and may be input from the Auxiliary Port, (either LRCKAUX or SCLKAUX), the DSP port, (either LRCK or SCLK), or from XTI/XTO. In this last case, a 1 Fs clock may be input into XTI, or a 1 Fs crystal attached across XTI/XTO. The gain of the internal inverter is adjusted for the low crystal frequency. Using a clock at 64 Fs will result in less PLL clock jitter than a clock at 1 Fs. The PLL will lock onto a new 1 Fs clock within 5,000 Fs periods. If the PLL input clock is removed, the VCO will drift to the low frequency end of its frequency range. In software mode, bits CS2/1/0 in the Clock Mode Byte establish the clock source and frequency. In Hardware mode, either LRCKAUX is the clock reference, at 1 Fs, or the clock may be input to XTI. Master Clock Output CLKOUT is a master clock output provided to allow synchronization of external components. Available CLKOUT frequencies of 1 Fs, 256 Fs, 384 Fs, and 512 Fs, are selectable by the CO0/1 bits of the Clock Mode Byte. When switching between clock sources, CLKOUT will always remain low or high for > 10ns. Synchronization In normal operation, the DSP port and Auxiliary port operate synchronously to the CS4225 clock source. It is advisable to mute the DACs when changing from one synchronization source to another to avoid the output of undesirable audio signals as the CS4225 resynchronizes. If data which is not synchronous to the clock source is input to the CS4225, then samples will be dropped or repeated, which will cause audible artifacts. Under such conditions, the CS4225 may not meet all data sheet performance specifications. DS86PP8 CS4225 LRCK Left Right FORMAT 0: SCLK SDIN MSB LSB MSB LSB MSB LRCK Left Right FORMAT 1: SCLK SDIN MSB LSB MSB LSB MSB LRCK Left Right FORMAT 2: SCLK SDIN LSB MSB LSB MSB LSB LRCK Left Right FORMAT 3: SCLK SDIN MSB LSB MSB LSB MSB Figure 3 - Audio DSP and Auxiliary Port Data Input Formats. LRCK Left Right FORMAT 0 SCLK SDOUT MSB LSB MSB LSB MSB FORMAT 1 LRCK SCLK SDOUT MSB Left Right LSB MSB LSB MSB LRCK Left Right FORMAT 2 SCLK SDOUT LSB MSB LSB MSB LSB LRCK Left Right FORMAT 3 SCLK SDOUT MSB LSB MSB LSB MSB Figure 4 - Audio DSP Port Data Output Formats. DS86PP8 13 CS4225 LRCK SCLK SDIN1 MSB LSB MSB LSB MSB LSB MSB LSB MSB DAC #1 SDOUT1 MSB LSB MSB DAC #2 LSB MSB DAC #3 0 MSB DAC #4 0 MSB Left ADC Right ADC AUX ADC 12-Bits 4 0's AUX ADC 12-Bits 4 0's Figure 5 - One data line mode (Format 4) Digital Interfaces There are 3 digital interface ports: the audio DSP port, the auxiliary digital audio port and the control port. In hardware mode (H/S pin high) the control port is disabled, and various modes can be set via pins. In hardware mode, control of the input gain, output level and some modes are not possible. Audio DSP Serial Interface Signals The serial interface clock, SCLK, is used for transmitting and receiving audio data. SCLK can be generated by the CS4225 (master mode) or it can be input from an external SCLK source (slave mode). The number of SCLK cycles in one system sample period is programmable to be 32, 48, or 64. When SCLK is an input, 32 SCLK’s per system sample period is not recommended, due to potential interference effects; 64 SCLK’s per sample period should be used instead. The Left/Right clock (LRCK) is used to indicate left and right data, also the start of a new sample period. It may be output from the CS4225, or it may be generated from an external controller. The frequency of LRCK is equal to the system sample rate, Fs. SDIN1 and SDIN2 are the data input pins, each of which drives a pair of DACs. SDIN1 left data is for DAC #1, SDIN1 right data is for DAC #2, SDIN2 left data is for DAC #3, and SDIN2 right 14 data is for DAC #4. SDOUT1 carries the data from the 2 16-bit ADCs. SDOUT2 carries the data from the 12-bit ADC. The audio DSP port may also be configured so that all 4 DAC’s data is input on SDIN1, and all 3 ADC’s data is output on SDOUT1. Audio DSP Serial Interface Formats The audio DSP port supports 5 alternate formats, shown in Figures 3, 4, and 5. These formats are chosen through the DSP Port Mode Byte in software mode. In hardware mode, four formats are available as selected by the DIF and IF0 pins. The 12-bit ADC data format is similar to the 16bit data format. The 12-bit data is positioned to the most significant end of a 16-bit field, with the lower 4 bits set to zero. The resulting 16-bit value is output on SDOUT2 in both the left and right channel positions. The format will be the same as the selected SDOUT1 format. Figure 5 shows the timing for format 4, where all 4 DAC data words are presented on SDIN1, and the 3 ADC data words are presented on SDOUT1. Format 5 is a combination mode. The data output is as in Format 1, on the SDOUT1 and SDOUT2 pins. The data input is as in Format 4 on SDIN1. In both format 4 and 5, LRCK duty cycle is 50% if it is an output. DS86PP8 CS4225 CS CCLK CHIP ADDRESS CDIN 0 AD1 AD0 R/W MAP MSB DATA LSB 0 CHIP ADDRESS AD1 AD0 R/W byte 1 CDOUT MAP = Memory Address Pointer byte n MSB LSB MSB LSB High Z Figure 6 - Control Port Timing, SPI mode Auxiliary Audio Port Signals The auxiliary port provides an alternate way to input digital audio signals into the CS4225, and allows the CS4225 to synchronize the system to an external digital audio source. This port consists of clock, data and left/right clock pins named, SCLKAUX, DATAAUX and LRCKAUX. These signals are fed through to the SCLK, SDOUT1 and LRCK pins. There is a two frame delay from DATAAUX to SDOUT1. When the auxiliary port is used, the frequency of LRCKAUX must equal to the system sample rate, Fs, but no particular phase relationship is required. Auxiliary Audio Port Formats Input data on DATAAUX is clocked into the part by SCLKAUX using the format selected in the Auxiliary Port Mode Byte. In hardware mode, the auxiliary port format is the same as the DSP port format and is determined by the DIF pin. The auxiliary audio port supports the same 4 formats as the audio DSP port in 2 data line mode. LRCKAUX is used to indicate left and right data samples, and the start of a new sample period. SCLKAUX and LRCKAUX may be output from the CS4225, or they may be generated from an external source, as set by the AMS control bit in Software mode or IF1 in Hardware mode. Control Port Signals The control port has 2 modes: SPI and I2C®, with the CS4225 as a slave device. The SPI mode is selected by setting the H/S pin low. I2C® mode is selected by floating the H/S pin. If the H/S pin is floated, add a 0.1µF capacitor to ground on the H/S pin to minimize noise pickup. SPI Mode In SPI mode, CS is the CS4225 chip select signal, CCLK is the control port bit clock, (input into the CS4225 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller, and AD0 and AD1 form the chip address. The pins AD0, AD1 must be tied to one of 4 possible chip addresses. To write to a particular CS4225, the AD0, AD1 bits must match the state of the AD0, AD1 pins for that chip. This allows up to 4 CS4225 devices to co-exist on one control port bus. Figure 6 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 5 bits on CDIN must be zero. The next 2 bits form the chip address. The eighth bit is a read/write indicator (R/W), which should be 15 DS86PP8 CS4225 Note 1 SDA 001 ADDR AD3-0 R/W ACK DATA 1-8 Note 2 ACK DATA 1-8 ACK SCL Start Note 1: The first 3 address bits for the CS4225 must be 001. Note 2: If operation is a write, this byte contains the Memory Address Pointer, MAP. Stop Figure 7 - Control Port Timing, I2C® Mode low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47kΩ resistor. The CS4225 has a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, then the MAP will stay constant for successive reads or writes. If INCR is set to a 1, then MAP will auto increment after each byte is read or written, allowing block reads or writes of successive registers. To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS high) immediately after the MAP byte. The auto MAP increment bit (INCR) may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear consecutively. I2C ®Mode In I2C® mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 7. There is no CS pin. Pins AD0, AD1, AD2, AD3 form the chip address. The upper 3 bits of the 7 bit address field must be 001. To communicate with a CS4225, the LSBs of the chip address field, which is the first byte sent to the CS4225, should match the settings of the AD0, AD1, AD2, AD3 pins. The eighth bit of the address bit is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the Memory Address Pointer will be output. Setting the auto increment bit in MAP, allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. Use of the I2C bus®compatible interface requires a license from Philips. I2C bus® is a registered trademark of Philips Semiconductors. Control Port Bit Definitions All registers can be written and read back, except the status report byte, which is read only. See the following bit definition tables for bit assignment information. 16 DS86PP8 CS4225 Memory Address Pointer (MAP) B7 INCR B6 0 B5 0 B4 0 B3 B2 B1 B0 MAP3 MAP2 MAP1 MAP0 Auxiliary Port Mode Byte (7) B7 0 B6 0 B5 0 B4 B3 B2 B1 B0 AMS ACK1 ACK0 ADF1 ADF0 ADF1 - ADF0 MAP3-MAP0 Register Function 0 - Reserved 1 - Output Attenuator 1 2 - Output Attenuator 2 3 - Output Attenuator 3 4 - Output Attenuator 4 5 - Input Gain 1 6 - Input Gain 2 7 - Auxiliary Port Mode 8 - DSP Port Mode 9 - Clock Mode 10 - Control Byte 11 - Status Report Byte 12 - Input Channel Select 13 - Aux Control Byte 14 - Reserved 15 - Reserved Auto Increment Control Bit 0 - No auto increment 1 - Auto increment on Sets Digital Interface Format 0 - Format 0 - I2S 1 - Format 1 2 - Format 2 3 - Format 3 ACK1 - ACK0 Sets number of bit clocks per Fs period 0 - 64 1 - 48 - gated 64Fs 2 - 32 - gated 64Fs 3 - 32 - continuous AMS AUX Master /Slave control bit 0 - port is master (SCLKAUX and LRCKAUX are outputs). 1 - port is slave (SCLKAUX and LRCKAUX are inputs). DSP Port Mode Byte (8) B7 0 B6 0 B5 B4 B3 B2 B1 B0 DMS DCK1 DCK0 DDF2 DDF1 DDF0 INCR Output Attenuator Data Byte (1, 2, 3, 4) B7 0 ATT6 to ATT0 B6 B5 B4 B3 B2 B1 B0 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 Sets Attenuator Level 0 - No attenuation 127 - 127 dB attenuation ATT0 represents 1.00 dB Input Gain Setting Data Byte (5, 6) B7 0 GN4 to GN0 B6 0 B5 0 B4 B3 B2 B1 B0 GN4 GN3 GN2 GN1 GN0 Sets Input Gain 0 - No gain 31 - 46.5 dB gain GN0 represents 1.5 dB DDF2 - DDF0 Sets Digital Interface Format 0 - Format 0 - I2S 1 - Format 1 2 - Format 2 3 - Format 3 4 - One data pin in, One data pin out mode (Format 4). 5 - Output is Format 1 on SDOUT1 and SDOUT2, input is Format 4 on SDIN1. DCK1 - DCK0 Set number of bit clocks per Fs period 0 - 64 1 - 48 - gated 64 Fs 2 - 32 - gated 64 Fs 3 - 32 - continuous DMS DSP Master /Slave control bit 0 - port is master (SLCK and LRCK are outputs). 1 - port is slave (SLCK and LRCK are inputs). DS86PP8 17 CS4225 Clock Mode Byte (9) B7 0 B6 B5 CO1 CO0 B4 CI1 B3 CI0 B2 CS2 B1 CS1 B0 CS0 Status Report Byte (11) B7 B6 B5 B4 OVL1 OVL0 OV12 ACK OVL1 to OVL0 B3 0 B2 B1 LOCK CALD B0 0 CS1 - CS0 Sets the source of the master clock which runs the CS4225. 0 - Crystal Oscillator or XTI (PLL Disabled) 1 - PLL driven by LRCKAUX at 1 Fs 2 - PLL driven by LRCK at 1 Fs 3 - PLL driven by XTI/XTO (XTI at 1 Fs) 4 - PLL driven by SCLK at 32 Fs 5 - PLL driven by SCLK at 64 Fs 6 - PLL driven by SCLKAUX at 32 Fs 7 - PLL driven by SCLKAUX at 64 Fs Cl1 - CI0 Determines frequency of XTI when PLL is disabled. 0 - 256 Fs 1 - 384 Fs 2 - 512 Fs 3 - Reserved CO1-CO0 Determines CLKOUT frequency 0 - 256 Fs 1 - 384 Fs 2 - 512 Fs 3 - 1 Fs OV12 ACK LOCK Control Byte (10) B7 B6 B5 B4 B3 B2 B1 B0 MUTC CAL DEMC DEM MUT4 MUT3 MUT2 MUT1 MUT4 to MUT1 DEM Mute Control Bits 0 - Normal Output Level 1 - Selected DAC output muted Selects De-Emphasis 0 - Normal Flat DAC frequency response 1 - CD De-Emphasis Selected Selects De-Emphasis Control Source 0 - De-emphasis is controlled by DEM pin. DEM bit is ignored. 1 - De-emphasis is controlled by DEM bit. DEM pin is ignored. 0 - Normal Operation 1 - Initiate Calibration Controls mute on consecutive zeros function 0 - 512 consecutive zeros will mute DAC 1 - DAC output will not mute on zeros. CALD 16 - bit ADC overload bits. 00 - Normal ADC input levels 01 - -6 dB level 10 - -3 dB level 11 - Clipping Indicates one of the ADC’s has been overdriven. These bits are "sticky". They will stay set until read, when they will return to 00 if the overload is no longer present. 12-bit ADC overload bit 0 - normal input 1 - clipped input This bit is also "sticky" Control port data check bit 0 - Multiple of 8 clocks received last word (SPI Mode) 1 - Error, not multiple of 8 clocks received. PLL lock indicator 0 - PLL not locked. If PLL is selected, DAC outputs will mute 1 - PLL locked 0 - Calibration done 1 - Calibration in progress Input Selection Byte (12) B7 0 IS1 - IS0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 IS1 B0 IS0 DEMC Select input channel 0 - Select AIN1 1 - Select AIN2 2 - Select AIN3 3 - Select Auxiliary Digital Input Port Aux Control Byte (13) B7 AIM AIM B6 0 B5 0 B4 0 B3 0 B2 0 B1 0 B0 0 CAL MUTC Auxiliary Input Mode Control Bit 0 - AINAUX signal is routed to 12-bit ADC 1 - AINAUX routed to AINL of 16-bit ADC 18 DS86PP8 CS4225 Reset RST-PDN going low causes all the internal control registers, used in software mode, to be set to the states indicated in Table 1. The reset states are different for hardware mode, see the section on Hardware Mode. RST-PDN must be brought low and high at least once after power up. RSTPDN returning high causes the CS4225 to execute an offset calibration cycle. RST-PDN returning high should occur at least 50ms after the power supply has stabilized. Power Down Mode Placing the RST-PDN pin into a high impedance state (floating) puts the CS4225 into the power down mode. This may be done by driving the RST-PDN pin with a three-state buffer, and setting the buffer to the hi-z state. In power-down mode CMOUT and VREF will not supply curATT6 → ATT0 GN4 → GN0 ADF1, ADF0 ACK1, ACK0 AMS DDF2 → DDF0 DCK1, DCK1 DMS MAP CAL = = = = = = = = = = 127 0 0 0 1 0 0 1 0 0 CS2, CS1,CS0 CI1, CI0 CO1, CO0 MUT4 →MUT1 DEM DEMC MUTC IS1, IS0 AIM = = = = = = = = = 3 0 0 1111 0 0 0 0 0 De-Emphasis Figure 8 shows the de-emphasis curve. De-emphasis may be enabled under hardware control, using the DEM pin, or by software control using the DEM bit. In software mode, either hardware or software control of de-emphasis may be selected. The de-emphasis corner frequencies are as shown in Figure 8 for a sample rate of 44.1kHz. Selection of de-emphasis at other sample rates will cause the filter to be applied, but with corner frequencies scaled proportionally to the sample rate. Hold Function (Software Mode only) If the digital audio source has an invalid data output pin, then the CS4225 may be configured to cause the last valid analog output level to be held constant. (This sounds much better than a potentially random output level.) HOLD is sampled on the active edge of SCLK. If HOLD is driven high any time during the stereo sample period, both pairs of DAC’s hold their current output level, and reject the data currently being input. SDIN input data is ignored while the HOLD pin is high. For normal operation, the HOLD pin must be low. Gain dB (0.072 Fs) T1=50us* 0dB (0.241 Fs) T2 = 15us* -10dB Table 1 - Reset State (Software Mode) rent. If the master clock source stops, the CS4225 will power down after 5µs. Power down will change all the control registers to the reset state shown in Table 1. After returning to normal operation from power down, an offset calibration cycle must be executed. To leave the power-down state, pull RST-PDN low for at least 50ms to allow the internal voltage reference time to settle, then high to initiate an offset calibration cycle. F1 * with Fs = 44.1 kHz F2 Frequency Figure 8 - De-emphasis Curve. DS86PP8 19 CS4225 Hardware Mode Hardware mode is selected by connecting the H/S pin to VD. In hardware mode, only certain functions are available: - de-emphasis, - digital interface formats 0, 1 and 2, and DSP format 4, - auxiliary audio port master/slave selection, - CLKOUT and XTI frequencies are restricted, - use of PLL is tied to master/slave selection, - the PLL locks to LRCKAUX only, - will mute on consecutive zeros. In addition, the input gain is set to 0dB (no gain), and the attenuator is set to 0dB (no attenuation). The DAC mute bits are set to 0 (not muted). The DSP port and Auxiliary port serial clocks are set to 64 bits per Fs period. In hardware mode, the DSP port is always in slave mode. The IF1 pin selects the Auxiliary port to be master or slave (low for master, high for slave). When the Auxiliary port is a master, XTI is the clock source and the PLL is off. CKF0 and CKF1 pins define both XTI and CLKOUT frequencies as follows: CKF1 0 0 1 1 CKF0 0 1 0 1 XTI 256 Fs 384 Fs 512 Fs 512 Fs CLKOUT 256 Fs 256 Fs 256 Fs 512 Fs Functions only available in software mode include: - input gain adjust & output level adjust, - digital interface format 3, DSP format 5, - more clocking flexibility, - DAC muting, - setting of number of bit clocks per Fs period, - turn off mute upon consecutive zeros function, - 12-bit ADC clipping indicator, - PLL lock flag, - routing the AINAUX signal to a 16-bit ADC, - hold last sample on error. Power Supply and Grounding The CS4225, along with associated analog circuitry, should be positioned near to the edge of your circuit board, and have its own, separate, ground plane (see Figure 9). Preferably, it should also have its own power plane. The +5V supply must be connected to the CS4225 via a ferrite bead, positioned closer than 1" to the device. A single connection between the CS4225 ground and the board ground should be positioned as shown in Figure 9. Figure 10 shows the recommended decoupling capacitor layout. Also see Crystal’s layout Applications Note, and the CDB4225 evaluation board data sheet for recommended layout of the decoupling components. The CS4225 will mute the analog outputs if the supply drops below approximately 4 volts. ADC and DAC Filter Response Plots When the Auxiliary port is a slave, LRCKAUX is the clock source at 1 Fs, the PLL is enabled. CKF1 and CKF0 determine CLKOUT as follows: CKF1 0 0 1 1 CKF0 0 1 0 1 CLKOUT 256 Fs 384 Fs 512 Fs 1 Fs Figures 11 through 18 show the overall frequency response, passband ripple and transition band for the CS4225 ADC’s and DAC’s. Figure 17 shows the DAC’s deviation from linear phase. The 12-bit ADC output is fully decimated to Fs, but is not filtered. Figure 18 shows the noise floor of the output, along with a low frequency full scale signal. External digital filtering is necessary to achieve the desired trade off between measurement bandwidth and dynamic range. DS86PP8 20 CS4225 > 1/8" Digital Ground Plane +5V Ferrite Bead Analog Ground Plane Note that the CS4225 is oriented with its digital pins towards the digital end of the board. CS4225 Ground Connection CPU & Digital Logic Codec digital signals Codec analog signals & components Figure 9. Suggested Layout Guideline Digital Supply 1.0 uF 0.1 uF 1 Digital Supply 0.1 uF 1.0 uF 1 = vias through to ground plane FILT 0.2 uF = vias through to ground plane FILT 0.2 uF Analog Supply 0.1 uF 1.0 uF 0.1 uF 1.0 uF 0.1 uF Analog Supply 1.0 uF 0.1 uF 1.0 uF Figure 10. Recommended Decoupling Capacitor Layout DS86PP8 21 CS4225 10 0 -10 -20 Magnitude (dB) Magnitude (dB) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Input Frequency (Fs) 0.8 0.9 1.0 -30 -40 -50 -60 -70 -80 -90 -100 0.0 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Input Frequency (Fs) 0.8 0.9 1.0 Figure 11. 16-bit ADC Filter Response. 0.2 0.1 -0.0 -0.1 Magnitude (dB) -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency (Fs) Magnitude (dB) 0.2 0.1 -0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 Figure 14. DAC Frequency Response. 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency (Fs) Figure 12. 16-bit ADC Passband Ripple. Figure 15. DAC Passband Ripple. 0 -10 -20 -30 Magnitude (dB) -40 -50 -60 -70 -80 -90 -100 0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70 Input Frequency (Fs) Magnitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Input Frequency (Fs) Figure 13. 16-bit ADC Transition Band. 22 Figure 16. DAC Transition Band. DS86PP8 CS4225 2.5 2.0 1.5 1.0 Phase (degree) 0.5 -0.0 -0.5 -1.0 -1.5 -2.0 -2.5 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency (Fs) Figure 17. DAC Phase Response. 0.00 -15.00 -30.00 -45.00 Magnitude (dB) -60.00 -75.00 -90.00 -105.00 -120.00 -135.00 -150.00 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency (Fs) Figure 18. 12-bit ADC Noise with a Low Frequency Full Scale Sine wave input signal. DS86PP8 23 CS4225 PIN DESCRIPTIONS SDOUT1 DGND VD DATAUX LRCKAUX SCLKAUX CCLK IF0 CDIN CKF1 CDOUT CKF0 CS IF1 OVL AD1 IS1 AD0 IS0 AIN3R AIN3L AIN2L AIN2R AIN1R AIN1L AINAUX CR CL SCL AD2 SDA AD3 AD1 AD0 7 8 9 10 11 12 13 14 15 16 17 6 4 2 1 44 42 40 top view 39 38 37 36 35 34 33 32 31 30 29 18 20 22 24 26 28 SDOUT2 SDIN1 SDIN2 LRCK SCLK H/S DIF HOLD DEM CLKOUT XTO XTI RST-PDN FILT AGND2 AOUT4 AOUT3 AOUT2 AOUT1 VA AGND1 VREF CMOUT Power Supply VA - Analog Power Input +5 V analog supply. AGND1, AGND2 - Analog Ground Analog grounds. VD - Digital Power Input + 5 V digital supply. DGND - Digital Ground Digital ground. Analog Inputs AIN1L, AIN1R - Left and Right Channel Mux Input 1 Analog signal input connections for the right and left channels for multiplexer input 1. 24 DS86PP8 CS4225 AIN2L, AIN2R - Left and Right Channel Mux Input 2 Analog signal input connections for the right and left channels for multiplexer input 2. AIN3L, AIN3R - Left and Right Channel Mux Input 3 Analog signal input connections for the right and left channels for multiplexer input 3. AINAUX - Auxiliary Line Level Input Analog signal input for the 12-bit A/D converter. In software mode, setting the AIM bit causes AINAUX to replace the left analog input at the multiplexer input. Analog Outputs AOUT1, AOUT2, AOUT3, AOUT4 - Audio Outputs The analog outputs from the 4 D/A converters. Each output can be independently controlled for output amplitude. CMOUT - Common Mode Output This common mode voltage output may be used for level shifting when DC coupling is desired. The load on CMOUT must be DC only, with an impedance of not less than 25kΩ. CMOUT should be bypassed with a 0.47µF to AGND. VREF - Voltage Reference Output, Pin 21 The on-chip generated ADC/DAC reference voltage is brought out to this pin for decoupling purposes. This output must be bypassed with a 10µF capacitor in parallel with a 0.1µF capacitor to the adjacent AGND pin. No other external load may be connected to this output. Digital Interface Signals SDIN1 - Serial Data Input 1 Digital audio data for the DACs 1 and 2 is presented to the CS4225 on this pin. SDIN2 - Serial Data Input 2 Digital audio data for the DACs 3 and 4 is presented to the CS4225 on this pin. SDOUT1- Serial Data Output 1 Digital audio data from the 16-bit audio ADCs is output from this pin. When selected, DATAAUX is output on SDOUT1. SDOUT2 - Serial Data Output 2 Digital audio data from the 12-bit audio ADC is output from this pin. SCLK - DSP Serial Port Clock I/O SCLK clocks digital audio data into the DACs via SDIN1/2, and clocks data out of the ADCs on SDOUT1/2. Active clock edge depends on the selected format. DS86PP8 25 CS4225 LRCK - Left/Right Select Signal I/O The Left/Right select signal. This signal has a frequency equal to the sample rate. The relationship of LRCK to the left and right channel data depends on the selected format. RST-PDN - Reset and Power-Down Input The CS4225 must be reset after power up by bringing this pin low, then high. To select power down mode, float this pin, or drive this pin with a three-state buffer, and place the buffer in the Hi-Z state. Low-to-high rise time should be less than 10µs. DEM - De-emphasis Control When high, DEM causes the standard Compact Disk de-emphasis frequency response for Fs = 44.1kHz to be applied to the DACs. If H/S is high, this pin is active. If H/S is low, then this pin is enabled by setting the DEMC control bit to 0, and disabled by setting the DEMC control bit to 1. HOLD/DIF - Digital Interface Format Select Pin / HOLD Control In software mode, when HOLD is high any time during the sample period, SDIN1 and SDIN2 data is ignored, and the previous "good" sample is presented to the DACs. In hardware mode, DIF becomes a selection pin which selects audio data I/O formats 0, 1 and 2 (when IF0 is low) using a 3-level selection. Low selects format 0. High selects format 1. Floating selects format 2. Float DIF by tying a 0.01µF capacitor from DIF to ground. In hardware mode, both the auxiliary audio data port and the audio DSP port are set to the same audio format. SCL/CCLK/IF0 - Serial Control Interface Clock / DSP Interface Mode Select. In software control mode, SCL/CCLK is the serial control interface clock, and is used to clock control bits into and out of the CS4225. In hardware control mode, when IF0 is low, the data for DACs 1 and 2 is input on SDIN1, and for DACs 3 and 4 is input on SDIN2. The data from the audio ADCs is presented on SDOUT1 and the data from the 12-bit auxiliary ADC is presented on SDOUT2. In hardware control mode, when IF0 is high, the data for all 4 DACs is input on the SDIN1 pin, and the data from the audio ADCs and the 12-bit auxiliary ADC is output on the SDOUT1 pin. This mode allows a DSP which has only 1 serial input and 1 serial output port to access all the DACs and ADCs. AD3/CS/IF1 - Control Port Chip Select / Interface Control In I2C® software control mode, AD3 is a chip address bit. In SPI software control mode, CS is used to enable the control port interface on the CS4225. In hardware control mode, IF1 low sets the auxiliary digital audio input port to be master and IF1 high sets the auxiliary digital audio input port to be slave. In slave mode, the PLL is used to generate the internal 256 Fs clock from LRCKAUX, and to generate CLKOUT. AD2/CDIN/CKF1 - Serial Control Data In / Interface Control In I2C® mode, AD2 is a chip address bit. In SPI software control mode, CDIN is the input data line for the control port interface. In hardware control mode, CKF0 and CKF1 controls the clock frequency of CLKOUT. 26 DS86PP8 CS4225 SDA/CDOUT/CKF0 - Serial Control Data Out / Clock Select In I2C® mode, SDA is the control data I/O line. In SPI software control mode, CDOUT is the output data from the control port interface on the CS4225. In hardware control mode, CKF0 and CKF1 controls the clock frequency of CLKOUT. DATAUX - Auxiliary Data Input DATAUX is the auxiliary audio data input line, usually connected to an external digital audio source. LRCKAUX - Auxiliary Word Clock Input or Output In auxiliary slave mode, LRCKAUX is a word clock (at Fs) from an external digital audio source. LRCKAUX can be used as the clock reference for the internal PLL. In auxiliary master mode, LRCKAUX is a word clock output (at Fs) to clock an external digital audio source. SCLKAUX - Auxiliary Bit Clock Input or Output In auxiliary slave mode, SCLKAUX is the serial data bit clock from an external digital audio source, used to clock in data on DATAAUX. SCLKAUX can be used as the clock reference for the internal PLL. In auxiliary master mode, SCLKAUX is a serial data bit clock output. AD0/IS0, AD1/IS1 - Input Select Control Pins In software mode, these pins are part of the chip address. In hardware mode, IS0 and IS1 select the audio input source from between 4 pairs of signals (AIN1, AIN2 and AIN3) and DATAUX. H/S - Hardware or Software Control Setting H/S high puts the CS4225 into hardware control mode, where many functions are controlled by dedicated pins. When H/S is low, many chip functions are controlled via the control port in SPI mode. When H/S is open circuit, then software mode I2C® protocol is selected for the control port. When floating H/S, a 100pF capacitor should be connected from the H/S pin to ground, to reduce the possibility of external interference influencing the pin. OVL - Overload Indicator If either of the 2 16-bit audio ADCs, or the 12-bit ADC, is clipped, then this pin goes high. Clock and Crystal Pins XTI, XTO - Crystal connections Input and output connections for the crystal which may be used to operate the CS4225. Alternatively, a clock may be input into XTI. CLKOUT - Master Clock Output CLKOUT allows external circuits to be synchronized to the CS4225. Alternate output frequencies are selectable by the control port or via hardware pins. DS86PP8 27 CS4225 Miscellaneous Pins FILT - PLL Loop Filter Pin A 0.22 µF capacitor should be connected from FILT to AGND. PARAMETER DEFINITIONS Resolution The number of bits in the input words to the DACs, and in the output words in the ADCs. Differential Nonlinearity The worst case deviation from the ideal codewidth; expressed in LSBs. Total Dynamic Range The ratio between the DAC full scale output and the noise floor with the DAC muted. Units are in dB. Total Harmonic Distortion + Noise (THD+N) THD+N is the ratio of the rms value of the input signal to the rms sum of all other spectral components within the measurement bandwidth (10Hz to 20kHz). THD+N is expressed in dB. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. Instantaneous Dynamic Range The S/(N+D) with a 1kHz, -60dB input signal, with 60dB added to compensate for the small input signal. Use of a small input signal reduces the harmonic distortion components of the noise to insignificance. Units are in dB. Interchannel Isolation The amount of 1kHz signal present on the output of the grounded input channel with 1kHz, 0dB signal present on the other channel. Units are in dB. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in dB. Frequency Response Worst case variation in output signal level versus frequency over 10Hz to 20kHz. Units in dB. Offset Error For the ADCs, the deviation in LSB’s of the output from mid-scale with the selected input grounded. For the DAC’s, the deviation of the output from zero with mid-scale input code. Units are in volts. 28 DS86PP8 44 pin PLCC NO. OF TERMINALS E1 E MILLIMETERS INCHES DIM MIN NOM MAX 4.20 2.29 0.33 4.45 2.79 0.41 MIN NOM MAX A A1 B 4.57 0.165 0.175 0.180 3.04 0.090 0.110 0.120 0.53 0.013 0.016 0.021 D/E 17.40 17.53 17.65 0.685 0.690 0.695 D1 D D1/E1 16.51 16.59 16.66 0.650 0.653 0.656 D2/E2 14.99 15.50 16.00 0.590 0.610 0.630 e 1.19 1.27 1.35 0.047 0.050 0.053 B e A1 D2/E2 A