CDB42448

CS42448 108 dB, 192 kHz 6-In, 8-Out CODEC FEATURES Six 24-bit A/D, Eight 24-bit D/A Converters ADC Dynamic Range – 105 dB Differential – 102 dB Single-Ended DAC Dynamic Range – 108 dB Differential – 105 dB Single-Ended ADC/DAC THD+N – -98 dB Differential – -95 dB Single-Ended Compatible with Industry-Standard Time Division Multiplexed (TDM) Serial Interface System Sampling Rates up to 192 kHz Programmable ADC High-Pass Filter for DC Offset Calibration Logarithmic Digital Volume Control I²C® & SPI™ Host Control Port Supports Logic Levels Between 5 V and 1.8 V Popguard® Technology Control Port & Serial Audio Port Supply = 1.8 V to 5 V GENERAL DESCRIPTION The CS42448 CODEC provides six multi-bit analog-todigital and eight multi-bit digital-to-analog delta-sigma converters. The CODEC is capable of operation with either differential or single-ended inputs and outputs, in a 64-pin LQFP package. Six fully differential, or single-ended, inputs are available on stereo ADC1, ADC2, and ADC3. When operating in Single-ended Mode, an internal MUX before ADC3 allows selection from up to four single-ended inputs. Digital volume control is provided for each ADC channel, with selectable overflow detection. All eight DAC channels provide digital volume control and can operate with differential or single-ended outputs. An auxiliary serial input is available for an additional two channels of PCM data. The CS42448 is available in a 64-pin LQFP package in Commercial (-10° to +70°) and Automotive (-40° to +105°) grades. The CDB42448 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 64 for complete ordering information. The CS42448 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and automotive audio systems. Digital Supply = 3.3 V to 5 V Analog Supply = 3.3 V to 5 V Level Translator I2C/SPI Software Mode Control Data Interrupt Reset Register Configuration ADC Overflow & Clock Error Interrupt Internal Voltage Reference External Mute Control Mute Control PCM or TDM Serial Interface Serial Audio Input Level Translator Auxilliary Serial Audio Input Input Master Clock Serial Audio Output Volume Controls Digital Filters ΔΣ Modulators Multibit DAC1-4 and Analog Filters 8 8 Differential or Single-Ended Outputs High Pass Filter Digital Filters Multibit Oversampling ADC1&2 Multibit Oversampling ADC3 4:2* 4 4 High Pass Filter Digital Filters 2 2 Differential or Single-Ended Analog Inputs *Optional MUX allows selection from up to 4 single-ended inputs. http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) NOVEMBER '06 DS648F2 CS42448 TABLE OF CONTENTS 1. PIN DESCRIPTIONS .................................................................................................................... 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. TYPICAL CONNECTION DIAGRAM ............................................................................................. 9 3. CHARACTERISTICS AND SPECIFICATIONS..................................................................................... 10 RECOMMENDED OPERATING CONDITIONS ................................................................................... 10 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 10 ANALOG INPUT CHARACTERISTICS (COMMERCIAL) .................................................................... 11 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE) ..................................................................... 12 ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 13 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL) ................................................................ 14 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE) ................................................................. 15 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 17 SWITCHING SPECIFICATIONS - ADC/DAC PORT ............................................................................ 18 SWITCHING CHARACTERISTICS - AUX PORT ................................................................................. 20 SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE ....................................................... 21 SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT ................................................. 22 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 23 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 23 4. APPLICATIONS .................................................................................................................................... 24 4.1 Overview ......................................................................................................................................... 24 4.2 Analog Inputs .................................................................................................................................. 24 4.2.1 Line-Level Inputs ................................................................................................................... 24 4.2.2 ADC3 Analog Input ................................................................................................................ 25 4.2.3 High-Pass Filter and DC Offset Calibration ........................................................................... 26 4.3 Analog Outputs ............................................................................................................................... 26 4.3.1 Initialization ............................................................................................................................ 26 4.3.2 Output Transient Control ....................................................................................................... 28 4.3.3 Popguard ............................................................................................................................... 28 4.3.3.1 Power-Up ................................................................................................................... 28 4.3.3.2 Power-Down .............................................................................................................. 28 4.3.4 Mute Control .......................................................................................................................... 28 4.3.5 Line-Level Outputs and Filtering ............................................................................................ 29 4.3.6 Digital Volume Control ........................................................................................................... 29 4.3.7 De-Emphasis Filter ................................................................................................................ 29 4.4 System Clocking ............................................................................................................................. 30 4.5 CODEC Digital Interface Formats ................................................................................................... 31 4.5.1 I²S .......................................................................................................................................... 32 4.5.2 Left-Justified .......................................................................................................................... 32 4.5.3 Right-Justified ........................................................................................................................ 32 4.5.4 OLM #1 .................................................................................................................................. 32 4.5.5 OLM #2 .................................................................................................................................. 33 4.5.6 TDM ....................................................................................................................................... 33 4.5.7 I/O Channel Allocation ........................................................................................................... 34 4.6 AUX Port Digital Interface Formats ................................................................................................. 34 4.6.1 I²S .......................................................................................................................................... 34 4.6.2 Left-Justified .......................................................................................................................... 34 4.7 Control Port Description and Timing ............................................................................................... 35 4.7.1 SPI Mode ............................................................................................................................... 35 4.7.2 I²C Mode ................................................................................................................................ 36 4.8 Interrupts ......................................................................................................................................... 37 4.9 Recommended Power-Up Sequence ............................................................................................. 37 4.10 Reset and Power-Up .................................................................................................................... 38 2 DS648F2 CS42448 4.11 Power Supply, Grounding, and PCB Layout ................................................................................. 38 5. REGISTER QUICK REFERENCE ......................................................................................................... 39 6. REGISTER DESCRIPTION ................................................................................................................... 41 6.1 Memory Address Pointer (MAP) ..................................................................................................... 41 6.1.1 Increment (INCR) .................................................................................................................. 41 6.1.2 Memory Address Pointer (MAP[6:0]) ..................................................................................... 41 6.2 Chip I.D. and Revision Register (Address 01h) (Read Only) .......................................................... 41 6.2.1 Chip I.D. (CHIP_ID[3:0]) ........................................................................................................ 41 6.2.2 Chip Revision (REV_ID[3:0]) ................................................................................................. 41 6.3 Power Control (Address 02h) ......................................................................................................... 42 6.3.1 Power Down ADC Pairs (PDN_ADCX) ................................................................................. 42 6.3.2 Power Down DAC Pairs (PDN_DACX) ................................................................................. 42 6.3.3 Power Down (PDN) ............................................................................................................... 42 6.4 Functional Mode (Address 03h) ...................................................................................................... 43 6.4.1 DAC Functional Mode (DAC_FM[1:0]) .................................................................................. 43 6.4.2 ADC Functional Mode (ADC_FM[1:0]) .................................................................................. 43 6.4.3 MCLK Frequency (MFREQ[2:0]) ........................................................................................... 43 6.5 Interface Formats (Address 04h) .................................................................................................... 44 6.5.1 Freeze Controls (FREEZE) ................................................................................................... 44 6.5.2 Auxiliary Digital Interface Format (AUX_DIF) ........................................................................ 44 6.5.3 DAC Digital Interface Format (DAC_DIF[2:0]) ....................................................................... 44 6.5.4 ADC Digital Interface Format (ADC_DIF[2:0]) ....................................................................... 45 6.6 ADC Control & DAC De-Emphasis (Address 05h) ......................................................................... 45 6.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) .................................................. 45 6.6.2 ADC3 High Pass Filter Freeze (ADC3_HPF FREEZE) ......................................................... 46 6.6.3 DAC De-Emphasis Control (DAC_DEM) ............................................................................... 46 6.6.4 ADC1 Single-Ended Mode (ADC1 SINGLE) ......................................................................... 46 6.6.5 ADC2 Single-Ended Mode (ADC2 SINGLE) ......................................................................... 46 6.6.6 ADC3 Single-Ended Mode (ADC3 SINGLE) ......................................................................... 47 6.6.7 Analog Input Ch. 5 Multiplexer (AIN5_MUX) ......................................................................... 47 6.6.8 Analog Input Ch. 6 Multiplexer (AIN6_MUX) ......................................................................... 47 6.7 Transition Control (Address 06h) .................................................................................................... 47 6.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) .................................................... 47 6.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0]) .................................. 48 6.7.3 Auto-Mute (AMUTE) .............................................................................................................. 48 6.7.4 Mute ADC Serial Port (MUTE ADC_SP) ............................................................................... 49 6.8 DAC Channel Mute (Address 07h) ................................................................................................. 49 6.8.1 Independent Channel Mute (AOUTX_MUTE) ....................................................................... 49 6.9 AOUTX Volume Control (Addresses 08h- 0Fh) .......................................................................... 49 6.9.1 Volume Control (AOUTX_VOL[7:0]) ...................................................................................... 49 6.10 DAC Channel Invert (Address 10h) .............................................................................................. 50 6.10.1 Invert Signal Polarity (INV_AOUTX) .................................................................................... 50 6.11 AINX Volume Control (Address 11h-16h) ..................................................................................... 50 6.11.1 AINX Volume Control (AINX_VOL[7:0]) .............................................................................. 50 6.12 ADC Channel Invert (Address 17h) .............................................................................................. 50 6.12.1 Invert Signal Polarity (INV_AINX) ........................................................................................ 50 6.13 When enabled, these bits will invert the signal polarity of their respective channels.Status Control (Address 18h) ....................................................................................................................................... 51 6.13.1 Interrupt Pin Control (INT[1:0]) ............................................................................................ 51 6.14 Status (Address 19h) (Read Only) ................................................................................................ 51 6.14.1 DAC CLOCK ERROR (DAC_CLK ERROR) ........................................................................ 51 6.14.2 ADC CLOCK ERROR (ADC_CLK ERROR) ........................................................................ 51 6.14.3 ADC Overflow (ADCX_OVFL) ............................................................................................. 51 6.15 Status Mask (Address 1Ah) .......................................................................................................... 52 DS648F2 3 CS42448 6.16 MUTEC Pin Control (Address 1Bh) .............................................................................................. 52 6.17 MUTEC Polarity Select (MCPOLARITY) ...................................................................................... 52 6.18 MUTE CONTROL ACTIVE (MUTEC ACTIVE) ............................................................................. 52 7. EXTERNAL FILTERS............................................................................................................................ 53 7.1 ADC Input Filter .............................................................................................................................. 53 7.1.1 Passive Input Filter ................................................................................................................ 54 7.1.2 Passive Input Filter w/Attenuation ......................................................................................... 54 7.2 DAC Output Filter ........................................................................................................................... 56 8. ADC FILTER PLOTS............................................................................................................................. 57 9. DAC FILTER PLOTS............................................................................................................................. 59 10. PARAMETER DEFINITIONS............................................................................................................... 61 11. REFERENCES..................................................................................................................................... 62 12. PACKAGE INFORMATION................................................................................................................. 63 12.1 Thermal Characteristics ............................................................................................................... 63 13. ORDERING INFORMATION ............................................................................................................... 64 14. REVISION HISTORY ........................................................................................................................... 64 LIST OF FIGURES Figure 1.Typical Connection Diagram ......................................................................................................... 9 Figure 2.Output Test Circuit for Maximum Load ....................................................................................... 16 Figure 3.Maximum Loading ....................................................................................................................... 16 Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 18 Figure 5.TDM Serial Audio Interface Timing ............................................................................................. 18 Figure 6.Serial Audio Interface Master Mode Timing ................................................................................ 19 Figure 7.Serial Audio Interface Slave Mode Timing .................................................................................. 20 Figure 8.Control Port Timing - I²C Format ................................................................................................. 21 Figure 9.Control Port Timing - SPI Format ................................................................................................ 22 Figure 10.Full-Scale Input ......................................................................................................................... 25 Figure 11.ADC3 Input Topology ................................................................................................................ 25 Figure 12.Audio Output Initialization Flow Chart ....................................................................................... 27 Figure 13.Full-Scale Output ...................................................................................................................... 29 Figure 14.De-Emphasis Curve .................................................................................................................. 30 Figure 15.I²S Format ................................................................................................................................. 32 Figure 16.Left Justified Format ................................................................................................................. 32 Figure 17.Right Justified Format ............................................................................................................... 32 Figure 18.One-Line Mode #1 Format ........................................................................................................ 32 Figure 19.One Line Mode #2 Format ........................................................................................................ 33 Figure 20.TDM Format .............................................................................................................................. 33 Figure 21.AUX I²S Format ......................................................................................................................... 34 Figure 22.AUX Left-Justified Format ......................................................................................................... 35 Figure 23.Control Port Timing in SPI Mode .............................................................................................. 36 Figure 24.Control Port Timing, I²C Write ................................................................................................... 36 Figure 25.Control Port Timing, I²C Read ................................................................................................... 37 Figure 26.Single to Differential Active Input Filter ..................................................................................... 53 Figure 27.Single-Ended Active Input Filter ................................................................................................ 53 Figure 28.Passive Input Filter ................................................................................................................... 54 Figure 29.Passive Input Filter w/Attenuation ............................................................................................. 55 Figure 30.Active Analog Output Filter ....................................................................................................... 56 Figure 31.Passive Analog Output Filter .................................................................................................... 56 Figure 32.SSM Stopband Rejection .......................................................................................................... 57 Figure 33.SSM Transition Band ................................................................................................................ 57 Figure 34.SSM Transition Band (Detail) ................................................................................................... 57 Figure 35.SSM Passband Ripple .............................................................................................................. 57 4 DS648F2 CS42448 Figure 36.DSM Stopband Rejection .......................................................................................................... 57 Figure 37.DSM Transition Band ................................................................................................................ 57 Figure 38.DSM Transition Band (Detail) ................................................................................................... 58 Figure 39.DSM Passband Ripple .............................................................................................................. 58 Figure 40.QSM Stopband Rejection ......................................................................................................... 58 Figure 41.QSM Transition Band ................................................................................................................ 58 Figure 42.QSM Transition Band (Detail) ................................................................................................... 58 Figure 43.QSM Passband Ripple .............................................................................................................. 58 Figure 44.SSM Stopband Rejection .......................................................................................................... 59 Figure 45.SSM Transition Band ................................................................................................................ 59 Figure 46.SSM Transition Band (detail) .................................................................................................... 59 Figure 47.SSM Passband Ripple .............................................................................................................. 59 Figure 48.DSM Stopband Rejection .......................................................................................................... 59 Figure 49.DSM Transition Band ................................................................................................................ 59 Figure 50.DSM Transition Band (detail) .................................................................................................... 60 Figure 51.DSM Passband Ripple .............................................................................................................. 60 Figure 52.QSM Stopband Rejection ......................................................................................................... 60 Figure 53.QSM Transition Band ................................................................................................................ 60 Figure 54.QSM Transition Band (detail) .................................................................................................... 60 Figure 55.QSM Passband Ripple .............................................................................................................. 60 LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Single-Speed Mode Common Frequencies ................................................................................ 30 Table 3. Double-Speed Mode Common Frequencies ............................................................................... 30 Table 4. Quad-Speed Mode Common Frequencies ................................................................................. 30 Table 5. I²S, LJ, RJ Clock Ratios .............................................................................................................. 31 Table 6. OLM#1 Clock Ratios ................................................................................................................... 31 Table 7. OLM#2 Clock Ratios ................................................................................................................... 31 Table 8. TDM Clock Ratios ....................................................................................................................... 31 Table 9. Serial Audio Interface Channel Allocations ................................................................................. 34 Table 10. MCLK Frequency Settings for I²S, Left and Right Justified Interface Formats .......................... 43 Table 12. DAC Digital Interface Formats .................................................................................................. 44 Table 11. MCLK Frequency Settings for TDM & OLM Interface Formats ................................................. 44 Table 13. ADC Digital Interface Formats .................................................................................................. 45 Table 14. Example AOUT Volume Settings .............................................................................................. 49 Table 15. Example AIN Volume Settings .................................................................................................. 50 DS648F2 5 CS42448 1. PIN DESCRIPTIONS AIN6+/AIN6A SDA/CDOUT AIN5+/AIN5A AIN6-/AIN6B AIN5-/AIN5B FILT+_ADC AGND FILT+_DAC SCL/CCLK DGND AIN4+ AIN3+ AIN4- INT 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AD0/CS AD1/CDIN RST VLC ADC_LRCK VD DGND VLS ADC_SCLK MCLK ADC_SDOUT3 ADC_SDOUT2 ADC_SDOUT1 DAC_SDIN4 DAC_SDIN3 DAC_SDIN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DAC_SDIN1 DAC_LRCK DAC_SCLK AOUT1+ AOUT2+ AOUT3+ AUX_LRCK AUX_SCLK AUX_SDIN AOUT4+ DGND VD AOUT1AOUT2AOUT3AOUT448 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AIN2+ AIN2AIN1+ AIN1VA VQ AGND AOUT8AOUT8+ AOUT7+ AOUT7AOUT6AOUT6+ MUTEC AOUT5+ AOUT5- 42448 Pin Name AD0/CS AD1/CDIN RST VLC ADC_LRCK VD DGND VLS ADC_SCLK MCLK ADC_SDOUT1 ADC_SDOUT2 ADC_SDOUT3 # 1 2 3 4 5 Pin Description Address Bit [0]/ Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select the chip in SPI Mode. Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I²C Mode. Input for SPI data. Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. Control Port Power (Input) - Determines the required signal level for the control port. See “Digital I/O Pin Characteristics” on page 8. ADC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the ADC serial audio data line. Signals the start of a new TDM frame in the TDM digital interface format. 6, 24 Digital Power (Input) - Positive terminal of the power supply for the digital section. 7, 23, Digital Ground (Input) - Ground terminal of the power supply for the digital section. 62 8 9 10 13 12 11 Serial Port Interface Power (Input) - Determines the required signal level for the serial interfaces. See “Digital I/O Pin Characteristics” on page 8. ADC Serial Clock (Input/Output) - Serial clock for the ADC serial audio interface. Input frequency must be 256xFs in the TDM digital interface format. Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters. Serial Audio Data Output (Output) - Outputs for two’s complement serial audio data. 6 VA AIN3- DS648F2 CS42448 DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 DAC_SCLK DAC_LRCK AUX_LRCK AUX_SCLK AUX_SDIN AOUT1 +,AOUT2 +,AOUT3 +,AOUT4 +,AOUT5 +,AOUT6 +,AOUT7 +,AOUT8 +,AGND VQ VA AIN1 +,AIN2 +,AIN3 +,AIN4 +,AIN5 +,AIN6 +,AIN5 A,B AIN6 A,B MUTEC FILT+_DAC FILT+_ADC INT SCL/CCLK SDA/CDOUT 17 16 15 14 18 19 20 21 22 DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data. DAC Serial Clock (Input/Output) - Serial clock for the DAC serial audio interface. Input frequency must be 256xFs in the TDM digital interface format. DAC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the DAC serial audio data line. Signals the start of a new TDM frame in the TDM digital interface format. Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line. Derived from the ADC serial port and equals Fs. Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. Auxiliary Serial Input (Input) - Provides an additional serial input for two’s complement serial audio data. Used only in the TDM digital interface format. 26,25 27,28 30,29 31,32 Differential Analog Output (Output) - The full-scale analog output level is specified in the Analog 34,33 Characteristics table. Each leg of the differential outputs may also be used single-ended. 36,37 39,38 40,41 42,56 Analog Ground (Input) - Ground reference for the analog section 43 44,53 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. Analog Power (Input) - Positive power supply for the analog section. See “Digital I/O Pin Characteristics” on page 8. 46,45 48,47 Differential Analog Input (Input) - Signals are presented differentially or single-ended to the 50,49 delta-sigma modulators. The full-scale input level is specified in the Analog Characteristics speci52,51 fication table. See below for a description of AIN5-AIN6 in Single-Ended Mode. 58,57 60,59 Single-Ended Analog Input (Input) - When stereo ADC3 is in Single-Ended Mode, an internal 58,57 analog mux allows selection between 2 channels for both analog inputs AIN5 and AIN6 (see Sec60,59 tion 4.2.3 on page 26 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics table. 35 54 55 61 63 64 Mute Control (Output) - Used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits of the DAC. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits of the ADC. Interrupt (Output) - Signals either an ADC overflow condition has occurred in one or more of the ADC inputs, or a clocking error has occurred in the DAC/ADC as specified in the Interrupt register. Serial Control Port Clock (Input) - Serial clock for the control port interface. Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Output for SPI data. DS648F2 7 CS42448 1.1 Digital I/O Pin Characteristics Various pins on the CS42448 are powered from separate power supply rails. The logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings. Power Rail VLC Pin Name RST SCL/CCLK SDA/CDOUT AD0/CS AD1/CDIN INT I/O Input Input Input/ Output Input Input Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Output Output Input Output Driver 1.8 V - 5.0 V, CMOS/Open Drain 1.8 V - 5.0 V, CMOS/Open Drain 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 3.3 V - 5.0 V, CMOS Receiver 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS, with Hysteresis 1.8 V - 5.0 V, CMOS, with Hysteresis 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS - VLS MCLK ADC_LRCK ADC_SCLK ADC_SDOUT1-3 DAC_LRCK DAC_SCLK DAC_SDIN1-4 AUX_LRCK AUX_SCLK AUX_SDIN VA MUTEC Table 1. I/O Power Rails 8 DS648F2 CS42448 2. TYPICAL CONNECTION DIAGRAM +3.3 V to +5 V 10 µF + 0.1 µF 0.01 µF 0.01 µF 0.1 µF + +3.3 V to +5 V 10 µF 0.1 µF 0.01 µF 6 24 53 44 0.01 µF 0.1 µF VD VD VA VA 26 25 27 28 30 29 31 32 34 33 36 37 39 38 40 41 AOUT1+ AOUT1AOUT2+ AOUT28 Analog Output Filter 2 Analog Output Filter2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 VLS AOUT3+ AOUT3AOUT4+ AOUT4- 0.01 µF 22 21 20 CS5341 A/D Converter AUX_SDIN AUX_SCLK AUX_LRCK AOUT5+ AOUT5AOUT6+ AOUT6AOUT7+ AOUT7- CS8416 Receiver S/PDIF OSC RMCK optional connection AOUT8+ AOUT8- MUTEC 10 9 35 Mute Drive (optional) MCLK ADC_SCLK ADC_LRCK ADC_SDOUT1 ADC_SDOUT2 ADC_SDOUT3 DAC_SCLK DAC_LRCK DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 INT RST SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS AIN1+ AIN1AIN2+ AIN2AIN3+ AIN3AIN4+ AIN4AIN5+/AIN5A 46 45 48 47 50 49 52 51 +1.8 V to +5.0 V Digital Audio Processor 5 13 12 11 18 19 17 16 15 14 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Analog Input 1 Analog Input 2 Analog Input 3 Analog Input 4 58 57 60 59 61 AIN5-/AIN5B AIN6+/AIN6A AIN6-/AIN6B Analog Input 5 MicroController 3 63 64 2 1 Analog Input 6 Analog Input 5A Analog Input 5B Analog Input 6A Analog Input 6B ** 2 kΩ +1.8 V to +5 V ** Resistors are required for I2C control port operation ** VL C 2 kΩ 4 0.1 µF VQ FILT+_ADC FILT+_DAC 43 55 54 + DGND DGND DGND 7 23 62 + 100 µF 0.1 µF 22 µF 0.1 µF + 4.7 µF AGND 56 AGND 42 0.1 µF Connect DGND and AGND near CODEC 1. See the ADC Input Filter section in the Appendix. 2. See the DAC Output Filter section in the Appendix. Figure 1. Typical Connection Diagram DS648F2 9 CS42448 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) Parameters DC Power Supply Analog Digital Serial Audio Interface Control Port Interface Ambient Temperature Commercial Automotive (Note 1) (Note 2) Symbol VA VD VLS VLC TA Min 3.14 3.14 1.71 1.71 -10 -40 Max 5.25 5.25 5.25 5.25 +70 +105 Units V V V V °C °C -CQZ -DQZ ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Analog Digital Serial Port Interface Control Port Interface (Note 3) (Note 4) Serial Port Interface Control Port Interface Symbol VA VD VLS VLC Iin VIN VIND-S VIND-C TA Tstg Min -0.3 -0.3 -0.3 -0.3 AGND-0.7 -0.3 -0.3 -50 -65 Max 6.0 6.0 6.0 6.0 ±10 VA+0.7 VLS+ 0.4 VLC+ 0.4 +125 +150 Units V V V V mA V V V °C °C Input Current Analog Input Voltage Digital Input Voltage (Note 4) Ambient Operating Temperature (power applied) Storage Temperature WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Typical Analog input/output performance will slightly degrade at VA = 3.3 V. 2. The ADC_SDOUT may not meet timing requirements in TDM, Double-Speed Mode. 3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 4. The maximum over/under voltage is limited by the input current. 10 DS648F2 CS42448 ANALOG INPUT CHARACTERISTICS (COMMERCIAL) (Test Conditions (unless otherwise specified): TA = -10 to +70°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%; Full-scale input sine wave: 1 kHz through the active input filter in Figure 26 on page 53 and Figure 27 on page 53; Measurement Bandwidth is 10 Hz to 20 kHz.) Differential Parameter Fs=48 kHz, 96 kHz, 192 kHz Dynamic Range Min Typ Max Min Single-Ended Typ Max Unit A-weighted 99 105 96 102 dB unweighted 96 102 93 99 dB 40 kHz bandwidth unweighted 99 96 dB dB -89 -95 -92 -98 Total Harmonic Distortion + Noise -1 dB dB -79 -82 (Note 5) -20 dB dB -39 -42 -60 dB dB -90 -90 40 kHz bandwidth -1 dB ADC1-3 Interchannel Isolation 90 90 dB ADC3 MUX Interchannel Isolation 90 90 dB DC Accuracy Interchannel Gain Mismatch 0.1 0.1 dB Gain Drift ±100 ±100 ppm/°C Analog Input Full-Scale Input Voltage 1.06*VA 1.12*VA 1.18*VA 0.53*VA 0.56*VA 0.59*VA Vpp Differential Input Impedance (Note 6) 18 kΩ Single-Ended Input Impedance (Note 7) 18 kΩ Common Mode Rejection Ratio (CMRR) 82 dB DS648F2 11 CS42448 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE) (Test Conditions (unless otherwise specified): TA = -40 to +85°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%; Full-scale input sine wave: 1 kHz through the active input filter in Figure 26 on page 53 and Figure 27 on page 53; Measurement Bandwidth is 10 Hz to 20 kHz.) Differential Parameter Fs=48 kHz, 96 kHz, 192 kHz Dynamic Range Min Typ Max Min Single-Ended Typ Max Unit A-weighted 97 105 94 102 dB unweighted 94 102 91 99 dB 40 kHz bandwidth unweighted 99 96 dB dB -87 -95 -90 -98 Total Harmonic Distortion + Noise -1 dB dB -79 -82 (Note 5) -20 dB dB -39 -42 -60 dB dB -87 -87 40 kHz bandwidth -1 dB ADC1-3 Interchannel Isolation 90 90 dB ADC3 MUX Interchannel Isolation 85 85 dB DC Accuracy Interchannel Gain Mismatch 0.1 0.1 dB Gain Drift ±100 ±100 ppm/°C Analog Input Full-Scale Input Voltage 1.04*VA 1.12*VA 1.20*VA 0.52*VA 0.56*VA 0.60*VA Vpp Differential Input Impedance (Note 6) 18 kΩ Single-Ended Input Impedance (Note 7) 18 kΩ Common Mode Rejection Ratio (CMRR) 82 dB Notes: 5. Referred to the typical full-scale voltage. 6. Measured between AINx+ and AINx-. 7. Measured between AINxx and AGND. 12 DS648F2 CS42448 ADC DIGITAL FILTER CHARACTERISTICS Parameter (Notes 8, 9) Single-Speed Mode (Note 9) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay Double-Speed Mode (Note 9) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay Quad-Speed Mode (Note 9) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay High-Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time Notes: 8. Filter response is guaranteed by design. 9. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 32 to 43) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. -3.0 dB -0.13 dB @ 20 Hz 1 20 10 105/Fs 0 0 Hz Hz Deg dB s to -0.1 dB corner 0 0.5000 60 5/Fs 0.2604 0.16 Fs dB Fs dB s to -0.1 dB corner 0 0.5604 69 9/Fs 0.4896 0.16 Fs dB Fs dB s to -0.1 dB corner 0 0.5688 70 12/Fs 0.4896 0.08 Fs dB Fs dB s Min Typ Max Unit DS648F2 13 CS42448 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL) (Test Conditions (unless otherwise specified): TA = -10 to +70°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%; Full-scale 997 Hz output sine wave (see Note 11) into passive filter in Figure 32 on page 57 and active filter in Figure 32 on page 57; Measurement Bandwidth is 10 Hz to 20 kHz.) Differential Typ Single-Ended Typ Max Parameter Min Fs = 48 kHz, 96 kHz, 192 kHz Dynamic Range 102 18 to 24-Bit A-weighted 99 unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) Analog Output Full-Scale Output 1.235•VA Interchannel Gain Mismatch Gain Drift Output Impedance DC Current draw from an AOUT pin (Note 10) AC-Load Resistance (RL) (Note 12) 3 Load Capacitance (CL) (Note 12) - Max Min Unit 108 105 99 96 -98 -85 -45 -93 -76 -36 100 -92 - 99 96 - 105 102 96 93 -95 -82 -42 -90 -73 -33 100 -89 - dB dB dB dB dB dB dB dB dB dB dB 1.300•VA 1.365•VA 0.618•VA 0.650•VA 0.683•VA Vpp 0.1 0.25 0.1 0.25 dB ±100 ±100 ppm/°C 100 100 Ω 10 10 μA 100 3 100 kΩ pF 14 DS648F2 CS42448 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE) (Test Conditions (unless otherwise specified): TA = -40 to +85°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%; Full-scale 997 Hz output sine wave (see Note 11) in Figure 32 on page 57 and Figure 32 on page 57; Measurement Bandwidth is 10 Hz to 20 kHz.) Differential Typ Single-Ended Typ Max Parameter Min Fs = 48 kHz, 96 kHz, 192 kHz Dynamic Range 100 18 to 24-Bit A-weighted 97 unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) Analog Output Full-Scale Output 1.210•VA Interchannel Gain Mismatch Gain Drift Output Impedance DC Current draw from an AOUT pin (Note 10) AC-Load Resistance (RL) (Note 12) 3 Load Capacitance (CL) Notes: (Note 12) - Max Min Unit 108 105 99 96 -98 -85 -45 -93 -76 -36 100 -90 - 97 94 - 105 102 96 93 -95 -82 -42 -90 -73 -33 100 -87 - dB dB dB dB dB dB dB dB dB dB dB 1.300•VA 1.392•VA 0.605•VA 0.650•VA 0.696•VA Vpp 0.1 0.25 0.1 0.25 dB ±100 ±100 ppm/°C 100 100 Ω 10 10 μA 100 3 100 kΩ pF 10. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC-blocking capacitors. 11. One-half LSB of triangular PDF dither is added to data. 12. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively move the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. See “External Filters” on page 53 for a recommended output filter. DS648F2 15 CS42448 125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region DAC1-4 AOUTxx 3.3 µF + CL Analog Output RL AGND 2.5 3 5 10 15 20 Resistive Load -- RL (kΩ ) Figure 2. Output Test Circuit for Maximum Load Figure 3. Maximum Loading 16 DS648F2 CS42448 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter (Notes 8, 13) Single-Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 15) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz (Note 14) to -0.05 dB corner to -3 dB corner 0 0 -0.2 0.5465 50 10/Fs 0.4780 0.4996 +0.08 Fs Fs dB Fs dB s Min Typ Max Unit +1.5/+0 dB +0.05/-0.25 dB -0.2/-0.4 dB Double-Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Quad-Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Notes: 13. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 44 to 55) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 14. Single- and Double-Speed Mode Measurement Bandwidth is from Stopband to 3 Fs. Quad-Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs. 15. De-emphasis is only available in Single-Speed Mode. (Note 14) to -0.1 dB corner to -3 dB corner 0 0 -0.2 0.7 51 2.5/Fs 0.397 0.476 +0.05 Fs Fs dB Fs dB s (Note 14) to -0.1 dB corner to -3 dB corner 0 0 -0.2 0.5770 55 5/Fs 0.4650 0.4982 +0.7 Fs Fs dB Fs dB s DS648F2 17 CS42448 SWITCHING SPECIFICATIONS - ADC/DAC PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT CLOAD = 15 pF.) Parameters (Note 20) Slave Mode RST pin Low Pulse Width MCLK Frequency MCLK Duty Cycle Input Sample Rate (LRCK) (Note 16) (Note 17) Single-Speed Mode Double-Speed Mode (Note 18) Quad-Speed Mode (Note 19) 1 0.512 45 4 50 100 45 45 8 8 5 16 3 5 5 10 15 45 45 3 5 50 55 50 100 200 55 55 35 MCLK / 256 55 64 x Fs 55 5 35 ms MHz % kHz kHz kHz % % ns ns ns ns ns ns ns ns ns ns kHz % MHz % ns ns ns ns Symbol Min Max Units Fs Fs Fs LRCK Duty Cycle SCLK Duty Cycle SCLK High Time SCLK Low Time LRCK Rising Edge to SCLK Rising Edge SCLK Rising Edge to LRCK Falling Edge SCLK Falling Edge to ADC_SDOUT Output Valid DAC_SDIN Setup Time Before SCLK Rising Edge DAC_SDIN Hold Time After SCLK Rising Edge DAC_SDIN Hold Time After SCLK Rising Edge ADC_SDOUT Hold Time After SCLK Rising Edge ADC_SDOUT Valid Before SCLK Rising Edge Master Mode Output Sample Rate (LRCK) All Speed Modes LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Edge to SCLK Rising Edge SCLK Falling Edge to ADC_SDOUT Output Valid DAC_SDIN Setup Time Before SCLK Rising Edge DAC_SDIN Hold Time After SCLK Rising Edge tsckh tsckl tfss tlcks tfsh tdpd tds tdh tdh1 tdh2 tdval Fs tlcks tdpd tds tdh1 LRCK LRCK (input) tlcks SCLK t sckh tsckl SCLK (input) tfss tfsh tsckh tsckl tds DAC_SDINx t dh MSB MSB-1 DAC_SDIN1 tds tdh1 MSB MSB-1 tdpd ADC_SDOUTx MSB MSB-1 ADC_SDOUT1 MSB tdh2 tdval MSB-1 Figure 4. Serial Audio Interface Slave Mode Timing Figure 5. TDM Serial Audio Interface Timing 18 DS648F2 CS42448 Notes: 16. After powering up the CS42448, RST should be held low after the power supplies and clocks are settled. 17. See Table 10 on page 43 and Table 11 on page 44 for suggested MCLK frequencies. 18. When operating in TDM interface format, VLS is limited to nominal 2.5 V to 5.0 V operation only. 19. ADC - I²S, Left-Justified, Right-Justified interface formats only. DAC - I²S, Left-Justified, Right-Justified and Time Division Multiplexed interface formats only. 20. “LRCK” and “SCLK” shall refer to the ADC and DAC left/right clock and serial clock, respectively. LRCK tlcks SCLK tds DAC_SDINx tdh MSB MSB-1 tdpd ADC_SDOUTx MSB MSB-1 Figure 6. Serial Audio Interface Master Mode Timing DS648F2 19 CS42448 SWITCHING CHARACTERISTICS - AUX PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS.) Parameters Master Mode Output Sample Rate (AUX_LRCK) AUX_SCLK Frequency AUX_SCLK Duty Cycle AUX_LRCK Edge to SCLK Rising Edge AUX_SDIN Setup Time Before SCLK Rising Edge AUX_SDIN Hold Time After SCLK Rising Edge tlcks tds tdh All Speed Modes Fs 45 3 5 ADC_LRCK 64·ADC_LRCK 55 5 kHz kHz % ns ns ns Symbol Min Max Units AUX_LRCK tlcks AUX_SCLK tsckh tsckl tds AUX_SDIN tdh MSB MSB-1 Figure 7. Serial Audio Interface Slave Mode Timing 20 DS648F2 CS42448 SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE (VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF) Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling Notes: 21. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 22. Guaranteed by design. (Note 22) (Note 22) (Note 21) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 1000 Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns RST t Stop irs Start R e p e a te d Sta rt t rd t fd Stop SDA t buf t hdst t high t hdst t fc t susp SCL t t t sud t ack t sust t rc lo w hdd Figure 8. Control Port Timing - I²C Format DS648F2 21 CS42448 SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT (VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL = 30 pF) Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN Notes: 23. Data must be held for sufficient time to bridge the transition time of CCLK. 24. For fsck