CDB4245

CS4245 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC D/A Features Multi-bit Delta Sigma Modulator 104 dB Dynamic Range -90 dB THD+N Up to 192 kHz Sampling Rates Single-Ended Analog Architecture Volume Control with Soft Ramp – 0.5 dB Step Size – Zero Crossing, Click-Free Transitions Popguard® Technology – Minimizes the Effects of Output Transients Filtered Line-Level Outputs Selectable Serial Audio Interface Formats – Left-Justified up to 24-bit – I²S up to 24-bit – Right-Justified 16-, 18-, 20-, and 24-bit Selectable 50/15 µs De-Emphasis Control Output for External Muting A/D Features Multi-bit Delta Sigma Modulator 104 dB Dynamic Range -95 dB THD+N Stereo 6:1 Input Multiplexer Programmable Gain Amplifier (PGA) – ± 12 dB Gain, 0.5 dB Step Size – Zero Crossing, Click-Free Transitions Stereo Microphone Inputs – +32 dB Gain Stage – Low-Noise Bias Supply Up to 192 kHz Sampling Rates Selectable Serial Audio Interface Formats – Left-Justified up to 24-bit – I²S up to 24-bit High-Pass Filter or DC Offset Calibration 1.8 V to 5 V 3.3 V to 5 V 3.3 V to 5 V PCM Serial Interface Serial Audio Input I2C/SPI Control Data Interrupt ADC Overflow Reset Level Translator Volume Control Volume Control Interpolation Filter Interpolation Filter Multibit ΔΣ M odulator Multibit ΔΣ M odulator Switched Capacitor DAC and Filter Left DAC Output Mute Control Mute Control Right DAC Output MUX Left Aux Output Right Aux Output Stereo Input 1 Stereo Input 2 Stereo Input 3 Switched Capacitor DAC and Filter Level Translator Register Configuration PCM Serial Interface Internal Voltage Reference Serial Audio Output Level Translator High Pass Filter Low-Latency Anti-Alias Filter Multibit Oversampling ADC Multibit Oversampling ADC PGA MUX PGA +32 dB High Pass Filter Low-Latency Anti-Alias Filter Stereo Input 4 / Mic Input 1 & 2 Stereo Input 5 Stereo Input 6 +32 dB http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) AUGUST '07 DS656F2 CS4245 System Features Direct Interface with 1.8 V to 5 V Logic Levels Optional Asynchronous Serial Port Operation – Each Serial Port Supports Master or Slave Operation Selectable Auxiliary Analog Output – Allows Analog Monitoring of Either the ADC Input Signal after PGA or DAC Output Signal Internal Digital Loopback Power-Down Mode – Available for A/D, D/A, CODEC, Mic Preamplifier +3.3 V to +5 V Analog Power Supply +3.3 V to +5 V Digital Power Supply Supports I²C® and SPITM Control Port Interfaces Pin-Compatible with CS5345 General Description The CS4245 is a highly integrated stereo audio CODEC. The CS4245 performs stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 192 kHz. A 6:1 stereo input multiplexer is included for selecting between line-level or microphone-level inputs. The microphone input path includes a +32 dB gain stage and a low-noise bias voltage supply. The PGA is available for line or microphone inputs and provides gain/attenuation of ±12 dB in 0.5 dB steps. The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the serial audio interface at rates from 4 kHz to 192 kHz in either Slave or Master Mode. The D/A converter is based on a 4th-order multi-bit delta sigma modulator with an ultra-linear low-pass filter and offers a volume control that operates with a 0.5 dB step size. It incorporates selectable soft ramp and zero crossing transition functions to eliminate clicks and pops. Standard 50/15 μs de-emphasis is available for a 44.1 kHz sample rate for compatibility with digital audio programs mastered using the 50/15 μs pre-emphasis technique. Integrated level translators allow easy interfacing between the CS4245 and other devices operating over a wide range of logic levels. The CS4245 is available in a 48-pin LQFP package in both Commercial (-10° to +70° C) and Automotive (-40° to +105° C) grade. The CDB4245 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 57 for complete details. 2 DS656F2 CS4245 TABLE OF CONTENTS 1. PIN DESCRIPTIONS ........................................................................................................................ 6 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8 SPECIFIED OPERATING CONDITIONS ............................................................................................. 8 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 8 DAC ANALOG CHARACTERISTICS ................................................................................................... 9 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................ 10 ADC ANALOG CHARACTERISTICS ................................................................................................. 12 ADC ANALOG CHARACTERISTICS ................................................................................................. 14 ADC DIGITAL FILTER CHARACTERISTICS ..................................................................................... 15 AUXILIARY OUTPUT ANALOG CHARACTERISTICS ...................................................................... 16 AUXILIARY OUTPUT ANALOG CHARACTERISTICS ...................................................................... 17 AUXILIARY OUTPUT ANALOG CHARACTERISTICS ...................................................................... 18 DC ELECTRICAL CHARACTERISTICS ............................................................................................. 19 DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 20 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 1 .......................................................... 21 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 2 .......................................................... 23 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................ 26 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 27 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 28 4. APPLICATIONS ................................................................................................................................... 29 4.1 Recommended Power-Up Sequence ............................................................................................. 29 4.2 System Clocking ............................................................................................................................. 29 4.2.1 Synchronous / Asynchronous Mode ...................................................................................... 29 4.2.2 Master Clock ......................................................................................................................... 29 4.2.3 Master Mode ......................................................................................................................... 30 4.2.4 Slave Mode ........................................................................................................................... 30 4.3 High-Pass Filter and DC Offset Calibration .................................................................................... 31 4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................ 32 4.5 Input Connections ........................................................................................................................... 32 4.6 Output Connections ........................................................................................................................ 32 4.7 Output Transient Control ................................................................................................................ 33 4.7.1 Power-Up .............................................................................................................................. 33 4.7.2 Power-Down .......................................................................................................................... 33 4.7.3 Serial Interface Clock Changes ............................................................................................. 33 4.8 Auxiliary Analog Output .................................................................................................................. 33 4.9 De-Emphasis Filter ......................................................................................................................... 33 4.10 Internal Digital Loopback .............................................................................................................. 34 4.11 Mute Control ................................................................................................................................. 34 4.12 Control Port Description and Timing ............................................................................................. 35 4.12.1 SPI Mode ............................................................................................................................. 35 4.12.2 I²C Mode .............................................................................................................................. 36 4.13 Interrupts and Overflow ................................................................................................................ 37 4.14 Reset ............................................................................................................................................ 38 4.15 Synchronization of Multiple Devices ............................................................................................. 38 4.16 Grounding and Power Supply Decoupling .................................................................................... 38 5. REGISTER QUICK REFERENCE ........................................................................................................ 39 6. REGISTER DESCRIPTION .................................................................................................................. 40 6.1 Chip ID - Register 01h .................................................................................................................... 40 6.2 Power Control - Address 02h ......................................................................................................... 40 6.2.1 Freeze (Bit 7) ......................................................................................................................... 40 6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 40 6.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 40 DS656F2 3 CS4245 6.2.4 Power-Down DAC (Bit 1) ....................................................................................................... 41 6.2.5 Power-Down Device (Bit 0) ................................................................................................... 41 6.3 DAC Control - Address 03h ............................................................................................................ 41 6.3.1 DAC Functional Mode (Bits 7:6) ............................................................................................ 41 6.3.2 DAC Digital Interface Format (Bits 5:4) ................................................................................. 41 6.3.3 Mute DAC (Bit 2) ................................................................................................................... 41 6.3.4 De-Emphasis Control (Bit 1) .................................................................................................. 42 6.3.5 DAC Master / Slave Mode (Bit 0) .......................................................................................... 42 6.4 ADC Control - Address 04h ............................................................................................................ 42 6.4.1 ADC Functional Mode (Bits 7:6) ............................................................................................ 42 6.4.2 ADC Digital Interface Format (Bit 4) ...................................................................................... 43 6.4.3 Mute ADC (Bit 2) ................................................................................................................... 43 6.4.4 ADC High-Pass Filter Freeze (Bit 1) ..................................................................................... 43 6.4.5 ADC Master / Slave Mode (Bit 0) .......................................................................................... 43 6.5 MCLK Frequency - Address 05h .................................................................................................... 43 6.5.1 Master Clock 1 Frequency (Bits 6:4) ..................................................................................... 43 6.5.2 Master Clock 2 Frequency (Bits 2:0) ..................................................................................... 44 6.6 Signal Selection - Address 06h ...................................................................................................... 44 6.6.1 Auxiliary Output Source Select (Bits 6:5) .............................................................................. 44 6.6.2 Digital Loopback (Bit 1) ......................................................................................................... 44 6.6.3 Asynchronous Mode (Bit 0) ................................................................................................... 44 6.7 Channel B PGA Control - Address 07h .......................................................................................... 45 6.7.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 45 6.8 Channel A PGA Control - Address 08h .......................................................................................... 45 6.8.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 45 6.9 ADC Input Control - Address 09h ................................................................................................... 45 6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 45 6.9.2 Analog Input Selection (Bits 2:0) ........................................................................................... 46 6.10 DAC Channel A Volume Control - Address 0Ah ........................................................................... 46 6.11 DAC Channel B Volume Control - Address 0Bh ........................................................................... 46 6.11.1 Volume Control (Bits 7:0) .................................................................................................... 46 6.12 DAC Control 2 - Address 0Ch ...................................................................................................... 47 6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6) ................................................................ 47 6.12.2 Invert DAC Output (Bit 5) .................................................................................................... 47 6.12.3 Active High/Low (Bit 0) ........................................................................................................ 48 6.13 Interrupt Status - Address 0Dh ..................................................................................................... 48 6.13.1 ADC Clock Error (Bit 3) ....................................................................................................... 48 6.13.2 DAC Clock Error (Bit 2) ....................................................................................................... 48 6.13.3 ADC Overflow (Bit 1) ........................................................................................................... 48 6.13.4 ADC Underflow (Bit 0) ......................................................................................................... 48 6.14 Interrupt Mask - Address 0Eh ....................................................................................................... 48 6.15 Interrupt Mode MSB - Address 0Fh .............................................................................................. 49 6.16 Interrupt Mode LSB - Address 10h ............................................................................................... 49 7. PARAMETER DEFINITIONS ................................................................................................................ 50 8. DAC FILTER PLOTS .................................................................................................................... 51 9. ADC FILTER PLOTS ......................................................................................................................... 53 10. PACKAGE DIMENSIONS .................................................................................................................. 55 11. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................. 55 12. ORDERING INFORMATION ..................................................................................................... 56 13. REVISION HISTORY .......................................................................................................................... 56 LIST OF FIGURES Figure 1.DAC Output Test Load ................................................................................................................ 11 4 DS656F2 CS4245 Figure 2.Maximum DAC Loading .............................................................................................................. 11 Figure 3.Master Mode Timing - Serial Audio Port 1 .................................................................................. 22 Figure 4.Slave Mode Timing - Serial Audio Port 1 .................................................................................... 22 Figure 5.Master Mode Timing - Serial Audio Port 2 .................................................................................. 24 Figure 6.Slave Mode Timing - Serial Audio Port 2 .................................................................................... 24 Figure 7.Format 0, Left-Justified up to 24-Bit Data ................................................................................... 25 Figure 8.Format 1, I²S up to 24-Bit Data ................................................................................................... 25 Figure 9.Format 2, Right-Justified 16-Bit Data. Format 3, Right-Justified 24-Bit Data. ....................................................................................................... 25 Figure 10.Control Port Timing - I²C Format ............................................................................................... 26 Figure 11.Control Port Timing - SPI Format .............................................................................................. 27 Figure 12.Typical Connection Diagram ..................................................................................................... 28 Figure 13.Master Mode Clocking .............................................................................................................. 30 Figure 14.Analog Input Architecture .......................................................................................................... 32 Figure 15.De-Emphasis Curve .................................................................................................................. 34 Figure 16.Suggested Active-Low Mute Circuit .......................................................................................... 35 Figure 17.Control Port Timing in SPI Mode .............................................................................................. 36 Figure 18.Control Port Timing, I²C Write ................................................................................................... 36 Figure 19.Control Port Timing, I²C Read ................................................................................................... 37 Figure 20.De-Emphasis Curve .................................................................................................................. 42 Figure 21.DAC Single-Speed Stopband Rejection ................................................................................... 51 Figure 22.DAC Single-Speed Transition Band .......................................................................................... 51 Figure 23.DAC Single-Speed Transition Band .......................................................................................... 51 Figure 24.DAC Single-Speed Passband Ripple ........................................................................................ 51 Figure 25.DAC Double-Speed Stopband Rejection .................................................................................. 51 Figure 26.DAC Double-Speed Transition Band ........................................................................................ 51 Figure 27.DAC Double-Speed Transition Band ........................................................................................ 52 Figure 28.DAC Double-Speed Passband Ripple ...................................................................................... 52 Figure 29.DAC Quad-Speed Stopband Rejection ..................................................................................... 52 Figure 30.DAC Quad-Speed Transition Band ........................................................................................... 52 Figure 31.DAC Quad-Speed Transition Band ........................................................................................... 52 Figure 32.DAC Quad-Speed Passband Ripple ......................................................................................... 52 Figure 33.ADC Single-Speed Stopband Rejection ................................................................................... 53 Figure 34.ADC Single-Speed Stopband Rejection ................................................................................... 53 Figure 35.ADC Single-Speed Transition Band (Detail) ............................................................................. 53 Figure 36.ADC Single-Speed Passband Ripple ........................................................................................ 53 Figure 37.ADC Double-Speed Stopband Rejection .................................................................................. 53 Figure 38.ADC Double-Speed Stopband Rejection .................................................................................. 53 Figure 39.ADC Double-Speed Transition Band (Detail) ............................................................................ 54 Figure 40.ADC Double-Speed Passband Ripple ...................................................................................... 54 Figure 41.ADC Quad-Speed Stopband Rejection ..................................................................................... 54 Figure 42.ADC Quad-Speed Stopband Rejection ..................................................................................... 54 Figure 43.ADC Quad-Speed Transition Band (Detail) .............................................................................. 54 Figure 44.ADC Quad-Speed Passband Ripple ......................................................................................... 54 LIST OF TABLES Table 1. Speed Modes .............................................................................................................................. 29 Table 2. Common Clock Frequencies ....................................................................................................... 30 Table 3. Slave Mode Serial Bit Clock Ratios ............................................................................................. 31 Table 4. Device Revision .......................................................................................................................... 40 Table 5. Freeze-able Bits .......................................................................................................................... 40 Table 6. Functional Mode Selection ......................................................................................................... 41 Table 7. DAC Digital Interface Formats .................................................................................................... 41 DS656F2 5 CS4245 Table 8. De-Emphasis Control .................................................................................................................. 42 Table 9. Functional Mode Selection .......................................................................................................... 42 Table 10. ADC Digital Interface Formats .................................................................................................. 43 Table 11. MCLK 1 Frequency ................................................................................................................... 43 Table 12. MCLK 2 Frequency ................................................................................................................... 44 Table 13. Auxiliary Output Source Selection ............................................................................................. 44 Table 14. Example Gain and Attenuation Settings ................................................................................... 45 Table 15. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 46 Table 16. Analog Input Multiplexer Selection ............................................................................................ 46 Table 17. Digital Volume Control Example Settings ................................................................................. 47 Table 18. DAC Soft Cross or Zero Cross Mode Selection ........................................................................ 47 6 DS656F2 CS4245 1. PIN DESCRIPTIONS SDOUT MCLK1 MCLK2 LRCK1 LRCK2 SCLK1 OVFL SCLK2 DGND 48 47 46 45 44 43 42 41 40 39 38 37 SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RESET AIN3A AIN3B AIN2A AIN2B AIN1A AIN1B SDIN INT VD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FILT1+ FILT2+ VQ1 VQ2 AIN4A/MICIN1 AIN4B/MICIN2 AGND AFILTA AFILTB VA AIN5A AIN5B 36 35 34 33 32 31 30 29 28 27 26 25 VLS MUTEC AOUTB AOUTA AGND AGND VA AUXOUTB AUXOUTA AIN6B AIN6A MICBIAS CS4245 Pin Name SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RESET AIN3A AIN3B AIN2A AIN2B AIN1A AIN1B # 1 2 3 4 5 6 7, 8 9, 10 11, 12 Pin Description Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDOUT is the output data line for the control port interface in SPI Mode. Serial Control Port Clock (Input) - Serial clock for the serial control port. Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS is the chip-select signal for SPI format. Address Bit 1 (I²C) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in I²C Mode; CDIN is the input data line for the control port interface in SPI Mode. Control Port Power (Input) - Determines the required signal level for the control port interface. Refer to the Recommended Operating Conditions for appropriate voltages. Reset (Input) - The device enters a low power mode when this pin is driven low. Stereo Analog Input 3 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Stereo Analog Input 2 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Stereo Analog Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. DS656F2 7 CS4245 AGND VA AFILTA AFILTB VQ1 VQ2 FILT1+ FILT2+ 13 14 15 16 17 18 19 20 Analog Ground (Input) - Ground reference for the internal analog section. Analog Power (Input) - Positive power for the internal analog section. Antialias Filter Connection (Output) - Antialias filter connection for the channel A ADC input. Antialias Filter Connection (Output) - Antialias filter connection for the channel B ADC input. Quiescent Voltage 1 (Output) - Filter connection for the internal quiescent reference voltage. Quiescent Voltage 2 (Output) - Filter connection for the internal quiescent reference voltage. Positive Voltage Reference 1 (Output) - Positive reference voltage for the internal sampling circuits. Positive Voltage Reference 2 (Output) - Positive reference voltage for the internal sampling circuits. AIN4A/MICIN1 Stereo Analog Input 4 / Microphone Input 1 & 2 (Input) - The full-scale level is specified in the ADC 21, 22 AIN4B/MICIN2 Analog Characteristics specification table. AIN5A AIN5B MICBIAS AIN6A AIN6B AUXOUTA AUXOUTB VA AGND AOUTA AOUTB MUTEC VLS SDIN SCLK2 LRCK2 MCLK2 SDOUT SCLK1 LRCK1 MCLK1 DGND VD INT OVFL 23, 24 25 26, 27 28, 29 30 Stereo Analog Input 5 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Microphone Bias Supply (Output) - Low-noise bias supply for external microphone. Electrical characteristics are specified in the DC Electrical Characteristics specification table. Stereo Analog Input 6 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Auxiliary Analog Audio Output (Output) - Analog output from either the DAC, the PGA block, or high impedance. See “Auxiliary Output Source Select (Bits 6:5)” on page 45. Analog Power (Input) - Positive power for the internal analog section. DAC Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table. Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages. Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Serial Port 2 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 2. Serial Port 2 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio input data line. Master Clock 2 (Input) - Optional asynchronous clock source for the DAC’s delta-sigma modulators. Serial Audio Data Output (Output) - Output for two’s complement serial audio data. Serial Port 1 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 1. Serial Port 1 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio output data line. Master Clock 1 (Input) - Clock source for the ADC’s delta-sigma modulators. By default, this signal also clocks the DAC’s delta-sigma modulators. Digital Ground (Input) - Ground reference for the internal digital section. Digital Power (Input) - Positive power for the internal digital section. Interrupt (Output) - Indicates an interrupt condition has occurred. ADC Overflow (Output) - Indicates an ADC overflow condition is present. 31, 32 Analog Ground (Input) - Ground reference for the internal analog section. 33, 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 8 DS656F2 CS4245 2. CHARACTERISTICS AND SPECIFICATIONS SPECIFIED OPERATING CONDITIONS AGND = DGND = 0 V; All voltages with respect to ground. Parameters DC Power Supplies: Analog Digital Logic - Serial Port Logic - Control Port Ambient Operating Temperature (Power Applied) Commercial Automotive Symbol VA VD VLS VLC TA TA Min 3.13 3.13 1.71 1.71 -10 -40 Nom 5.0 3.3 3.3 3.3 - Max 5.25 (Note 1) 5.25 5.25 +70 +105 Units V V V V °C °C Notes: 1. Maximum of VA+0.25 V or 5.25 V, whichever is less. ABSOLUTE MAXIMUM RATINGS AGND = DGND = 0 V All voltages with respect to ground. (Note 2) Parameter DC Power Supplies: Analog Digital Logic - Serial Port Logic - Control Port (Note 3) Logic - Serial Port Logic - Control Port Symbol VA VD VLS VLC Iin VINA VIND-S VIND-C TA Tstg Min -0.3 -0.3 -0.3 -0.3 AGND-0.3 -0.3 -0.3 -50 -65 Max +6.0 +6.0 +6.0 +6.0 ±10 VA+0.3 VLS+0.3 VLC+0.3 +125 +150 Units V V V V mA V V V °C °C Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature 2. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. DS656F2 9 CS4245 DAC ANALOG CHARACTERISTICS Test Conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; TA = -10° to +70° C for Commercial or -40° to +85° C for Automotive; Output test signal: 997 Hz full-scale sine wave; Test load RL = 3 kΩ, CL = 10 pF (see Figure 1), Fs = 48/96/192 kHz. Measurement Bandwidth 10 Hz to 20 kHz Synchronous mode; All Connections as shown in Figure 12 on page 29. Commercial Grade Parameter Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit (Note 4) A-Weighted unweighted A-Weighted unweighted (Note 4) 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB (Note 4) A-Weighted unweighted A-Weighted unweighted (Note 4) 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB (1 kHz) Automotive Grade Min Typ Max Unit Symbol Min Typ Max Dynamic Performance for VA = 4.75 V to 5.25 V 98 95 90 87 104 101 96 93 -90 -81 -41 -93 -73 -33 -84 -87 96 93 88 85 104 101 96 93 -90 -81 -41 -93 -73 -33 -82 -85 dB dB dB dB dB dB dB dB dB dB 16-Bit Dynamic Performance for VA = 3.13 V to 3.46 V Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 95 92 88 85 101 98 93 90 -87 -78 -38 -90 -70 -30 100 0.1 100 -79 -82 0.25 93 90 86 83 101 98 93 90 -87 -78 -38 -90 -70 -30 100 0.1 100 -77 -80 0.25 dB dB dB dB dB dB dB dB dB dB dB dB ppm/°C Vpp μA kΩ pF Ω 16-Bit Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Full Scale Output Voltage DC Current draw from an AOUT pin AC-Load Resistance Load Capacitance Output Impedance (Note 5) (Note 6) (Note 6) IOUT RL CL ZOUT 0.60*VA 0.65*VA 0.70*VA 0.60*VA 0.65*VA 0.70*VA 3 150 10 100 3 150 10 100 - 4. One-half LSB of triangular PDF dither added to data. 5. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC blocking capacitors. 10 DS656F2 CS4245 6. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp’s stability. CL affects the dominant pole of the internal output amp; increasing CL beyond 100 pF can cause the internal op-amp to become unstable. DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter (Note 7,10) Combined Digital and On-chip Analog Filter Response Passband (Note 7) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 9) Fs = 44.1 kHz (Note 8) tgd to -0.1 dB corner to -3 dB corner Symbol Min Typ Max Unit Single-Speed Mode 0 0 -0.175 0.5465 50 10/Fs 0.35 0.4992 +0.01 +0.05/-0.25 Fs Fs dB Fs dB s dB Combined Digital and On-chip Analog Filter Response Passband (Note 7) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay (Note 8) tgd to -0.1 dB corner to -3 dB corner Double-Speed Mode 0 0 -0.15 0.5770 55 5/Fs 0.22 0.501 +0.15 Fs Fs dB Fs dB s Combined Digital and On-chip Analog Filter Response Passband (Note 7) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay (Note 8) tgd to -0.1 dB corner to -3 dB corner Quad-Speed Mode 0 0 -0.12 0.7 51 2.5/Fs 0.110 0.469 0 Fs Fs dB Fs dB s 7. Filter response is guaranteed by design. 8. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs. 9. De-emphasis is available only in Single-Speed Mode. 10. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this data (Figures 21 to 30) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. DS656F2 11 CS4245 125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region 3.3 µF AOUTx R L C L V out AGND 2.5 3 5 10 15 20 Resistive Load -- RL (kΩ ) Figure 1. DAC Output Test Load Figure 2. Maximum DAC Loading 12 DS656F2 CS4245 ADC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; TA = -10° to +70° C for Commercial or -40° to +85° C for Automotive; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48/96/192 kHz. Synchronous mode; All connections as shown in Figure 12 on page 29. Line-Level Inputs Commercial Grade Parameter Symbol Dynamic Performance for VA = 4.75 V to 5.25 V Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted 40 kHz bandwidth unweighted PGA Setting: +12 dB Gain A-weighted unweighted 40 kHz bandwidth unweighted 98 95 92 89 104 101 98 98 95 92 96 93 90 87 104 101 98 98 95 92 dB dB dB dB dB dB Automotive Grade Min Typ Max Unit Min Typ Max (Note 13) (Note 13) Total Harmonic Distortion + Noise (Note 12) PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB (Note 13) 40 kHz bandwidth -1 dB THD+N PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB (Note 13) 40 kHz bandwidth -1 dB - -95 -81 -41 -92 -92 -75 -35 -89 -89 -86 - - -95 -81 -41 -92 -92 -75 -35 -89 -87 -84 - dB dB dB dB dB dB dB dB Dynamic Performance for VA = 3.13 V to 3.46 V Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted 40 kHz bandwidth unweighted PGA Setting: +12 dB Gain A-weighted unweighted 40 kHz bandwidth unweighted 93 90 89 86 101 98 95 95 92 89 91 88 87 84 101 98 95 95 92 89 dB dB dB dB dB dB (Note 13) (Note 13) Total Harmonic Distortion + Noise (Note 12) PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB (Note 13) 40 kHz bandwidth -1 dB THD+N PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB (Note 13) 40 kHz bandwidth -1 dB - -92 -78 -38 -84 -89 -72 -32 -81 -86 -83 - - -92 -78 -38 -84 -89 -72 -32 -81 -84 -81 - dB dB dB dB dB dB dB dB DS656F2 13 CS4245 Line-Level Inputs Commercial Grade Parameter Interchannel Isolation Automotive Grade Min - Symbol Min - Typ 90 - Max ±10 - Typ 90 - Max ±10 - Unit dB % ppm/°C Vpp kΩ % DC Accuracy Gain Error Gain Drift ±100 ±100 Line-Level Input Characteristics Full-scale Input Voltage Input Impedance (Note 11) Maximum Interchannel Input Impedance Mismatch 0.51*VA 0.57*VA 0.63*VA 0.51*VA 0.57*VA 0.63*VA 6.12 6.8 7.48 5.44 6.8 8.16 5 5 - Line-Level and Microphone-Level Inputs Commercial Grade Parameter DC Accuracy Interchannel Gain Mismatch 0.1 0.5 0.4 0.1 0.5 0.4 dB dB dB Automotive Grade Min Typ Max Unit Symbol Min Typ Max Programmable Gain Characteristics Gain Step Size Absolute Gain Step Error 11. Valid for the selected input pair. 14 DS656F2 CS4245 ADC ANALOG CHARACTERISTICS (Continued) Microphone-Level Inputs Commercial Grade Parameter Symbol Dynamic Performance for VA = 4.75 V to 5.25 V Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 12) PGA Setting: -12 dB to 0 dB -1 dB -20 dB THD+N -60 dB PGA Setting: +12 dB -1 dB 77 74 83 80 75 72 83 80 dB dB Automotive Grade Min Typ Max Unit Min Typ Max 65 62 71 68 - 63 60 71 68 - dB dB - -80 -60 -20 -74 - - -80 -60 -20 -72 - dB dB dB - -68 - - -68 - dB Dynamic Performance for VA = 3.13 V to 3.46 V Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 12) PGA Setting: -12 dB to 0 dB -1 dB -20 dB THD+N -60 dB PGA Setting: +12 dB -1 dB Interchannel Isolation 77 74 83 80 75 72 83 80 dB dB 65 62 71 68 - 63 60 71 68 - dB dB - -80 -60 -20 -74 - - -80 -60 -20 -72 - dB dB dB - -68 80 ±5 - - -68 80 ±5 - dB dB % ppm/°C Vpp kΩ DC Accuracy Gain Error Gain Drift ±300 ±300 Microphone-Level Input Characteristics Full-scale Input Voltage Input Impedance (Note 14) 0.013*VA 0.017*VA 0.021*VA 0.013*VA 0.017*VA 0.021*VA 60 60 - 12. Referred to the typical line-level full-scale input voltage 13. Valid for Double- and Quad-Speed Modes only. 14. Valid when the microphone-level inputs are selected. DS656F2 15 CS4245 ADC DIGITAL FILTER CHARACTERISTICS Parameter (Notes 15, 17) Single-Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd (-0.1 dB) 0 0.5688 70 0 0.5604 69 tgd 0 0.5000 60 tgd (Note 16) (Note 16) 12/Fs 9/Fs 5/Fs 1 20 10 105/Fs 0.4896 0.035 0.4896 0.025 0.2604 0.025 0 Fs dB Fs dB s Fs dB Fs dB s Fs dB Fs dB s Hz Hz Deg dB s Symbol Min Typ Max Unit Double-Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB) Quad-Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB) High-Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time -3.0 dB -0.13 dB @ 20 Hz 15. Filter response is guaranteed by design. 16. Response shown is for Fs = 48 kHz. 17. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 33 to 44) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 16 DS656F2 CS4245 AUXILIARY OUTPUT ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; TA = -10° to +70° C for Commercial or -40° to +85° C for Automotive; Input test signal: 1 kHz sine wave; Measurement bandwidth: 10 Hz to 20 kHz; Fs = 48/96/192 kHz; Synchronous mode; All connections as shown in Figure 12 on page 29. VA = 4.75 V to 5.25 V Commercial Grade Parameter Symbol Min Typ Max Dynamic Performance with PGA Output Selected, Line Level Input Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted PGA Setting: +12 dB Gain A-weighted unweighted Total Harmonic Distortion + Noise (Note 19) PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB THD+N PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 19) PGA Setting: -12 dB to 0 dB -1 dB -20 dB THD+N -60 dB PGA Setting: +12 dB -1 dB 77 74 65 62 83 80 71 68 75 72 63 60 83 80 71 68 dB dB dB dB 98 95 92 89 104 101 98 95 96 93 90 87 104 101 98 95 dB dB dB dB Automotive Grade Min Typ Max Unit - -80 -81 -41 -80 -75 -35 -74 -74 - - -80 -81 -41 -80 -75 -35 -72 -72 - dB dB dB dB dB dB Dynamic Performance with PGA Output Selected, Mic Level Input - -74 -60 -20 -68 -68 - - -74 -60 -20 -68 -66 - dB dB dB dB Dynamic Performance with DAC Output Selected (Notes 18) A-weighted unweighted 16-Bit A-Weighted unweighted Total Harmonic Distortion + Noise (Notes 18, 20) 18 to 24-Bit 0 dB -20 dB -60 dB THD+N 16-Bit 0 dB -20 dB -60 dB Dynamic Range 18 to 24-Bit 98 95 90 87 104 101 96 93 -80 -81 -41 -80 -73 -33 -74 -74 96 93 88 85 104 101 96 93 -80 -81 -41 -80 -73 -33 -72 -72 dB dB dB dB dB dB dB dB dB dB DS656F2 17 CS4245 AUXILIARY OUTPUT ANALOG CHARACTERISTICS (Continued) VA = 3.13 V to 3.46 V Commercial Grade Parameter Symbol Min Typ Max Dynamic Performance with PGA Output Selected, Line Level Input Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted PGA Setting: +12 dB Gain A-weighted unweighted Total Harmonic Distortion + Noise (Note 19) PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB THD+N PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 19) PGA Setting: -12 dB to 0 dB -1 dB -20 dB THD+N -60 dB PGA Setting: +12 dB -1 dB 77 74 65 62 83 80 71 68 75 72 63 60 83 80 71 68 dB dB dB dB 93 90 89 86 101 98 95 92 91 88 87 84 101 98 95 92 dB dB dB dB Automotive Grade Min Typ Max Unit - -80 -78 -38 -80 -72 -32 -74 -74 - - -80 -78 -38 -80 -72 -32 -72 -72 - dB dB dB dB dB dB Dynamic Performance with PGA Output Selected, Mic Level Input - -74 -60 -20 -68 -68 - - -74 -60 -20 -68 -66 - dB dB dB dB Dynamic Performance with DAC Output Selected (Notes 18) A-Weighted unweighted 16-Bit A-Weighted unweighted Total Harmonic Distortion + Noise (Notes 18, 20) 18 to 24-Bit 0 dB -20 dB -60 dB THD+N 16-Bit 0 dB -20 dB -60 dB Dynamic Range 18 to 24-Bit 95 92 88 85 101 98 93 90 -80 -78 -38 -80 -70 -30 -74 -74 93 90 86 83 101 98 93 90 -80 -78 -38 -80 -70 -30 -72 -72 dB dB dB dB dB dB dB dB dB dB 18. One-half LSB of triangular PDF dither added to data. 19. Referred to the typical Line-Level Full-Scale Input Voltage. 18 DS656F2 CS4245 20. Referred to the typical DAC Full-Scale Output Voltage. AUXILIARY OUTPUT ANALOG CHARACTERISTICS (Continued) VA = 3.13 V to 5.25 V Commercial Grade Parameter Symbol Min DC Accuracy with PGA Output Selected, Line Level Input Interchannel Gain Mismatch Gain Error Gain Drift (Note 22) (Note 21) IOUT RL CL -0.1dB 100 - Automotive Grade Min - Typ 0.1 ±5 ±100 0.3 ±5 ±300 0.1 Max - Typ 0.1 ±5 ±100 0.3 ±5 ±300 0.1 Max +0.1dB 1 20 Unit dB % ppm/°C dB % ppm/°C dB ppm/°C dB deg μA kΩ pF DC Accuracy with PGA Output Selected, Mic Level Input Interchannel Gain Mismatch Gain Error Gain Drift DC Accuracy with DAC Output Selected Interchannel Gain Mismatch Gain Drift ±100 180 - ±100 180 - Analog Output Frequency Response 10 Hz to 20 kHz Analog In to Analog Out Phase Shift DC Current draw from an AUXOUT pin AC-Load Resistance Load Capacitance +0.1dB -0.1dB 1 100 20 - 21. Valid only when PGA output is selected. 22. Guaranteed by design. DS656F2 19 CS4245 DC ELECTRICAL CHARACTERISTICS AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode. Parameter Power Supply Current (Normal Operation) VA = 5 VA = 3.3 VD, VLS, VLC = 5 VD, VLS, VLC = 3.3 V V V V Symbol IA IA ID ID IA ID PSRR VQ1 (Note 25) IQ1 ZQ1 VQ2 (Note 25) IQ2 ZQ2 FILT1+ FILT2+ MICBIAS IMB Min - Typ 41 37 39 23 0.50 0.54 400 198 4.2 55 0.5 x VA 23 0.5 x VA 4.5 VA VA 0.8 x VA - Max 50 45 47 28 485 241 1 1 2 Unit mA mA mA mA mA mA mW mW mW dB VDC μA kΩ VDC μA kΩ VDC VDC VDC mA Power Supply Current (Power-Down Mode) (Note 23) Power Consumption (Normal Operation) (Power-Down Mode) VA = 5 V VLS, VLC, VD=5 V VA, VD, VLS, VLC = 5 V VA, VD, VLS, VLC = 3.3 V VA, VD, VLS, VLC = 5 V (Note 24) Power Supply Rejection Ratio (1 kHz) VQ Characteristics Quiescent Voltage 1 DC Current from VQ1 VQ1 Output Impedance Quiescent Voltage 2 DC Current from VQ2 VQ2 Output Impedance FILT1+ Nominal Voltage FILT2+ Nominal Voltage Microphone Bias Voltage Current from MICBIAS 23. Power-Down Mode is defines as RESET = Low with all clock and data lines held static and no analog input. 24. Valid with the recommended capacitor values on FILT1+, FILT2+, VQ1 and VQ2 as shown in the Typical Connection Diagram. 25. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors. 20 DS656F2 CS4245 DIGITAL INTERFACE CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 1.71 V to 5.25 V. Parameters (Note 26) High-Level Input Voltage VL = 1.71 V VL > 2.0 V Low-Level Input Voltage High-Level Output Voltage at Io = 2 mA Serial Port Control Port Serial Port Control Port Serial Port Control Port Serial Port Control Port MUTEC Serial Port Control Port MUTEC (Note 27) VIH VIH VIH VIH VIL VIL VOH VOH VOH VOL VOL VOL Iin 0.8xVLS 0.8xVLC 0.7xVLS 0.7xVLC VLS-1.0 VLC-1.0 VA-1.0 10 ------------------LRCK 1 6 Symbol Min Typ 3 - Max 0.2xVLS 0.2xVLC 0.4 0.4 0.4 ±10 1 - Units V V V V V V V V V V V V μA pF mA μs Low-Level Output Voltage at Io = 2 mA Input Leakage Current Input Capacitance Maximum MUTEC Drive Current Minimum OVFL Active Time 26. Serial Port signals include: MCLK1, MCLK2, SCLK1, SCLK2, LRCK1, LRCK2, SDIN, SDOUT. Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, RESET, INT, OVFL. 27. Guaranteed by design. DS656F2 21 CS4245 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 1 Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, CL = 20 pF. (Note 28) Parameter Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Symbol Fs Fs Fs fmclk tclkhl Min 4 50 100 1.024 8 -10 0 40 Typ 50 50 50 - Max 50 100 200 51.200 10 36 60 - Unit kHz kHz kHz MHz ns % % ns ns % ns MCLK Specifications MCLK1 Input Frequency MCLK1 Input Pulse Width High/Low Master Mode LRCK1 Duty Cycle SCLK1 Duty Cycle SCLK1 falling to LRCK1 edge SCLK1 falling to SDOUT valid tslr tsdo Slave Mode LRCK1 Duty Cycle SCLK1 Period Single-Speed Mode tsclkw tsclkw tsclkw tsclkh tsclkl tslr tsdo 10 -------------------( 128 ) Fs 10 ----------------( 64 ) Fs 10 ----------------( 64 ) Fs 30 48 -10 0 9 9 9 Double-Speed Mode - - ns Quad-Speed Mode SCLK1 Pulse Width High SCLK1 Pulse Width Low SCLK1 falling to LRCK1 edge SCLK1 falling to SDOUT valid - 10 36 ns ns ns ns ns 28. See Figure 3 and Figure 4 on page 23. 22 DS656F2 CS4245 LRCK1 Output t SCLK1 Output t SDOUT sdo slr Figure 3. Master Mode Timing - Serial Audio Port 1 LRCK1 Input t SCLK1 Input t SDOUT sdo t sclkw t sclkh t slr sclkl Figure 4. Slave Mode Timing - Serial Audio Port 1 DS656F2 23 CS4245 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 2 Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, CL = 20 pF. (Note 29) Parameter Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Symbol Fs Fs Fs fmclk tclkhl Min 4 50 100 1.024 8 -10 16 20 40 Typ 50 50 50 - Max 50 100 200 51.200 10 60 - Unit kHz kHz kHz MHz ns % % ns ns ns % ns MCLK Specifications MCLK2 Input Frequency MCLK2 Input Pulse Width High/Low Master Mode LRCK2 Duty Cycle SCLK2 Duty Cycle SCLK2 falling to LRCK edge SDIN valid to SCLK2 rising setup time SCLK2 rising to SDIN hold time tslr tsdis tsdih Slave Mode LRCK2 Duty Cycle SCLK2 Period Single-Speed Mode tsclkw tsclkw tsclkw tsclkh tsclkl tslr tsdis tsdih 10 -------------------( 128 ) Fs 10 ----------------( 64 ) Fs 10 ----------------( 64 ) Fs 30 48 -10 16 20 9 9 9 Double-Speed Mode - - ns Quad-Speed Mode SCLK2 Pulse Width High SCLK2 Pulse Width Low SCLK2 falling to LRCK2 edge SDIN valid to SCLK2 rising setup time SCLK2 rising to SDIN hold time - 10 - ns ns ns ns ns ns 29. See Figure 5 and Figure 6 on page 25. 24 DS656F2 CS4245 LRCK2 Output t SCLK2 Output t SDIN sdis t slr sdih Figure 5. Master Mode Timing - Serial Audio Port 2 LRCK2 Input t SCLK2 Input t sclkw t SDIN sdis t sdih t sclkh t slr sclkl Figure 6. Slave Mode Timing - Serial Audio Port 2 DS656F2 25 CS4245 LRCK SCLK SDATA Channel A - Left Channel B - Right MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 7. Format 0, Left-Justified up to 24-Bit Data LRCK SCLK SDATA Channel A - Left Channel B - Right MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 8. Format 1, I²S up to 24-Bit Data LRCK SCLK Channel A - Left Channel B - Right SDATA LSB MSB -1 -2 -3 -4 -5 -6 +6 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 -5 -6 +6 +5 +4 +3 +2 +1 LSB Figure 9. Format 2, Right-Justified 16-Bit Data. Format 3, Right-Justified 24-Bit Data. 26 DS656F2 CS4245 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF. Parameter SCL Clock Frequency RESET Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 31) (Note 31) (Note 30) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trd tfc, tfd tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 1000 Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns 30. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 31. Guaranteed by design. RST t Stop irs Start R e p e ate d Sta rt t rd t fd Stop SDA t buf t hdst t high t hdst t fc t susp SCL t t t sud t ack t sust t rc lo w hdd Figure 10. Control Port Timing - I²C Format DS656F2 27 CS4245 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF. Parameter CCLK Clock Frequency RESET Rising Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 33) (Note 33) (Note 32) Symbol fsck tsrs tcsh tcss tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2 Min 500 1.0 20 66 66 40 15 - Max 6.0 50 25 25 100 100 Units MHz ns μs ns ns ns ns ns ns ns ns ns ns 32. Data must be held for sufficient time to bridge the transition time of CCLK. 33. For fsck