CDB4270

CS4270 24-Bit, 192 kHz Stereo Audio CODEC D/A Features High Performance – – 105 dB Dynamic Range -95 dB THD+N A/D Features High Performance – 105 dB Dynamic Range – -95 dB THD+N Multi-bit ∆Σ Conversion High-Pass Filter to Remove DC Offsets Selectable Serial Audio Interface Formats – Left-Justified up to 24-bit – I²S up to 24-bit Single-Ended Input Selectable Serial Audio Interface Formats – – – Left-Justified up to 24-bit I²S up to 24-bit Right-Justified 16-, and 24-Bit Control Output for External Muting On-Chip Digital De-Emphasis Popguard® Technology System Features Direct Interface with Logic Levels 1.8 V to 5 V Internal Digital Loopback Stand-Alone or Control Port Functionality Single-Ended Analog Architecture Supports all Audio Sample Rates from 4 kHz to 216 kHz 3.3 V or 5 V Core Supply Digital Supply 3.3 V to 5 V Analog Supply 3.3 V to 5 V Multi-bit ∆Σ Conversion Digital Volume Control Single-Ended Output Control Port Supply 1.8 V to 5 V Level Translator Hardware Mode or I2C/SPI Software Mode Control Data Register/Hardware Configuration Internal Voltage Reference Reset External Mute Control 2 Mute Signals PCM Serial Audio Input Serial Interface 2 Volume Controls Digital Filters Multi-bit ∆Σ Modulators Switch-Cap DAC and Analog Filters 2 Single-Ended Outputs PCM Serial Audio Output 2 High-Pass Filter Digital Filters Switch-Cap ADC 2 Single-Ended Inputs Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) MAY '06 DS686PP1 CS4270 Stand-Alone Mode Feature Set System Features – – Serial Audio Port Master or Slave Operation Single-, Double-, or Quad-Speed Operation General Description The CS4270 is a high-performance, integrated audio CODEC. The CS4270 performs stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 216 kHz. Standard 50/15 µs de-emphasis is available for sampling rates of 44.1 kHz for compatibility with digital audio programs mastered using the 50/15 µs pre-emphasis technique. Integrated level translators allow easy interfacing between the CS4270 and other devices operating over a wide range of logic levels. Independently addressable high-pass filters are available for the right and left channel of the A/D. This allows the A/D to be used in a wide variety of applications where one audio channel and one DC measurement channel is desired. The CS4270 is available in a 24-pin TSSOP package in both Commercial (-10° to +70° C) and Automotive grades (-40° to +85° C). The CDB4270 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 47 for complete ordering information. The CS4270’s wide dynamic range, negligible distortion, and low noise make it ideal for applications such as DVD-recorders, digital televisions, set-top boxes, effects processors, and automotive audio systems. D/A Features – – – Auto-Mute on Static Samples 44.1 kHz 50/15 µs De-emphasis Available Selectable Serial Audio Interface Formats • • Left-Justified up to 24-bit I²S up to 24-bit A/D Features – – High-Pass Filter Selectable Serial Audio Interface Formats • • Left-Justified up to 24-bit I²S up to 24-bit Software Mode Feature Set System Features – – Serial Audio Port Master or Slave Operation Internal Digital Loopback Available D/A Features – – – – – Selectable Auto-mute 44.1-kHz De-emphasis Filters Configurable Muting Controls Volume Control Selectable Serial Audio Interface Formats • • • Left-Justified up to 24-bit I²S up to 24-bit Right-Justified 16, and 24-bit A/D Features – – Selectable High-Pass Filter or DC Offset Calibration Selectable Serial Audio Interface Formats • • Left-Justified up to 24-bit I²S up to 24-bit 2 DS686PP1 CS4270 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE MODE ........................................................................................... 6 2. PIN DESCRIPTIONS - STAND-ALONE MODE ..................................................................................... 7 3. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 8 4. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 9 SPECIFIED OPERATING CONDITIONS ............................................................................................... 9 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 9 THERMAL CHARACTERISTICS ............................................................................................................ 9 DAC ANALOG CHARACTERISTICS - COMMERCIAL GRADE .......................................................... 10 DAC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE .......................................................... 10 DAC ANALOG CHARACTERISTICS - ALL MODES ........................................................................... 11 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 12 ADC ANALOG CHARACTERISTICS - COMMERCIAL GRADE .......................................................... 13 ADC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE .......................................................... 14 ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 15 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 16 DIGITAL CHARACTERISTICS ............................................................................................................. 16 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................... 17 SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT ..................................................... 20 SWITCHING CHARACTERISTICS - SPITM CONTROL PORT .......................................................... 21 5. APPLICATIONS ................................................................................................................................... 22 5.1 Stand-Alone Mode ......................................................................................................................... 22 5.1.1 Recommended Power-Up Sequence .................................................................................... 22 5.1.2 Master/Slave Mode ............................................................................................................... 22 5.1.3 System Clocking .................................................................................................................... 22 5.1.4 Clock Ratio Selection ............................................................................................................ 23 5.1.5 Interpolation Filter ................................................................................................................. 23 5.1.6 High-Pass Filter ..................................................................................................................... 23 5.1.7 Mode Selection & De-Emphasis ............................................................................................ 24 5.1.8 Serial Audio Interface Format Selection ................................................................................ 24 5.2 Control Port Mode ......................................................................................................................... 24 5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode ................................... 24 5.2.2 Master / Slave Mode Selection .............................................................................................. 24 5.2.3 System Clocking .................................................................................................................... 25 5.2.4 Clock Ratio Selection ............................................................................................................ 25 5.2.5 Internal Digital Loopback ....................................................................................................... 26 5.2.6 Auto-Mute .............................................................................................................................. 26 5.2.7 High-Pass Filter and DC Offset Calibration ........................................................................... 26 5.2.8 De-Emphasis ......................................................................................................................... 27 5.2.9 Oversampling Modes ............................................................................................................ 27 5.3 De-Emphasis Filter ........................................................................................................................ 27 5.4 Analog Connections ...................................................................................................................... 28 5.4.1 Input Connections ................................................................................................................. 28 5.4.2 Output Connections ............................................................................................................... 30 5.5 Mute Control .................................................................................................................................. 30 5.6 Synchronization of Multiple Devices .............................................................................................. 31 5.7 Grounding and Power Supply Decoupling .................................................................................... 31 6. CONTROL PORT INTERFACE ............................................................................................................ 32 6.1 SPI™ Mode ................................................................................................................................... 32 6.2 I²C® Mode ...................................................................................................................................... 33 7. REGISTER QUICK REFERENCE ........................................................................................................ 34 8. REGISTER DESCRIPTION .................................................................................................................. 35 8.1 Chip ID - Address 01h ................................................................................................................... 35 DS686PP1 3 CS4270 8.2 Power Control - Address 02h ........................................................................................................ 35 8.2.1 Freeze (Bit 7) ......................................................................................................................... 35 8.2.2 PDN_ADC (Bit 5) ................................................................................................................... 35 8.2.3 PDN_DAC (Bit 1) ................................................................................................................... 35 8.2.4 Power Down (Bit 0) ............................................................................................................... 35 8.3 Mode Control - Address 03h ......................................................................................................... 36 8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4) ...................................................... 36 8.3.2 Ratio Select (Bits 3:1) ............................................................................................................ 36 8.3.3 PopguardTM Disable (Bit 0) .................................................................................................. 36 8.4 ADC and DAC Control - Address 04h ........................................................................................... 36 8.4.1 ADC HPF Freeze A (Bit 7) .................................................................................................... 36 8.4.2 ADC HPF Freeze B (Bit 6) .................................................................................................... 37 8.4.3 Digital Loopback (Bit 5) ......................................................................................................... 37 8.4.4 DAC Digital Interface Format (Bits 4:3) ................................................................................. 37 8.4.5 ADC Digital Interface Format (Bit 0) ...................................................................................... 37 8.5 Transition Control - Address 05h ................................................................................................... 38 8.5.1 DAC Single Volume (Bit 7) .................................................................................................... 38 8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ........................................................................... 38 8.5.3 Invert Signal Polarity (Bits 4:1) .............................................................................................. 38 8.5.4 De-Emphasis Control (Bit 0) .................................................................................................. 39 8.6 Mute Control - Address 06h .......................................................................................................... 39 8.6.1 Auto-Mute (Bit 5) ................................................................................................................... 39 8.6.2 ADC Channel A & B Mute (Bits 4:3) ...................................................................................... 39 8.6.3 Mute Polarity (Bit 2) ............................................................................................................... 39 8.6.4 DAC Channel A & B Mute (Bits 1:0) ...................................................................................... 39 8.7 DAC Channel A Volume Control - Address 07h ............................................................................ 40 8.8 DAC Channel B Volume Control - Address 08h ............................................................................ 40 9. FILTER PLOTS ................................................................................................................................ 41 10. PARAMETER DEFINITIONS .............................................................................................................. 45 11. PACKAGE DIMENSIONS .................................................................................................................. 46 12. ORDERING INFORMATION .............................................................................................................. 47 13. REVISION HISTORY .......................................................................................................................... 47 LIST OF FIGURES Figure 1. CS4270 Typical Connection Diagram .......................................................................................... 8 Figure 2. Output Test Load ....................................................................................................................... 11 Figure 3. Maximum Loading ...................................................................................................................... 11 Figure 4. Master Mode, Left-Justified SAI ................................................................................................. 18 Figure 5. Slave Mode, Left-Justified SAI ................................................................................................... 18 Figure 6. Master Mode, I²S SAI ................................................................................................................. 18 Figure 7. Slave Mode, I²S SAI ................................................................................................................... 18 Figure 8. Master and Slave Mode SDIN vrs. SCLK .................................................................................. 18 Figure 9. Format 0, Left-Justified up to 24-Bit Data .................................................................................. 19 Figure 10. Format 1, I²S up to 24-Bit Data ................................................................................................ 19 Figure 11. Format 2, Right-Justified 16-Bit Data. (Available in Control Port Mode only) Format 3, Right-Justified 24-Bit Data. (Available in Control Port Mode only) ........................................... 19 Figure 12. I²C Mode Control Port Timing .................................................................................................. 20 Figure 13. SPI Control Port Timing ........................................................................................................... 21 Figure 14. De-Emphasis Curve ................................................................................................................. 27 Figure 15. CS4270 Recommended Analog Input Network ....................................................................... 28 Figure 16. A/D THD+N Performance vrs. Input Source Resistance ......................................................... 28 Figure 17. A/D Dynamic Range vrs. Input Source Resistance ................................................................. 29 Figure 18. CS4270 Example Analog Input Network .................................................................................. 30 4 DS686PP1 CS4270 Figure 19. CS4270 Recommended Analog Output Filter .......................................................................... 30 Figure 20. Suggested Active-Low Mute Circuit ......................................................................................... 31 Figure 21. Control Port Timing, SPI Mode ................................................................................................ 32 Figure 22. Control Port Timing, I²C Mode ................................................................................................. 33 Figure 23. De-Emphasis Curve ................................................................................................................. 39 Figure 24. DAC Single-Speed Stopband Rejection .................................................................................. 41 Figure 25. DAC Single-Speed Transition Band ......................................................................................... 41 Figure 26. DAC Single-Speed Transition Band (detail) ............................................................................. 41 Figure 27. DAC Single-Speed Passband Ripple ....................................................................................... 41 Figure 28. DAC Double-Speed Stopband Rejection ................................................................................. 41 Figure 29. DAC Double-Speed Transition Band ....................................................................................... 41 Figure 30. DAC Double-Speed Transition Band (detail) ........................................................................... 42 Figure 31. DAC Double-Speed Passband Ripple ..................................................................................... 42 Figure 32. DAC Quad-Speed Stopband Rejection .................................................................................... 42 Figure 33. DAC Quad-Speed Transition Band .......................................................................................... 42 Figure 34. DAC Quad-Speed Transition Band (detail) .............................................................................. 42 Figure 35. DAC Quad-Speed Passband Ripple ........................................................................................ 42 Figure 36. ADC Single-Speed Stopband Rejection .................................................................................. 43 Figure 37. ADC Single-Speed Stopband (detail) ...................................................................................... 43 Figure 38. ADC Single-Speed Transition Band (detail) ............................................................................. 43 Figure 39. ADC Single-Speed Passband Ripple ....................................................................................... 43 Figure 40. ADC Double-Speed Stopband Rejection ................................................................................. 43 Figure 41. ADC Double-Speed Stopband (detail) ..................................................................................... 43 Figure 42. ADC Double-Speed Transition Band (detail) ........................................................................... 44 Figure 43. ADC Double-Speed Passband Ripple ..................................................................................... 44 Figure 44. ADC Quad-Speed Stopband Rejection .................................................................................... 44 Figure 45. ADC Quad-Speed Stopband (detail) ........................................................................................ 44 Figure 46. ADC Quad-Speed Transition Band (detail) .............................................................................. 44 Figure 47. ADC Quad-Speed Passband Ripple ........................................................................................ 44 LIST OF TABLES Table 1. Speed Modes .............................................................................................................................. Table 2. Clock Ratios - Stand-Alone Mode ............................................................................................... Table 3. CS4270 Stand-Alone Mode Control............................................................................................ Table 4. Speed Modes .............................................................................................................................. Table 5. Clock Ratios - Control Port Mode................................................................................................ Table 6. Analog Input Design Parameters ................................................................................................ Table 7. Memory Address Pointer............................................................................................................. Table 8. Functional Mode Selection.......................................................................................................... Table 9. MCLK Divider Configuration........................................................................................................ Table 10. DAC Digital Interface Formats .................................................................................................. Table 11. ADC Digital Interface Formats .................................................................................................. Table 12. Soft Cross or Zero Cross Mode Selection................................................................................. Table 13. Digital Volume Control .............................................................................................................. 22 23 24 25 25 29 33 36 36 37 37 38 40 DS686PP1 5 CS4270 1. PIN DESCRIPTIONS - SOFTWARE MODE SDIN LRCK MCLK SCLK VD DGND SDOUT VLC SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST AD2 Pin Name SDIN LRCK MCLK SCLK VD DGND SDOUT VLC SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN AD2 RST AINA AINB VQ FILT+ VA AGND MUTEA MUTEB AOUTA AOUTB # 1 Pin Description Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Digital Power (Input) - Positive power supply for the digital section. Digital Ground (Input) - Ground reference for the internal digital section. Serial Audio Data Output (Output) - Output for two’s complement serial audio data. Control Port Power (Input) - Determines the signal level for the Control Port. Serial Control Data (Input/Output) - SDA is a data I/O in I²C® Mode. CDOUT is the output data line for the Control Port interface in SPI® Mode. Serial Control Port Clock (Input) - Serial clock for the serial Control Port. Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode. CS is the chip select signal for SPI format. Address Bit 1 (I²C) / Serial Control Data (Input) - AD1 is a chip address pin in I²C Mode. CDIN is the input data line for the Control Port interface in SPI Mode. Address Bit 2 (I²C) (Input) - AD2 is a chip address pin in I²C Mode. Reset (Input) - The device enters a low power mode when low. Analog Input (Input) - The full-scale analog input level is specified in the ADC Analog Characteristics specification table. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Analog Power (Input) - Positive power for the analog sections. Analog Ground (Input) - Ground reference. Must be connected to analog ground. Mute Control (Output) - Each pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down. Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 24 22 23 6 DS686PP1 CS4270 2. PIN DESCRIPTIONS - STAND-ALONE MODE SDIN LRCK MCLK SCLK VD DGND SDOUT VLC M1 M0 I²S/LJ MDIV1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST MDIV2 Pin Name SDIN LRCK MCLK SCLK VD DGND SDOUT (M/S) VLC M1 M0 I²S/LJ MDIV1 MDIV2 RST AINA AINB VQ FILT+ VA AGND MUTEA MUTEB AOUTA AOUTB # 1 Pin Description Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Digital Power (Input) - Positive power supply for the digital section. Digital Ground (Input) - Ground reference for the internal digital section. Serial Audio Data Output (Output) - Output for two’s complement serial audio data. This pin must be pulled-up or pulled-down to select Master or Slave Mode. Control Port Power (Input) - Determines the signal level for the Control Port. Mode Selection (Input) - Determines the operational mode of the device. Serial Audio Interface Select (Input) - Selects either the Left-Justified or I²S format for the Serial Audio Interface. MCLK Divide (Input) - Configures MCLK divider to divide by 1, 1.5, 2, or 4. Reset (Input) - The device enters a low power mode when low. Analog Input (Input) - The full-scale analog input level is specified in the ADC Analog Characteristics specification table. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Analog Power (Input) - Positive power for the analog sections. Analog Ground (Input) - Ground reference. Must be connected to analog ground. Mute Control (Output) - Each pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down. Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 24 22 23 DS686PP1 7 CS4270 3. TYPICAL CONNECTION DIAGRAM +3.3 V to 5 V 0.1 µF 1 µF 5.1 Ω 1. 0.1 µF 1 µF +3.3 V to 5 V VA FILT+ 47 µF 0.1 µF 1. VD 2. GND or VD AGND 10 µF 0.1 µF 47 kΩ VQ Analog Input Network (see Figures 12 & 13) SDOUT (M/ S) SDIN Audio Data Processor AINA AINB MCLK Timing Logic & Clock CS4270 AD2 (MDIV1) Power Down and Mode Settings (Control Port) AD1 (MDIV2) AD0 / CS (I2S/LJ) SDA / CDIN (M1) SCL / CCLK (M0) RST SCLK LRCK MUTEA AOUTA AOUTB MUTEB Analog Conditioning & Mute (see Figures 14 & 15) 2 kΩ +1.8 V to 5 V 3. 2 kΩ 3. VLC DGND 1. If using separate supplies for VA and VD, 5.1 Ω resistor not needed. See "Grounding and Power Supply Decoupling." 2. Use a 47 kΩ pull-down to select Slave Mode or 47 k Ω pull-up to VD to select Master Mode. See "Master/Slave Mode Selection." 3. Use pull-up resistors in Software Mode. In Hardware Mode, use pull-up or pull-down. See "Mode Selection & De-Emphasis." Figure 1. CS4270 Typical Connection Diagram 8 DS686PP1 CS4270 4. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.) SPECIFIED OPERATING CONDITIONS (AGND = 0 V; all voltages with respect to ground.) Parameters Analog Digital Control Port Interface Ambient Operating Temperature (Power Applied) Commercial Automotive DC Power Supplies: Symbol VA VD VLC TA Min 3.1 3.1 1.7 -10 -40 Nom 5.0 3.3 3.3 - Max 5.25 5.25 5.25 +70 +85 Units V V V °C °C ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V, All voltages with respect to ground.) (Note 1) Parameter DC Power Supplies: Symbol Analog Digital Control Port Interface (Note 2) Control Port Interface Digital Interface VA VD VLC Iin VIN VIND-C VIND-D TAC Tstg Min -0.3 -0.3 -0.3 -10 AGND-0.7 -0.3 -0.3 -50 -65 Typ - Max +6.0 +6.0 +6.0 +10 VA+0.7 VLC+0.3 VD+0.3 +95 +150 Units V V V mA V V V °C °C Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SRC latch-up. THERMAL CHARACTERISTICS Parameters Allowable Junction Temperature Junction to Ambient Thermal Impedance (Note 3) Symbol Min - Typ 70 105 Max 135 - Units °C °C/W °C/W (Multi-layer PCB) TSSOP (Single-layer PCB) TSSOP θJA-M θJA-S 3. θJA is specified according to JEDEC specifications for multi-layer PCBs. DS686PP1 9 CS4270 DAC ANALOG CHARACTERISTICS - COMMERCIAL GRADE (Full-Scale Output Sine Wave, 997 Hz (Note 4), Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 10 pF (see Figure 2). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.) VA = 5 V Parameter Dynamic Range 18 to 24-Bit A-weighted 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit VA = 3.3 V Max -83 -70 -30 -81 -61 -21 Min 97 94 90 87 Typ 103 100 96 93 -89 -76 -36 -87 -67 -27 Max -83 -70 -30 -81 -61 -21 Unit dB dB dB dB dB dB dB dB dB dB Min unweighted A-weighted unweighted 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 99 96 90 87 - Typ 105 102 96 93 -89 -76 -36 -87 -67 -27 16-Bit DAC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE (Full-Scale Output Sine Wave, 997 Hz (Note 4), Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 10 pF (see Figure 2). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.) VA = 5 V Parameter Dynamic Range 18 to 24-Bit A-weighted 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit VA = 3.3 V Max -79 -66 -26 -77 -57 -17 Min 93 90 86 83 Typ 103 100 96 93 -89 -76 -36 -87 -67 -27 Max -79 -66 -26 -77 -57 -17 Unit dB dB dB dB dB dB dB dB dB dB Min unweighted A-weighted unweighted 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 95 92 86 83 - Typ 105 102 96 93 -89 -76 -36 -87 -67 -27 16-Bit 4. One-half LSB of triangular PDF dither added to data. 10 DS686PP1 CS4270 DAC ANALOG CHARACTERISTICS - ALL MODES Parameter Interchannel Isolation Symbol (1 kHz) Min -100 0.6•VA Typ 100 0.1 Max 0.25 +100 Unit dB dB ppm/°C Vpp µA kΩ pF Ω DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Full Scale Output Voltage Max DC Current draw from AOUTA or AOUTB Max AC-Load Resistance (see Figure 3) Max Load Capacitance (see Figure 3) Output Impedance of AOUTA and AOUTB 0.65•VA 10 3 100 100 0.7•VA - IOUTmax RL CL ZOUT - 3.3 µF Capacitive Load -- C (pF) L 125 100 75 50 25 Safe Operating Region AOUTx R C V out L L AGND 2.5 3 5 10 15 20 Resistive Load -- RL (kΩ ) Figure 2. Output Test Load Figure 3. Maximum Loading DS686PP1 11 CS4270 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) (See Note 5) Parameter Single-Speed Mode Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 8) (Note 7) Symbol to -0.1 dB corner to -3 dB corner Min 0 0 -.175 .5465 50 Typ 10/Fs 5/Fs 2.5/Fs Max .35 .4992 +.01 +1.5/+0 +.05/-.25 -.2/-.4 .22 .501 +.15 0.110 0.469 +0 - Unit Fs Fs dB Fs dB s dB dB dB Fs Fs dB Fs dB s Fs Fs dB Fs dB s tgd Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.1 dB corner to -3 dB corner 0 0 -.15 .5770 Double-Speed Mode Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay (Note 7) 55 tgd 0 0 -.12 0.7 Quad-Speed Mode Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay (Note 7) to -0.1 dB corner to -3 dB corner 51 tgd - 5. Amplitude vs. Frequency plots of this data are available in Section 9. “Filter Plots” on page 41. See Figures 24 through 47. 6. Response is clock dependent and will scale with Fs. 7. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs. 8. De-emphasis is available only in Single-Speed Mode. 12 DS686PP1 CS4270 ADC ANALOG CHARACTERISTICS - COMMERCIAL GRADE Measurement bandwidth is 10 Hz to 20 kHz unless otherwise specified. Figure 18 input circuit, 1 kHz sine wave in. Dynamic Performance for Commercial Grade Single-Speed Mode Dynamic Range Total Harmonic Distortion + Noise VA = 5 V VA = 3.3 V Fs = 48 kHz A-weighted unweighted (Note 9) Symbol Min 99 96 Typ 105 102 -95 -82 -42 Max -90 - Min 96 93 - Typ 102 99 -92 -79 -39 Max -87 - Unit dB dB dB dB dB THD+N - -1 dB -20 dB -60 dB Double-Speed Mode Dynamic Range Fs = 96 kHz 99 96 THD+N -95 -82 -42 -95 -90 -92 -79 -39 -87 -87 dB dB dB dB 105 102 99 96 93 102 99 96 dB dB dB A-weighted unweighted 40 kHz bandwidth unweighted (Note 9) Total Harmonic Distortion + Noise 40 kHz bandwidth Quad-Speed Mode Dynamic Range -1 dB -20 dB -60 dB -1 dB Fs = 192 kHz 99 96 THD+N -95 -82 -42 -95 -90 -92 -79 -39 -87 -87 dB dB dB dB 105 102 99 96 93 102 99 96 dB dB dB A-weighted unweighted 40 kHz bandwidth unweighted (Note 9) Total Harmonic Distortion + Noise 40 kHz bandwidth -1 dB -20 dB -60 dB -1 dB Dynamic Performance for Commercial Grade - All Modes Parameter Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Analog Input Characteristics Full-Scale Input Voltage Input Impedance 0.53*VA 0.56*VA 300 0.58*VA Vpp -3 0.1 +3 dB % Min Typ 90 Max Unit dB ±100 ppm/°C kΩ 9. Referred to the typical full-scale input voltage. DS686PP1 13 CS4270 ADC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Figure 18 input circuit, 1 kHz sine wave in. Dynamic Performance for Automotive Grade Single-Speed Mode Dynamic Range Total Harmonic Distortion + Noise VA = 5 V Symbol Min 97 94 THD+N -95 -82 -42 -90 Typ 105 102 Max Min 94 91 VA = 3.3 V Typ 102 99 -92 -79 -39 Max -87 Unit dB dB dB dB dB Fs = 48 kHz A-weighted unweighted (Note 10) -1 dB -20 dB -60 dB Double-Speed Mode Dynamic Range Fs = 96 kHz 97 94 THD+N -95 -82 -42 -95 -90 -92 -79 -39 -87 -87 dB dB dB dB 105 102 99 94 91 102 99 96 dB dB dB A-weighted unweighted 40 kHz bandwidth unweighted (Note 10) Total Harmonic Distortion + Noise 40 kHz bandwidth Quad-Speed Mode Dynamic Range -1 dB -20 dB -60 dB -1 dB Fs = 192 kHz 97 94 THD+N -95 -82 -42 -95 -90 -92 -79 -39 -87 -87 dB dB dB dB 105 102 99 94 91 102 99 96 dB dB dB A-weighted unweighted 40 kHz bandwidth unweighted (Note 10) Total Harmonic Distortion + Noise 40 kHz bandwidth -1 dB -20 dB -60 dB -1 dB Dynamic Performance for Automotive Grade - All Modes Parameter Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Analog Input Characteristics Full-Scale Input Voltage Input Impedance 0.53*VA 0.56*VA 300 0.58*VA Vpp -3 0.1 +3 dB % Min Typ 90 Max Unit dB ±100 ppm/°C kΩ 10. Referred to the typical full-scale input voltage. 14 DS686PP1 CS4270 ADC DIGITAL FILTER CHARACTERISTICS (Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified) (Note 11) Parameter Single-Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Group Delay (Note 12) (-0.1 dB) (Note 12) Symbol Min 0 0.57 70 Typ 12/Fs 9/Fs 5/Fs 1 20 10 - Max 0.49 0.035 0.49 0.05 0.26 0.05 0 Unit Fs dB Fs dB s Fs dB Fs dB s Fs dB Fs dB s Hz Hz deg dB tgd (-0.1 dB) (Note 12) (Note 12) 0 0.56 69 Double-Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Group Delay tgd (-0.1 dB) (Note 12) (Note 12) 0 0.50 60 Quad-Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Group Delay tgd -3.0 dB -0.13 dB @ 20 Hz - High-Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple (Note 13) (Note 13) - 11. Plots of this data are contained in Section 9. “Filter Plots” on page 41. See Figures 24 through 47. 12. The filter frequency response scales precisely with Fs. 13. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. DS686PP1 15 CS4270 DC ELECTRICAL CHARACTERISTICS (TA = 25° C; AGND=DGND=0, all voltages with respect to ground; MLCK=12.288 MHz; Master Mode) Parameter Power Supply Power Supply Current (Normal Operation) Symbol VA = 5 V VA = 3.3 V VD, VLC = 5 V VD, VLC = 3.3 V VA = 5 V VD, VLC = 5 V IA IA ID ID IA ID PSRR VQ Min - Typ 31 27 29 20 1.51 0.45 221 255 9.8 55 VA/2 1 25 VA 10 18 0 VA 3 Max 40 35 38 29 296 323 - Unit mA mA mA mA mA mA mW mW mW dB VDC µA kΩ VDC µA kΩ V V mA Power Supply Current (Power-Down Mode) (Note 14) Power Consumption VA = 5 V, VD = VLC= 3.3 V VA = 5 V, VD = VLC = 5 V Normal Operation Normal Operation Power-Down Mode (Note 14) (Note 15) Power Supply Rejection Ratio (1 kHz) Common Mode Voltage Nominal Common Mode Voltage Maximum DC Current Source/Sink from VQ VQ Output Impedance Positive Voltage Reference FILT+ Nominal Voltage Maximum DC Current Source/Sink from FILT+ FILT+ Output Impedance FILT+ - Mute Control MUTEA, MUTEB Low-Level Output Voltage MUTEA, MUTEB High-Level Output Voltage Maximum MUTEA & MUTEB Drive Current 14. Power Down Mode is defined as RST = Low with all clocks and data lines held static. 15. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram. DIGITAL CHARACTERISTICS Parameter (Note 16) High-Level Input Voltage Low-Level Input Voltage Symbol Serial Port Control Port Serial Port Control Port Serial Port Control Port MUTEA, MUTEB VIH VIL VOH Min 0.7xVD 0.7xVLC VD - 1.0 VLC - 1.0 VA - 1.0 -10 Typ - Max 0.2xVD 0.2xVLC 0.4 10 Units V V V V V V V V µA High-Level Output Voltage at Io = 2 mA Low-Level Output Voltage at Io = 2 mA Input Leakage Current VOL Iin 16. Serial Port signals include: SCLK, LRCK, SDOUT, SDIN Control Port signals include: SDA/CDOUT, SCL/CCLK, AD1/CDIN, AD0/CS, RST 16 DS686PP1 CS4270 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = AGND = 0 V; Logic "1" = VD, CL = 20 pF) Parameter Sample Rate Symbol Single-Speed Mode Double-Speed Mode Quad-Speed Mode tand-Alone Mode Control Port Mode Fs Fs Fs fmclk fmclk Min 4 50 100 1.024 1.024 40 - Typ 50 50 1 ----------------( 64 ) Fs Max 54 108 216 55.296 55.296 60 20 32 60 55 20 - Unit kHz kHz kHz MHz MHz ns % s % ns ns ns ns % s s s ns ns ns ns ns ns MCLK Specifications MCLK Frequency (Note 17) MCLK Duty Cycle Master Mode LRCK Duty Cycle SCLK Period (Note 18) SCLK Duty Cycle SCLK falling to LRCK edge SCLK falling to SDOUT valid SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time tsclkw - 50 50 50 - tmslr tsdo tsdis tsdih -20 16 20 40 Slave Mode LRCK Duty Cycle SCLK Period (Note 17) Single-Speed Mode Double-Speed Mode Quad-Speed Mode tsclkw tsclkw tsclkw 1 -------------------( 128 ) Fs 1 ----------------( 64 ) Fs 1 ----------------( 64 ) Fs SCLK Duty Cycle SCLK falling to LRCK edge SDOUT valid before SCLK rising SDOUT valid after SCLK rising SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time tslrd tstp thld tsdis tsdih 45 -20 10 5 16 20 17. In Control Port Mode, MCLK Frequency and Functional Mode Select bits must be configured according to Table 5, Table 8, and Table 12. 18. tsclkw = tsclkh + tsclkl in Figures 5 and 7. DS686PP1 17 CS4270 LRCK output tmslr LRCK input t slrd SCLK output t sdo SCLK input t sclkh t stp t hld t sclkl SDOUT MSB MSB-1 MSB-2 MSB-3 SDOUT MSB MSB-1 Figure 4. Master Mode, Left-Justified SAI Figure 5. Slave Mode, Left-Justified SAI LRCK output tmslr LRCK input t slrd SCLK output t sdo SCLK input t sclkh t sclkl t stp t hld SDOUT MSB MSB-1 MSB-2 MSB-3 SDOUT MSB Figure 6. Master Mode, I²S SAI Figure 7. Slave Mode, I²S SAI t sclkw SCLK t SDIN sdis t sdih Figure 8. Master and Slave Mode SDIN vrs. SCLK 18 DS686PP1 CS4270 LRCK SCLK Left Channel Right Channel SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 9. Format 0, Left-Justified up to 24-Bit Data LRCK SCLK Left Channel Right Channel SDINx MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 10. Format 1, I²S up to 24-Bit Data LRCK Channel A - Left Left Channel Channel B - Right Right Channel SCLK SDATA LSB MSB -1 -2 -3 -4 -5 -6 +6 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 -5 -6 +6 +5 +4 +3 +2 +1 LSB 32 clocks Figure 11. Format 2, Right-Justified 16-Bit Data. (Available in Control Port Mode only) Format 3, Right-Justified 24-Bit Data. (Available in Control Port Mode only) DS686PP1 19 CS4270 SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT (Inputs: logic 0 = DGND, logic 1 = VLC) Parameter I²C Mode SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Symbol fscl tirs tbuf thdst tlow thigh tsust (Note 19) thdd tsud tr tf tsusp Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 Max 100 1 300 - Unit kHz ns µs µs µs µs µs µs ns µs ns µs 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. RST t irs Stop SDA t buf SCL Repeated Start Start Stop t hdst t high t hdst tf t susp t low t hdd t sud t sust tr Figure 12. I²C Mode Control Port Timing 20 DS686PP1 CS4270 SWITCHING CHARACTERISTICS - SPITM CONTROL PORT (Inputs: logic 0 = DGND, logic 1 = VLC) Parameter SPI Mode CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN Symbol fsclk tsrs (Note 20) tspi tcsh tcss tscl tsch tdsu (Note 21) (Note 22) (Note 22) tdh tr2 tf2 Min 500 500 1.0 20 82 82 40 15 - Max 6 100 100 Unit MHz ns ns µs ns ns ns ns ns ns ns 20. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 21. Data must be held for sufficient time to bridge the transition time of CCLK. 22. For FSCK < 1 MHz RST t srs CS t spi t css CCLK t r2 CDIN t scl t sch t csh t f2 t dsu t dh Figure 13. SPI Control Port Timing DS686PP1 21 CS4270 5. APPLICATIONS 5.1 Stand-Alone Mode 5.1.1 Recommended Power-Up Sequence Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. 5.1.2 Master/Slave Mode The CS4270 supports operation in either Master Mode or Slave Mode. In Master Mode, LRCK and SCLK are outputs and are synchronously generated on-chip. LRCK is equal to Fs and SCLK is equal to 64x Fs. In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recommended that SCLK be 48x or 64x Fs to maximize system performance. In Stand-Alone Mode, the CS4270 will enter Slave Mode when SDOUT (M/S) is pulled low through a 47 kΩ resistor. Master Mode may be accessed by placing a 47 kΩ pull-up to VD on the SDOUT (M/S) pin. Configuration of clock ratios in each of these modes is outlined in Table 2. 5.1.3 System Clocking The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three speed modes as shown in Table 1 . Mode Single-Speed Double-Speed Quad-Speed Sampling Frequency 4-54 kHz 50-108 kHz 100-216 kHz Table 1. Speed Modes 22 DS686PP1 CS4270 5.1.4 Clock Ratio Selection Depending on whether the CS4270 is in Master or Slave Mode, different MCLK/LRCK and SCLK/LRCK ratios may be used. These ratios are shown in the Table 2. Master Mode MCLK/LRCK 256 Single-Speed 384 512 1024 128 Double-Speed 192 256 512 64 Quad-Speed 96 128 256 MCLK/LRCK 256 Single-Speed 384 512 1024 128 Double-Speed 192 256 512 64 Quad-Speed 96 128 256 SCLK/LRCK 64 64 64 64 64 64 64 64 64 64 64 64 Slave Mode SCLK/LRCK 32, 48, 64, 128 32, 48, 64, 96 32, 48, 64, 128 32, 48, 64, 96 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 LRCK Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs MDIV2 0 0 1 1 0 0 1 1 0 0 1 1 MDIV1 0 1 0 1 0 1 0 1 0 1 0 1 LRCK Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs MDIV2 0 0 1 1 0 0 1 1 0 0 1 1 MDIV1 0 1 0 1 0 1 0 1 0 1 0 1 Table 2. Clock Ratios - Stand-Alone Mode 5.1.5 Interpolation Filter In Stand-Alone Mode, the fast roll-off interpolation filter is used. Filter specifications can be found in Section 4. Plots of the data are contained in Section 9. “Filter Plots” on page 41. 5.1.6 High-Pass Filter The operational amplifiers in the input circuitry driving the CS4270 may generate a small DC offset into the ADC. The CS4270 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. In Stand-Alone Mode, the high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter This function cannot be disabled in Stand-Alone Mode. DS686PP1 23 CS4270 5.1.7 Mode Selection & De-Emphasis The sample rate, Fs, can be adjusted from 4 kHz to 216 kHz and De-emphasis, optimized for 44.1 kHz, is available in Single-Speed Mode. In Stand-Alone Master Mode, the CS4270 must be set to the proper mode via the mode pins, M1 and M0. In Slave Mode, the CS4270 auto-detects Speed Mode and the M0 pin becomes De-emphasis select. Stand-alone definitions of the mode pins are shown in Table 3. Mode 1 0 0 1 1 Mode 0 0 1 0 1 Mode Single-Speed Mode Single-Speed Mode Double-Speed Mode Quad-Speed Mode Sample Rate (Fs) 4 kHz - 54 kHz 4 kHz - 54 kHz 50 kHz - 108 kHz 100 kHz - 216 kHz De-Emphasis Off 44.1 kHz Off Off Table 3. CS4270 Stand-Alone Mode Control 5.1.8 Serial Audio Interface Format Selection Either I²S or Left-Justified serial audio data format may be selected in Stand-Alone Mode. The selection will affect both the input and output format. Placing a 10 kΩ pull-up to VD on the I²S/LJ pin will select the I²S format, while placing a 10 kΩ pull-down to DGND on the I²S/LJ pin will select the Left-Justified format. 5.2 Control Port Mode 5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode 1. Pull RST low until the power supply, MCLK, and LRCK are stable. 2. Release RST. The Control Port will be accessible. 3. Set the power down bit (register 0x02h, bit 0) to “1” for 1 ms minimum within 10 ms after releasing RST and then set to “0” prior to reading or writing to other registers. 4. Initiate a SPI or I²C transaction as described in Section 6.1 or Section 6.2, respectively. 5.2.2 Master / Slave Mode Selection The CS4270 supports operation in either Master Mode or Slave Mode. In Master Mode, LRCK and SCLK are outputs and are synchronously generated on-chip. LRCK is equal to Fs and SCLK is equal to 64x Fs. In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recommended that SCLK be 48x or 64x Fs to maximize system performance. Configuration of clock ratios in each of these modes will be outlined in the Table 10 and Table 9. In Control Port Mode the CS4270 will default to Slave Mode. The user may change this default setting by changing the status of the M/S bits in the Functional Control Register (03h). 24 DS686PP1 CS4270 5.2.3 System Clocking The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three speed modes as shown in Table 4. Mode Single-Speed Double-Speed Quad-Speed Sampling Frequency 4-54 kHz 50-108 kHz 100-216 kHz Table 4. Speed Modes 5.2.4 Clock Ratio Selection In Control Port Master Mode, the user must configure the mode bits (MCLK Freq) to set the speed mode and select the appropriate clock ratios. Depending on whether the CS4270 is in Master or Slave Mode, different MCLK/LRCK and SCLK/LRCK ratios may be used. These ratios as well as the Control Port Register Bits are shown in Table 5, Table 9 and Section 8.3 on page 36. Master Mode MCLK/LRCK 256 384 Single-Speed 512 768 1024 128 192 Double-Speed 256 384 512 64 96 Quad-Speed 128 192 256 MCLK/LRCK 256 384 Single-Speed 512 768 1024 SCLK/LRCK 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Slave Mode SCLK/LRCK 32, 64, 128 32, 48, 64, 96, 128 32, 64, 128 32, 48, 64, 96, 128 32, 64, 128 LRCK Fs Fs Fs Fs Fs MCLK Freq 0 0 0 0 1 MCLK Freq 0 0 1 1 0 MCLK Freq 0 1 0 1 0 LRCK Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs MCLK Freq 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 MCLK Freq 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 MCLK Freq 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 Table 5. Clock Ratios - Control Port Mode DS686PP1 25 CS4270 128 192 Double-Speed 256 384 512 64 96 Quad-Speed 128 192 256 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 64 32 48, 64 32, 64 48, 64 32, 64 Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 Table 5. Clock Ratios - Control Port Mode (Continued) 5.2.5 Internal Digital Loopback In Control Port Mode, the CS4270 supports an internal digital loopback mode in which the output of the ADC is routed to the input of the DAC. This mode may be activated by setting the Digital Loopback bit in the ADC & DAC Ctrl register (04h). When this bit is set, the status of the DAC_DIF(4:3) bits in register 04h will be disregarded by the CS4270. Any changes made to the DAC_DIF(4:3) bits while the Digital Loopback bit is set will have no impact on operation until the Digital Loopback bit is released, at which time the Digital Interface Format of the DAC will operate according to the format selected in the DAC_DIF(4:3) bits. While the Digital Loopback bit is set, data will be present on the SDOUT pin in the format selected in the ADC_DIF(0) bit in register 04h. 5.2.6 Auto-Mute The Auto-Mute function is controlled by the status of the Auto Mute bit in the Mute register. When set, the DAC output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting are done independently for each channel. The common mode on the output will be retained and the Mute Control pin for that channel will become active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and ZeroCross bits in the Transition and Control register. The Auto Mute bit is set by default. 5.2.7 High-Pass Filter and DC Offset Calibration The input circuitry driving the CS4270 may generate a small DC offset into the A/D converter. The CS4270 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. The high-pass filter can be enabled if the hpf_freeze bit is set during normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1. Running the CS4270 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2. Disabling the high-pass filter and freezing the stored DC offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS4270. 26 DS686PP1 CS4270 5.2.8 De-Emphasis One de-emphasis mode is available via the Control Port and is optimized for 44.1 kHz sampling rate. 5.2.9 Oversampling Modes The CS4270 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the FM_&_M/S_Mode[1:0] bits in the Functional Mode register (03h). Single-Speed Mode supports input sample rates up to 54 kHz and uses a 128x oversampling ratio. Double-Speed Mode supports input sample rates up to 108 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode supports input sample rates up to 216 kHz and uses an oversampling ratio of 32x. See Table 10 for Control Port Mode settings. 5.3 De-Emphasis Filter The CS4270 includes on-chip digital de-emphasis. Figure 14 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see Section 5.1.7 for the desired de-emphasis control for Stand-Alone Mode and Section 5.2.8 for Control Port Mode. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 µs pre-emphasis equalization as a means of noise reduction. De-emphasis is only available in Single-Speed Mode. Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 3.183 kHz F2 Frequency 10.61 kHz Figure 14. De-Emphasis Curve DS686PP1 27 CS4270 5.4 Analog Connections 5.4.1 Input Connections The analog modulator samples the input at 6.144 MHz.The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are multiples of the input sampling frequency (n × 6.144 MHz), where n=0,1,2,... Refer to Figure 15 which shows the recommended topology of the analog input network. The capacitor values chosen not only provide the appropriate filtering of noise at the modulator sampling frequency, but also act as a charge source for the internal sampling circuits. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. Analog Input R1 R2 220 pF 10 µF AINx CS4270 Figure 15. CS4270 Recommended Analog Input Network Three parameters determine the values of resistors R1 and R2 as shown in Figure 15 source impedance, attenuation, and input impedance. Table 6 shows the design equation used to determine these values. Source Impedance: Source impedance is defined as the impedance as seen from the ADC looking back into the signal network. The ADC achieves optimal THD+N performance when source impedance is minimized and THD+N degrades for source impedance greater than 1 kΩ. See Figure 16 and 17 below. Figure 16. A/D THD+N Performance vrs. Input Source Resistance 28 DS686PP1 CS4270 Figure 17. A/D Dynamic Range vrs. Input Source Resistance Attenuation: The required attenuation factor depends on the magnitude of the input signal. For VA = 5 V, the full-scale input voltage equals 1 Vrms. The full-scale input voltage scales with VA as indicated on pages 13 and 14. The user should select values for R1 and R2 such that the magnitude of the incoming signal multiplied by the attenuation factor is less than or equal to the full-scale input voltage of the device. Input Impedance: Input impedance is the impedance from the signal source to the ADC analog input pins. Table 6 shows the input parameters and the associated design equations. Source Impedance ( R1 × R2) -----------------------R1 + R2 (R2) -----------------------( R1 + R2) ( R1 + R2) Attenuation Factor Input Impedance Table 6. Analog Input Design Parameters Figure 18 illustrates an example configuration using two 2 kΩ resistors in place of R1 and R2. This circuit will attenuate a typical line level voltage, 2 Vrms, to the full-scale input of the ADC, 1 Vrms when VA = 5 V and is the maximum source impedance for the ADC specifications listed in this Data Sheet. DS686PP1 29 CS4270 Analog Input 2 kΩ 10 µ F 2 kΩ 220 pF AINx CS4270 Figure 18. CS4270 Example Analog Input Network 5.4.2 Output Connections The analog output filter present in the CS4270 is a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 24 - 47. The recommended external analog circuitry is shown in Figure 19. 3.3µF AOUTx 470Ω Analog Output + 10kΩ C R ext CS4270 R ext C= + 470 4 π Fs ( Rext 470 ) For best 20 kHz response Figure 19. CS4270 Recommended Analog Output Filter 5.5 Mute Control The Mute Control pins become active during power-up initialization, reset, muting, when the MCLK to LRCK ratio is incorrect, and during power-down. The MUTE pins are intended to be used as control for an external mute circuit in order to add off-chip mute capability. The CS4270 also features Auto-Mute, which is enabled by default. The Auto-Mute function causes the MUTE pin corresponding to an individual channel to activate following the reception of 8192 consecutive static-level audio samples on the respective channel. A single transition of data on the channel will cause the corresponding MUTE pin to deactivate. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. The MUTE pins are active-low. See Figure 20 for a suggested active-low mute circuit. 30 DS686PP1 CS4270 +V EE AC Couple AOUTx LPF 560 Ω Audio Out 47 k Ω -V EE CS4270 +V A MMUN2111LT1 MUTEx 2 kΩ 10 k Ω -V EE Figure 20. Suggested Active-Low Mute Circuit 5.6 Synchronization of Multiple Devices In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS4270’s in the system. If only one MCLK source is needed, one solution is to place one CS4270 in Master Mode, and slave all of the other CS4270’s to the one master. If multiple MCLK sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS4270 reset with the inactive edge of MCLK. This will ensure that all converters begin sampling on the same clock edge. 5.7 Grounding and Power Supply Decoupling As with any high resolution converter, the CS4270 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA and VD connected to clean supplies. VD, which powers the digital filter, may be run from the system digital supply (VD) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as near to the CS4270 as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into the modulators. The VREF and VCOM decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from VREF and AGND. The CDB4270 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the CS4270 digital outputs only to CMOS inputs. DS686PP1 31 CS4270 6. CONTROL PORT INTERFACE The Control Port is used to load all the internal settings of the CS4270. The operation of the Control Port may be completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the Control Port pins should remain static if no operation is required. The Control Port has 2 modes: SPI and I²C, with the CS4270 operating as a slave to control messages in both modes. If I²C operation is desired, AD0/CS should be tied to VLC or DGND. If the CS4270 ever detects a high to low transition on AD0/CS after power-up, SPI Mode will be selected. Upon release of the RST pin, the CS4270 will wait approximately 10 ms before it begins its start-up sequence. The part defaults to Stand-Alone Mode, in which all operational modes are controlled as described in Section 5.1 on page 22. If the user initiates communication to the part through the SPI or I²C interface, the part enters Control-Port Mode and all operational modes are controlled by the Control Port registers. If system requirements do not allow writing to the Control Port immediately following the release of RST, the SDIN line should be held at logic “0” until the proper serial mode can be selected. 6.1 SPI™ Mode In SPI Mode, CS is the CS4270 chip select signal, CCLK is the Control Port bit clock, CDIN is the input data line from the microcontroller and the chip address is 1001111. All control signals are inputs and data is clocked in on the rising edge of CCLK. Figure 21 shows the operation of the Control Port in SPI Mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and must be 1001111. The eighth bit is a read/write indicator (R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into the register designated by the MAP. See Table 9 on page 36. CS CCLK CHIP ADDRESS CDIN 1001111 R/W MAP MSB DATA LSB byte 1 MAP = Memory Address Pointer byte n Figure 21. Control Port Timing, SPI Mode The CS4270 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte is written, allowing block writes to successive registers. 32 DS686PP1 CS4270 6.2 I²C® Mode In I²C Mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 22. There is no CS pin. Pins AD0, AD1, and AD2 form the partial chip address and should be tied to VLC or DGND as required. The upper 4 bits of the 7-bit address field must be 1001. To communicate with the CS4270, the three lower bits of the chip address field should match the setting on the AD0, AD1, and AD2 pins. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). The next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. If the operation is a write, the MAP is then followed by the data to be written. If the operation is a read, then the contents of the register pointed to by the MAP will be output after the chip address. The CS4270 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. Note 1 SDA 1001 ADDR AD2 - AD0 R/W ACK DATA 1-8 ACK DATA 1-8 ACK SCL Start Stop Note: If operation is a write, this byte contains the Memory Address Pointer, MAP. Figure 22. Control Port Timing, I²C Mode 7 INCR 0 6 Reserved 0 5 Reserved 0 4 3 Reserved MAP3 0 0 INCR - Auto MAP Increment Enable Default = ‘0’. 0 - Disabled 1 - Enabled 2 MAP2 0 1 MAP1 0 0 MAP0 0 MAP(3:0) - Memory Address Pointer Default = ‘0000’. Table 7. Memory Address Pointer DS686PP1 33 CS4270 7. REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Addr Function 7 id 1 6 id 1 5 id 0 4 id 0 Reserved 0 3 rev 0 Reserved 0 MCLK freq 0 DAC_DIF0 0 2 rev 0 Reserved 0 MCLK freq 0 Reserved 0 1 rev 0 PDN_DAC 0 MCLK freq 0 Reserved 0 Invert DAC ch A 0 Mute DAC ch B 0 rev 1 PDN 0 PopGuard Disable 0 ADC_DIF0 0 De-Emph 0 Mute DAC ch A 01h ID 02h Power Control Freeze 0 Reserved PDN_ADC 0 0 03h Funct Mode Reserved Reserved 0 Freeze A 0 0 Freeze B 0 soft_dac 1 FM_&_M/S FM_&_M/S_ _Mode1 Mode0 1 Digital Loopback 0 zc_dac 1 1 DAC_DIF1 0 Invert ADC ch B 0 Mute ADC SP ch B 04h Serial Format ADC HPF ADC HPF 05h Transition Control DAC Single Vol 0 Invert ADC Invert DAC ch A ch B 0 Mute ADC SP ch A 0 Mute Polarity 06h Mute Reserved Reserved Auto Mute 0 07h Vol Ctrl AOUTA dacA vol 0 dacA vol 1 dacA vol 0 dacA vol 0 dacA vol 0 dacA vol 0 dacA vol 0 dacA vol 0 08h Vol Ctrl AOUTB dacB vol 0 dacB vol 0 dacB vol 0 dacB vol 0 dacB vol 0 dacB vol 0 dacB vol 0 dacB vol 0 0 0 0 0 0 0 0 34 DS686PP1 CS4270 8. REGISTER DESCRIPTION ** All registers are read/write in I²C Mode and SPI Mode, unless otherwise noted** 8.1 Chip ID - Address 01h 7 id 6 id 5 id 4 id 3 rev 2 rev 1 rev 0 rev Function: This register is Read-Only. Bits 7 through 4 are the part number ID which is 1100b (01h) and the remaining bits (b3:b0) are for the chip revision. 8.2 Power Control - Address 02h 7 Freeze 6 Reserved 5 PDN_ADC 4 Reserved 3 Reserved 2 Reserved 1 PDN_DAC 0 PDN 8.2.1 Freeze (Bit 7) Function: This function allows modifications to be made to certain Control Port bits without the changes taking effect until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed below: – – – – Register 05h (Bits 7:0) Register 06h (Bits 7:0) Register 07h (Bits 7:0) Register 08h (Bits 7:0) 8.2.2 PDN_ADC (Bit 5) Function: The ADC portion of the device will enter a low-power state whenever this bit is set. 8.2.3 PDN_DAC (Bit 1) Function: The DAC portion of the device will enter a low-power state whenever this bit is set. 8.2.4 Power Down (Bit 0) Function: The device will enter a low-power state whenever this bit is set. The contents of the control registers are retained when the device is in power-down. DS686PP1 35 CS4270 8.3 7 Mode Control - Address 03h 6 Reserved Reserved 5 FM_&_M/S_ Mode1 4 3 2 1 FM_&_M/S_ MCLK freq MCLK freq MCLK freq Mode0 0 Popguard Disable 8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4) Function: In Control Port Master Mode, the user must configure the CS4270 Speed Mode with these bits. In Control Port Slave Mode, the CS4270 auto-detects speed mode. FM_&_M/S_ FM_&_M/S_ Mode1 Mode0 Mode Single-Speed Mode: 4 to 54 kHz sample rates Double-Speed Mode: 50 to 108 kHz sample rates Quad-Speed Mode: 100 to 216 kHz sample rates Slave Mode (default) Table 8. Functional Mode Selection 0 0 1 1 0 1 0 1 8.3.2 Ratio Select (Bits 3:1) Function: These bits are used to select the clocking ratios. MCLK freq 0 0 0 0 1 MCLK freq 0 0 1 1 0 MCLK freq 0 1 0 1 0 Mode Divide by 1 (default) Divide by 1.5 Divide by 2 Divide by 3 Divide by 4 Table 9. MCLK Divider Configuration 8.3.3 Popguard Disable (Bit 0) Function: Disables Popguard when set. Popguard is enabled by default. 8.4 ADC and DAC Control - Address 04h 6 ADC HPF Freeze B 5 Digital Loopback 4 3 2 1 0 7 ADC HPF Freeze A DAC_DIF1 DAC_DIF0 Reserved Reserved ADC_DIF0 8.4.1 ADC HPF Freeze A (Bit 7) Function: When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC offset value will be frozen and continuously subtracted from the conversion result. Section 5.2.7 “HighPass Filter and DC Offset Calibration” on page 26. 36 DS686PP1 CS4270 8.4.2 ADC HPF Freeze B (Bit 6) Function: When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC offset value will be frozen and continuously subtracted from the conversion result. Section 5.2.7 “HighPass Filter and DC Offset Calibration” on page 26. 8.4.3 Digital Loopback (Bit 5) Function: When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to Section 5.2.5 “Internal Digital Loopback” on page 26. 8.4.4 DAC Digital Interface Format (Bits 4:3) Function: The DAC Digital Interface Format and the options are detailed in Table 10 and Figures 9 through 11. DAC_DIF1 DAC_DIF0 0 0 0 1 1 1 1 0 Description Left-Justified, up to 24-bit data (default) I²S, up to 24-bit data Right-Justified, 16-bit Data Right-Justified, 24-bit Data Table 10. DAC Digital Interface Formats Format 0 1 2 3 Figure 9 10 11 11 8.4.5 ADC Digital Interface Format (Bit 0) Function: The required relationship between LRCK, SCLK and SDOUT for the ADC is defined by the ADC Digital Interface Format. The options are detailed in Table 11 and may be seen in Figures 9 and 10. ADC_DIF 0 1 Description Left-Justified, up to 24-bit data (default) I²S, up to 24-bit data Table 11. ADC Digital Interface Formats Format 0 1 Figure 9 10 DS686PP1 37 CS4270 8.5 Transition Control - Address 05h 6 5 7 DAC Single Volume 4 invert ADC ch B 3 invert ADC ch A 2 invert DAC ch B 1 invert DAC ch A 0 soft_dac zc_dac De-emph 8.5.1 DAC Single Volume (Bit 7) Function: The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by the A Channel Volume Control Byte (07h) and the B Channel Byte (08h) is ignored when this function is enabled. Volume and muting functions are affected by the Soft Ramp and ZeroCross functions below. 8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5) Function: Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. See Table 12 on page 38. Zero Cross Enable Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 9 on page 36. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 9 on page 36. Soft ZeroCross Mode 0 0 Changes to affect immediately 0 1 Zero Cross enabled 1 0 Soft Ramp enabled 1 1 Soft Ramp and Zero Cross enabled (default) Table 12. Soft Cross or Zero Cross Mode Selection 8.5.3 Invert Signal Polarity (Bits 4:1) Function: When set, this bit activates an inversion of the signal polarity for the appropriate channel. This is useful if a board layout error has occurred or in other situations where a 180 degree phase shift is desirable. 38 DS686PP1 CS4270 8.5.4 De-Emphasis Control (Bit 0) Function: Implementation of the standard 50/15 µs digital de-emphasis filter on the DAC output requires reconfiguration of the digital filter to maintain the proper filter response for 44.1 kHz sample rate. Figure 23 shows the filter response. NOTE: De-emphasis is available only in Single-Speed Mode. Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 3.183 kHz F2 Frequency 10.61 kHz Figure 23. De-Emphasis Curve 8.6 7 Mute Control - Address 06h 6 5 Reserved Reserved Auto Mute 4 3 Mute ADC SP Mute ADC SP ch B ch A 2 mute polarity 1 0 Mute DAC SP Mute DAC SP ch B ch B 8.6.1 Auto-Mute (Bit 5) Function: When set, enables the Auto-Mute function. Section 5.2.6 “Auto-Mute” on page 26. 8.6.2 ADC Channel A & B Mute (Bits 4:3) Function: When this bit is set, the output of the ADC for the selected channel will be muted. 8.6.3 Mute Polarity (Bit 2) Function: The MUTEA and MUTEB pins (pins 24 and 21) are active low by default. When this bit is set, these pins are active high. 8.6.4 DAC Channel A & B Mute (Bits 1:0) Function: When this bit is set, the output of the DAC for the selected channel will be muted. DS686PP1 39 CS4270 8.7 DAC Channel A Volume Control - Address 07h 7 dacA vol 6 dacA vol 5 dacA vol 4 dacA vol 3 dacA vol 2 dacA vol 1 dacA vol 0 dacA vol Function: See Section 8.8 DAC Channel B Volume Control - Address 08h. 8.8 DAC Channel B Volume Control - Address 08h 7 dacB vol 6 dacB vol 5 dacB vol 4 dacB vol 3 dacB vol 2 dacB vol 1 dacB vol 0 dacB vol Function: The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to -127 dB. The vol bit activates a 0.5 dB attenuation when set, and no attenuation when cleared. The Vol[7:1] bits activate attenuation equal to their decimal value (in dB). Example volume settings are decoded as shown in Table 13. The volume changes are implemented as dictated by the DACSoft and DACZeroCross bits in the Transition Control register (see Section 8.5.2). Binary Code 00000000 00000001 00101000 00101001 11111110 11111111 Volume Setting 0 dB -0.5 dB -20 dB -20.5 dB -127 dB -127.5 dB Table 13. Digital Volume Control 40 DS686PP1 CS4270 9. FILTER PLOTS Figure 24. DAC Single-Speed Stopband Rejection Figure 25. DAC Single-Speed Transition Band 0 -1 0.05 -2 0 -3 -0.05 Amplitude dB Amplitude dB -4 -5 -0. 1 -6 -0.15 -7 -0. 2 -8 -0.25 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency (normalized to Fs) 0.52 0.53 0.54 0.5 5 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (normalized to Fs) 0.35 0.4 0.45 0.5 Figure 26. DAC Single-Speed Transition Band (detail) Figure 27. DAC Single-Speed Passband Ripple Figure 28. DAC Double-Speed Stopband Rejection Figure 29. DAC Double-Speed Transition Band DS686PP1 41 CS4270 1 0 -1 -2 -3 0.8 0.7 0.6 0.5 0.4 0.3 0.2 Amplitude dB -4 -5 -6 Amplitude dB 0.1 -7 -8 -9 - 10 0.45 0 -0. 1 -0. 2 0.46 0.47 0.48 0.49 0.5 0.51 Frequency (normalized to Fs) 0.52 0.53 0.54 0.55 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (normalized to Fs) 0.35 0.4 0.45 0.5 Figure 30. DAC Double-Speed Transition Band (detail) Figure 31. DAC Double-Speed Passband Ripple 0 0 -10 -10 -20 -30 -20 -40 Amplitude (dB) Amplitude (dB) 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 0.9 1 -30 -50 -60 -40 -70 -50 -80 -60 -90 -100 0.35 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 0.75 Figure 32. DAC Quad-Speed Stopband Rejection Figure 33. DAC Quad-Speed Transition Band 0 -5 -10 -15 0 -0. 5 Amplitude (dB) Amplitude dB -20 -25 -30 -35 -40 -45 -50 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 -1 -1. 5 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (normalized to Fs) 0.35 0.4 0.45 0.5 Figure 34. DAC Quad-Speed Transition Band (detail) Figure 35. DAC Quad-Speed Passband Ripple 42 DS686PP1 CS4270 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -10 -20 -30 Amplitude (dB) Amplitude (dB) -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (norm alized to Fs) Frequency (norm alized to Fs) Figure 36. ADC Single-Speed Stopband Rejection Figure 37. ADC Single-Speed Stopband (detail) 0 -1 -2 0.10 0.08 0.06 Amplitude (dB) Amplitude (dB) -3 -4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (norm alized to Fs) Frequency (norm alized to Fs) Figure 38. ADC Single-Speed Transition Band (detail) Figure 39. ADC Single-Speed Passband Ripple 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Amplitude (dB) Amplitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (norm alized to Fs) Frequency (norm alized to Fs) Figure 40. ADC Double-Speed Stopband Rejection Figure 41. ADC Double-Speed Stopband (detail) DS686PP1 43 CS4270 0 -1 -2 0.10 0.08 0.06 Amplitude (dB) Amplitude (dB) -3 -4 -5 -6 -7 -8 -9 -10 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (norm alized to Fs) Frequency (norm alized to Fs) Figure 42. ADC Double-Speed Transition Band (detail) Figure 43. ADC Double-Speed Passband Ripple 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 Amplitude (dB) Amplitude (dB) Frequency (norm alized to Fs) Frequency (norm alized to Fs) Figure 44. ADC Quad-Speed Stopband Rejection Figure 45. ADC Quad-Speed Stopband (detail) 0 -1 -2 0.10 0.08 0.06 Amplitude (dB) -3 Amplitude (dB) 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 -4 -5 -6 -7 -8 -9 -10 0.10 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 Frequency (norm alized to Fs) -0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28 Frequency (norm alized to Fs) Figure 46. ADC Quad-Speed Transition Band (detail) Figure 47. ADC Quad-Speed Passband Ripple 44 DS686PP1 CS4270 10.PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS686PP1 45 CS4270 11.PACKAGE DIMENSIONS 24L TSSOP (4.4 mm BODY) PACKAGE DRAWING N D E11 A2 A1 L E A ∝ e b2 SIDE VIEW 123 END VIEW SEATING PLANE TOP VIEW DIM A A1 A2 b D E E1 e L µ MIN INCHES NOM MAX MIN -0.05 0.80 0.19 7.70 BSC 6.30 4.30 -0.50 0° MILLIMETERS NOM -0.10 1.00 0.245 7.80 BSC 6.40 4.40 0.65 BSC 0.60 4° NOTE MAX 1.20 0.15 1.05 0.30 7.90 BSC 6.50 4.50 -0.75 8° --0.47 0.00197 0.00394 0.00591 0.03150 0.0394 0.04137 0.00748 0.00965 0.01182 0.30338 BSC 0.30732 BSC 0.31126 BSC 0.24822 0.25216 0.25610 0.16942 0.17336 0.17730 -0.026 BSC -0.01970 0.02364 0.02955 0° 4° 8° 2,3 1 1 JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. 46 DS686PP1 CS4270 12.ORDERING INFORMATION Product Description Package 24-Bit 192 kHz Stereo 24-TSSOP Audio CODEC 24-Bit 192 kHz Stereo 24-TSSOP Audio CODEC CS4270 Evaluation Board Pb-Free Container Order # Rail CS4270-CZZ Commercial -10° to +70° C Tape & Reel CS4270-CZZR Rail CS4270-DZZ Automotive -40° to +85° C Tape & Reel CS4270-DZZR CDB4270 Grade Temp Range CS4270 CS4270 CDB4270 YES YES - 13.REVISION HISTORY Release A1 Initial Release Changes DS686PP1 47 CS4270 Release – – – – – – – – – – – – – Changes Update Release after B0 chip validation Changed value of A/D shunt capacitor from 2200 pF to 220 pF in Figure 18 Added “single ended input” to “A/D Features” on page 1 and “single ended output” to “D/A Features” on page 1 Added “3.3 V or 5 V core supply” to “System Features” on page 1 Added package/grade & ordering info to “General Description” on page 2 Changed note 2. in Figure 1 Moved ordering info to Section 12 Moved Typical Connection Diagram to Section 3 Removed SOIC data from Thermal Characteristics Table on page 9 Changed DAC THD+N specs in “DAC Analog Characteristics - Commercial Grade” on page 10 and “DAC Analog Characteristics - Automotive Grade” on page 10 Changed DAC Full Scale Output Voltage specs in “DAC Analog Characteristics - all Modes” on page 11 Revised specifications in “DAC Combined Interpolation & on-Chip Analog FIlter Response” on page 12 Changed A/D THD+N and Full Scale Input Voltage specs in “ADC Analog Characteristics Commercial Grade” on page 13 and “ADC Analog Characteristics - Automotive Grade” on page 14 Specified A/D input circuit for performance specs in “ADC Analog Characteristics Commercial Grade” on page 13 and “ADC Analog Characteristics - Automotive Grade” on page 14 Revised specifications in “ADC Digital Filter CharacteristicS” on page 15 Changed PSRR spec in “DC Electrical Characteristics” on page 16 Revised Serial Audio Port specifications and acronyms in “Switching Characteristics - Serial Audio Port” on page 17 Replaced serial port timing diagrams with Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8, revised Note 17 and Note 18. Revised power up sequence text in “Recommended Power-Up Sequence - Access to Control Port Mode” on page 24 Changed text in “Input Connections” on page 28 to specify maximum source impedance for A/D performance specifications in the A/D Specification Tables Added “A/D THD+N Performance vrs. Input Source Resistance” on page 28 and “A/D Dynamic Range vrs. Input Source Resistance” on page 29 Revised text in “Input Connections” on page 28 that describes A/D input attenuator (resistor divider) circuit Replaced Figure 18 on page 30 Moved Parameter Definitions to Section 10 Moved “Filter Plots” to Section 9 and updated all plots Moved “Package Dimensions” to Section 11 and updated dimensions data PP1 – – – – – – – – – – – – – 48 DS686PP1 CS4270 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com. 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IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. DS686PP1 49