CDB42L51

CS42L51 Low Power, Stereo CODEC with Headphone Amp DIGITAL to ANALOG FEATURES 98 dB Dynamic Range (A-wtd) -86 dB THD+N Headphone Amplifier - GND Centered – On-Chip Charge Pump Provides -VA_HP – No DC-Blocking Capacitor Required – 46 mW Power Into Stereo 16 Ω @ 1.8 V – 88 mW Power Into Stereo 16 Ω @ 2.5 V – -75 dB THD+N Digital Signal Processing Engine – Bass & Treble Tone Control, De-Emphasis – PCM + ADC Mix w/Independent Vol Control – Master Digital Volume Control – Soft Ramp & Zero Cross Transitions Beep Generator – Tone Selections Across Two Octaves – – – Separate Volume Control Programmable On & Off Time Intervals Continuous, Periodic or One-Shot Beep Selections ANALOG to DIGITAL FEATURES 98 dB Dynamic Range (A-wtd) -88 dB THD+N Analog Gain Controls – +32 dB or +16 dB MIC Pre-Amplifiers – Analog Programmable Gain Amplifier (PGA) +20 dB Digital Boost Programmable Automatic Level Control (ALC) – Noise Gate for Noise Suppression – Programmable Threshold and Attack/Release Rates Independent Channel Control Digital Volume Control High-Pass Filter Disable for DC Measurements Stereo 3:1 Analog Input MUX Dual MIC Inputs – Programmable, Low Noise MIC Bias Levels – Differential MIC Mix for Common Mode Noise Rejection Programmable Peak-Detect and Limiter Pop and Click Suppression 1.8 V to 3.3 V 1.8 V to 2.5 V MUX Very Low 64 Fs Oversampling Clock Reduces Power Consumption 1.8 V to 2.5 V Switched Capacitor DAC and Filter Switched Capacitor DAC and Filter 1.8 V to 2.5 V Headphone Amp - GND Centered Headphone Amp - GND Centered Charge Pump Serial Audio Input Hardware Mode or I2C & SPI Software Mode Control Data Beep Generator Digital Signal Processing Engine MUX Left HP Out Multibit ∆Σ M odulator Right HP Out PCM Serial Interface Level Translator ALC Multibit Oversampling ADC Multibit Oversampling ADC MUX Reset PGA MUX +32 dB Stereo Input 1 Stereo Input 2 Stereo Input 3 / Mic Input 1 & 2 +32 dB Serial Audio Output High Pass Filters Volume Controls MUX PGA Register Configuration ALC MIC Bias http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) JULY '06 DS679F1 CS42L51 SYSTEM FEATURES 24-bit Converters 4 kHz to 96 kHz Sample Rate Multi-bit Delta Sigma Architecture Low Power Operation – Stereo Playback: 12.93 mW @ 1.8 V – Stereo Record and Playback: 20.18 mW @ 1.8 V GENERAL DESCRIPTION The CS42L51 is a highly integrated, 24-bit, 96 kHz, low power stereo CODEC. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. Both the ADC and DAC offer many features suitable for low power, portable system applications. The ADC input path allows independent channel control of a number of features. An input multiplexer selects between line-level or microphone level inputs for each channel. The microphone input path includes a selectable programmable-gain pre-amplifier stage and a low noise MIC bias voltage supply. A PGA is available for line or microphone inputs and provides analog gain with soft ramp and zero cross transitions. The ADC also features a digital volume attenuator with soft ramp transitions. A programmable ALC and Noise Gate monitor the input signals and adjust the volume levels appropriately. The DAC output path includes a digital signal processing engine. Tone Control provides bass and treble adjustment of four selectable corner frequencies. The Mixer allows independent volume control for both the ADC mix and the PCM mix, as well as a master digital volume control for the analog output. All volume level changes may be configured to occur on soft ramp and zero cross transitions. The DAC also includes de-emphasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves. The stereo headphone amplifier is powered from a separate positive supply and the integrated charge pump provides a negative supply. This allows a ground-centered analog output with a wide signal swing and eliminates external DC-blocking capacitors. In addition to its many features, the CS42L51 operates from a low-voltage analog and digital core, making this CODEC ideal for portable systems that require extremely low power consumption in a minimal amount of space. The CS42L51 is available in a 32-pin QFN package in both Commercial (-10 to +70° C) and Automotive grades (-40 to +85° C). The CDB42L51 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 85 for complete details. Variable Power Supplies – 1.8 V to 2.5 V Digital & Analog – 1.8 V to 3.3 V Interface Logic Power Down Management – ADC, DAC, CODEC, MIC Pre-Amplifier, PGA Software Mode (I²C® & SPI™ Control) Hardware Mode (Stand-Alone Control) Digital Routing/Mixes: – Analog Out = ADC + Digital In – – – Digital Out = ADC + Digital In Internal Digital Loopback Mono Mixes Flexible Clocking Options – Master or Slave Operation – High-Impedance Digital Output Option (for easy MUXing between CODEC and Other Data Sources) Quarter-Speed Mode - (i.e. Allows 8 kHz Fs while maintaining a flat noise floor up to 16 kHz) – APPLICATIONS HDD & Flash-Based Portable Audio Players MD Players/Recorders PDAs Personal Media Players Portable Game Consoles Digital Voice Recorders Digital Camcorders Digital Cameras Smart Phones 2 DS679F1 CS42L51 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 7 1.1 Digital I/O Pin Characteristics ........................................................................................................... 9 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 10 3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 12 SPECIFIED OPERATING CONDITIONS ............................................................................................. 12 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 12 ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ) .......................................................... 13 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) .......................................................... 14 ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 15 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ...................................................... 16 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ...................................................... 17 LINE OUTPUT VOLTAGE CHARACTERISTICS ................................................................................. 18 HEADPHONE OUTPUT POWER CHARACTERISTICS ...................................................................... 19 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 20 SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 20 SWITCHING SPECIFICATIONS - I²C® CONTROL PORT .................................................................. 22 SWITCHING CHARACTERISTICS - SPI™ CONTROL PORT ............................................................ 23 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 24 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 24 POWER CONSUMPTION .................................................................................................................... 25 4. APPLICATIONS ................................................................................................................................... 26 4.1 Overview ......................................................................................................................................... 26 4.1.1 Architecture ........................................................................................................................... 26 4.1.2 Line & MIC Inputs .................................................................................................................. 26 4.1.3 Line & Headphone Outputs ................................................................................................... 26 4.1.4 Signal Processing Engine ..................................................................................................... 26 4.1.5 Beep Generator ..................................................................................................................... 26 4.1.6 Device Control (Hardware or Software Mode) ...................................................................... 26 4.1.7 Power Management .............................................................................................................. 26 4.2 Hardware Mode .............................................................................................................................. 27 4.3 Analog Inputs ................................................................................................................................. 28 4.3.1 Digital Code, Offset & DC Measurement ............................................................................... 28 4.3.2 High-Pass Filter and DC Offset Calibration ........................................................................... 29 4.3.3 Digital Routing ....................................................................................................................... 29 4.3.4 Differential Inputs .................................................................................................................. 29 4.3.4.1 External Passive Components ................................................................................... 29 4.3.5 Analog Input Multiplexer ........................................................................................................ 31 4.3.6 MIC & PGA Gain ................................................................................................................... 31 4.3.7 Automatic Level Control (ALC) .............................................................................................. 32 4.3.8 Noise Gate ............................................................................................................................ 33 4.4 Analog Outputs ............................................................................................................................... 34 4.4.1 De-Emphasis Filter ................................................................................................................ 34 4.4.2 Volume Controls .................................................................................................................... 35 4.4.3 Mono Channel Mixer ............................................................................................................. 35 4.4.4 Beep Generator ..................................................................................................................... 35 4.4.5 Tone Control .......................................................................................................................... 36 4.4.6 Limiter .................................................................................................................................... 36 4.4.7 Line-Level Outputs and Filtering ........................................................................................... 37 4.4.8 On-Chip Charge Pump .......................................................................................................... 38 4.5 Serial Port Clocking ........................................................................................................................ 38 4.5.1 Slave ..................................................................................................................................... 39 4.5.2 Master ................................................................................................................................... 39 DS679F1 3 CS42L51 4.5.3 High-Impedance Digital Output ............................................................................................. 40 4.5.4 Quarter- and Half-Speed Mode ............................................................................................. 40 4.6 Digital Interface Formats ................................................................................................................ 40 4.7 Initialization ..................................................................................................................................... 41 4.8 Recommended Power-Up Sequence ............................................................................................. 41 4.9 Recommended Power-Down Sequence ........................................................................................ 42 4.10 Software Mode ............................................................................................................................. 43 4.10.1 SPI Control .......................................................................................................................... 43 4.10.2 I²C Control ........................................................................................................................... 43 4.10.3 Memory Address Pointer (MAP) .......................................................................................... 45 4.10.3.1 Map Increment (INCR) ............................................................................................. 45 5. REGISTER QUICK REFERENCE ........................................................................................................ 46 6. REGISTER DESCRIPTION .................................................................................................................. 49 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 49 6.2 Power Control 1 (Address 02h) ...................................................................................................... 49 6.3 MIC Power Control & Speed Control (Address 03h) ...................................................................... 50 6.4 Interface Control (Address 04h) ..................................................................................................... 52 6.5 MIC Control (Address 05h) ............................................................................................................. 53 6.6 ADC Control (Address 06h) ............................................................................................................ 54 6.7 ADCx Input Select, Invert & Mute (Address 07h) ........................................................................... 56 6.8 DAC Output Control (Address 08h) ................................................................................................ 57 6.9 DAC Control (Address 09h) ............................................................................................................ 58 6.10 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ............... 59 6.11 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh) ................................................ 60 6.12 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) .............................. 61 6.13 PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h) ..................................................................................... 62 6.14 Beep Frequency & Timing Configuration (Address 12h) .............................................................. 62 6.15 Beep Off Time & Volume (Address 13h) ...................................................................................... 63 6.16 Beep Configuration & Tone Configuration (Address 14h) ............................................................ 64 6.17 Tone Control (Address 15h) ......................................................................................................... 65 6.18 AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h) ................................................................................. 66 6.19 PCM Channel Mixer (Address 18h) .............................................................................................. 67 6.20 Limiter Threshold SZC Disable (Address 19h) ............................................................................. 67 6.21 Limiter Release Rate Register (Address 1Ah) .............................................................................. 69 6.22 Limiter Attack Rate Register (Address 1Bh) ................................................................................. 70 6.23 ALC Enable & Attack Rate (Address 1Ch) ................................................................................... 70 6.24 ALC Release Rate (Address 1Dh) ................................................................................................ 71 6.25 ALC Threshold (Address 1Eh) ...................................................................................................... 71 6.26 Noise Gate Configuration & Misc. (Address 1Fh) ......................................................................... 72 6.27 Status (Address 20h) (Read Only) ............................................................................................... 73 6.28 Charge Pump Frequency (Address 21h) ...................................................................................... 74 7. ANALOG PERFORMANCE PLOTS .................................................................................................... 75 7.1 Headphone THD+N versus Output Power Plots ............................................................................ 75 7.2 Headphone Amplifier Efficiency ...................................................................................................... 77 7.3 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 78 8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 79 8.1 Auto Detect Enabled ....................................................................................................................... 79 8.2 Auto Detect Disabled ...................................................................................................................... 80 9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 81 9.1 Power Supply, Grounding ............................................................................................................... 81 9.2 QFN Thermal Pad .......................................................................................................................... 81 10. ADC & DAC DIGITAL FILTERS ........................................................................................................ 82 4 DS679F1 CS42L51 11. PARAMETER DEFINITIONS .............................................................................................................. 83 12. PACKAGE DIMENSIONS ................................................................................................................. 84 THERMAL CHARACTERISTICS ........................................................................................................ 84 13. ORDERING INFORMATION ............................................................................................................. 85 14. REFERENCES .................................................................................................................................... 85 15. REVISION HISTORY ......................................................................................................................... 86 LIST OF FIGURES Figure 1.Typical Connection Diagram (Software Mode) ........................................................................... 10 Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 11 Figure 3.Headphone Output Test Load ..................................................................................................... 19 Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 21 Figure 5.Serial Audio Interface Master Mode Timing ................................................................................ 21 Figure 6.Control Port Timing - I²C ............................................................................................................. 22 Figure 7.Control Port Timing - SPI Format ................................................................................................ 23 Figure 8.Analog Input Architecture ............................................................................................................ 28 Figure 9.MIC Input Mix w/Common Mode Rejection ................................................................................. 30 Figure 10.Differential Input ........................................................................................................................ 30 Figure 11.ALC ........................................................................................................................................... 32 Figure 12.Noise Gate Attenuation ............................................................................................................. 33 Figure 13.Output Architecture ................................................................................................................... 34 Figure 14.De-Emphasis Curve .................................................................................................................. 35 Figure 15.Beep Configuration Options ...................................................................................................... 36 Figure 16.Peak Detect & Limiter ............................................................................................................... 37 Figure 17.Master Mode Timing ................................................................................................................. 39 Figure 18.Tri-State Serial Port .................................................................................................................. 40 Figure 19.I²S Format ................................................................................................................................. 40 Figure 20.Left-Justified Format ................................................................................................................. 41 Figure 21.Right-Justified Format (DAC only) ............................................................................................ 41 Figure 22.Initialization Flowchart ............................................................................................................... 42 Figure 23.Control Port Timing in SPI Mode .............................................................................................. 43 Figure 24.Control Port Timing, I²C Write ................................................................................................... 44 Figure 25.Control Port Timing, I²C Read ................................................................................................... 44 Figure 26.AIN & PGA Selection ................................................................................................................ 56 Figure 27.THD+N vs. Output Power per Channel at 1.8 V (16 Ω load) .................................................... 75 Figure 28.THD+N vs. Output Power per Channel at 2.5 V (16 Ω load) .................................................... 75 Figure 29.THD+N vs. Output Power per Channel at 1.8 V (32 Ω load) .................................................... 76 Figure 30.THD+N vs. Output Power per Channel at 2.5 V (32 Ω load) .................................................... 76 Figure 31.Power Dissipation vs. Output Power into Stereo 16 Ω ......................................................................77 Figure 32.Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail) .......................................... 77 Figure 33.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 78 Figure 34.ADC Passband Ripple .............................................................................................................. 82 Figure 35.ADC Stopband Rejection .......................................................................................................... 82 Figure 36.ADC Transition Band ................................................................................................................ 82 Figure 37.ADC Transition Band Detail ...................................................................................................... 82 Figure 38.DAC Passband Ripple .............................................................................................................. 82 Figure 39.DAC Stopband .......................................................................................................................... 82 Figure 40.DAC Transition Band ................................................................................................................ 82 Figure 41.DAC Transition Band (Detail) .................................................................................................... 82 DS679F1 5 CS42L51 LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 9 Table 2. Hardware Mode Feature Summary ............................................................................................. 27 Table 3. MCLK/LRCK Ratios .................................................................................................................... 39 6 DS679F1 CS42L51 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE SDOUT (M/S) DGND MCLK SCLK SDIN VD 32 31 30 29 28 27 26 VL LRCK SDA/CDIN (MCLKDIV2) SCL/CCLK (I²S/LJ) ADO/CS (DEM) VA_HP FLYP GND_HP FLYN RESET 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 AIN1B AIN1A AFILTB AFILTA AIN2B/BIAS AIN2A MICIN2/BIAS/AIN3B MICIN1/AIN3A CS42L51 21 20 19 18 17 Pin Name LRCK SDA/CDIN (MCLKDIV2) # 1 Pin Description Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the control port interface in SPI Mode. MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry. Serial Control Port Clock (Input) - Serial clock for the serial control port. 2 SCL/CCLK (I²S/LJ) 3 Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface formats for the ADC & DAC. Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS is the chip-select signal for SPI format. De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter. AD0/CS (DEM) VA_HP FLYP GND_HP FLYN VSS_HP 4 5 6 7 8 9 Analog Power For Headphone (Input) - Positive power for the internal analog headphone section. Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor. Analog Ground (Input) - Ground reference for the internal headphone/charge pump section. Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor. Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog headphone section. DS679F1 DAC_FILT+ ADC_FILT+ AOUTA VSS_HP AOUTB AGND VA VQ 7 CS42L51 AOUTB AOUTA VA AGND DAC_FILT+ VQ ADC_FILT+ MICIN1/ AIN3A MICIN2/ BIAS/AIN3B AIN2A 10 11 12 13 14 15 16 17 Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table Analog Power (Input) - Positive power for the internal analog section. Analog Ground (Input) - Ground reference for the internal analog section. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Microphone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Microphone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. Filter Connection (Output) - Filter connection for the ADC inputs. Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Reset (Input) - The device enters a low power mode when this pin is driven low. Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port. Refer to the Recommended Operating Conditions for appropriate voltages. Digital Power (Input) - Positive power for the internal digital section. Digital Ground (Input) - Ground reference for the internal digital section. Serial Audio Data Output (Output) - Output for two’s complement serial audio data. 29 30 31 32 Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and Slave Mode for the serial port. Master Clock (Input) - Clock source for the delta-sigma modulators. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 81. 18 19 AIN2B/BIAS AFILTA AFILTB AIN1A AIN1B RESET VL VD DGND SDOUT (M/S) MCLK SCLK SDIN Thermal Pad 20 21 22 23 24 25 26 27 28 8 DS679F1 CS42L51 1.1 Digital I/O Pin Characteristics The logic level for each input should not exceed the maximum ratings for the VL power supply. Pin Name SW/(HW) RESET SCL/CCLK (I²S/LJ) SDA/CDIN (MCLKDIV2) AD0/CS (DEM) MCLK LRCK SCLK SDOUT (M/S) SDIN I/O Input Input Input/Output Input Input Input/Output Input/Output Input/Output Input Driver 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS Table 1. I/O Power Rails Receiver 1.8 V - 3.3 V 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V DS679F1 9 CS42L51 2. TYPICAL CONNECTION DIAGRAMS +1.8 V or +2.5 V 1 µF 0.1 µF 0.1 µF 0.1 µF See Note 4 +1.8 V or +2.5 V 1 µF Note 4: Series resistance in the path of the power supplies must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output . VD VA VA_HP AOUTB 1.5 µF See Note 5 ** 1 µF ** FLYP FLYN VSS_HP AOUTA 0.022 µF 51.1 Ω Headphone Out Left & Right 1.5 µF ** 1 µF ** GND_HP * *Use low ESR ceramic capacitors. Note 2 : For best response to Fs/2 : 470 Ω C Rext Line Level Out Left & Right See Note 2 Rext CS42L51 470 Ω C Rext + 470 C= 4πFs (Rext × 470 ) This circuitry is intended for applications where the CS42L51 connects directly to an unbalanced output of the device. For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations. Note 5 : Larger capacitors, such as 1.5 µF, improves the charge pump performance (and subsequent THD+N) at the full scale output power achieved with gain (G) settings greater than default. Speaker Driver AIN1A 1800 pF 1800 pF * * 1 µF 100 Ω Left Analog Input 1 100 kΩ 100 kΩ MCLK SCLK LRCK Digital Audio Processor SDIN SDOUT RESET SCL/CCLK SDA/CDIN AD0/CS AIN1B 1 µF 100 Ω Right Analog Input 1 Left Analog Input 2 100 kΩ 100 kΩ AIN2A 1800 pF 1800 pF * 1 µF * 1 µF 100 Ω AIN2B BIAS1 M ICIN1 AIN3A BIAS2 AIN3B/MICIN2 100 Ω Right Analog Input 2 Microphone Input 1 µF 100 kΩ Microphone Bias 0.1 µF RL See Note 3 2k Ω 2k Ω Note 3: The value of R L is dictated by the microphone cartridge. +1.8 V, +2.5 V or +3.3 V See Note 1 0.1 µF VL ADC_FILT+ DAC_FILT+ 1 µF 10 µF Note 1: Resistors are required for I²C control port operation AGND * * 150 pF 150 pF 1 µF AFILTA AFILTB VQ DGND * Capacitors must be C0G or equivalent Figure 1. Typical Connection Diagram (Software Mode) 10 DS679F1 CS42L51 +1.8V or +2.5V 1 µF 0.1 µF 0.1 µF 0.1 µF 1 µF Note 4: Series resistance in the path of the power supplies (typically used for added filtering) must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output . See Note 4 +1.8V or +2.5V VD VA VA_HP AOUTB 1 µF ** FLYP FLYN AOUTA 0.022 µF 51.1 Ω Headphone Out Left & Right 1 µF ** VSS_HP GND_HP 470Ω C Rext Line Level Out Left & Right See Note 2 * *Use low ESR ceramic capacitors. CS42L51 470Ω C Rext MCLK SCLK LRCK VL or DGND (1) Speaker Driver SDIN SDOUT/ M/S AIN1A 1800 pF * 1 µF 100 Ω 1800 pF * 100 Ω 1 µF Left Analog Input 1 100 kΩ 100 kΩ Digital Audio Processor AIN1B RESET I²S/LJ MCLKDIV2 DEM AGND * * 150 pF Right Analog Input 1 ADC_FILT+ DAC_FILT+ 1 µF 10 µF +1.8V, 2.5 V or +3.3V 0.1 µF VL DGND (1) Pull-up to VL (47 kΩ  Master Mode. for Pull-down to DGND for Slave Mode. AFILTA AFILTB VQ 150 pF 1 µF * Capacitors must be C0G or equivalent Note 2 : This circuitry is intended for applications where the CS 42L51 connects directly to an unbalanced output of the device . For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations . For best response to Fs/2 : C= Rext + 470 4πFs (Rext × 470 ) Figure 2. Typical Connection Diagram (Hardware Mode) DS679F1 11 CS42L51 3. CHARACTERISTIC AND SPECIFICATION TABLES (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) Parameters DC Power Supply (Note 1) Analog Core Headphone Amplifier Digital Core Serial/Control Port Interface Ambient Temperature Commercial - CNZ Automotive - DNZ Symbol Min 1.65 2.37 1.65 2.37 1.65 2.37 1.65 2.37 3.14 -10 -40 Nom 1.8 2.5 1.8 2.5 1.8 2.5 1.8 2.5 3.3 - Max 1.89 2.63 1.89 2.63 1.89 2.63 1.89 2.63 3.47 +70 +85 Units V V V V V V V V V °C °C VA VA_HP VD VL TA ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Symbol Min -0.3 -0.3 -0.3 AGND-0.7 -0.3 -50 -65 Max 3.0 3.0 4.0 ±10 VA+0.7 VL+ 0.4 +115 +150 Units V V V mA Analog VA, VA_HP VD Digital VL Serial/Control Port Interface (Note 2) Iin Input Current Analog Input Voltage Digital Input Voltage (Note 3) Ambient Operating Temperature (power applied) Storage Temperature VIN VIND TA Tstg V V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. The device will operate properly over the full range of the analog, headphone amplifier, digital core and serial/control port interface supplies. 2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current. 12 DS679F1 CS42L51 ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ) (Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz) Parameter (Note 5) VA = 2.5 V (nominal) Min Typ Max A-weighted unweighted -1 dBFS -20 dBFS -60 dBFS 93 90 99 96 -86 -76 -36 -80 - VA = 1.8 V (nominal) Min Typ Max 90 87 96 93 -84 -73 -33 -78 - Unit dB dB dB dB dB Analog In to ADC (PGA bypassed) Dynamic Range Total Harmonic Distortion + Noise Analog In to PGA to ADC Dynamic Range PGA Setting: 0 dB PGA Setting: +12 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB PGA Setting: +12 dB -1 dBFS -60 dBFS -1 dBFS -88 -35 -85 -81 -79 -86 -32 -83 -80 -77 dB dB dB A-weighted unweighted A-weighted unweighted 92 89 85 82 98 95 91 88 89 86 82 79 95 92 88 85 dB dB dB dB Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC Dynamic Range PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -76 -74 dB A-weighted unweighted 86 83 83 80 dB dB Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC Dynamic Range PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -74 -71 dB A-weighted unweighted 78 74 75 71 dB dB Other Characteristics DC Accuracy Interchannel Gain Mismatch Gain Drift Offset Error Input Interchannel Isolation DAC Isolation (Note 4) Full-scale Input Voltage 0.74•VA ADC PGA (0 dB) 0.75•VA MIC (+16 dB) MIC (+32 dB) ADC PGA MIC 90 0.74•VA 0.75•VA 90 70 0.78•VA 0.794•VA 0.129•VA 0.022•VA 20 39 50 0.82•VA 0.83•VA dB dB Vpp Vpp Vpp Vpp kΩ kΩ kΩ 70 0.78•VA 0.82•VA 0.794•VA 0.83•VA 0.129•VA 0.022•VA 20 39 50 SDOUT Code with HPF On 0.2 ±100 352 0.2 ±100 352 dB ppm/°C LSB Input Impedance (Note 6) - - DS679F1 13 CS42L51 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) (Test Conditions (unless otherwise specified): Input sine wave (relative to full scale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz) Parameter (Note 5) VA = 2.5 V (nominal) Min Typ Max A-weighted unweighted -1 dBFS -20 dBFS -60 dBFS 91 78 99 96 -86 -76 -36 -78 - VA = 1.8 V (nominal) Min Typ Max 88 85 96 93 -84 -73 -33 -76 - Unit dB dB dB dB dB Analog In to ADC Dynamic Range Total Harmonic Distortion + Noise Analog In to PGA to ADC Dynamic Range PGA Setting: 0 dB PGA Setting: +12 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB PGA Setting: +12 dB -1 dBFS -60 dBFS -1 dBFS -88 -35 -85 -80 -77 -86 -32 -83 -78 -75 dB dB dB A-weighted unweighted A-weighted unweighted 90 87 83 80 98 95 91 88 87 84 80 77 95 92 88 85 dB dB dB dB Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC Dynamic Range PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -76 -74 dB A-weighted unweighted 86 83 83 80 dB dB Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC Dynamic Range PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -74 -71 dB A-weighted unweighted 78 74 75 71 dB dB Other Characteristics DC Accuracy Interchannel Gain Mismatch Gain Drift Offset Error Input Interchannel Isolation DAC Isolation (Note 4) Full-scale Input Voltage ADC 0.74•VA PGA (0 dB) 0.75•VA MIC (+16 dB) MIC (+32 dB) 18 ADC 40 PGA 50 MIC 90 70 0.78•VA 0.794•VA 0.129•VA 0.022•VA 0.82•VA 0.83•VA 0.74•VA 0.75•VA 90 70 0.78•VA 0.794•VA 0.129•VA 0.022•VA 0.82•VA 0.83•VA dB dB Vpp Vpp Vpp Vpp kΩ kΩ kΩ SDOUT Code with HPF On 0.1 ±100 352 0.1 ±100 352 dB ppm/°C LSB Input Impedance (Note 6) - 18 40 50 - 4. Measured with DAC delivering full-scale output power into 16 Ω. 14 DS679F1 CS42L51 5. Referred to the typical full-scale voltage. Applies to all THD+N and Dynamic Range values in the table. 6. Measured between AINxx and AGND. ADC DIGITAL FILTER CHARACTERISTICS Parameter (Note 7) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay to -0.1 dB corner Min 0 -0.09 0.6 33 - Typ 7.6/Fs Max 0.4948 0.17 - Unit Fs dB Fs dB s High-Pass Filter Characteristics (48 kHz Fs) Frequency Response Phase Deviation Passband Ripple Filter Settling Time -3.0 dB -0.13 dB @ 20 Hz 10 3.7 24.2 10 5/Fs 0.17 0 Hz Hz Deg dB s 7. Response is clock-dependent and will scale with Fs. Note that the response plots (Figure 33 to Figure 41) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. HPF parameters are for Fs = 48 kHz. DS679F1 15 CS42L51 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) (Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF for the line output (see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.) Parameter (Note 8) VA = 1.8V (nominal) VA = 2.5V (nominal) Min Typ Max Min Typ Max Unit R L = 10 k Ω Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB -86 -75 -35 -86 -73 -33 -78 -88 -72 -32 -88 -70 -30 -82 dB dB dB dB dB dB A-weighted unweighted A-weighted unweighted 92 89 98 95 96 93 89 86 95 92 93 90 dB dB dB dB 16-Bit R L = 16 Ω Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Modulation Index (MI) Analog Gain Multiplier (G) -75 -75 -35 -75 -73 -33 -69 -75 -72 -32 -75 -70 -30 -69 dB dB dB dB dB dB A-weighted unweighted A-weighted unweighted 92 89 98 95 96 93 89 86 95 92 93 90 dB dB dB dB 16-Bit Other Characteristics for RL = 16 Ω or 10 kΩ Output Parameters (Note 9) 0.6787 0.6787 0.6047 0.6047 Refer to Table “Line Output Voltage Characteristics” on page 18 Refer to Table “Headphone Output Power Characteristics” on page 19 80 80 95 93 (Note 10) (Note 10) 16 0.1 ±100 0.25 150 16 0.1 ±100 0.25 150 Full-scale Output Voltage (2•G•MI•VA) (Note 9) Full-scale Output Power (Note 9) Interchannel Isolation (1 kHz) Interchannel Gain Mismatch Gain Drift AC-Load Resistance (RL) Load Capacitance (CL) 16 Ω 10 kΩ Vpp mW dB dB dB ppm/° C Ω pF 16 DS679F1 CS42L51 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) (Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load RL = 10 kΩ, CL = 10 pF for the line output (see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.) Parameter (Note 8) VA = 2.5V (nominal) Min Typ Max VA = 1.8V (nominal) Min Typ Max Unit RL = 1 0 k Ω Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB -86 -75 -35 -86 -73 -33 -73 -88 -72 -32 -88 -70 -30 -80 dB dB dB dB dB dB A-weighted unweighted A-weighted unweighted 90 87 98 95 96 93 87 84 95 92 93 90 dB dB dB dB 16-Bit RL = 1 6 Ω Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Modulation Index (MI) Analog Gain Multiplier (G) -75 -75 -35 -75 -73 -33 -67 -75 -72 -32 -75 -70 -30 -67 dB dB dB dB dB dB A-weighted unweighted A-weighted unweighted 90 87 98 95 96 93 87 84 95 92 93 90 dB dB dB dB 16-Bit Other Characteristics for RL = 16 Ω or 10 kΩ Output Parameters (Note 9) 0.6787 0.6787 0.6047 0.6047 Refer to Table “Line Output Voltage Characteristics” on page 18 Refer to Table “Headphone Output Power Characteristics” on page 19 80 80 95 93 (Note 10) (Note 10) 16 0.1 ±100 0.25 150 16 0.1 ±100 0.25 150 Full-scale Output Voltage (2•G•MI•VA) (Note 9) Full-scale Output Power (Note 9) Interchannel Isolation (1 kHz) Interchannel Gain Mismatch Gain Drift AC-Load Resistance (RL) Load Capacitance (CL) 16 Ω 10 kΩ Vpp mW dB dB dB ppm/° C Ω pF DS679F1 17 CS42L51 LINE OUTPUT VOLTAGE CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF (see Figure 3). Parameter VA = 2.5V (nominal) Min Typ Max Analog Gain (G) 0.3959 0.4571 0.5111 0.6047 0.7099 0.8399 1.0000 1.1430 VA_HP 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.95 1.34 1.34 1.55 1.55 1.73 1.73 2.05 2.05 2.41 2.41 2.85 2.85 3.39 3.39 (See (Note 11) 3.88 2.15 - VA = 1.8V (nominal) Min Typ Max Unit AOUTx Voltage Into RL = 10 kΩ HP_GAIN[2:0] 000 001 010 011 (default) 100 101 110 111 1.41 - 0.97 0.97 1.12 1.12 1.25 1.25 1.48 1.48 1.73 1.73 2.05 2.05 2.44 2.44 2.79 2.79 1.55 - Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp 18 DS679F1 CS42L51 HEADPHONE OUTPUT POWER CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 16 Ω, CL = 10 pF (see Figure 3). Parameter VA = 2.5V (nominal) Min Typ Max Analog Gain (G) 0.3959 0.4571 0.5111 0.6047 0.7099 0.8399 1.0000 1.1430 VA = 1.8V (nominal) Min Typ Max Unit AOUTx Power Into RL = 16 Ω HP_GAIN[2:0] 000 001 010 011 (default) 100 101 110 111 VA_HP 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 14 14 19 19 23 23 (Note 11) 32 (Note 11) 44 (Note 9, 11) 7 7 10 10 12 12 17 17 23 23 (Note 9) 32 mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms 8. One-half LSB of triangular PDF dither is added to data. 9. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog Gain (HP_GAIN[2:0])” on page 57. High gain settings at certain VA and VA_HP supply levels may cause clipping when the audio signal approaches full-scale, maximum power output, as shown in Figures 27 - 30 on page 76. 10. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recommended 150 pF can cause the internal op-amp to become unstable. 11. VA_HP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC may not achieve the full THD+N performance at full-scale output voltage and power. AOUTx 51 Ω 0.022 µ F C L R L AGND Figure 3. Headphone Output Test Load DS679F1 19 CS42L51 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter (Note 12) Frequency Response 10 Hz to 20 kHz Passband StopBand StopBand Attenuation (Note 13) Group Delay De-emphasis Error Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.05 dB corner to -3 dB corner Min -0.01 0 0 0.5465 50 - Typ 10.4/Fs - Max +0.08 0.4780 0.4996 +1.5/+0 +0.05/-0.25 -0.2/-0.4 Unit dB Fs Fs Fs dB s dB dB dB Notes: 12. Response is clock dependent and will scale with Fs. Note that the response plots (Figure 38 to Figure 41 on page 82) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 13. Measurement Bandwidth is from Stopband to 3 Fs. SWITCHING SPECIFICATIONS - SERIAL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.) Parameters RESET pin Low Pulse Width MCLK Frequency MCLK Duty Cycle (Note 15) (Note 14) Symbol Min 1 1.024 45 Max 38.4 55 Units ms MHz % Slave Mode Input Sample Rate (LRCK) Quarter-Speed Mode Half-Speed Mode Single-Speed Mode Double-Speed Mode Fs Fs Fs Fs 1/tP ts(LK-SK) td(MSB) ts(SDO-SK) th(SK-SDO) ts(SD-SK) th 4 8 4 50 45 45 40 20 30 20 20 12.5 25 50 100 55 64•Fs 55 52 kHz kHz kHz kHz % Hz % ns ns ns ns ns ns LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Setup Time Before SCLK Rising Edge LRCK Edge to SDOUT MSB Output Delay SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge 20 DS679F1 CS42L51 Parameters Master Mode (Note 17) Output Sample Rate (LRCK) LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Edge to SDOUT MSB Output Delay SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge td(MSB) ts(SDO-SK) th(SK-SDO) ts(SD-SK) th 1/tP All Speed Modes (Note 17) Fs 45 45 20 30 20 20 MCLK ---------------128 55 64•Fs 55 52 Hz % Hz % ns ns ns ns ns Symbol Min Max Units 14. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are settled. 15. See “Example System Clock Frequencies” on page 79 for typical MCLK frequencies. 16. See 17. “Master” on page 39 18. “MCLK” refers to the external master clock applied. // LRCK ts(LK-SK) // // // td(MSB) th(SK-SDO) // MSB // th // MSB // ts(SDO-SK) MSB-1 tP SCLK SDOUT ts(SD-SK) SDIN MSB-1 Figure 4. Serial Audio Interface Slave Mode Timing // LRCK // tP // // td(MSB) th(SK-SDO) // MSB // th // MSB // ts(SDO-SK) MSB-1 SCLK SDOUT ts(SD-SK) SDIN MSB-1 Figure 5. Serial Audio Interface Master Mode Timing DS679F1 21 CS42L51 SWITCHING SPECIFICATIONS - I²C® CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF) Parameter SCL Clock Frequency Symbol fscl tirs tbuf thdst tlow thigh tsust (Note 19) thdd tsud trc tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 3450 Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns RESET Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling 19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. RST t irs Stop SDA t buf SCL Repeated Start Start Stop t hdst t high t hdst tf t susp t low t hdd t sud t sust tr Figure 6. Control Port Timing - I²C 22 DS679F1 CS42L51 SWITCHING CHARACTERISTICS - SPI™ CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL) Parameter CCLK Clock Frequency Symbol fsck tsrs tcss tcsh tscl tsch tdsu (Note 20) (Note 21) (Note 21) tdh tr2 tf2 Min 0 20 20 1.0 66 66 40 15 - Max 6.0 100 100 Units MHz ns ns µs ns ns ns ns ns ns RESET Rising Edge to CS Falling CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN 20. Data must be held for sufficient time to bridge the transition time of CCLK. 21. For fsck