CDB4341

CS4341 24-Bit, 96 kHz Stereo DAC with Volume Control Features ! 101 Description The CS4341 is a complete stereo digital-to-analog system including digital interpolation, fourth-order DeltaSigma digital-to-analog conversion, digital de-emphasis and switched capacitor analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. The CS4341 accepts data at audio sample rates from 4 kHz to 100 kHz, consumes very little power, and operates over a wide power supply range. The features of the CS4341 are ideal for DVD players, CD players, settop box and automotive systems. ORDERING INFORMATION CS4341-KS 16-pin SOIC, -10 to 70 °C CS4341-CZZ, Lead Free 16-pin TSSOP, -10 to 70 °C CDB4341 Evaluation Board dB Dynamic Range ! -91 dB THD+N ! +3.0 V or +5.0 V Power Supply ! Low Clock-Jitter Sensitivity ! Filtered Line-Level Outputs ! On-Chip Digital De-Emphasis for 32, 44.1 and 48 kHz ! ATAPI Mixing ! Digital Volume Control with Soft Ramp – 94 dB Attenuation – 1 dB Step Size – Zero Crossing Click-Free Transitions ! Popguard® Technology for Control of Clicks and Pops ! 33 mW with 3.0 V Supply I SCL/CCLK SDA/CDIN AD0/CS MUTEC External Mute Control Control Port RST Interpolation Filter Volume Control ∆Σ DAC Analog Filter AOUTA Serial Port SCLK LRCK SDATA Mixer Interpolation Filter Volume Control ∆Σ DAC Analog Filter AOUTB ÷2 MCLK http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) DECEMBER '05 DS298F5 1 CS4341 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4 SPECIFIED OPERATING CONDITIONS .............................................................................................. 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4 ANALOG CHARACTERISTICS (CS4341-KS/CZZ)............................................................................... 5 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE........................................ 7 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE........................................................ 10 SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK ..................................................... 11 SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (I²C®) ..................................... 12 SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (SPI™) ................................... 13 DC ELECTRICAL CHARACTERISTICS.............................................................................................. 14 DIGITAL INPUT CHARACTERISTICS ................................................................................................ 14 DIGITAL INTERFACE SPECIFICATIONS........................................................................................... 14 2. PIN DESCRIPTION ............................................................................................................................. 15 3. TYPICAL CONNECTION DIAGRAM ................................................................................................. 16 4. APPLICATIONS ................................................................................................................................... 17 4.1 Sample Rate Range/Operational Mode ........................................................................................ 17 4.2 System Clocking ........................................................................................................................... 17 4.2.1 Internal Serial Clock Mode ............................................................................................... 17 4.2.2 External Serial Clock Mode .............................................................................................. 18 4.3 Digital Interface Format ................................................................................................................. 18 4.4 De-Emphasis ................................................................................................................................ 19 4.5 Power-Up Sequence .................................................................................................................... 19 4.6 Popguard® Transient Control ........................................................................................................ 19 4.6.1 Power-Up ......................................................................................................................... 19 4.6.2 Power-Down ..................................................................................................................... 20 4.6.3 Discharge Time ................................................................................................................ 20 4.7 Mute Control ................................................................................................................................. 20 4.8 Grounding and Power Supply Arrangements ............................................................................... 20 4.9 Control Port Interface .................................................................................................................... 20 4.9.1 Rise Time for Control Port Clock ...................................................................................... 21 4.9.2 Memory Address Pointer (MAP) ...................................................................................... 21 4.9.2a INCR (Auto Map Increment) .............................................................................. 21 4.9.2b MAP0-3 (Memory Address Pointer) .................................................................. 21 4.9.3 I²C Mode .......................................................................................................................... 21 4.9.3a I²C Write ............................................................................................................ 22 4.9.3b I²C Read ............................................................................................................ 22 4.9.4 SPI Mode ......................................................................................................................... 23 4.9.4a SPI Write ........................................................................................................... 23 5. REGISTER QUICK REFERENCE ....................................................................................................... 24 6. REGISTER DESCRIPTION ................................................................................................................. 25 6.1 MCLK Control (address 00h) ......................................................................................................... 25 6.2 Mode Control (address 01h) .......................................................................................................... 25 6.3 Transition and Mixing Control (address 02h) ................................................................................. 27 6.4 Channel A Volume Control (address 03h) ..................................................................................... 29 6.5 Channel B Volume Control (address 04h) ..................................................................................... 29 7. PARAMETER DEFINITIONS ............................................................................................................... 31 8. PACKAGE DIMENSIONS .................................................................................................................... 32 2 DS298F5 CS4341 8.1 SOIC ..............................................................................................................................................32 8.2 TSSOP ..........................................................................................................................................33 9. PACKAGE THERMAL RESISTANCE .................................................................................................33 10. REFERENCES ....................................................................................................................................34 11. REVISION HISTORY ..........................................................................................................................34 LIST OF FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Output Test Load .........................................................................................................................6 Maximum Loading ........................................................................................................................6 Single-Speed Stopband Rejection ...............................................................................................8 Single-Speed Transition Band .....................................................................................................8 Single-Speed Transition Band (Detail) .........................................................................................8 Single-Speed Passband Ripple ...................................................................................................8 Double-Speed Stopband Rejection ..............................................................................................8 Double-Speed Transition Band ....................................................................................................8 Double-Speed Transition Band (Detail) .......................................................................................9 Double-Speed Passband Ripple ..................................................................................................9 Serial Input Timing (External SCLK) ..........................................................................................10 Internal Serial Mode Input Timing ..............................................................................................11 Internal Serial Clock Generation ................................................................................................11 Control Port Timing - I²C Mode ..................................................................................................12 Control Port Timing - SPI Mode .................................................................................................13 Typical Connection Diagram ......................................................................................................16 CS4341 Formats 0-1 - I²S up to 24-Bit Data ..............................................................................18 CS4341 Format 2 - Left Justified up to 24-Bit Data ...................................................................18 CS4341 Formats 3-6 - Right Justified ........................................................................................18 De-Emphasis Curve ...................................................................................................................19 I²C Buffer Example .....................................................................................................................21 I²C Write .....................................................................................................................................22 I²C Read .....................................................................................................................................23 Control Port Timing, SPI Mode ..................................................................................................23 ATAPI Block Diagram ................................................................................................................29 LIST OF TABLES Table 1. CS4341 Speed Modes .....................................................................................................................17 Table 2. Single-Speed Mode Standard Frequencies .....................................................................................17 Table 3. Double-Speed Mode Standard Frequencies ....................................................................................17 Table 4. Internal SCLK/LRCK Ratio ...............................................................................................................18 Table 5. Digital Interface Format ....................................................................................................................26 Table 6. ATAPI Decode..................................................................................................................................28 Table 7. Example Digital Volume Settings .....................................................................................................30 DS298F5 3 CS4341 1. CHARACTERISTICS AND SPECIFICATIONS (Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at TA = 25°C.) SPECIFIED OPERATING CONDITIONS (All voltages with respect to AGND = 0 V.) Parameters DC Power Supply Nominal 3.3 V Nominal 5.0 V Specified Operating Temperature (Power Applied) -KS/CZZ VA VA TA 2.7 4.75 -10 3.3 5.0 3.6 5.5 +70 V V °C Symbol Min Nom Max Units ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to AGND. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Parameters DC Power Supply Input Current Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Notes: 1. Any pin except supplies. (Note 1) Symbol VA Iin VIND TA Tstg Min -0.3 -0.3 -55 -65 Max 6.0 ±10 VA+0.4 125 150 Units V mA V °C °C 4 DS298F5 CS4341 ANALOG CHARACTERISTICS (CS4341-KS/CZZ) (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load R L = 10 kΩ, CL = 10 pF (see Figure 1).) VA = 5.0 V Parameter Single-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit Fs = 48 kHz (Note 2) VA = 3.0 V Max Min Typ Max Unit Min Typ unweighted A-Weighted unweighted A-Weighted (Note 2) 93 96 - 98 101 92 95 -91 -78 -38 -90 -72 -32 -86 - 89 92 - 94 97 92 95 -94 -74 -34 -91 -72 -32 -89 - dB dB dB dB dB dB dB dB dB dB 16-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Fs = 96 kHz (Note 2) Double-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit unweighted A-Weighted unweighted A-Weighted (Note 2) 93 96 - 98 101 92 95 -91 -78 -38 -90 -72 -32 -86 - 89 92 - 94 97 92 95 -94 -74 -34 -91 -72 -32 -89 - dB dB dB dB dB dB dB dB dB dB 16-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB DS298F5 5 CS4341 ANALOG CHARACTERISTICS (CS4341-KS/CZZ) Parameters Dynamic Performance for All Modes Interchannel Isolation (1 kHz) DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Characteristics and Specifications Full-Scale Output Voltage Output Impedance Minimum AC-Load Resistance Maximum Load Capacitance (Note 3) (Note 3) (Continued) Min 0.6•VA Typ 100 0.1 ±100 0.7•VA 100 3 100 Max 0.8•VA Units dB dB ppm/°C Vpp Ω kΩ pF Symbol RL CL - Notes: 2. One-half LSB of triangular PDF dither is added to data. 3. Refer to Figure 2. . 3.3 µF AOUTx + V out R L C L AGND Figure 1. Output Test Load 125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region 2.5 3 5 10 15 20 Resistive Load -- RL (kΩ ) Figure 2. Maximum Loading 6 DS298F5 CS4341 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) Parameter Single-Speed Mode - (4 kHz to 50 kHz sample rates) Passband to -0.05 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Passband Group Delay Deviation De-emphasis Error (Relative to 1 kHz) (Note 5) (Note 4) Min Typ Max Unit 0 0 -0.02 0.5465 50 - 9/Fs ±0.36/Fs - 0.4535 0.4998 +0.08 +0.2/-0.1 +0.05/-0.14 +0/-0.22 Fs Fs dB Fs dB s s dB dB dB 0 - 20 kHz Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz Double-Speed Mode - (50 kHz to 100 kHz sample rates) Passband to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Passband Group Delay Deviation 0 - 40 kHz 0 - 20 kHz (Note 4) 0 0 -0.06 0.577 55 - 4/Fs ±1.39/Fs ±0.23/Fs 0.4621 0.4982 +0.2 - Fs Fs dB Fs dB s s s Notes: 4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 5. De-emphasis is only available in Single-Speed Mode. DS298F5 7 CS4341 Figure 3. Single-Speed Stopband Rejection Figure 4. Single-Speed Transition Band Figure 5. Single-Speed Transition Band (Detail) Figure 6. Single-Speed Passband Ripple Figure 7. Double-Speed Stopband Rejection Figure 8. Double-Speed Transition Band 8 DS298F5 CS4341 Figure 9. Double-Speed Transition Band (Detail) Figure 10. Double-Speed Passband Ripple DS298F5 9 CS4341 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE Parameters MCLK Frequency MCLK Duty Cycle Input Sample Rate LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Frequency SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time Single-Speed Mode Double-Speed Mode tslrd tslrs tsdlrs tsdh tsclkl tsclkh Single-Speed Mode Double-Speed Mode Fs Fs Symbol Min 1.024 45 4 50 40 20 20 20 20 20 20 Max 51.2 55 50 100 60 128xFs 64xFs Units MHz % kHz kHz % ns ns Hz Hz ns ns ns ns LRCK t slrd t slrs t sclkl t sclkh SCLK t sdlrs SDATA Figure 11. Serial Input Timing (External SCLK) t sdh 10 DS298F5 CS4341 SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK Parameters MCLK Frequency MCLK Duty Cycle Input Sample Rate LRCK Duty Cycle SCLK Period SCLK rising to LRCK edge tsclkr SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time MCLK / LRCK = 512, 256 or 128 SCLK rising to SDATA hold time MCLK / LRCK = 384 or 192 tsdlrs tsdh tsdh 1 --------------------- + 10 ( 512 ) Fs 1 --------------------- + 15 ( 512 ) Fs 1 --------------------- + 15 ( 384 ) Fs t sclkw ------------2 (Note 7) Symbol Min 1.024 45 Typ (Note 6) Max 51.2 55 50 100 - Units MHz % kHz kHz % s Single-Speed Mode Double-Speed Mode Fs Fs tsclkw 4 50 1 --------------SCLK - - s ns ns ns - Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period. 7. See section 4.2.1 for derived internal frequencies. LRCK t sclkr SDATA t sclkw t sdlrs *INTERNAL SCLK t sdh Figure 12. Internal Serial Mode Input Timing *The SCLK pulses shown are internal to the CS4341. LRCK MCLK 1 *INTERNAL SCLK N 2 N SDATA Figure 13. Internal Serial Clock Generation * The SCLK pulses shown are internal to the CS4341. N equals MCLK divided by SCLK DS298F5 11 CS4341 SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (I²C®) Parameter I²C Mode SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL Fall Time of SCL Rise Time SDA Fall Time of SDA Setup Time for Stop Condition (Note 9) (Note 8) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc trd tfd tsusp Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 Max 100 25 25 1 300 - Unit kHz ns µs µs µs µs µs µs ns ns ns µs ns µs Notes: 8. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 9. See “Rise Time for Control Port Clock” on page 21 for a recommended circuit to meet rise time specification. RST t irs Stop SDA t buf SCL Repeated Start Start Stop t hdst t high t hdst tf t susp t low t hdd t sud t sust tr Figure 14. Control Port Timing - I²C Mode 12 DS298F5 CS4341 SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (SPI™) Parameter SPI Mode CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 11) (Note 12) (Note 12) (Note 10) Symbol fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2 Min 500 500 1.0 20 1 ---------------MCLK 1 ---------------MCLK Max 6 100 100 Unit MHz ns ns µs ns ns ns ns ns ns ns 40 15 - Notes: 10. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 11. Data must be held for sufficient time to bridge the transition time of CCLK. 12. For fsclk < 1 MHz. RST t srs CS t spi t css CCLK t r2 CDIN t scl t sch t csh t f2 t dsu t dh Figure 15. Control Port Timing - SPI Mode DS298F5 13 CS4341 DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.) Parameters Normal Operation (Note 13) Power Supply Current Power Dissipation Power-down Mode (Note 14) Power Supply Current Power Dissipation All Modes of Operation Power Supply Rejection Ratio (Note 15) VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink MUTEC Low-Level Output Voltage MUTEC High-Level Output Voltage Maximum MUTEC Drive Current 1 kHz 60 Hz PSRR 60 40 0.45•VA 250 0.01 VA 250 0.01 0 VA 3 dB dB V VA = 5.0 V VA = 3.0 V VA = 5.0 V VA = 3.0 V IA 60 30 0.3 0.09 µA µA mW mW VA = 5.0 V VA = 3.0 V VA = 5.0 V VA = 3.0 V IA IA 15 11 75 33 18 14 90 42 mA mA mW mW Symbol Min Typ Max Units kΩ mA V kΩ mA V V mA Notes: 13. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. 14. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 15. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 16. Increasing the capacitance will also increase the PSRR. DIGITAL INPUT CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.) Parameters Input Leakage Current Input Capacitance Symbol Iin Min Typ 8 Max ±10 Units µA pF DIGITAL INTERFACE SPECIFICATIONS (AGND = 0 V; all voltages with respect to AGND.) Parameters 3.3 V Logic (3.0 V to 3.6 V DC Supply) High-Level Input Voltage Low-Level Input Voltage 5.0 V Logic (4.75 V to 5.25 V DC Supply) High-Level Input Voltage Low-Level Input Voltage VIH VIL 2.0 0.8 V V VIH VIL 2.0 0.8 V V Symbol Min Max Units 14 DS298F5 CS4341 2. PIN DESCRIPTION RST SDATA SCLK LRCK MCLK SCL/CCLK SDA/CDIN AD0/CS 1 2 3 4 5 6 7 16 15 14 13 12 11 10 MUTEC AOUTA VA AGND AOUTB REF_GND VQ FILT+ 8 9 Pin Name RST SDATA SCLK LRCK MCLK SCL/CCLK SDA/CDIN AD0/CS FILT+ VQ REF_GND AOUTB AOUTA AGND VA MUTEC # 1 2 3 4 5 6 7 8 9 10 11 12 15 13 14 16 Pin Description Reset (Input) - Powers down device and resets registers to their default settings. Serial Audio Data (Input) - Input for two’s complement serial audio data. Serial Clock (Input) -Serial clock for the serial audio interface. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Serial Control Port Clock (Input) - Serial clock for the control port interface. Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Input for SPI data. Address Bit / Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select the chip in SPI mode. Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling circuits. Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. Reference Ground (Input) - Ground reference for the internal sampling circuits. Analog Outputs (Output) - The full-scale analog output level is specified in the Analog Characteristics table. Analog Ground (Input) Power (Input) - Positive power for the analog, digital, and serial audio interface sections. Mute Control (Output) - Control signal for an optional mute circuit. DS298F5 15 CS4341 3. TYPICAL CONNECTION DIAGRAM +3.0 V or +5.0 V + 14 VA 0.1 µF 1 µF 2 Serial Audio Data Processor 3 4 SDATA SCLK LR CK CS4341 M UTEC 16 AOUT A 15 3.3 µF + 10 k Ω 560 Ω Audio O utput A C RL External Clock 5 M CLK FILT+ VQ 9 10 .1 µF + 1 µF 11 0.1 µF + 1 µF O PTIO NAL MUTE CIRCUIT 6 7 Micro-Controlled Configuration 8 SCL/CCLK SDA/CDIN REF_GND 3.3 µF 12 AO UTB + 560 Ω Audio O utput B C R L + 560 C= 4 π Fs(R L 560) RL AD0/CS 1 RST AG ND 13 10 k Ω Figure 16. Typical Connection Diagram 16 DS298F5 CS4341 4. 4.1 APPLICATIONS Sample Rate Range/Operational Mode The device operates in one of two operational modes determined by the Master Clock to Left/Right Clock ratio (see section 4.2). Sample rates outside the specified range for each mode are not supported. Input Sample Rate (Fs) 4 kHz - 50 kHz 50 kHz - 100 kHz MODE Single-Speed Mode Double-Speed Mode Table 1. CS4341 Speed Modes 4.2 System Clocking The device requires external generation of the master (MCLK) and left/right (LRCK) clocks. The device also requires external generation of the serial clock (SCLK) if the internal serial clock is not used. The LRCK, defined also as the input sample rate Fs, must be synchronously derived from MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 2 and 3. Sample Rate (kHz) 32 44.1 48 256x 8.1920 11.2896 12.2880 384x 12.2880 16.9344 18.4320 MCLK (MHz) 512x 16.3840 22.5792 24.5760 768x* 24.5760 33.8688 36.8640 1024x* 32.768 45.1584 49.1520 Table 2. Single-Speed Mode Standard Frequencies Sample Rate (kHz) 64 88.2 96 MCLK (MHz) 128x 8.1920 11.2896 12.2880 192x 12.2880 16.9344 18.4320 256x* 16.3840 22.5792 24.5760 384x* 24.5760 33.8688 36.8640 Table 3. Double-Speed Mode Standard Frequencies *Requires MCLKDIV bit = 1 in the MCLK Control (address 00h) register. 4.2.1 Internal Serial Clock Mode The device will enter the Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK. In this mode, the SCLK is internally derived and synchronous with MCLK and LRCK. The SCLK/LRCK ratio is either 32, 48, or 64 depending upon the MCLK/LRCK ratio and the Digital Interface Format selection (see Table 4). Operation in the Internal Serial Clock mode is identical to operation with an external SCLK synchronized with LRCK; however, External SCLK mode is recommended for system clocking applications. DS298F5 17 CS4341 Input MCLK/LRCK Ratio 512, 256, 128 384, 192 512, 256, 128 Digital Interface Format Selection Right Justified I S up to 16 or Left Justified 24 Right Justified Bits 18, 20 or 24 Bits 16 Bits 24 Bits (Format 1) X 2 Internal SCLK/LRCK Ratio 32 48 64 X (Format 0) X X X X X - Table 4. Internal SCLK/LRCK Ratio 4.2.2 External Serial Clock Mode The device will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK. 4.3 Digital Interface Format The device will accept audio samples in several digital interface formats. The desired format is selected via the DIF0, DIF1 and DIF2 bits in the Mode Control register (see section 6.2.2). For an illustration of the required relationship between LRCK, SCLK and SDATA, see Figures 17 through 19. LR C K Left C ha nnel R ig ht C ha nnel SCLK SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 17. CS4341 Formats 0-1 - I²S up to 24-Bit Data Left C ha nnel LR C K R ig ht C ha nnel SCLK SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 18. CS4341 Format 2 - Left Justified up to 24-Bit Data LRCK Left Channel R ight Cha nnel SCLK SDATA LSB MSB -1 -2 -3 -4 -5 +7 +6 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 -5 +7 +6 +5 +4 +3 +2 +1 LSB Figure 19. CS4341 Formats 3-6 - Right Justified 18 DS298F5 CS4341 4.4 De-Emphasis The device includes on-chip digital de-emphasis. The Mode Control (address 01h) bits select either the 32, 44.1 or 48 kHz de-emphasis filter. Figure 20 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see section 6.2.3 for the desired de-emphasis control. De-emphasis is only available in Single-Speed Mode. Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 3.183 kHz F2 Frequency 10.61 kHz Figure 20. De-Emphasis Curve 4.5 Power-Up Sequence 1) Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default settings and VQ will remain low. 2) Bring RST high. The device will remain in a low power state with VQ low. 3) Load the desired register settings while keeping the PDN bit set to 1. 4) Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µS when the POR bit is set to 0. If the POR bit is set to 1, see section 4.6 for a complete description of powerup timing. 4.6 Popguard® Transient Control The CS4341 uses Popguard® technology to minimize the effects of output transients during power-up and power-down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when RST is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors. 4.6.1 Power-Up When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient. DS298F5 19 CS4341 4.6.2 Power-Down To prevent transients at power-down, the device must first enter its power-down state by enabling RST or setting the PDN bit. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on. 4.6.3 Discharge Time To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds. 4.7 Mute Control The Mute Control pin goes high during power-up initialization, reset, muting (see section 6.2.1 and 6.5.1) or if the MCLK to LRCK ratio is incorrect. This pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single-ended single supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4341 data sheet for a suggested mute circuit. 4.8 Grounding and Power Supply Arrangements As with any high resolution converter, the CS4341 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 16 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & AGND should be connected to the analog ground plane. Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and should also be located on the same layer as the DAC. The CDB4341 evaluation board demonstrates the optimum layout and power supply arrangements. 4.9 Control Port Interface The control port is used to load all the internal register settings (see section 6). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in one of two modes: I²C or SPI. Notes: MCLK must be applied during all I²C communication. 20 DS298F5 CS4341 4.9.1 Rise Time for Control Port Clock When excess capacitive loading is present on the I²C clock line, pin 6 (SCL/CCLK) may not have sufficient hysteresis to meet the standard I²C rise time specification. This prevents the use of common I²C configurations with a resistor pull-up. A workaround is achieved by placing a Schmitt Trigger buffer, a 74HC14 for example, on the SCL line just prior to the CS4341. This will not affect the operation of the I²C bus as pin 6 is an input only. VA SCL P in 6 Figure 21. I²C Buffer Example 4.9.2 Memory Address Pointer (MAP) The MAP byte precedes the control port register byte during a write operation and is not available again until after a start condition is initiated. During a read operation the byte transmitted after the ACK will contain the data of the register pointed to by the MAP (see section 4.9.3 for write/read details). 7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0 4.9.2a INCR (Auto Map Increment) The device has a MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. Default = ‘0’ 0 - Disabled 1 - Enabled 4.9.2b 4.9.3 MAP0-3 (Memory Address Pointer) Default = ‘0000’ I²C Mode In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL. There is no CS pin. Pin AD0 enables the user to alter the chip address (001000[AD0][R/W]) and should be tied to VA or AGND as required, before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected. DS298F5 21 CS4341 SDA 001000 AD0 W ACK MAP 1-8 ACK DATA 1-8 ACK SCL S tart Stop Figure 22. I²C Write 4.9.3a I²C Write To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 6. 1) Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit. 2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written. 3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP. 4) If the INCR bit (see section 4.9.2a) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5) If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to repeat the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus. 4.9.3b I²C Read To read from the device, follow the procedure below while adhering to the control port Switching Specifications. During this operation it is first necessary to write to the device, specifying the appropriate register through the MAP. 1) After writing to the MAP (see section 4.9.3a), initiate a repeated START condition to the I²C bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. 2) Signal the end of the address byte by not issuing an acknowledge. The device will then transmit the contents of the register pointed to by the MAP. The MAP will contain the address of the last register written to the MAP. 3) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock but do not issue an ACK on the bytes clocked out of the device. After all the desired registers are read, initiate a STOP condition to the bus. 4) If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to repeat the procedure detailed from step 1. If no further reads from other registers are desired, initiate a STOP condition to the bus. 22 DS298F5 CS4341 SDA 001000 AD0 W ACK M AP 1-8 ACK 001000 AD0 R ACK Data 1-8 (pointed to by MAP) ACK Data 1-8 (pointed to by MAP) SCL S tart Repeated START or Aborted W RITE Stop Figure 23. I²C Read 4.9.4 SPI Mode In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 24 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and is used to control SPI writes to the control port. When the device detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK. 4.9.4a SPI Write To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 1. 1) Bring CS low. 2) The address byte on the CDIN pin must then be 00100000. 3) Write to the memory address pointer, MAP. This byte points to the register to be written. 4) Write the desired data to the register pointed to by the MAP. 5) If the INCR bit (see section 4.9.2a) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high. 6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and repeat the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high. CS CCLK CHIP ADDRESS CDIN 0010000 R/W MAP MSB DATA LSB byte 1 MAP = Memory Address Pointer Figure 24. Control Port Timing, SPI Mode byte n DS298F5 23 CS4341 5. REGISTER QUICK REFERENCE Addr 0h 1h 2h Function MCLK Control DEFAULT 7 Reserved 0 AMUTE 1 A=B 0 MUTEA 0 MUTEB 0 6 Reserved 0 DIF2 0 SCZ1 0 VOLA6 0 VOLB6 0 5 Reserved 0 DIF1 0 SCZ0 0 VOLA5 0 VOLB5 0 4 Reserved 0 DIF0 0 ATAPI4 0 VOLA4 0 VOLB4 0 3 Reserved 0 DEM1 0 ATAPI3 0 VOLA3 0 VOLB3 0 2 0 DEM1 0 ATAPI2 0 VOLA2 0 VOLB2 0 1 0 POR 1 ATAPI1 0 VOLA1 0 VOLB1 0 0 0 PDN 1 ATAPI0 0 VOLA0 0 VOLB0 0 Reserved MCLKDIV Reserved Mode Control 2 DEFAULT Transition and Mixing Control DEFAULT 3h Channel A Volume Control DEFAULT 4h Channel B Volume Control DEFAULT 24 DS298F5 CS4341 6. REGISTER DESCRIPTION NOTE: All registers are read/write in I²C Mode and write only in SPI mode, unless otherwise stated. 6.1 MCLK CONTROL (ADDRESS 00H) 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 MCLKDIV 0 0 Reserved 0 7 Reserved 0 6.1.1 MCLK DIVIDE-BY-2 (MCLKDIV) BIT 1 Default = 0 0 - Disabled 1 - Enabled Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2. 6.2 MODE CONTROL (ADDRESS 01H) 6 DIF2 0 5 DIF1 0 4 DIF0 0 3 DEM1 0 2 DEM0 0 1 POR 1 0 PDN 1 7 AMUTE 1 6.2.1 AUTO-MUTE (AMUTE) BIT 7 Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. DS298F5 25 CS4341 6.2.2 DIGITAL INTERFACE FORMAT (DIF) BIT 4-6 Default = 000 - Format 0 (I²S, up to 24-bit data, 64 x Fs Internal SCLK) Function: The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 17 through 19. DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 DESCRIPTION I²S, up to 24-bit data, 64Fs Internal SCLK I²S, up to 16-bit data, 32Fs Internal SCLK Left Justified, up to 24-bit data, Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 16-bit data Right Justified, 18-bit data Identical to Format 1 Format 0 1 2 3 4 5 6 1 FIGURE 17 17 18 19 19 19 19 17 Table 5. Digital Interface Format 6.2.3 DE-EMPHASIS CONTROL (DEM) BIT 2-3 Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Implementation of the standard 15µs/50µs digital de-emphasis filter response, Figure 20, requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates. NOTE: De-emphasis is only available in Single-Speed Mode. 6.2.4 POPGUARD® TRANSIENT CONTROL (POR) BIT 1 Default = 1 0 - Disabled 1 - Enabled Function: The Popguard® Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-down. Please refer to section 4.6 for implementation details. 6.2.5 POWER DOWN (PDN) Default = 1 0 - Disabled 1 - Enabled Function: The device will enter a low-power state when this function is enabled. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation can occur. The contents of the control registers are retained in this mode. BIT 0 26 DS298F5 CS4341 6.3 TRANSITION AND MIXING CONTROL (ADDRESS 02H) 7 A=B 0 6 SZC1 1 5 SZC0 0 4 ATAPI4 0 3 ATAPI3 1 2 ATAPI2 0 1 ATAPI1 0 0 ATAPI0 1 6.3.1 CHANNEL A VOLUME = CHANNEL B VOLUME (A = B) BIT 7 Default = 0 0 - Disabled 1 - Enabled Function: The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled. 6.3.2 SOFT RAMP AND ZERO CROSS CONTROL (SZCX) BIT 5-6 Default = 10 00 - Immediate Changes 01 - Changes On Zero Crossings 10 - Soft Ramped Changes 11 - Soft Ramped Changes On Zero Crossings Function: Immediate Changes When Immediate Changes is selected all level changes will take effect immediately in one step. Changes On Zero Crossings Changes on Zero Crossings dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramped Changes Soft Ramped Changes allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock periods. Soft Ramped Changes on Zero Crossings Soft Ramped Changes On Zero Crossings dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. DS298F5 27 CS4341 6.3.3 ATAPI CHANNEL MIXING AND MUTING (ATAPI) BIT 0-4 Default = 01001 - AOUTA = Left Channel, AOUTB = Right Channel (Stereo) Function: The CS4341 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 6 and Figure 25 for additional information. ATAPI4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AOUTA MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL aL/2 [(aL+bR)/2] [(bL+aR)/2] [(aL+bR)/2] AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL bL/2 MUTE bR bL [(aR+bL)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2] Table 6. ATAPI Decode 28 DS298F5 CS4341 Left Channel Audio Data A Channel Volume Control MUTE AoutA Σ Σ Right Channel Audio Data B Channel Volume Control MUTE AoutB Figure 25. ATAPI Block Diagram 6.4 CHANNEL A VOLUME CONTROL (ADDRESS 03H) Same as CHANNEL B Volume Control. 6.5 CHANNEL B VOLUME CONTROL (ADDRESS 04H) 6 VOLx6 0 BIT 7 7 MUTEx 0 5 VOLx5 0 4 VOLx4 0 3 VOLx3 0 2 VOLx2 0 1 VOLx1 0 0 VOLx0 0 6.5.1 MUTE (MUTE) Default = 0 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be retained. The muting function is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. The MUTEC will go active during the mute period if the Mute function is enabled for both channels. DS298F5 29 CS4341 6.5.2 VOLUME (VOLx) BIT 0-6 Default = 0 dB (No Attenuation) Function: The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -90 dB. Volume settings are decoded as shown in Table 7. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. All volume settings less than - 94 dB are equivalent to enabling the Mute bit. Binary Code 0000000 0010100 0101000 0111100 1011010 Decimal Value 0 20 40 60 90 Volume Setting 0 dB -20 dB -40 dB -60 dB -90 dB Table 7. Example Digital Volume Settings 30 DS298F5 CS4341 7. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. DS298F5 31 CS4341 8. PACKAGE DIMENSIONS 8.1 SOIC 16L SOIC (150 MIL BODY) PACKAGE DRAWING E H 1 b c D SEATING PLANE e A1 A L ∝ DIM A A1 b C D E e H L ∝ MIN 0.053 0.004 0.013 0.0075 0.386 0.150 0.040 0.228 0.016 0° INCHES NOM 0.064 0.006 0.016 0.008 0.390 0.154 0.050 0.236 0.025 4° MAX 0.069 0.010 0.020 0.010 0.394 0.157 0.060 0.244 0.050 8° JEDEC #: MS-012 MIN 1.35 0.10 0.33 0.19 9.80 3.80 1.02 5.80 0.40 0° MILLIMETERS NOM 1.63 0.15 0.41 0.20 9.91 3.90 1.27 6.0 0.64 4° MAX 1.75 0.25 0.51 0.25 10.00 4.00 1.52 6.20 1.27 8° Controling Dimension is Millimeters 32 DS298F5 CS4341 8.2 TSSOP 16L TSSOP (4.4 mm BODY) PACKAGE DRAWING N D E11 A2 A1 L E A ∝ e b2 SIDE VIEW 123 END VIEW SEATING PLANE TOP VIEW DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.03346 0.00748 0.193 0.248 0.169 -0.020 0° INCHES NOM -0.004 0.0354 0.0096 0.1969 0.2519 0.1732 0.026 BSC 0.024 4° MAX 0.043 0.006 0.037 0.012 0.201 0.256 0.177 -0.028 8° MIN -0.05 0.85 0.19 4.90 6.30 4.30 -0.50 0° MILLIMETERS NOM --0.90 0.245 5.00 6.40 4.40 0.65 BSC 0.60 4° NOTE MAX 1.10 0.15 0.95 0.30 5.10 6.50 4.50 -0.70 8° 2,3 1 1 JEDEC #: MO-153 Controlling Dimension is Millimeters Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. 9. PACKAGE THERMAL RESISTANCE Package SOIC TSSOP (for multi-layer boards) (for multi-layer boards) Symbol θJA θJA Min - Typ 74 89 Max - Units °C/Watt °C/Watt DS298F5 33 CS4341 10.REFERENCES CDB4341 Evaluation Board Datasheet 11.REVISION HISTORY Revision F4 F5 Added lead-free packaging information Corrected Dimension e in TSSOP Package Drawing value for NOM Millimeters from 0.065 to 0.65 Changes Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. 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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. 34 DS298F5