CDB4354

CS4354 5 V Stereo DAC with 2 VRMS Ground-centered Output Features  Advanced Multi-bit Delta-Sigma Modulator  101 dB A-wt Dynamic Range  -86 dB THD+N  Single-ended Ground Centered Analog Description The CS4354 is a complete stereo digital-to-analog system including digital interpolation, third-order multi-bit delta-sigma digital-to-analog conversion, digital de-emphasis, analog filtering, and on-chip 2 VRMS line-level driver from a 5 V supply. The advantages of this architecture include ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components. The CS4354 is available in a 14-pin SOIC package in Commercial (-40°C to +85°C) grade. The CDB4354 Customer Demonstration Board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 23 for complete details. These features are ideal for cost-sensitive, 2-channel audio systems including video game consoles, Blu-Ray Disc® and DVD players, set-top boxes, digital TVs, and DAB/DMB devices. Architecture – No DC-blocking Capacitors Required – Integrated Inverting Charge Pump – Filtered Line-level Outputs – 2 VRMS Full-scale Output  Low-latency Digital Filtering  Supports Sample Rates up to 192 kHz  24-bit I²S Input  +5 V Analog Supply with Integrated Inverting Charge Pump and Regulator for Core Logic, and +1.8 V to +5 V Interface Power Supplies  50 mW Power Consumption  14-pin SOIC, Lead-free Assembly Interface Supply (VL) +1.8V to +5V Analog Supply (VA) +5 V 1.8V reg Inverting Charge Pump Power-On Reset -VA Ground-Centered, 2 Vrms Line Level Outputs Level Shifter Left Channel PCM Serial Audio Port Interpolation Filters + HPF Multibit Modulator I²S Serial Audio Input DAC Right Channel Auto Speed Mode Detect Advance Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Logic, Inc. 2010 (All Rights Reserved) JULY '10 DS895A2 CS4354 TABLE OF CONTENTS 1. PIN DESCRIPTIONS ........................................................................................................................... 4 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5 RECOMMENDED OPERATING CONDITIONS .................................................................................... 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 5 DAC ANALOG CHARACTERISTICS .................................................................................................... 6 COMBINED DIGITAL AND ON-CHIP ANALOG FILTER CHARACTERISTICS ................................... 7 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ......................................................... 8 DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 10 INTERNAL POWER-ON RESET THRESHOLD VOLTAGES ............................................................. 10 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 11 2.1 Digital I/O Pin Characteristics ........................................................................................................ 11 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12 4. APPLICATIONS ................................................................................................................................... 13 4.1 Ground-Centered Line Outputs ...................................................................................................... 13 4.2 Sample Rate Range/Operational Mode Detect .............................................................................. 13 4.3 System Clocking ............................................................................................................................ 13 4.4 Serial Clock .................................................................................................................................... 14 4.4.1 External Serial Clock Mode ................................................................................................... 14 4.4.2 Internal Serial Clock Mode .................................................................................................... 14 4.4.2.1 De-Emphasis Control ................................................................................................. 14 4.5 Internal High-Pass Filter ................................................................................................................ 15 4.6 Digital Interface Format .................................................................................................................. 15 4.7 Internal Power-On Reset ............................................................................................................... 15 4.8 Initialization .................................................................................................................................... 16 4.9 Recommended Power-Up and Power-Down Sequences .............................................................. 18 4.9.1 Power-Up Sequence ............................................................................................................. 18 4.9.2 Power-Down Sequence ......................................................................................................... 18 4.10 Grounding and Power Supply Arrangements .............................................................................. 18 4.10.1 Capacitor Placement ........................................................................................................... 18 5. COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE PLOTS .............................. 19 6. PARAMETER DEFINITIONS ................................................................................................................ 21 7. PACKAGE INFORMATION .................................................................................................................. 22 7.1 Dimensions .................................................................................................................................... 22 7.2 Thermal Characteristics ................................................................................................................. 22 8. ORDERING INFORMATION ................................................................................................................ 23 9. REVISION HISTORY ............................................................................................................................ 24 LIST OF FIGURES Figure 1. External Serial Clock Mode Input Timing ..................................................................................... 9 Figure 2. Internal Serial Clock Mode Input Timing ...................................................................................... 9 Figure 3. Internal Serial Clock Generation .................................................................................................. 9 Figure 4. Power-On Reset Threshold Sequence ...................................................................................... 10 Figure 5. Typical Connection Diagram ...................................................................................................... 12 Figure 6. CS4354 Data Format (I²S) ......................................................................................................... 14 Figure 7. De-Emphasis Curve, Fs = 44.1 kHz .......................................................................................... 15 Figure 8. Internal Power-On Reset Circuit ................................................................................................ 15 Figure 9. Initialization and Power-Down Sequence Diagram .................................................................... 17 Figure 10. Single-Speed Stopband Rejection ........................................................................................... 19 Figure 11. Single-Speed Transition Band ................................................................................................. 19 Figure 12. Single-Speed Transition Band (detail) ..................................................................................... 19 Figure 13. Single-Speed Passband Ripple ............................................................................................... 19 Figure 14. Double-Speed Stopband Rejection .......................................................................................... 19 2 DS895A2 CS4354 Figure 15. Double-Speed Transition Band ................................................................................................ 19 Figure 16. Double-Speed Transition Band (detail) .................................................................................... 20 Figure 17. Double-Speed Passband Ripple .............................................................................................. 20 Figure 18. Quad-Speed Stopband Rejection ............................................................................................ 20 Figure 19. Quad-Speed Transition Band .................................................................................................. 20 Figure 20. Quad-Speed Transition Band (detail) ...................................................................................... 20 Figure 21. Quad-Speed Passband Ripple ................................................................................................ 20 LIST OF TABLES Table 1. Power-On Reset Threshold Voltages .......................................................................................... 10 Table 2. Digital I/O Pin Characteristics ..................................................................................................... 11 Table 3. CS4354 Operational Mode Auto-Detect ...................................................................................... 13 Table 4. Common MCLK and LRCK Frequencies .................................................................................... 13 Table 5. Internal SCLK Frequencies ......................................................................................................... 14 DS895A2 3 CS4354 1. PIN DESCRIPTIONS VL SDIN MCLK LRCK SCLK/DEM GND FILT+ 1 2 3 4 5 6 7 14 13 12 11 10 9 8 -VFILT FLYN FLYP VA GND AOUTB AOUTA Pin Name Pin # VL SDIN MCLK LRCK SCLK/DEM FILT+ AOUTA AOUTB GND VA FLYP FLYN -VFILT 1 2 3 4 5 Pin Description Serial Audio Interface Power (Input) - Positive power for the serial audio interface. Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Clock (Input) - Serial clock for the serial audio interface. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Analog Outputs (Output) - The full-scale analog line output level is specified in the Analog Characteristics table. Analog, Charge Pump, and Regulator Power (Input) - Positive power supply for the analog, inverting charge pump, and regulator for the digital core logic sections. Inverting Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the inverting charge pump’s flying capacitor. Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the output amplifiers. 7 8 9 6, 10 Ground (Input) - Ground reference. See Section 4.10 on page 18 for layout considerations. 11 12 13 14 4 DS895A2 CS4354 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground.(Note 1) Parameters DC Power Supply Ambient Operating Temperature (Power Applied) Analog power Interface power -CSZ Symbol VA VL TA Min 4.75 1.4 -40 Typ 5.0 1.8, 3.3, 5.0 - Max 5.25 5.25 +85 Units V V °C Notes: 1. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. ABSOLUTE MAXIMUM RATINGS GND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Low Voltage Analog Power Interface Power Digital Interface Symbol VA VL Iin VIN-L TA Tstg Min -0.3 -0.3 -0.3 -55 -65 Max 6.0 6.0 ±10 VL+ 0.4 +125 +150 Units V V mA V °C °C Input Current, Any Pin Except Supplies Digital Input Voltage (Note 2) Ambient Operating Temperature (Power Applied) Storage Temperature WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin. DS895A2 5 CS4354 DAC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): TA = 25 °C; VA = 5 V, VL = 3.3 V; GND = 0 V; FILT+, -VFILT, and FLYP/N capacitors as shown in Figure 5 on page 12; input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 20 Hz to 20 kHz. Parameter Dynamic Range 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB (A-wt) (1 kHz) (Notes 6, 7) Symbol Min 95 92 0.38•VA 1.07•VA - Typ 101 98 96 93 -86 -78 -38 -86 -73 -33 101 100 0.40•VA 1.13•VA 0.1 ±1 100 100 - Max -80 -72 -32 0.42•VA 1.19•VA ±8 100 Unit dB dB dB dB dB dB dB dB dB dB dB dB VRMS Vpp dB mV ppm/°C  k pF Dynamic Performance, Fs = 48, 96, and 192 kHz (Notes 3, 5) Total Harmonic Distortion + Noise 24-bit 16-bit Idle Channel Noise / Signal-to-Noise Ratio Interchannel Isolation Analog Output (Note 4) Full Scale AOUTx Output Voltage Interchannel Gain Mismatch Output Offset Gain Drift Output Impedance Load Resistance Load Capacitance ZOUT RL CL 3 - Notes: 3. Measured at the output of the external low-pass filter on AOUTx as shown in Figure 5 on page 12. 4. Measured between the AOUTx and GND pins. 5. One LSB of triangular PDF dither is added to data. 6. Does not include attenuation due to ZOUT. Additional impedance between the AOUTx pin and the load will lower the voltage delivered to the load. 7. VPP is the controlling specification. VRMS specification valid for sine wave signals only. V pp Note that for sine wave signals: V RMS = ---------22 6 DS895A2 CS4354 COMBINED DIGITAL AND ON-CHIP ANALOG FILTER CHARACTERISTICS The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Reference level (0 dB) is set at 997 Hz. (Note 11) Parameter Single-Speed Mode - 48 kHz Passband (Note 8) to -0.05 dB corner to -3 dB corner Min 1.796•10-4 1.947•10-5 -0.05 0.550 80 dB 8.980•10-5 9.736•10-6 -0.05 0.583 82 dB 4.490•10-5 4.868•10-6 -0.05 0.630 85 dB - Typ 2.452•104/Fs 9.4/Fs 4.903•104/Fs 7.0/Fs 9.807•104/Fs 4.9/Fs Max 0.470 0.500 +0.05 ±0.14 0.290 0.500 +0.05 0.253 0.486 +0.05 - Unit Fs Fs dB Fs dB s s dB Fs Fs dB Fs dB s s Fs Fs dB Fs dB s s Frequency Response 20 Hz to 20 kHz StopBand StopBand Attenuation (Note 9) High Pass Filter Settling Time (input signal goes to 95% of its final value) Total Group Delay De-emphasis Error (Note 10)(Relative to 1 kHz) Fs = 44.1 kHz Double-Speed Mode - 96 kHz Passband (Note 8) to -0.05 dB corner to -3 dB corner Frequency Response 20 Hz to 20 kHz StopBand StopBand Attenuation (Note 9) High Pass Filter Settling Time (input signal goes to 95% of its final value) Total Group Delay Quad-Speed Mode - 192 kHz Passband (Note 8) to -0.05 dB corner to -3 dB corner Frequency Response 20 Hz to 20 kHz StopBand StopBand Attenuation (Note 9) High Pass Filter Settling Time (input signal goes to 95% of its final value) Total Group Delay Notes: 8. Response is clock-dependent and will scale with Fs. 9. For Single- and Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 10. De-emphasis is available only in Single-Speed Mode. 11. Amplitude vs. frequency plots of this data are available in “Combined Digital and On-chip Analog Filter Response Plots” on page 19. DS895A2 7 CS4354 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE Parameters MCLK Frequency MCLK Duty Cycle Input Sample Rate (Note 12) All MCLK/LRCK ratios combined (SSM) 256x, 384x, 512x, 768x, 1024x (DSM) 128x, 192x, 256x, 384x, 512x (QSM) 128x, 192x, 256x Fs Symbol Min 7.6 45 30 30 84 170 45 Typ - Max 55.3 55 216 54 108 216 55 55 - Units MHz % kHz kHz kHz kHz % ns ns % ns ns ns ns External SCLK Mode LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Duty Cycle SCLK rising to LRCK edge delay LRCK edge to SCLK rising delay SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time tslrd tslrs tsdlrs tsdh tsclkl tsclkh 20 20 45 20 20 20 20 Internal SCLK Mode LRCK Duty Cycle 1 50% – --------------------------2  MCLK (Note 14) - 1 50% + --------------------------2  MCLK ns ns ns ns SCLK Period MCLK falling to LRCK edge LRCK edge to SCLK rising SDIN valid to SCLK rising setup time (Note 13) tsclkw tmclkf tsclkr tsdlrs 10 9 --------------SCLK – 10 9 -------------------------4  MCLK 10 9 ---------------------- + 10 512  Fs 10 9 ---------------------- + 15 512  Fs 10 9 ---------------------- + 15 384  Fs 10 9 -------------------------4  MCLK - SCLK rising to SDIN hold time MCLK / LRCK = 1024, 512, 256, 128 tsdh MCLK / LRCK = 768, 384, 192 - ns - - 12. Not all sample rates are supported for all clock ratios. See Section 4.2 “Sample Rate Range/Operational Mode Detect” on page 13 for supported ratios and frequencies. SSM = Single-Speed Mode, DSM = Double-Speed Mode, QSM = Quad-Speed Mode. 13. SCLK period is defined by the SCLK / LRCK ratio. The SCLK / LRCK ratio may be either 32, 48, or 64. See Table 5 on page 14. t sclkw 10 14. t sclkr = ----------------- + -------------------------- + t mclkf 2 2  MCLK 9 8 DS895A2 CS4354 LRCK t slrd SCLK t sdlrs SDIN t sdh t slrs t sclkl t sclkh Figure 1. External Serial Clock Mode Input Timing MCLK t mclkf LRCK t sclkr SDIN t sdlrs * INTERNAL SCLK t sclkw t sdh The SCLK pulses shown are internal to the CS4354. Figure 2. Internal Serial Clock Mode Input Timing LRCK MCLK 1 *INTERNAL SCLK N 2 N SDIN * The SCLK pulses shown are internal to the CS4354. N equals MCLK divided by SCLK Figure 3. Internal Serial Clock Generation DS895A2 9 CS4354 DIGITAL INTERFACE CHARACTERISTICS Test conditions (unless otherwise specified): GND = 0 V; all voltages with respect to ground. Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance 1.8 V