CDB4361

Confidential Draft 2/12/08 CS4361 20-Pin, 24-Bit, 192 kHz, 6-Channel D/A Converter Features Multi-Bit Delta-Sigma Modulator 24-Bit Conversion Automatically Detects Sample Rates Up To 192 kHz 103 dB Dynamic Range -94 dB THD+N Low Clock-Jitter Sensitivity +5 V Core Power +1.8 V to +5 V Interface Power Filtered Line-Level Outputs On-Chip Digital De-emphasis Popguard® Technology Mute Output Control Small 20-pin TSSOP Package Description The CS4361 is a complete 6-channel digital-to-analog output system including interpolation, multi-bit D/A conversion, and output analog filtering in a small 20-pin package. The CS4361 supports all major audio data interface formats. The CS4361 is based on a fourth-order, multi-bit, deltasigma modulator with a linear analog low-pass filter. This device also includes auto-speed mode detection using both sample rate and master clock ratio as a method of auto-selecting sampling rates between 2 kHz and 216 kHz. The CS4361 contains on-chip digital de-emphasis, operates from a single +5 V power supply with separate built-in level shifter for the digital interface, and requires minimal support circuitry. These features are ideal for DVD players and recorders, digital televisions, home theater and set-top box products, and automotive audio systems. The CS4361 is available in a 20-pin TSSOP Commercial grade package (-40 to 85° C). The CDB4361 is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 23 for complete ordering information. Serial Audio Port & Control Supply (1.8 V to 5 V) Analog & Digital Core Supply (5 V) Digital De-emphasis Mode Control Level Translator Internal Voltage Reference PCM Serial Audio Input Auto-Speed Detecting PCM Serial Interface 6 Digital Filters Multi-bit ∆Σ M odulators Switch-Cap DAC and Analog Filters 6 Single-Ended Outputs (Six Channels +5 Volt-tolerant Reset External Mute Control Mute Control http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) February '08 DS672F1 Confidential Draft 2/12/08 TABLE OF CONTENTS CS4361 1. PIN DESCRIPTIONS .............................................................................................................................. 4 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5 RECOMMENDED OPERATING CONDITIONS .................................................................................... 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 5 DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ) ............................................................. 6 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................................ 7 DIGITAL INPUT CHARACTERISTICS .................................................................................................. 8 POWER & THERMAL CHARACTERISTICS ......................................................................................... 8 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE ...................................................... 9 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 11 4. APPLICATIONS ................................................................................................................................... 12 4.1 Master Clock .................................................................................................................................. 12 4.2 Serial Clock .................................................................................................................................... 12 4.2.1 External Serial Clock Mode ................................................................................................... 12 4.2.2 Internal Serial Clock Mode .................................................................................................... 12 4.3 De-Emphasis ................................................................................................................................. 14 4.4 Mode Select ................................................................................................................................... 14 4.5 Initialization and Power-Down ........................................................................................................ 15 4.6 Output Transient Control ................................................................................................................ 16 4.6.1 Power-Up .............................................................................................................................. 16 4.6.2 Power-Down .......................................................................................................................... 16 4.7 Grounding and Power Supply Decoupling ..................................................................................... 16 4.8 Analog Output and Filtering ........................................................................................................... 16 4.9 Mute Control .................................................................................................................................. 17 5. PERFORMANCE PLOTS ..................................................................................................................... 18 6. PARAMETER DEFINITIONS ................................................................................................................ 21 7. PACKAGE INFORMATION .................................................................................................................. 22 8. ORDERING INFORMATION ................................................................................................................ 23 9. REVISION HISTORY ............................................................................................................................ 24 2 Confidential Draft 2/12/08 LIST OF FIGURES CS4361 Figure 1.Equivalent Output Test Load ........................................................................................................ 8 Figure 2.Maximum Loading ......................................................................................................................... 8 Figure 3.External Serial Mode Input Timing .............................................................................................. 10 Figure 4.Internal Serial Mode Input Timing ............................................................................................... 10 Figure 5. Internal Serial Clock Generation ................................................................................................ 10 Figure 6.Recommended Connection Diagram .......................................................................................... 11 Figure 7.CS4361 Data Format (I²S) .......................................................................................................... 13 Figure 8.CS4361 Data Format (Left-Justified) .......................................................................................... 13 Figure 9.CS4361 Data Format (Right-Justified 24) ................................................................................... 13 Figure 10.CS4361 Data Format (Right-Justified 16) ................................................................................. 14 Figure 11.De-Emphasis Curve (Fs = 44.1kHz) ......................................................................................... 14 Figure 12.CS4361 Initialization and Power-Down Sequence ................................................................... 15 Figure 13.Suggested Active-Low Mute Circuit .......................................................................................... 17 Figure 14.Single-Speed Stopband Rejection ............................................................................................ 18 Figure 15.Single-Speed Transition Band .................................................................................................. 18 Figure 16.Single-Speed Transition Band .................................................................................................. 18 Figure 17.Single-Speed Passband Ripple ................................................................................................ 18 Figure 18.Double-Speed Stopband Rejection ........................................................................................... 19 Figure 19.Double-Speed Transition Band ................................................................................................. 19 Figure 20.Double-Speed Transition Band ................................................................................................. 19 Figure 21.Double-Speed Passband Ripple ............................................................................................... 19 Figure 22.Quad-Speed Stopband Rejection ............................................................................................. 20 Figure 23.Quad-Speed Transition Band ................................................................................................... 20 Figure 24.Quad-Speed Transition Band ................................................................................................... 20 Figure 25.Quad-Speed Passband Ripple ................................................................................................. 20 LIST OF TABLES Table 1. Common Clock Frequencies ...................................................................................................... 12 Table 2. Mode Pin Settings ...................................................................................................................... 14 3 Confidential Draft 2/12/08 1. PIN DESCRIPTIONS CS4361 VL SDIN1 SDIN2 SDIN3 DEM/SCLK LRCK MCLK RST MODE FILT+ 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Pin Description MUTEC AOUT1 AOUT2 AOUT3 AOUT4 VA GND AOUT5 AOUT6 VQ Pin Name SDIN1 SDIN2 SDIN3 DEM/SCLK LRCK MCLK VQ FILT+ AOUT1 AOUT2 AOUT3 AOUT4 AOUT5 AOUT6 GND VA VL RST MUTEC MODE # 2 3 4 5 6 7 11 10 19 18 17 16 13 12 14 15 1 8 20 9 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. De-emphasis/External Serial Clock Input (Input) - used for de-emphasis filter control or external serial clock input. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Analog Output (Output) - The full scale analog output level is specified in the Analog Characteristics specification table. Ground (Input) - ground reference. Analog Power (Input) - Positive power for the analog and core digital sections. Interface Power (Input) - Positive power for the digital interface level shifters. Reset (Input) - Applies reset to the internal circuitry when low. Mute Control (Output) - Control signal for optional external muting circuitry. Mode Control (Input) - Selects operational modes (see Table 2). 4 Confidential Draft 2/12/08 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS AGND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Specified Temperature Range Commercial (-CZZ) Symbol VA VL TA Min 4.75 1.7 -40 Nom 5.0 3.3 Max 5.25 5.25 +85 CS4361 Units V V °C ABSOLUTE MAXIMUM RATINGS AGND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage (pin 8, RST) Digital Input Voltage (all other digital pins) Ambient Operating Temperature (power applied) Storage Temperature Symbol VA VL Iin VIND VIND Top Tstg Min -0.3 -0.3 -0.3 -0.3 -55 -65 Max 6.0 VA ±10 VA+0.4 VL+0.4 125 150 Units V V mA V V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 5 Confidential Draft 2/12/08 DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ) CS4361 Test Conditions (unless otherwise specified). VA = 5.0 V, VL = 3.3 V, and TA = 25° C. Full-scale input sine wave. Measurement Bandwidth is 10 Hz to 20 kHz. See (Note 1). Specifications apply to all channels unless otherwise indicated. Parameter Dynamic Performance Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit A-weighted unweighted A-weighted unweighted Ch. 1-2, 0 dB Ch. 3-4, 0 dB Ch. 5-6, 0 dB -20 dB -60 dB Ch. 1-2, 0 dB Ch. 3-4, 0 dB Ch. 5-6, 0 dB -20 dB -60 dB Symbol 99 96 90 87 Min 0.60•VA VQ IOUTmax IQmax RL CL ZOUT - Min Typ 103 100 96 93 -93 -90 -94 -80 -40 -92 -89 -93 -73 -33 Typ 100 0.1 100 0.65•VA 0.5•VA 10 100 3 100 100 Max -86 -83 -87 -76 -36 -85 -82 -86 -67 -27 Max 0.25 0.70•VA - Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB 16-Bit DAC Analog Characteristics - All Modes Parameter Interchannel Isolation (1 kHz) dB dB ppm/°C Vpp VDC µA µA kΩ pF Ω DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Full Scale Output Voltage Quiescent Voltage Max DC Current draw from an AOUT pin Max Current draw from VQ Min AC-Load Resistance (see Figure 2) Max Load Capacitance (see Figure 2) Output Impedance Notes: 1. One-half LSB of triangular PDF dither added to data. 6 Confidential Draft 2/12/08 CS4361 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. (See Note 5) Parameter Single-Speed Mode Passband (Note 2) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 4) Double-Speed Mode Passband (Note 2) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Quad-Speed Mode Passband (Note 2) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay 2. Response is clock-dependent and will scale with Fs. 3. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. For Quad-Speed Mode, the measurement bandwidth is 0.7 Fs to 1 Fs. 4. De-emphasis is available only in Single-Speed Mode. 5. Amplitude vs. Frequency plots of this data are available in “Performance Plots” on page 18. (Note 3) tgd to -0.1 dB corner to -3 dB corner 0 0 0 0.7 51 2.5/Fs 0.397 0.476 +0.00004 Fs Fs dB Fs dB s (Note 3) tgd to -0.1 dB corner to -3 dB corner 0 0 -.05 .5770 55 5/Fs .4650 .4982 +.2 Fs Fs dB Fs dB s Fs = 44.1 kHz (Note 3) tgd to -0.05 dB corner to -3 dB corner 0 0 -.01 .5465 50 10/Fs .4780 .4996 +.08 +.05/-.25 Fs Fs dB Fs dB s dB Symbol Min Typ Max Unit 7 Confidential Draft 2/12/08 DIGITAL INPUT CHARACTERISTICS Parameters High-Level Input Voltage -all input Pins except RST Low-Level Input Voltage -all input Pins except RST High-Level Input Voltage -RST pin (Note 6) Low-Level Input Voltage -RST pin Input Leakage Current Input Capacitance 7. Iin for LRCK is ±20 µA max. (% of VL) (% of VL) (% of VL) (% of VL) (Note 7) Symbol VIH VIL VIH VIL Iin Min 70% 90% Typ 8 Max 30% 10% ±10 - CS4361 Units V V V V µA pF 6. RST pin has an input threshold relative to VL, but is VA tolerant. POWER & THERMAL CHARACTERISTICS Parameters Power Supplies Power Supply Current (Note 8) Power Dissipation normal operation power-down state (Note 9) normal operation power-down state (Note 9) θJA (1 kHz) PSRR (60 Hz) IA IL IA IL 66 0.1 300 26 331 1.63 72 60 40 90 1 455 mA mA µA µA mW mW °C/Watt dB dB Symbol 5 V Nom Min Typ Max Units Package Thermal Resistance Power Supply Rejection Ratio (Note 10) 8. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are based on highest FS and highest MCLK. Current variance between speed modes is small. 9. Power-Down Mode is defined when all clock and data lines are held static. 10. Valid with the recommended capacitor values on VQ and FILT+ as shown in the typical connection diagram in Section 4. 125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region 3.3 µF AO U Tx R C V o ut L L AG N D 2.5 3 5 10 15 20 Resistive Load -- RL (kΩ ) Figure 1. Equivalent Output Test Load 8 Figure 2. Maximum Loading Confidential Draft 2/12/08 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE Parameters MCLK Frequency MCLK Duty Cycle Input Sample Rate (Note 11) All MCLK/LRCK ratios combined 256x, 384x, 1024x 256x, 384x 512x, 768x 1152x 128x, 192x 64x, 96x 128x, 192x Fs Symbol Min 0.512 45 2 2 84 42 30 50 100 168 45 tsclkl tsclkh tslrd tslrs tsdlrs tsdh (Note 12) (Note 13) tsclkw tsclkr tsdlrs tsdh 20 20 45 20 20 20 20 10 9 --------------SCLK CS4361 Typ - Max 50 55 216 54 134 67 34 108 216 216 Units MHz % kHz kHz kHz kHz kHz kHz kHz kHz % ns ns % ns ns ns ns % ns µs ns External SCLK Mode LRCK Duty Cycle (External SCLK only) SCLK Pulse Width Low SCLK Pulse Width High SCLK Duty Cycle SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time Internal SCLK Mode LRCK Duty Cycle (Internal SCLK only) SCLK Period SCLK rising to LRCK edge SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time MCLK / LRCK =1152, 1024, 512, 256, 128, or 64 SCLK rising to SDIN hold time MCLK / LRCK = 768, 384, 192, or 96 50 50 50 55 55 - 10 9 --------------------- + 10 ( 512 ) Fs 10 9 --------------------- + 15 ( 512 ) Fs 10 9 --------------------- + 15 ( 384 ) Fs tsclkw ----------------2 - - - ns tsdh - - ns 11. Not all sample rates are supported for all clock ratios. See table “Common Clock Frequencies” on page 12 for supported ratios and frequencies. 12. In Internal SCLK Mode, the duty cycle must be 50% ± 1/2 MCLK period. 13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on data format and MCLK/LRCK ratio. (See Figures 7-10) 9 Confidential Draft 2/12/08 CS4361 LRCK t slrd t slrs t sclkl t sclkh SCLK t sdlrs SDATA t sdh Figure 3. External Serial Mode Input Timing LR C K t s clkr S D A TA t sclkw t sdlrs *IN TE R N AL S C L K t sdh Figure 4. Internal Serial Mode Input Timing * The SCLK pulses shown are internal to the CS4361. LRCK MCLK 1 *INTERNAL SCLK N 2 N SDATA Figure 5. Internal Serial Clock Generation * The SCLK pulses shown are internal to the CS4361. N equals MCLK divided by SCLK 10 Confidential Draft 2/12/08 3. TYPICAL CONNECTION DIAGRAM CS4361 +1.8 V to +5 V 1 VL 2 3 Audio Data Processor 4 5 6 SDIN1 SDIN2 SDIN3 DEM/SCLK LRCK AOUT1 AOUT2 AOUT3 AOUT4 AOUT5 AOUT6 19 18 17 16 13 12 20 15 VA 0.1 µF + 1 µF +5 V Note* 3.3 µF + 10 kΩ C 470 Ω Audio Output Optional Muting Circuit Rext MUTEC CS4361 External Clock 7 MCLK µControler VL I2S LRCK MCLK RJ24 RJ16 8 Rext + 470 For best 20 kHz response 4πFs(Rext 470) Note* = This circuitry is intended for applications where the CS4361 connects directly to an unbalanced output of the design. For internal routing applications please see the DAC analog output characteristics for loading limitations. C= FILT+ 10 + 33 µF RST 9 MODE GND 14 VQ 11 0.1 µF *3.3 µF or *10 µF *Popguard ramp can be adjusted by selecting this capacitor value to be 3.3 µF to give 250 ms ramp time or 10 µF to give a 420 ms ramp time. + GND LJ Figure 6. Recommended Connection Diagram 11 Confidential Draft 2/12/08 4. APPLICATIONS CS4361 The CS4361 accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pin (SDIN). The Left/Right Clock (LRCK) determines which channel is currently being input on SDIN, and the optional Serial Clock (SCLK) clocks audio data into the input data buffer. 4.1 Master Clock MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and speed mode is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are set to generate the proper clocks. Table 1 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK, and SCLK must be synchronous. LRCK (kHz) 32 44.1 48 64 88.2 96 128 176.4 192 Mode 64x 8.1920 11.2896 12.2880 96x 128x 192x 12.2880 16.9344 18.4320 33.8680 36.8640 MCLK (MHz) 256x 384x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 22.5792 33.8680 24.5760 36.8640 32.7680 49.1520 DSM 512x 22.5792 24.5760 32.7680 - 768x 1024x 1152x 36.8640 - 8.1920 11.2896 12.2880 12.2880 16.9344 22.5792 18.4320 24.5760 QSM 32.7680 33.8680 45.1580 36.8640 49.1520 49.1520 SSM Table 1. Common Clock Frequencies 4.2 Serial Clock The serial clock controls the shifting of data into the input data buffers. The CS4361 supports both external and internal serial clock generation modes. Refer to Figures 7-10 for data formats. 4.2.1 External Serial Clock Mode The CS4361 will enter the External Serial Clock Mode when 16 low-to-high transitions are detected on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial Clock Mode and de-emphasis filter cannot be accessed. The CS4361 will switch to Internal Serial Clock Mode if no low-to-high transitions are detected on the DEM/SCLK pin for two consecutive frames of LRCK. Refer to Figure 12. 4.2.2 Internal Serial Clock Mode In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and LRCK. The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format. Operation in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode allows access to the digital de-emphasis function. Refer to Figures 7 - 12 for details. 12 Confidential Draft 2/12/08 CS4361 R ig h t C ha n ne l LR C K SCLK Left C ha nn el SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Internal SCLK Mode I²S, 16-Bit data and INT SCLK = 32 Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 I²S, Up to 24-Bit data and INT SCLK = 48 Fs if MCLK/LRCK = 768, 384, 192, or 96 I²S, Up to 24-Bit data and INT SCLK = 72 Fs if MCLK/LRCK = 1152 External SCLK Mode I²S, up to 24-Bit Data Data Valid on Rising Edge of SCLK Figure 7. CS4361 Data Format (I²S) LR C K SCLK Left C ha nn el R ig h t C ha n ne l SDATA M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LS B M SB -1 -2 -3 -4 +5 +4 +3 +2 +1 LS B Internal SCLK Mode Left-Justified, up to 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 INT SCLK = 48 Fs if MCLK/LRCK = 768, 384, 192, or 96 INT SCLK = 72 Fs if MCLK/LRCK = 1152 External SCLK Mode Left-Justified, up to 24-Bit Data Data Valid on Rising Edge of SCLK Figure 8. CS4361 Data Format (Left-Justified) LR C K Left C ha nn el R ig ht C h an nel SCLK SDATA 0 23 22 21 20 19 18 7 6 5 4 3 2 1 0 23 22 21 20 19 18 7 6 5 4 3 2 1 0 Internal SCLK Mode Right-Justified, 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 INT SCLK = 48 Fs if MCLK/LRCK = 768, 384, 192, or 96 INT SCLK = 72 Fs if MCLK/LRCK = 1152 32 clocks External SCLK Mode Right-Justified, 24-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 48 Cycles per LRCK Period Figure 9. CS4361 Data Format (Right-Justified 24) 13 Confidential Draft 2/12/08 LR CK R ig ht C h a n ne l CS4361 L e ft C h a nn e l SCLK SDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Internal SCLK Mode 32 clocks Right-Justified, 16-Bit Data INT SCLK = 32 Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 INT SCLK = 48 Fs if MCLK/LRCK = 768, 384, 192, or 96 INT SCLK = 72 Fs if MCLK/LRCK = 1152 External SCLK Mode Right-Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period Figure 10. CS4361 Data Format (Right-Justified 16) 4.3 De-Emphasis The CS4361 includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for five consecutive falling edges of LRCK. This function is available only in the internal Serial Clock Mode when LRCK < 50 kHz. Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 3.183 kHz F2 Frequency 10.61 kHz Figure 11. De-Emphasis Curve (Fs = 44.1kHz) 4.4 Mode Select Mode selection is determined by the Mode Select pin. The value of this pin is locked 1024 LRCK cycles after RST is released. This pin requires a specific connection to supply, ground, MCLK, or LRCK as outlined in Table 2. Mode pin is: Tied to VL Tied to GND Tied to LRCK Tied to MCLK Mode I²S Left-Justified Right-Justified - 24 bit Right-Justified - 16bit Table 2. Mode Pin Settings Figure 7 8 9 10 14 Confidential Draft 2/12/08 4.5 Initialization and Power-Down CS4361 The initialization and power-down sequence flow chart is shown in Figure 12. The CS4361 enters the power-down state upon initial power-up. The interpolation filters and delta-sigma modulators are reset, and the internal voltage reference, multi-bit digital-to-analog converters, and switched-capacitor low-pass filters are powered down. The device will remain in the Power-Down Mode until RST is released and MCLK and LRCK are present. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Finally, power is applied to the D/A converters and switched-capacitor filters, and the analog outputs will ramp to the quiescent voltage, VQ. USER: Apply Power VQ and outputs ramp down Power-Down State VQ and outputs low VQ and outputs ramp down USER: Apply MCLK, release RST USER: Apply RST or remove MCLK VQ and outputs ramp up USER: Apply RST or remove MCLK USER: Remove LRCK Wait State USER: Remove LRCK USER: Apply LRCK and MCLK USER: change MCLK/LRCK ratio MCLK/LRCK Ratio Detection USER: change MCLK/LRCK ratio USER: No SCLK USER: Applied SCLK SCLK mode = internal SCLK mode = external Normal Operation De-emphasis available Normal Operation De-emphasis not available Analog Output is Generated Analog Output is Generated Figure 12. CS4361 Initialization and Power-Down Sequence 15 Confidential Draft 2/12/08 4.6 Output Transient Control CS4361 The CS4361 uses Popguard technology to minimize the effects of output transients during power-up and power-down. When implemented with external DC-blocking capacitors connected in series with the audio outputs, this feature eliminates the audio transients commonly produced by single-ended, single-supply converters. To make the best use of this feature, it is necessary to understand its operation. 4.6.1 Power-Up When the device is initially powered up, the audio outputs, AOUT1-6, are clamped to VQ, which is initially low. After RST is released and MCLK is applied, the outputs begin to ramp with VQ towards the nominal quiescent voltage. This ramp takes approximately 200 ms to complete. The gradual voltage ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Audio output begins approximately 2000 sample periods after valid LRCK and SDIN are supplied (and SCLK, if used). 4.6.2 Power-Down To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turning off the power. In order to do this, either stop MCLK or hold RST low for a period of about 250 ms before removing power. During this time, voltage on VQ and the audio outputs discharge gradually to GND. If power is removed before this 250 ms time period has passed, a transient will occur when the VA supply drops below that of VQ. There is no minimum time for a power cycle; power may be reapplied at any time. When changing clock ratio or sample rate, it is recommended that zero data (or near zero data) be present on SDIN for at least 10 LRCK samples before the change is made. During the clocking change, the DAC outputs will always be in a zero data state. If non-zero audio is present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes to its zero data state. 4.7 Grounding and Power Supply Decoupling As with any high-resolution converter, the CS4361 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 6 shows the recommended power arrangement, with VA connected to a clean +5 V supply. For best performance, decoupling and filter capacitors should be located as close to the device package as possible, with the smallest capacitors placed closest. 4.8 Analog Output and Filtering The analog filter present in the CS4361 is a switched-capacitor filter followed by a continuous-time, lowpass filter. Its response, combined with that of the digital interpolator, is given in Figures 14 - 21. The recommended external analog circuitry is shown in the “Typical Connection Diagram” on page 11. The analog outputs are named AOUT1-6. The SDIN1 feeds AOUT1 as the ‘Left’ marked data and AOUT2 as the ‘Right’ marked data. The SDIN2 feeds AOUT3 as the ‘Left’ marked data and AOUT4 as the ‘Right’ marked data. The SDIN3 feeds AOUT5 as the ‘Left’ marked data and AOUT6 as the ‘Right’ marked data. 16 Confidential Draft 2/12/08 4.9 Mute Control CS4361 The MUTEC pin is intended to be used as control for an external mute circuit in order to add off-chip mute capability. This pin becomes active under the following conditions: 1. During power-up initialization 2. Upon reset 3. If the MCLK to LRCK ratio is incorrect 4. Upon receipt of 512 consecutive samples of zero 5. During power-down The MUTEC pin will only go active on static zero data only if all 6 channels satisfy the 512 sample requirement. If any channel receives non-zero data, the mute pin will return low (inactive). Use of the mute control function is not mandatory but is recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the mute control function can enable the system designer to achieve idle channel noise and signal-to-noise ratios that are only limited by the external mute circuit. The MUTEC pin is an active-high CMOS driver. See Figure 13 below for a suggested active-high mute circuit. AC Couple AO UT 470 Ω Filter Cap 6 10 k Ω A udio O ut 47 k Ω C S 4361 +V A MMU N 2111LT1 2 kΩ MU TE C 10 k Ω MMU N 2211LT1 -V (if a va ila ble ) 6 (Low R on) Figure 13. Suggested Active-Low Mute Circuit 17 Confidential Draft 2/12/08 5. PERFORMANCE PLOTS CS4361 Figure 14. Single-Speed Stopband Rejection Figure 15. Single-Speed Transition Band Figure 16. Single-Speed Transition Band Figure 17. Single-Speed Passband Ripple 18 Confidential Draft 2/12/08 CS4361 Figure 18. Double-Speed Stopband Rejection Figure 19. Double-Speed Transition Band Figure 20. Double-Speed Transition Band Figure 21. Double-Speed Passband Ripple 19 Confidential Draft 2/12/08 0 0 CS4361 -10 -10 -20 -30 -20 -40 Amplitude (dB) Amplitude (dB) -30 -50 -60 -40 -70 -50 -80 -60 -90 -100 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 0.9 1 0.35 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 0.75 Figure 22. Quad-Speed Stopband Rejection Figure 23. Quad-Speed Transition Band 0 0.2 -5 0.15 -10 -15 -20 -25 -30 -35 -0.1 -40 -0.15 -45 -0.2 -50 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.1 0.05 Amplitude (dB) Amplitude (dB) 0 -0.05 Figure 24. Quad-Speed Transition Band Figure 25. Quad-Speed Passband Ripple 20 Confidential Draft 2/12/08 6. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) CS4361 The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 21 Confidential Draft 2/12/08 7. PACKAGE INFORMATION 20L TSSOP (4.4 mm BODY) PACKAGE DRAWING N CS4361 D E11 A2 A1 L E A ∝ e b2 SIDE VIEW 123 END VIEW SEATING PLANE TOP VIEW DIM A A1 A2 b D E E1 e L µ MIN -0.002 0.03346 0.00748 0.252 0.248 0.169 -0.020 0° INCHES NOM -0.004 0.0354 0.0096 0.256 0.2519 0.1732 -0.024 4° MAX 0.043 0.006 0.037 0.012 0.259 0.256 0.177 0.026 0.028 8° MIN -0.05 0.85 0.19 6.40 6.30 4.30 -0.50 0° MILLIMETERS NOM --0.90 0.245 6.50 6.40 4.40 -0.60 4° NOTE MAX 1.10 0.15 0.95 0.30 6.60 6.50 4.50 0.65 0.70 8° 2,3 1 1 JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. 22 Confidential Draft 2/12/08 8. ORDERING INFORMATION Product CS4361 CDB4361 CS4361 Description Package Pb-Free Yes - Grade Commercial - Temp Range -40 to 85° C - Container Tube - Order # CS4361-CZZ CDB4361 20-pin, 24-bit, 20-Plastic 192 kHz, 6-channel TSSOP D/A Converter CS4361 Evaluation Board 23 Confidential Draft 2/12/08 9. REVISION HISTORY Release A1 A2 F1 Initial Release. Correction to PDF file size. CS4361 Changes Removed VA = 3.3 V operation. Updated Typ and Max THD+N and Dynamic Range specs in “DAC Analog Characteristics - Commercial (CZZ)” on page 6. Corrected “Output Transient Control” on page 16 and “CS4361 Initialization and Power-Down Sequence” on page 15 to show ramp down when MCLK is removed. Corrected MUTEC description “512 LRCK cycles” in “Mute Control” on page 17. Removed -DZZ ordering option. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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