CDB4362

CS4362 114 dB, 192 kHz 6-Channel D/A Converter Features 24-bit Conversion Up to 192 kHz Sample Rates 114 dB Dynamic Range -100 dB THD+N Supports PCM or DSD Data Formats Selectable Digital Filters Volume Control with Soft Ramp – 1 dB Step Size – Zero Crossing Click-free Transitions Description The CS4362 is a complete 6-channel digital-to-analog system including digital interpolation, fifth-order deltasigma digital-to-analog conversion, digital de-emphasis, volume control and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. The CS4362 accepts PCM data at sample rates from 4 kHz to 192 kHz, DSD audio data, and operates over a wide power supply range. These features are ideal for multi-channel audio systems including DVD players. SACD players, A/V receivers, digital TV’s, mixing consoles, and effects processors. ORDERING INFORMATION CS4362-KQZ, Lead Free -10 to 70 °C 48-pin LQFP CDB4362 Evaluation Board Dedicated DSD inputs Low Clock Jitter Sensitivity Simultaneous Support for Two Synchronous Sample Rates for DVD Audio µC or Stand-Alone Operation I M 3/DSD_SCLK M1/SCL/CCLK M 2/SDA/CDIN M 0/AD0/CS VLC M UTEC[1:6] 6 RST Control Port/M ode Select E xt e rn a l M u t e C o n tr ol ∆Σ D A C VLS S CLK1 LRCK1 S CLK 2 S e ri a l P o r t L R CK 2 SD I N1 SD I N2 SD I N3 V olu m e C o nt r o l Mixer V olu m e C o nt r o l I n t e r p o la t i o n F i lt e r A n a lo g F i lt e r A O U T A1+ A O U T A1A O U T B1+ A O U T B1A O U T A2+ A O U T A2A O U T B2+ A O U T B2A O U T A3+ A O U T A3A O U T B3+ A O U T B3VQ FILT+ I n t e r p o la t i o n F i lt e r ∆Σ D A C A n a lo g F i lt e r V olu m e C o nt r o l Mixer V olu m e C o nt r o l I n t e r p o la t i o n F i lt e r ∆Σ D A C A n a lo g F i lt e r I n t e r p o la t i o n F i lt e r ∆Σ D A C A n a lo g F i lt e r V olu m e C o nt r o l M CLK Mixer V olu m e C o nt r o l I n t e r p o la t i o n F i lt e r ∆Σ D A C A n a lo g F i lt e r I n t e r p o la t i o n F i lt e r ∆Σ D A C A n a lo g F i lt e r ÷2 DSDxx 6 VD GND GND VA http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2004 (All Rights Reserved) NOV ‘04 DS257F1 CS4362 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 ANALOG CHARACTERISTICS ................................................................................................ 4 POWER AND THERMAL CHARACTERISTICS....................................................................... 5 ANALOG FILTER RESPONSE................................................................................................. 6 DIGITAL CHARACTERISTICS ................................................................................................. 7 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7 RECOMMENDED OPERATING CONDITIONS ....................................................................... 7 SWITCHING CHARACTERISTICS .......................................................................................... 8 DSD - SWITCHING CHARACTERISTICS................................................................................ 9 SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT ................................ 10 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT............................ 11 2. REGISTER QUICK REFERENCE .......................................................................................... 14 3. REGISTER DESCRIPTION .................................................................................................... 15 4. PIN DESCRIPTION ................................................................................................................. 24 5. APPLICATIONS ...................................................................................................................... 27 5.1 Grounding and Power Supply Decoupling ....................................................................... 27 5.2 Oversampling Modes ....................................................................................................... 27 5.3 Recommended Power-up Sequence ............................................................................... 27 5.4 Analog Output and Filtering ............................................................................................. 27 5.5 Interpolation Filter ............................................................................................................ 27 5.6 Clock Source Selection .................................................................................................... 28 5.7 Using DSD mode ............................................................................................................. 28 5.8 Recommended Procedure for Switching Operational Modes .......................................... 28 6. CONTROL PORT INTERFACE .............................................................................................. 29 6.1 Enabling the Control Port ................................................................................................. 29 6.2 Format Selection .............................................................................................................. 29 6.3 I2C Format ....................................................................................................................... 29 6.3.1 Writing in I2C Format ........................................................................................... 29 6.3.2 Reading in I2C Format ........................................................................................ 29 6.4 SPI Format ....................................................................................................................... 30 6.4.1 Writing in SPI ...................................................................................................... 30 6.5 Memory Address Pointer (MAP) ................................................................................ 31 7. PARAMETER DEFINITIONS .................................................................................................. 39 8. REFERENCES ........................................................................................................................ 40 9. PACKAGE DIMENSIONS ....................................................................................................... 41 LIST OF FIGURES Figure 1. Serial Mode Input Timing ................................................................................................. 8 Figure 2. Direct Stream Digital - Serial Audio Input Timing............................................................. 9 Figure 3. Control Port Timing - I2C Format ................................................................................... 10 Figure 4. Control Port Timing - SPI Format................................................................................... 11 Figure 5. Typical Connection Diagram Control Port...................................................................... 12 Figure 6. Typical Connection Diagram Stand-Alone ..................................................................... 13 Figure 7. Control Port Timing, I2C Format .................................................................................... 30 Figure 8. Control Port Timing, SPI Format .................................................................................... 30 Figure 9. Single Speed (fast) Stopband Rejection ........................................................................ 32 Figure 10. Single Speed (fast) Transition Band ............................................................................ 32 Figure 11. Single Speed (fast) Transition Band (detail) ................................................................ 32 Figure 12. Single Speed (fast) Passband Ripple .......................................................................... 32 Figure 13. Single Speed (slow) Stopband Rejection..................................................................... 32 Figure 14. Single Speed (slow) Transition Band ........................................................................... 32 2 DS257F1 CS4362 Figure 15. Single Speed (slow) Transition Band (detail)............................................................... 33 Figure 16. Single Speed (slow) Passband Ripple......................................................................... 33 Figure 17. Double Speed (fast) Stopband Rejection..................................................................... 33 Figure 18. Double Speed (fast) Transition Band........................................................................... 33 Figure 19. Double Speed (fast) Transition Band (detail)............................................................... 33 Figure 20. Double Speed (fast) Passband Ripple......................................................................... 33 Figure 21. Double Speed (slow) Stopband Rejection ................................................................... 34 Figure 22. Double Speed (slow) Transition Band ......................................................................... 34 Figure 23. Double Speed (slow) Transition Band (detail) ............................................................. 34 Figure 24. Double Speed (slow) Passband Ripple ....................................................................... 34 Figure 25. Quad Speed (fast) Stopband Rejection ....................................................................... 34 Figure 26. Quad Speed (fast) Transition Band ............................................................................. 34 Figure 27. Quad Speed (fast) Transition Band (detail) ................................................................. 35 Figure 28. Quad Speed (fast) Passband Ripple ........................................................................... 35 Figure 29. Quad Speed (slow) Stopband Rejection...................................................................... 35 Figure 30. Quad Speed (slow) Transition Band ............................................................................ 35 Figure 31. Quad Speed (slow) Transition Band (detail) ................................................................ 35 Figure 32. Quad Speed (slow) Passband Ripple .......................................................................... 35 Figure 33. Format 0 - Left Justified up to 24-bit Data.................................................................... 36 Figure 34. Format 1 - I2S up to 24-bit Data................................................................................... 36 Figure 35. Format 2 - Right Justified 16-bit Data .......................................................................... 36 Figure 36. Format 3 - Right Justified 24-bit Data .......................................................................... 36 Figure 37. Format 4 - Right Justified 20-bit Data .......................................................................... 37 Figure 38. Format 5 - Right Justified 18-bit Data .......................................................................... 37 Figure 39. De-Emphasis Curve..................................................................................................... 37 Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, or 3)....................................... 37 Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, or 3) ...................................................... 38 Figure 42. Recommended Output Filter........................................................................................ 38 LIST OF TABLES Table 1. Digital Interface Formats - PCM Mode............................................................................ 16 Table 2. Digital Interface Formats - DSD Mode ............................................................................ 16 Table 3. ATAPI Decode ................................................................................................................ 21 Table 4. Example Digital Volume Settings .................................................................................... 22 Table 5. Common Clock Frequencies........................................................................................... 26 Table 6. Digital Interface Format, Stand-Alone Mode Options...................................................... 26 Table 7. Mode Selection, Stand-Alone Mode Options .................................................................. 26 Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................... 26 Table 9. Revision History ............................................................................................................. 42 DS257F1 3 CS4362 1. CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Test load RL = 3 kΩ, CL = 100 pF, VA = 5 V, VD = 3.3 V (see Figure 5) For Single speed Mode Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz; For Double Speed Mode Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz; For Quad Speed Mode Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz; For Direct Stream Digital Mode Fs = 128 x 48 kHz, DSD_SCLK = 6.144 MHz, MCLK = 12.288 MHz). Parameters Specified Temperature Range Dynamic Range (Note 2) unweighted A-Weighted 16-bit unweighted (Note 3) A-Weighted 24-bit (Note 2) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB (1 kHz) 24-bit Symbol TA Min -10 105 108 Typ 111 114 94 97 -100 -91 -51 -94 -74 -34 114 90 Max 70 -94 Unit °C dB dB dB dB dB dB dB dB dB dB dB dB CS4362-KQZ Dynamic Performance - All PCM modes and DSD (Note 1) Total Harmonic Distortion + Noise 16-bit (Note 3) Idle Channel Noise / Signal-to-noise ratio Interchannel Isolation Notes: 1. CS4362-KQZ parts are tested at 25 °C. 2. One-half LSB of triangular PDF dither is added to data. 3. Performance limited by 16-bit quantization noise. 4 DS257F1 CS4362 ANALOG CHARACTERISTICS (Continued) Parameters Analog Output - All PCM modes and DSD Full Scale Differential Output Voltage (Note 4) Quiescent Voltage Max Current from VQ Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance Load Capacitance Symbol VFS VQ IQMAX Min 86% VA 3 Typ 91% VA 50% VA 1 0.1 100 100 Max 96% VA 100 Units Vpp VDC µA dB ppm/°C Ω kΩ pF (Note 4) ZOUT RL CL POWER AND THERMAL CHARACTERISTICS Parameters Power Supplies Power Supply Current (Note 5) normal operation, VA= 5 V VD= 5 V VD= 3.3 V Interface current, VLC=5 V (Note 6, 7) VLS=5 V power-down state (all supplies) (Note 8) Power Dissipation (Note 5) VA = 5 V, VD = 3.3 V normal operation power-down (Note 8) VA = 5 V, VD = 5 V normal operation power-down (Note 8) Package Thermal Resistance Power Supply Rejection Ratio (Note 9) (1 kHz) (60 Hz) Symbol IA ID ID ILC ILS Ipd Min Typ 50 38 25 2 84 200 335 1 440 1 48 15 60 40 Max 55 60 40 410 575 Units mA mA mA µA µA µA mW mW mW mW °C/Watt °C/Watt dB dB θJA θJC PSRR Notes: 4. VFS is tested under load RL and includes attenuation due to ZOUT 5. Current consumption increases with increasing FS within a given speed mode and is signal dependant. Max values are based on highest FS and highest MCLK. 6. ILC measured with no external loading on the SDA pin. 7. This specification is violated when the VLC supply is greater than VD and when pin 16 (M1/SDA) is tied or pulled low. Logic tied to pin 16 needs to be able to sink this current. 8. Power down mode is defined as RST pin = Low with all clock and data lines held static. 9. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6. DS257F1 5 CS4362 ANALOG FILTER RESPONSE Fast Roll-Off Slow Roll-Off (Note 10) Parameter Min Typ Max Min Typ Max Unit Combined Digital and On-chip Analog Filter Response - Single Speed Mode (Note 11) Passband (Note 12) to -0.01 dB corner 0 .454 0 0.417 Fs to -3 dB corner 0 .499 0 0.499 Fs Frequency Response 10 Hz to 20 kHz -0.01 +0.01 -0.01 +0.01 dB StopBand .547 .583 Fs StopBand Attenuation (Note 13) 90 64 dB Group Delay 12/Fs 6.5/Fs s Passband Group Delay Deviation 0 - 20 kHz ±0.41/Fs ±0.14/Fs s De-emphasis Error (Note 14) Fs = 32 kHz ±0.23 ±0.23 dB (Relative to 1 kHz) Fs = 44.1 kHz ±0.14 ±0.14 dB Fs = 48 kHz ±0.09 ±0.09 dB Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96 kHz (Note 11) Passband (Note 12) to -0.01 dB corner 0 .430 0 .296 Fs to -3 dB corner 0 .499 0 .499 Fs Frequency Response 10 Hz to 20 kHz -0.01 0.01 -0.01 0.01 dB StopBand .583 .792 Fs StopBand Attenuation (Note 13) 80 70 dB Group Delay 4.6/Fs 3.9/Fs s Passband Group Delay Deviation 0 - 20 kHz ±0.03/Fs ±0.01/Fs s Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192 kHz (Note 11) Passband (Note 12) to -0.01 dB corner 0 .105 0 .104 Fs to -3 dB corner 0 .490 0 .481 Fs Frequency Response 10 Hz to 20 kHz -0.01 0.01 -0.01 0.01 dB StopBand .635 .868 Fs StopBand Attenuation (Note 13) 90 75 dB Group Delay 4.7/Fs 4.2/Fs s Passband Group Delay Deviation 0 - 20 kHz ±0.01/Fs ±0.01/Fs s Combined Digital and On-chip Analog Filter Response - DSD Mode (Note 11) Passband (Note 12) to -0.1 dB corner 0 20 kHz to -3 dB corner 0 120 kHz Frequency Response 10 Hz to 20 kHz -.01 0.1 dB Notes: 10. Slow Roll-Off interpolation filter is only available in control port mode. 11. Filter response is not tested but is guaranteed by design. 12. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 to 32) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 13. Single and Double Speed Mode Measurement Bandwidth is from stopband to 3 Fs. Quad Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs. 14. De-emphasis is available only in Single Speed Mode; Only 44.1 kHz De-emphasis is available in StandAlone Mode 6 DS257F1 CS4362 DIGITAL CHARACTERISTICS (For KQZ TA = -10 to +70 °C; VLC = VLS = 1.8 V to 5.5 V) Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Maximum MUTEC Drive Current MUTEC High-Level Output Voltage MUTEC Low-Level Output Voltage Symbol Min 70% VLS VIH Serial Data Port 70% VLC Control Port VIH VIL Serial Data Port VIL Control Port (Note 7) Iin Typ 8 3 VA 0 Max 20% VLS 20% VLC ±10 Units V V V V µA pF mA V V VOH VOL ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.) Parameters Analog power Digital internal power Serial data port interface power Control port interface power Input Current, Any Pin Except Supplies Digital Input Voltage Serial data port interface Control port interface Ambient Operating Temperature (power applied) Storage Temperature DC Power Supply Symbol VA VD VLS VLC Iin VIND-S VIND-C TA Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 -65 Max 6.0 6.0 6.0 6.0 ±10 VLS+ 0.4 VLC+ 0.4 125 150 Units V V V V mA V V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Analog power Digital internal power Serial data port interface power Control port interface power Symbol VA VD VLS VLC Min 4.5 3.0 1.8 1.8 Typ 5.0 3.3 5.0 5.0 Max 5.5 5.5 5.5 5.5 Units V V V V DS257F1 7 CS4362 SWITCHING CHARACTERISTICS (For KQZ TA = -10 to +70 °C; VLS = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF) Parameters MCLK Frequency (Note 15) Single Speed Mode Double Speed Mode Quad Speed Mode MCLK Duty Cycle Input Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Fs Fs Fs tsclkl tsclkh tsclkw (Note 16) SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time LRCK1 to LRCK2 frequency ratio (Note 17) tsclkw tslrd tslrs tsdlrs tsdh 1.024 6.400 6.400 40 4 50 100 45 20 20 2 ----------------MCLK 4 ----------------MCLK Symbol Min Typ 50 50 1.00 Max 51.2 51.2 51.2 60 50 100 200 55 4.00 Units MHz MHz MHz % kHz kHz kHz % ns ns ns ns ns ns ns ns LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Period 20 20 20 20 0.25 Notes: 15. See Table 5 on page 26 for suggested MCLK frequencies 16. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled. 17. The higher frequency LRCK must be an exact integer multiple (1, 2, or 4) of the lower frequency LRCK . LR C K t slrd t slrs t sclkl t sclkh S C LK t sdlrs S D ATA t sd h Figure 1. Serial Mode Input Timing 8 DS257F1 CS4362 DSD - SWITCHING CHARACTERISTICS (TA= -10 to 70°C; Logic 0 = GND; VLS = 1.8 V to 5.5 V; Logic 1 = VLS Volts; CL = 30 pF) Parameter Master Clock Frequency MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency Symbol (Note 18) (All DSD modes) tsclkl tsclkh Min 4.096 40 20 20 1.024 2.048 20 20 Typ 50 Max 38.4 60 3.2 6.4 Unit MHz % ns ns MHz MHz ns ns (64x Oversampled) (128x Oversampled) DSD_L / _R valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_L or DSD_R hold time tsdlrs tsdh Note: 18. Min is 4 times 64x DSD or 2 times 128x DSD, and Max is 12 times 64x DSD or 6 times 128x DSD. The proper MCLK to DSD_SCLK ratio must be set either by the DIF registers or the M0:2 pins t sclkh t sclkl D SD_SC LK t sd lrs D S D _L, D S D _R t sd h Figure 2. Direct Stream Digital - Serial Audio Input Timing DS257F1 9 CS4362 SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT (For KQZ TA = -10 to +70 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 20) (Note 19) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trc tfc, tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 Max 100 1 300 (Note 21) Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns Notes: 19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed. 21. 15 15 15 -------------------- for Single-Speed Mode, -------------------- for Double-Speed Mode, ----------------- for Quad-Speed Mode. 256 × Fs 128 × Fs 64 × Fs RST t S top irs R e p e a te d S t a rt S t a rt S top t rd t fd SDA t buf t t hdst high t hdst t fc t susp SCL t lo w t hdd t sud t ack t sust t rc Figure 3. Control Port Timing - I2C Format 10 DS257F1 CS4362 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT (For KQZ TA = -10 to +70 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 23) (Note 24) (Note 24) (Note 22) Symbol fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2 Min 500 500 1.0 20 1----------------MCLK 1----------------MCLK Max MCLK ----------------2 Unit MHz ns ns µs ns ns ns ns ns ns ns 100 100 40 15 - Notes: 22. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 23. Data must be held for sufficient time to bridge the transition time of CCLK. 24. For FSCK < 1 MHz. RST t srs CS t spi t css CCLK t r2 C D IN t scl t sch t csh t f2 t dsu t dh Figure 4. Control Port Timing - SPI Format DS257F1 11 CS4362 +3.3 V to +5 V 1 µF + 0.1 µF 4 VD 32 VA 0.1 µF + 1 µF +5 V 6 7 PCM D igital A udio S ource 9 10 12 8 11 13 M C LK LRC K 1 S C LK 1 LRC K 2 S C LK 2 S D IN1 S D IN2 S D IN3 A O U TA 2+ 35 36 34 33 29 30 28 27 A nalog Conditioning and M uting A nalog Conditioning and M uting A O U TA 1+ A O U TA 1A O U TB 1+ A O U TB 139 40 38 37 A nalog Conditioning and M uting A nalog Conditioning and M uting +1.8 V to +5 V 0.1 µF 43 V LS A O U TA 2- C S 4362 A O U TB 2+ A O U TB 23 2 1 DSDA1 DSDB1 DSDA2 DSDB2 D S DA 3 D S DB 3 D S D _S CLK M UTE C 1 A O U TB 3+ A O U TB 3A O U TA 3+ A O U TA 3- A nalog Conditioning and M uting A nalog Conditioning and M uting DSD A udio S ource 48 47 46 42 41 19 M icroController 15 16 17 2 KΩ 2 KΩ RST S C L/C C LK S D A /C D IN A D O /C S M UTE C 2 26 25 M UTE C 3 24 M UTE C 4 23 M UTE C 5 M UTE C 6 22 M ute D rive N ote* +1.8 V to +5 V 18 0.1 µF V LC FILT+ 20 CM O UT 21 0.1 µ F + 1 µF 0.1 µ F + 47 µF Note*: Necessary for I 2 C control port operation G ND 5 G ND 31 Figure 5. Typical Connection Diagram Control Port 12 DS257F1 CS4362 +3.3 V to +5 V 1 µF + 0.1 µF 4 VD VLS Note DSD 47 K Ω 32 VA 0.1 µF + 1 µF +5 V 6 7 9 PCM Digital Audio Source 10 12 8 11 13 M CLK LRCK 1 SCLK 1 LRCK 2 SCLK 2 SDIN1 SDIN2 SDIN3 A O UTB1+ AO UTB 1M UTE C2 38 37 26 A nalog Conditioning and M uting A O UTA1+ AO UTA 1M UTE C1 39 40 41 A nalog Conditioning and M uting +1.8 V to +5 V 0.1 µF 43 VLS CS4362 A O UTA2+ AO UTA 23 2 1 48 47 46 DSDA 1 DSDB 1 DSDA 2 DSDB 2 DSDA 3 DSDB 3 A O UTA3+ 29 30 23 A nalog Conditioning and M uting A O UTB2+ AO UTB 2M UTE C4 34 33 24 A nalog Conditioning and M uting M UTE C3 35 36 25 A nalog Conditioning and M uting DS D A udio Source Note DS D AO UTA 3M UTE C5 47 K Ω 42 15 M 3(DSD_S CLK ) M2 M1 M0 RS T A O UTB3+ AO UTB 3M UTE C6 28 27 22 Analog Conditioning and M uting Stand-Alone M ode Configuration 16 17 19 Note VLC 18 0.1 µF FILT+ 20 CM O UT 21 0.1 µ F + 1 µF 0.1 µ F + 47 µF +1.8 V to +5 V VLC Note VLC : If series resistors are used they m ust be