CDB4392

CS4392 24-Bit, 192 kHz Stereo DAC with Volume Control Features Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering 114 dB Dynamic Range 100 dB THD+N Up to 192kHz Sample Rates Direct Stream Digital Mode Low Clock Jitter Sensitivity Single +5 V Power Supply Selectable Digital Filters – Fast and Slow roll-off Description The CS4392 is a complete stereo digital-to-analog system including digital interpolation, fifth-order delta-sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, and a high tolerance to clock jitter. The CS4392 accepts PCM data at sample rates from 4 kHz to 192 kHz, DSD audio data, has selectable digital filters, and consumes very little power. These features are ideal for DVD, SACD players, A/V receivers, CD and set-top box systems. The CS4392 is pin and register compatible with the CS4391, making easy performance upgrades possible. ORDERING INFORMATION CS4392-KS -10 to 70 °C 20-pin SOIC CS4392-KZ -10 to 70 °C 20-pin TSSOP CS4392-KZZ, Lead Free -10 to 70 °C 20-pin TSSOP CDB4392 Evaluation Board Volume Control with Soft Ramp – 1 dB Step Size – Zero Crossing Click-Free Transitions Direct Interface with 5 V to 1.8 V Logic ATAPI Mixing Functions Pin Compatible with the CS4391 I M1 (SDA/CDIN) M3 M2 (SCL/CCLK) M0 (AD0/CS) AMUTEC BMUTEC CMOUT FILT+ MODE SELECT (CONTROL PORT) RST EXTERNAL MUTE CONTROL REFERENCE VOLUME CONTROL SCLK SERIAL PORT LRCK VOLUME CONTROL MIXER INTERPOLATION FILTER ∆Σ DAC ANALOG FILTER AOUTA+ AOUTA- AOUTB+ INTERPOLATION FILTER ∆Σ DAC ANALOG FILTER AOUTB- SDATA MCLK Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2002 (All Rights Reserved) SEP ‘04 DS459PP3 CS4392 TABLE OF CONTENTS 1. PIN DESCRIPTION - PCM DATA MODE .................................................................... 5 1.1 PIN DESCRIPTION - DSD mode ..................................................................... 6 2. TYPICAL CONNECTION DIAGRAMS ........................................................................ 7 3. APPLICATIONS ........................................................................................................... 9 3.1 Recommended Power-up Sequence for Hardware Mode ................................ 9 3.2 Recommended Power-up Sequence and Access to Control Port Mode ............................................................................................. 9 3.3 Analog Output and Filtering .............................................................................. 9 3.4 Interpolation Filter ........................................................................................... 10 3.5 System Clocking ............................................................................................. 10 3.6 Digital Interface Format .................................................................................. 11 3.7 De-Emphasis .................................................................................................. 12 3.8 Oversampling Modes ...................................................................................... 12 3.9 Using DSD mode ............................................................................................ 13 3.10 Mute Control ................................................................................................. 13 4. CONTROL PORT INTERFACE ................................................................................. 14 4.0.1 MAP Auto Increment ............................................................................. 14 4.0.2 I2C Mode ............................................................................................... 14 I2C Write.................................................................................................... 14 I2C Read ................................................................................................... 15 4.0.3 SPI Mode ............................................................................................... 16 SPI Write.................................................................................................... 16 4.1 Memory Address Pointer (MAP) ...................................................................... 16 5. REGISTER QUICK REFERENCE ............................................................................. 17 6. REGISTER DESCRIPTION ........................................................................................ 18 6.1 Mode Control 1 - Address 01h ........................................................................ 18 6.1.1 Auto-Mute (Bit 7) ................................................................................... 18 6.1.2 Digital Interface Formats (Bits 6:4) ........................................................ 18 6.1.3 De-Emphasis Control (Bits 3:2) ............................................................. 19 6.1.4 Functional Mode (Bits 1:0) .................................................................... 19 6.2 Volume and Mixing Control (Address 02h) ..................................................... 20 6.2.1 Channel A Volume = Channel B Volume (Bit 7) .................................... 20 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. 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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 2 DS459PP3 CS4392 6.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ...........................................20 6.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) .........................................20 6.3 Channel A Volume Control - Address 03h ......................................................22 6.4.1 Mute (Bit 7) ............................................................................................22 6.4.2 Volume Control (Bits 6:0) .......................................................................22 6.5 Mode Control 2 - Address 05h ........................................................................22 6.5.1 Invert Signal Polarity (Bits 7:6) ...............................................................22 6.5.2 Control Port Enable (Bit 5) .....................................................................23 6.5.3 Power Down (Bit 4) ................................................................................23 6.5.4 AMUTEC = BMUTEC (Bit 3) ..................................................................23 6.5.5 Freeze (Bit 2) .........................................................................................23 6.5.6 Master Clock Divide (Bit 1) ....................................................................23 6.6 Mode Control 3 - Address 06h ........................................................................23 6.6.1 Interpolation Filter Select (Bit 4) .............................................................23 6.6.2 Soft Volume Ramp-up after Reset (Bit 3) ..............................................24 6.6.3 Soft Ramp-down before Reset (Bit 2) ....................................................24 6.7 Chip ID - Register 07h .....................................................................................24 7. CHARACTERISTICS/SPECIFICATIONS ..................................................................25 ANALOG CHARACTERISTICS (CS4392-KS/KZ/KZZ)...........................................25 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................................................................................................26 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE .......................32 SWITCHING SPECIFICATIONS - DSD INTERFACE.............................................33 SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE....................34 SWITCHING CHARACTERISTICS - SPI CONTROL PORT ..................................35 DC ELECTRICAL CHARACTERISTICS .................................................................36 DIGITAL INPUT CHARACTERISTICS & SPECIFICATIONS .................................36 RECOMMENDED OPERATING SPECIFICATIONS ..............................................37 ABSOLUTE MAXIMUM RATINGS ..........................................................................37 8. PARAMETER DEFINITIONS ......................................................................................38 9. REFERENCES ............................................................................................................38 10. PACKAGE DIMENSIONS ........................................................................................39 LIST OF TABLES Table 1. Clock Ratios .................................................................................................................... 10 Table 2. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies ......................... 10 Table 3. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies................... 10 Table 4. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies ................... 10 Table 5. Digital Interface Format, Stand-Alone Mode Options...................................................... 11 Table 5. De-Emphasis Select, Stand-Alone Mode........................................................................ 12 Table 6. Mode Selection, Stand-Alone Mode Options .................................................................. 12 Table 7. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................... 13 Table 8. Digital Interface Formats - PCM Modes .......................................................................... 18 Table 10. De-Emphasis Mode Selection...................................................................................... 19 Table 11. Functional Mode Selection............................................................................................ 19 Table 12. Soft Cross or Zero Cross Mode Selection.................................................................... 20 Table 13. ATAPI Decode .............................................................................................................. 21 Table 14. Digital Volume Control Example Settings ..................................................................... 22 DS459PP3 3 CS4392 LIST OF FIGURES Figure 1. Typical Connection Diagram - PCM Mode....................................................................... 7 Figure 2. Typical Connection Diagram - DSD Mode ....................................................................... 8 Figure 3. CS4392 Output Filter ....................................................................................................... 9 Figure 4. Format 0, Left Justified up to 24-Bit Data....................................................................... 11 Figure 5. Format 1, I2S up to 24-Bit Data ..................................................................................... 11 Figure 6. Format 2, Right Justified 16-Bit Data Format 3, Right Justified 24-Bit Data Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only) Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)................ 11 Figure 7. De-Emphasis Curve ....................................................................................................... 12 Figure 8. Control Port Timing, I2C Mode....................................................................................... 15 Figure 9. Control Port Timing, SPI mode ...................................................................................... 16 Figure 10. De-Emphasis Curve ..................................................................................................... 19 Figure 11. ATAPI Block Diagram .................................................................................................. 21 Figure 12. Single Speed (fast) Stopband Rejection ...................................................................... 28 Figure 13. Single Speed (fast) Transition Band ............................................................................ 28 Figure 14. Single Speed (fast) Transition Band (detail) ................................................................ 28 Figure 15. Single Speed (fast) Passband Ripple .......................................................................... 28 Figure 16. Single Speed (slow) Stopband Rejection..................................................................... 28 Figure 17. Single Speed (slow) Transition Band ........................................................................... 28 Figure 18. Single Speed (slow) Transition Band (detail) ............................................................... 29 Figure 19. Single Speed (slow) Passband Ripple ......................................................................... 29 Figure 20. Double Speed (fast) Stopband Rejection..................................................................... 29 Figure 21. Double Speed (fast) Transition Band ........................................................................... 29 Figure 22. Double Speed (fast) Transition Band (detail) ............................................................... 29 Figure 23. Double Speed (fast) Passband Ripple ......................................................................... 29 Figure 24. Double Speed (slow) Stopband Rejection ................................................................... 30 Figure 25. Double Speed (slow) Transition Band.......................................................................... 30 Figure 26. Double Speed (slow) Transition Band (detail).............................................................. 30 Figure 27. Double Speed (slow) Passband Ripple........................................................................ 30 Figure 28. Quad Speed (fast) Stopband Rejection ....................................................................... 30 Figure 29. Quad Speed (fast) Transition Band.............................................................................. 30 Figure 30. Quad Speed (fast) Transition Band (detail).................................................................. 31 Figure 31. Quad Speed (fast) Passband Ripple............................................................................ 31 Figure 32. Quad Speed (slow) Stopband Rejection ...................................................................... 31 Figure 33. Quad Speed (slow) Transition Band ............................................................................ 31 Figure 34. Quad Speed (slow) Transition Band (detail) ................................................................ 31 Figure 35. Quad Speed (slow) Passband Ripple .......................................................................... 31 Figure 36. Serial Mode Input Timing ............................................................................................. 32 Figure 37. Direct Stream Digital - Serial Audio Input Timing......................................................... 33 Figure 38. I2C Mode Control Port Timing...................................................................................... 34 Figure 39. SPI Control Port Timing ............................................................................................... 35 4 DS459PP3 CS4392 1. PIN DESCRIPTION - PCM DATA MODE RST VL SDATA SCLK LRCK MCLK M3 (SCL/CCLK) M2 (SDA/CDIN) M1 (AD0/CS) M0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AMUTEC AOUTAAOUTA+ VA AGND AOUTB+ AOUTBBMUTEC CMOUT FILT+ RST VL SDATA SCLK LRCK MCLK FILT+ CMOUT AMUTEC BMUTEC AOUTBAOUTB+ AOUTA+ AOUTA AGND VA M3 SCL/CCLK SDA/CDIN AD0/CS 1 2 3 4 5 6 11 12 20 13 14 15 18 19 16 17 7 8 9 10 Reset (Input) - Powers down device and resets all internal registers to their default settings. Logic Power (Input) - Positive power for the digital input/output. Serial Audio Data (Input) - Input for two’s complement serial audio data. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Common Mode Voltage (Output) - Filter connection for internal quiescent voltage. Mute Control (Output) - The Mute Control pin goes high during power-up initialization, reset, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. Differential Analog Output (Outputs) - The full scale differential analog output level is specified in the Analog Characteristics specification table. Ground (Input) Analog Power (Input) - Positive power for the analog section. Mode Selection (Input) - This pins should be tied to GND level during control port mode. Serial Control Port Clock (Input) - Serial clock for the serial control port. Serial Control Data (Input/Output) - SDA is a data I/O line in I2C mode. CDIN is the input data line for the control port interface in SPI mode. Address Bit 0 (I2C) / Control Port Chip Select (SPI) (Input/Output) - AD0 is a chip address pin in I2C mode; CS is the chip select signal for SPI format. Mode Selection (Input) - Determines the operational mode of the device. Control Port Mode Definitions Stand-Alone Mode Definitions M3 M2 M1 M0 7 8 9 10 DS459PP3 5 CS4392 1.1 PIN DESCRIPTION - DSD mode RST VL DSD_A DSD_B DSD_MODE MCLK DSD_SCLK (SCL/CCLK) M2 (SDA/CDIN) M1 (AD0/CS) M0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AMUTEC AOUTAAOUTA+ VA AGND AOUTB+ AOUTBBMUTEC CMOUT FILT+ DSD_A DSD_B DSD_Mode DSD_SCLK 3 4 5 7 DSD Data (Input) - Input for Direct Stream Digital serial audio data. DSD Mode (Input) - In stand alone mode, this pin must be set to a logic ‘1’ for operation of DSD Mode. DSD Serial Clock (Input/Output) - Serial clock for the Direct Stream Digital audio interface. 6 DS459PP3 CS4392 2. TYPICAL CONNECTION DIAGRAMS 0.1 µf 17 VA M0 (AD0/CS) M1 (SDA/CDIN) M2 (SCL/CCLK) M3 CS4392 Logic Power +5V to 1.8V 2 0.1 µf 5 Audio Data Processor * 4 3 1 VL AOUTA19 FILT+ 11 + 1.0 µ f +5V Analog 10 Mode Select (Control Port) * 9 8 7 0.1 µf + 10 µf Analog Conditioning & Mute AMUTEC 20 LRCK SCLK SDATA RST AOUTB+ 6 MCLK AGND 16 AOUTBBMUTEC 14 AOUTA+ 18 Analog 13 15 Conditioning & Mute CMOUT 12 + 1.0 µf External Clock Figure 1. Typical Connection Diagram - PCM Mode * A high logic level for all digital inputs should not exceed VL. DS459PP3 7 CS4392 0.1 µf 17 VA 10 Mode Select (Control Port) 9 8 + 1.0 µ f +5V Analog M0 (AD0/CS) M1 (SDA/ CDIN) M2 (SCL/CCLK) CS4392 FILT+ 11 0.1 µf + 10 µf Logic Power +5V to 1.8V 0.1 µf 2 5 7 Audio Data Processor * 4 3 1 AOUTAVL AMUTEC DSD_MODE AOUTA+ DSD_CLK DSD_B AOUTBDSD_A BMUTEC RST AOUTB+ 19 Analog 20 18 Conditioning & Mute 14 Analog 13 15 Conditioning & Mute 6 MCLK CMOUT AGND 16 12 + 1.0 µf External Clock Figure 2. Typical Connection Diagram - DSD Mode * A high logic level for all digital inputs should not exceed VL. 8 DS459PP3 CS4392 3. APPLICATIONS 3.1 Recommended Power-up Sequence for Hardware Mode 1) Hold RST low until the power supplies, master, and left/right clocks are stable. 2) Bring RST high. After 10ms the device will begin normal operation. 3.2 Recommended Power-up Sequence and Access to Control Port Mode 1) Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control port is reset to its default settings and FILT+ will remain low. 2) Bring RST high. The device will remain in a low power state with FILT+ low and the control port is accessible. 3) Write 30h to register 05h within 10 ms cycles following the release of RST. If after 10ms the control port has not been initiated with this command, the device will enter stand-alone mode. The CPEN bit, however, may be written at any time after 10ms. It is recommended to write CPEN before 10ms in order to reduce the possibility of any extraneous click or pop noise from occurring. 4) The desired register settings can be loaded while keeping the PDN bit set to 1. 5) Set the PDN bit to 0. This will initiate the power-up sequence which requires approximately 10 µS. 3.3 Analog Output and Filtering The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order Butterworth filter and differential to single-ended converter as seen in Figure 3. An alternate configuration can be seen on the CDB4392. This alternate filter configuration accounts for the differing AC loads on the + and - differential output pins which are normally present in a circuit like Figure 3. It also shows an AC coupling configuration which reduces the number of required AC coupling capacitors to 2 caps per channel. The circuit in figure 3 may also be DC coupled, however the filter on the CDB4392 must be AC coupled. The CS4392 is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry. 3.32k 2700 pF 680 pF Aout + 10 uF 3.01k 1.58k C10 2700 pF R17 3.32k 680 pF Figure 3. CS4392 Output Filter DS459PP3 + 3 - Aout - 10 uF 3.01k 1.58k 2 1 10 uF 560 Analog_Out 47k 9 CS4392 3.4 Interpolation Filter To accommodate the increasingly complex requirements of digital audio systems, the CS4392 incorporates selectable interpolation filters for each mode of operation. A fast and a slow roll-off filter is available in each of Single, Double, and Quad Speed modes. These filters have been designed to accommodate a variety of musical tastes and styles. Bit 5 of the Mode Control 3 register (06h) is used to select which filter is used. Filter specifications can be found in Section 8, and filter response plots can be found in Figures 12 to 35. In stand-alone mode, only the fast roll-off filter is available. 3.5 System Clocking The required MCLK to LRCK and suggested SCLK to LRCK ratios are outlined in table 1. MCLK can be at any phase in regards to LRCK and SCLK. SCLK, LRCK and SDATA must meet the phase and timing relationships outlined in Section 7. Some common MCLK frequencies have been outlined in tables 2 to 4. MCLK/LRCK Single Speed Double Speed 256, 384, 512, 768, 1024* 128, 192, 256, 384, 512* 64 Quad Speed 96 128, 256* 192 Table 1. Clock Ratios Sample Rate (kHz) 32 44.1 48 MCLK (MHz) 256x 8.1920 11.2896 12.2880 384x 12.2880 16.9344 18.4320 512x 16.3840 22.5792 24.5760 768x 24.5760 33.8688 36.8640 See Note 1024x* 32.7680 45.1584 49.1520 SCLK/LRCK 32, 48, 64, 96, 128 32, 48, 64 32 (16 bits only) 32, 48 32, 64 32, 48, 64, 96 LRCK Fs Fs Fs Fs Fs Fs Table 2. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies Sample Rate (kHz) 64 88.2 96 128x 8.1920 11.2896 12.2880 MCLK (MHz) 192x 256x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 384x 24.5760 33.8688 36.8640 See Note 512x* 32.7680 45.1584 49.1520 Table 3. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies Sample Rate (kHz) 176.4 192 64x 11.2896 12.2880 MCLK (MHz) 96x 128x 16.9344 22.5792 18.4320 24.5760 192x 33.8688 36.8640 See Note 256x* 45.1584 49.1520 Table 4. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies *Note:These clocking ratios are only available in Control Port Mode when the MCLK Divide bit is enabled. 10 DS459PP3 CS4392 3.6 Digital Interface Format The device will accept audio samples in several digital interface formats as illustrated in Tables 5 and 8. The desired format is selected via the M0 and M1 pins for stand alone mode, and through the DIF2:0 bits in the control port. For an illustration of the required relationship between the Left/Right Clock, Serial Clock and Serial Audio Data, see Figures 4-6. M1 0 0 1 1 M0 0 1 0 1 DESCRIPTION Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data FORMAT 0 1 2 3 FIGURE 4 5 6 6 Table 5. Digital Interface Format, Stand-Alone Mode Options Left C ha nn el LR C K SCLK R ig h t C ha n ne l SDATA M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LS B M SB -1 -2 -3 -4 +5 +4 +3 +2 +1 LS B Figure 4. Format 0, Left Justified up to 24-Bit Data LR C K SCLK Le ft C ha n nel R ig h t C ha n nel SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 5. Format 1, I2S up to 24-Bit Data LR C K L e ft C h a n ne l R ig h t C h a n n e l SC LK SD ATA LS B MS -1 -2 -3 -4 -5 -6 B B +6 +5 +4 +3 +2 +1 LS MS -1 -2 -3 -4 -5 -6 B B +6 +5 +4 +3 +2 +1 LS 3 2 c lo cks Figure 6. Format 2, Right Justified 16-Bit Data Format 3, Right Justified 24-Bit Data Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only) Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only) DS459PP3 11 CS4392 3.7 De-Emphasis The device includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve for FS equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see Table 5 for the desired de-emphasis control for Stand-alone mode and Table 10 for control port mode. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 µS pre-emphasis equalization as a means of noise reduction. De-emphasis is only available in Single Speed Mode. Gain dB T1=50 µs 0dB T2 = 15 µs -10dB M2 DESCRIPTION (DEM) No De-Emphasis 0 De-Emphasis Enabled 1 FIGURE 7 Table 5. De-Emphasis Select, Stand-Alone Mode F1 3.183 kHz F2 Frequency 10.61 kHz Figure 7. De-Emphasis Curve 3.8 Oversampling Modes The CS4392 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the M3 and M2 pins in Stand-Alone mode or the FM bits in Control Port mode. SingleSpeed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x M3 0 0 1 1 M2 0 1 0 1 DESCRIPTION Single-Speed without De-Emphasis (4 to 50 kHz sample rates) Single-Speed with 44.1kHz De-Emphasis Double-Speed (50 to 100 kHz sample rates) Quad-Speed (100 to 200 kHz sample rates) Table 6. Mode Selection, Stand-Alone Mode Options 12 DS459PP3 CS4392 3.9 Using DSD mode In stand-alone mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD data and clocks to the appropriate pins. The M2:0 pins set the expected DSD rate and MCLK ratio. In control-port mode the FM bits set the device into DSD mode (DSD_EN pin is not required to be held high). The DIF register then controls the expected DSD rate and MCLK ratio. DSD_Mode 1 1 1 1 1 1 1 1 M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 DESCRIPTION 64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 7. Direct Stream Digital (DSD), Stand-Alone Mode Options 3.10 Mute Control The Mute Control pins go high during power-up initialization, reset, or if the Master Clock to Left Right Clock ratio is incorrect. These pins will also go high following the reception of 8192 consecutive audio samples of static 0 or -1 on both the left and right channels. A single sample of non-zero data on either channel will cause the Mute Control pins to go low. These pins are intended to be used as control for an external mute circuit in order to add off-chip mute capability. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4392 data sheet for a suggested mute circuit. DS459PP3 13 CS4392 4. CONTROL PORT INTERFACE The control port is used to load all the internal register settings (see section 6). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in one of two modes: I2C or SPI. Notes: MCLK must be applied during all I2C communication. 4.0.1 MAP Auto Increment The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I2C writes or reads, and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. 4.0.2 I2C Mode In the I2C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL (see Figure 8 for the clock to data relationship). There is no CS pin. Pin AD0 enables the user to alter the chip address (001000[AD0][R/W]) and should be tied to VL or AGND as required, before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected. 4.0.2a I2C Write To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 7. 1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit. 2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written. 3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP. 4) If the INCR bit (see section 4.0.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5) If the INCR bit is set to 0 and further I2C writes to other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus. 14 DS459PP3 CS4392 4.0.2b I2C Read To read from the device, follow the procedure below while adhering to the control port Switching Specifications. 1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. 2) After transmitting an acknowledge (ACK), the device will then transmit the contents of the register pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP, or the default address (see section 4.1) if an I2C read is the first operation performed on the device. 3) Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK. 4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock and issue an ACK after each byte until all the desired registers are read, then initiate a STOP condition to the bus. 5) If the INCR bit is set to 0 and further I2C reads from other registers are desired, it is necessary to initiate a STOP condition and follow the procedure detailed from steps 1 and 2 from the I2C Write instructions followed by step 1 of the I2C Read section. If no further reads from other registers are desired, initiate a STOP condition to the bus. N ote 1 SDA 0 01 0 00 ADDR AD0 R /W ACK D ATA 1 -8 ACK D A TA 1-8 ACK SCL S ta rt Stop N o te : If o p eration is a w rite , th is byte con ta in s the M e m o ry A d dress P o inter, M A P . Figure 8. Control Port Timing, I2C Mode DS459PP3 15 CS4392 4.0.3 SPI Mode In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 9 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and is used to control SPI writes to the control port. When the device detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK. 4.0.3a SPI Write To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 7. 1) Bring CS low. 2) The address byte on the CDIN pin must then be 00100000. 3) Write to the memory address pointer, MAP. This byte points to the register to be written. 4) Write the desired data to the register pointed to by the MAP. 5) If the INCR bit (see section 4.0.1) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high. 6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high. CS CC LK C H IP ADDRESS C D IN 0010000 R/W MAP MSB DATA LSB b yte 1 M A P = M em ory Ad dress P oin te r byte n Figure 9. Control Port Timing, SPI mode 4.1 Memory Address Pointer (MAP) 7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0 4.1.1 INCR (AUTO MAP INCREMENT ENABLE) Default = ‘0’ 0 - Disabled, the MAP will stay constant for successive writes 1 - Enabled, the MAP will auto increment after each byte is written, writes of successive registers 4.1.2 allowing block reads or MAP3-0 (MEMORY ADDRESS POINTER) Default = ‘0000’ 16 DS459PP3 CS4392 5. REGISTER QUICK REFERENCE Addr 01h 02h Function Mode Control 1 Volume and MIxing Control Channel A Volume Control Channel B Volume Control 7 AMUTE 1 A=B 0 6 DIF2 0 Soft 1 VOL6 0 VOL6 0 0 Reserved 0 PART2 0 5 DIF1 0 Zero Cross 0 VOL5 0 VOL5 0 CPEN 0 Reserved 0 PART1 0 4 DIF0 0 ATAPI4 0 VOL4 0 VOL4 0 PDN 1 FILT_SEL 0 PART0 0 3 DEM1 0 ATAPI3 1 VOL3 0 VOL3 0 MUTEC A = B 0 RMP_UP 0 REV3 - 2 DEM0 0 ATAPI2 0 VOL2 0 VOL2 0 FREEZE 0 RMP_DN 0 REV2 - 1 FM1 0 ATAPI1 0 VOL1 0 VOL1 0 0 0 REV1 - 0 FM0 0 ATAPI0 1 VOL0 0 VOL0 0 0 0 REV0 - 03h MUTE 0 04h MUTE 0 05h 06h 07h Mode Control 2 INVERT_A INVERT_B 0 Mode Control 3 Chip ID Reserved 0 PART3 1 MCLKDIV2 Reserved Reserved Reserved DS459PP3 17 CS4392 6. 6.1 REGISTER DESCRIPTION Mode Control 1 - Address 01h 6 DIF2 5 DIF1 4 DIF0 3 DEM1 2 DEM0 1 FM1 0 FM0 ** All registers are read/write in Two-Wire mode and write only in SPI mode, unless otherwise noted** 7 AMUTE 6.1.1 Auto-Mute (Bit 7) Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. (However, Auto-Mute detection and muting can become dependent on either channel if the Mute A = B function is enabled.) The common mode on the output will be retained and the Mute Control pin for that channel will go active during the mute period. The muting function is effected, similar to volume control changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. 6.1.2 Digital Interface Formats (Bits 6:4) Function: PCM Mode - The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Table 8 and Figures 4-6. DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIFO 0 1 0 1 0 1 0 1 DESCRIPTION Left Justified, up to 24-bit data (default) I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data Right Justified, 20-bit Data Right Justified, 18-bit Data Reserved Reserved Format 0 1 2 3 4 5 Figure 4 5 6 6 6 6 Table 8. Digital Interface Formats - PCM Modes 18 DS459PP3 CS4392 DSD Mode - The relationship between the oversampling ratio of the DSD audio data and the required Master clock to DSD data rate is defined by the Digital interface Format pins. Note that the Functional Mode registers must be set to DSD Mode. See 9 for register options. DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIFO 0 1 0 1 0 1 0 1 DESCRIPTION 64x oversampled DSD data with a 4x MCLK to DSD data rate (default) 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 9. Digital Interface Formats - DSD Mode 6.1.3 De-Emphasis Control (Bits 3:2) Function: Implementation of the standard 15 µs/50 µs digital de-emphasis filter response, Figure 7, requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates. NOTE: De-emphasis is available only in Single-Speed Mode. See 10 below. Gain dB DEM1 0 0 1 1 DEMO 0 1 0 1 DESCRIPTION Disabled (default) 44.1 kHz de-emphasis 48 kHz de-emphasis 32 kHz de-emphasis T1=50 µs 0dB T2 = 15 µs -10dB Table 10. De-Emphasis Mode Selection F1 3.183 kHz F2 Frequency 10.61 kHz Figure 10. De-Emphasis Curve 6.1.4 Functional Mode (Bits 1:0) Function: Selects the required range of input sample rates or DSD Mode. See Table 11. FM1 0 0 1 1 FM0 0 1 0 1 MODE Single-Speed Mode: 4 to 50 kHz sample rates (default) Double-Speed Mode: 50 to 100 kHz sample rates Quad-Speed Mode: 100 to 200 kHz sample rates Direct Stream Digital Mode Table 11. Functional Mode Selection DS459PP3 19 CS4392 6.2 Volume and Mixing Control (Address 02h) 7 A=B 6 Soft 5 Zero Cross 4 ATAPI4 3 ATAPI3 2 ATAPI2 1 ATAPI1 0 ATAPI0 6.2.1 Channel A Volume = Channel B Volume (Bit 7) Function: The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled. 6.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5) Function: Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock periods. Zero Cross Enable Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 12 SOFT 0 0 1 1 ZERO 0 1 0 1 Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled (default) Soft Ramp and Zero Cross enabled Table 12. Soft Cross or Zero Cross Mode Selection 6.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) Function: The CS4392 implements the channel mixing functions of the ATAPI CD-ROM specification. See Table 13 on page 21 20 DS459PP3 CS4392 ATAPI4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AOUTA MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL [(aL+bR)/2] [(aL+bR)/2] [(bL+aR)/2] [(aL+bR)/2] AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL [(bL+aR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2] Table 13. ATAPI Decode Left Channel Audio Data A Channel Volume Control MUTE AoutA Σ Σ Right Channel Audio Data B Channel Volume Control MUTE AoutB Figure 11. ATAPI Block Diagram DS459PP3 21 CS4392 6.3 Channel A Volume Control - Address 03h See 4.4 Channel B Volume Control - Address 04h 6.4 CHANNEL B VOLUME CONTROL - ADDRESS 04H 7 MUTE 6 VOL6 5 VOL5 4 VOL4 3 VOL3 2 VOL2 1 VOL1 0 VOL0 6.4.1 Mute (Bit 7) Function: The Digital-to-Analog converter output will mute when enabled. The common mode voltage on the output will be retained. The muting function is effected, similiar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. The MUTEC pin for that channel will go active during the mute period if the Mute function is enabled. Both the AMUTEC and BMUTEC will go active if either MUTE register is enabled and the MUTEC A = B bit (register 5) is enabled. 6.4.2 Volume Control (Bits 6:0) Function: The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -127 dB. Volume settings are decoded as shown in Table 14. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Volume and Mixing Control register (see section 6.2.2). Binary Code 0000000 0010100 0101000 0111100 1011010 Decimal Value 0 20 40 60 90 Volume Setting 0 dB -20 dB -40 dB -60 dB -90 dB Table 14. Digital Volume Control Example Settings 6.5 Mode Control 2 - Address 05h 6 INVERT_B 5 CPEN 4 PDN 3 MUTEC A = B 2 FREEZE 1 MCLKDIV2 0 Reserved 7 INVERT_A 6.5.1 Invert Signal Polarity (Bits 7:6) Function: When set to 1, this bit inverts the signal polarity for the appropriate channel. This is useful if a board layout error has occurred, or an other situations where a 180 degree phase shift is desirable. Default is 0. 22 DS459PP3 CS4392 6.5.2 Control Port Enable (Bit 5) Function: This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean powerup, the user should write 30h to register 5 within 10 ms following the release of Reset. 6.5.3 Power Down (Bit 4) Function: The device will enter a low-power state whenever this function is activated (set to 1). The power-down bit defaults to ‘enabled’ (1) on power-up and must be disabled before normal operation will begin. The contents of the control registers are retained when the device is in power-down. 6.5.4 AMUTEC = BMUTEC (Bit 3) Function: When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally connected through a AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only when the requirements for both AMUTEC and BMUTEC are valid. 6.5.5 Freeze (Bit 2) Function: This function allows modifications to the control port registers without the changes taking effect until Freeze is disabled. To make multiple changes in the Control port registers take effect simultaneously, set the Freeze Bit, make all register changes, then Disable the Freeze bit. 6.5.6 Master Clock Divide (Bit 1) Function: This function allows the user to select an internal divide by 2 of the Master Clock. This selection is required to access the higher Master Clock rates as shown in Tables 2 through 4 on page 10. 6.6 Mode Control 3 - Address 06h B6 Reserved B5 Reserved B4 FILT_SEL B3 RMP_UP B2 RMP_DN B1 Reserved B0 Reserved B7 Reserved 6.6.1 Interpolation Filter Select (Bit 4) Function: This Function allows the user to select whether the Interpolation Filter has a fast (set to 0 - default) or slow (set to 1) roll off. The - 3dB corner is approximately the same for both filters, but the slope of the roll of is greater for the ‘fast’ roll off filter. DS459PP3 23 CS4392 6.6.2 Soft Volume Ramp-up after Reset (Bit 3) Function: This function allows the user to control whether a soft ramp up in volume is applied when reset is released either by the reset pin or internal to the chip. The modes are as follows: 0 - An instantaneous change is made from max attenuation to the control port volume setting on release of reset (default setting). 1 - Volume is ramped up using the soft-ramp settings in Bits 6:5 of register 02h (see 6.2.2) from max attenuation to the control port volume setting on release of reset. 6.6.3 Soft Ramp-down before Reset (Bit 2) Function: This function allows the user to control if a soft ramp-down in volume is applied before a known reset condition. The modes are as follows: 0 - An instantaneous change is made from the control port volume setting to max attenuation when chip resets (default setting). 1 - Volume is ramped down using the soft-ramp settings in Bits 6:5 of register 02h (see 6.2.2) from the control port volume setting to max attenuation when chip resets. 6.7 Chip ID - Register 07h B6 PART2 B5 PART1 B4 PART0 B3 REV3 B2 REV2 B1 REV1 B0 REV0 B7 PART3 Function: This register is Read-Only. Bits 7 through 4 are the part number ID which is 1000b (8h) and the remaining Bits (3 through 0) are for the chip revision. 24 DS459PP3 CS4392 7. CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS (CS4392-KS/KZ/KZZ) ((Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL = 3kΩ, CL = 10 pF. Typical performance characteristics are derived from measurements taken at TA = 25 °C, VL = VA = 5.0V. Min/Max performance characteristics are guaranteed over the specified operating temperature and voltages.) VA = 5.0V Parameter Dynamic Performance for All Speed Modes and DSD Dynamic Range (Note 1) Total Harmonic Distortion + Noise (Note 1) unweighted A-Weighted 0 dB THD+N -20 dB -60 dB (1 kHz) ICGM 105 108 VFS (Note 2) Symbol Min Typ 111 114 -100 -91 -51 114 100 0.1 100 0.99xVA 100 3 100 Max -94 -45 1.05xVA - Unit dB dB dB dB dB dB dB dB ppm/°C Vpp Ω kΩ pF Idle Channel Noise / Signal-to-Noise Ratio Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Characteristics and Specifications Full Scale Differential Output Voltage Output Resistance Minimum AC-Load Resistance Maximum Load Capacitance 0.95xVA - Zout RL CL Notes: 1. One-half LSB of Triangular PDF dither is added to data. 2. VFS is tested under load RL but does not include attenuation due to ZOUT DS459PP3 25 CS4392 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) Parameter Single-Speed Mode - (4 kHz to 50 kHz sample rates) Passband to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 4) Group Delay Passband Group Delay Deviation 0 - 20 kHz De-emphasis Error (Relative to 1kHz) Fs = 32 kHz (Note 5) Fs = 44.1 kHz Fs = 48 kHz Double-Speed Mode - (50 kHz to 100 kHz sample rates) Passband to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 4) Group Delay Passband Group Delay Deviation 0 - 20 kHz Quad Speed Mode - (100 kHz to 200 kHz) Passband to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 4) Group Delay Passband Group Delay Deviation 0 - 20 kHz DSD Mode Passband to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz Min 0 0 -0.01 0.547 90 0 0 -0.01 0.583 80 0 0 -0.01 0.635 90 0 0 -.01 Fast Roll-Off Typ 12/Fs 4.6/Fs 4.7/Fs Max 0.454 0.499 +0.01 ±0.41/Fs ±0.23 ±0.14 ±0.09 0.430 0.499 0.01 ±0.03/Fs 0.105 0.490 0.01 ±0.01/Fs 20 120 0.1 Unit Fs Fs dB Fs dB s s dB dB dB Fs Fs dB Fs dB s s Fs Fs dB Fs dB s s kHz kHz dB 26 DS459PP3 CS4392 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (Cont.) Parameter Single-Speed Mode - (4 kHz to 50 kHz sample rates) Passband to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 4) Group Delay Passband Group Delay Deviation 0 - 20 kHz De-emphasis Error (Relative to 1kHz) Fs = 32 kHz (Note 5) Fs = 44.1 kHz Fs = 48 kHz Double-Speed Mode - (50 kHz to 100 kHz sample rates) Passband to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 4) Group Delay Passband Group Delay Deviation 0 - 20 kHz Quad Speed Mode - (100 kHz to 200 kHz) Passband to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 4) Group Delay Passband Group Delay Deviation 0 - 20 kHz DSD Mode Passband to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz Slow Roll-Off (Note 3) Min Typ Max 0 0 -0.01 0.583 64 0 0 -0.01 0.792 70 6.5/Fs 3.9/Fs 4.2/Fs 0.417 0.499 +0.01 ±0.14/Fs ±0.23 ±0.14 ±0.09 0.296 0.499 0.01 ±0.01/Fs 0.104 0.481 0.01 ±0.01/Fs 20 120 0.1 Unit Fs Fs dB Fs dB s s dB dB dB Fs Fs dB Fs dB s s Fs Fs dB Fs dB s s kHz kHz dB 0 0 -0.01 0.868 75 - 0 0 -.01 Notes: 3. Slow Roll-Off interpolation filter is only available in control port mode. 4. For Single and Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 5. De-emphasis is only available in Single Speed Mode; The 44.1kHz De-emphasis filter is the only filter available in Stand-Alone Mode. DS459PP3 27 CS4392 0 0 20 20 Amplitude (dB) Amplitude (dB) 40 40 60 60 80 80 100 100 120 120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1 0.4 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 12. Single Speed (fast) Stopband Rejection 0 Figure 13. Single Speed (fast) Transition Band 0.02 1 0.015 2 0.01 3 0.005 Amplitude (dB) Amplitude (dB) 4 5 0 6 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 Figure 14. Single Speed (fast) Transition Band (detail) Figure 15. Single Speed (fast) Passband Ripple 0 0 20 20 Amplitude (dB) 40 60 Amplitude (dB) 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1 40 60 80 80 100 100 120 120 0.4 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 16. Single Speed (slow) Stopband Rejection Figure 17. Single Speed (slow) Transition Band 28 DS459PP3 CS4392 0 0.02 1 0.015 2 0.01 3 0.005 Amplitude (dB) Amplitude (dB) 4 5 0 6 0.005 7 0.01 8 0.015 9 10 0.45 0.02 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 Figure 18. Single Speed (slow) Transition Band (detail) Figure 19. Single Speed (slow) Passband Ripple 0 0 20 20 Amplitude (dB) Amplitude (dB) 40 40 60 60 80 80 100 100 120 120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1 0.4 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 20. Double Speed (fast) Stopband Rejection 0 Figure 21. Double Speed (fast) Transition Band 0.02 1 0.015 2 0.01 3 Amplitude (dB) 5 Amplitude (dB) 4 0.005 0 6 0.005 7 0.01 8 9 0.015 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 Figure 22. Double Speed (fast) Transition Band (detail) Figure 23. Double Speed (fast) Passband Ripple DS459PP3 29 CS4392 0 0 20 20 Amplitude (dB) Amplitude (dB) 40 40 60 60 80 80 100 100 120 120 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 24. Double Speed (slow) Stopband Rejection 0 Figure 25. Double Speed (slow) Transition Band 0.02 1 0.015 2 0.01 3 0.005 Amplitude (dB) Amplitude (dB) 4 5 0 6 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0.02 0 0.05 0.1 0.15 0.2 Frequency(normalized to Fs) 0.25 0.3 0.35 Figure 26. Double Speed (slow) Transition Band (detail) 0 Figure 27. Double Speed (slow) Passband Ripple 0 20 20 40 Amplitude (dB) Amplitude (dB) 40 60 60 80 80 100 100 120 120 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 28. Quad Speed (fast) Stopband Rejection Figure 29. Quad Speed (fast) Transition Band 30 DS459PP3 CS4392 0 0.2 1 0.15 2 0.1 3 0.05 Amplitude (dB) Amplitude (dB) 0.05 0.1 0.15 0.2 4 5 0 6 7 8 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0 0.05 0.1 0.15 Frequency(normalized to Fs) 0.2 0.25 Figure 30. Quad Speed (fast) Transition Band (detail) Figure 31. Quad Speed (fast) Passband Ripple 0 0 20 20 Amplitude (dB) Amplitude (dB) 40 40 60 60 80 80 100 100 120 120 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 0.1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 0.9 Figure 32. Quad Speed (slow) Stopband Rejection 0 Figure 33. Quad Speed (slow) Transition Band 0.02 1 0.015 2 0.01 3 0.005 Amplitude (dB) Amplitude (dB) 4 5 0 6 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0.02 0 0.02 0.04 0.06 0.08 Frequency(normalized to Fs) 0.1 0.12 Figure 34. Quad Speed (slow) Transition Band (detail) Figure 35. Quad Speed (slow) Passband Ripple DS459PP3 31 CS4392 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE (Inputs: Logic 0 = 0 V, Logic 1 = VL) . Parameters Input Sample Rate LRCK Duty Cycle MCLK Duty Cycle SCLK Frequency Single Speed Mode Double Speed Mode Quad Speed Mode (MCLKDIV=0) Quad Speed Mode (MCLKDIV=1) tslrd tslrs tsdlrs tsdh Symbol Fs Min 4 45 40 20 20 20 20 Typ 50 50 Max 200 55 60 128•LRCK 64•LRCK MCLK/2 MCLK/4 Units kHz % % Hz Hz Hz Hz ns ns ns ns SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time LR C K t slrd t slrs SC LK t sdlrs S D ATA t sdh Figure 36. Serial Mode Input Timing 32 DS459PP3 CS4392 SWITCHING SPECIFICATIONS - DSD INTERFACE (Logic 0 = AGND; Logic 1 = VL) Parameter MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Period DSD_L or DSD_R valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_L or DSD_R hold time tsclkl tsclkh tsclkw tsdlrs tsdh Symbol Min 40 20 20 20 20 20 Max 60 Unit % ns ns ns ns ns t sclkh t sclkl D S D _S C LK t sdlrs D SD_L, DSD_R t sdh Figure 37. Direct Stream Digital - Serial Audio Input Timing DS459PP3 33 CS4392 SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (Inputs: logic 0 = AGND, logic 1 = VL) Parameter I2C Mode SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition (Note 6) fscl tirs tbuf thdst tlow thigh tsust thdd tsud tr tf tsusp 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 100 1 300 kHz ns µs µs µs µs µs µs ns µs ns µs Symbol Min Max Unit Notes: 6. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. RST t irs Stop SDA t buf SCL R e p e a te d S ta rt S ta rt Stop t hdst t high t hdst tf t susp t lo w t hdd t sud t sust tr Figure 38. I2C Mode Control Port Timing 34 DS459PP3 CS4392 SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: logic 1 = VL) Parameter SPI Mode CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 8) (Note 9) (Note 9) (Note 7) fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2 500 500 1.0 20 82 82 40 15 6 100 100 MHz ns ns µs ns ns ns ns ns ns ns Symbol Min Max Unit logic 0 = AGND, Notes: 7. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 8. Data must be held for sufficient time to bridge the transition time of CCLK. 9. For FSCK < 1 MHz RST t srs CS t spi CCLK t r2 C D IN t css t scl t sch t csh t f2 t d su t dh Figure 39. SPI Control Port Timing DS459PP3 35 CS4392 DC ELECTRICAL CHARACTERISTICS (AGND = 0V; all voltages with respect to AGND.) Parameter Normal Operation (Note 10) Power Supply Current Power Dissipation Power-Down Mode (Note 11) Power Supply Current Power Dissipation All Modes of Operation Power Supply Rejection Ratio (Note 12) All Supplies=5.0V Symbol IA + IL Min Typ 26 130 300 1.5 60 40 0.48•VA 250 0.001 VA 250 0.001 0 VA 3 Max 30 150 Units mA mW µA mW dB dB V All Supplies=5.0V IA + IL (1 kHz) (60 Hz) PSRR CMOUT Common Mode Voltage Output Impedance Maximum allowable DC current source/sink Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink MUTEC Low-Level Output Voltage MUTEC High-Level Output Voltage Maximum MUTEC Drive Current kΩ mA V kΩ mA V V mA Notes: 10. Normal operation is defined as RST = HI with a 997 Hz, 0dBFS input sampled at Fs = 48kHz, and open outputs, unless otherwise stated. 11. Power-Down Mode is defined as RST = LO with all clocks and data lines held static. 12. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 1 and 2. DIGITAL INPUT CHARACTERISTICS & SPECIFICATIONS with respect to AGND.) Parameters Input Leakage Current Input Capacitance High-Level Input Voltage Low-Level Input Voltage Symbol Iin VIH VIL Min 70% (AGND = 0V; all voltages Max ±10 20% Units µA pF VL VL Typ 8 - THERMAL CHARACTERISTICS AND SPECIFICATIONS Parameters Package Thermal Resistance Ambient Operating Temperature CS4392-KS CS4392-KZ/KZZ (Power Applied) Symbol θJA θJA TA Min -10 Typ 68 72 Max +70 Units °C/Watt °C/Watt °C 36 DS459PP3 CS4392 RECOMMENDED OPERATING SPECIFICATIONS to AGND.) Parameters DC Power Supply Symbol VA VL Min 4.75 1.8 Typ 5.0 Max 5.25 VA Units V V (AGND = 0V; all voltages with respect ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Symbol VA VL Iin VIND TA Tstg Min -0.3 -0.3 -0.3 -55 -65 Max 6.0 VA ±10 VL+0.4 125 150 Units V V mA V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. DS459PP3 37 CS4392 8. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 9. REFERENCES 1. CDB4392 Evaluation Board Datasheet 2. “The I2C-Bus Specification: Version 2.1” Philips Semiconductors, January 2000. http://www.semiconductors.philips.com 38 DS459PP3 CS4392 10.PACKAGE DIMENSIONS 20L TSSOP (4.4 mm BODY) PACKAGE DRAWING N D E11 A2 A1 SEATING PLANE A E b2 SIDE VIEW 123 ∝ e L END VIEW TOP VIEW INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.03346 0.00748 0.252 0.248 0.169 -0.020 0° NOM -0.004 0.0354 0.0096 0.256 0.2519 0.1732 -0.024 4° MAX 0.043 0.006 0.037 0.012 0.259 0.256 0.177 0.026 0.028 8° MIN -0.05 0.85 0.19 6.40 6.30 4.30 -0.50 0° MILLIMETERS NOM --0.90 0.245 6.50 6.40 4.40 -0.60 4° MAX 1.10 0.15 0.95 0.30 6.60 6.50 4.50 0.65 0.70 8° NOT E 2,3 1 1 ∝ JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. DS459PP3 39 CS4392 PACKAGE DIMENSIONS(cont.). 20L SOIC (300 MIL BODY) PACKAGE DRAWING E H 1b c D ∝ L A SEATING PLANE e A1 DIM A A1 b C D E e H L ∝ MIN 0.093 0.004 0.013 0.009 0.496 0.291 0.040 0.394 0.016 0° INCHES NOM 0.098 0.008 0.017 0.011 0.504 0.295 0.050 0.407 0.025 4° MAX 0.104 0.012 0.020 0.013 0.512 0.299 0.060 0.419 0.050 8° JEDEC #: MS-013 MIN 2.35 0.10 0.33 0.23 12.60 7.40 1.02 10.00 0.40 0° MILLIMETERS NOM 2.50 0.20 0.43 0.28 12.80 7.50 1.27 10.34 0.64 4° MAX 2.65 0.30 0.51 0.32 13.00 7.60 1.52 10.65 1.27 8° Controlling Dimension is Millimeters 40 DS459PP3