CDB43L21

CS43L21 Low Power, Stereo Digital to Analog Converter FEATURES 98 dB Dynamic Range (A-wtd) -86 dB THD+N Headphone Amplifier - GND Centered – On-Chip Charge Pump Provides -VA_HP – No DC-Blocking Capacitor Required – 46 mW Power Into Stereo 16 Ω @ 1.8 V – 88 mW Power Into Stereo 16 Ω @ 2.5 V – -75 dB THD+N Digital Signal Processing Engine – Bass & Treble Tone Control, De-Emphasis – PCM Mix w/Independent Vol Control – Master Digital Volume Control and Limiter – Soft Ramp & Zero Cross Transitions Beep Generator – Tone Selections Across Two Octaves – Separate Volume Control – Programmable On & Off Time Intervals – Continuous, Periodic or One-Shot Beep Selections Programmable Peak-Detect and Limiter Pop and Click Suppression SYSTEM FEATURES 24-bit Conversion 4 kHz to 96 kHz Sample Rate Multi-bit Delta Sigma Architecture Low Power Operation – Stereo Playback: 12.93 mW @ 1.8 V Variable Power Supplies – 1.8 V to 2.5 V Digital & Analog – 1.8 V to 3.3 V Interface Logic Power Down Management Software Mode (I²C® & SPI™ Control) Hardware Mode (Stand-Alone Control) Digital Routing/Mixes: – Mono Mixes Flexible Clocking Options – Master or Slave Operation – High-Impedance Digital Output Option (for easy MUXing between DAC and Other Data Sources) – Quarter-Speed Mode - (i.e. Allows 8 kHz Fs while maintaining a flat noise floor up to 16 kHz) 1.8 V to 3.3 V 1.8 V to 2.5 V 1.8 V to 2.5 V PCM Serial Interface Serial Audio Input Hardware Mode or I2C & SPI Software Mode Control Data Level Translator MUX Beep Generator Digital Signal Processing Engine MUX Multibit ∆Σ Modulator Switched Capacitor DAC and Filter Switched Capacitor DAC and Filter Headphone Amp - GND Centered Headphone Amp - GND Centered Charge Pump Left HP Out Right HP Out Reset Register Configuration Advance Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) JULY '06 DS723A1 CS43L21 APPLICATIONS Portable Audio Players MD Players PDAs Personal Media Players Portable Game Consoles Smart Phones Wireless Headsets GENERAL DESCRIPTION The CS43L21 is a highly integrated, 24-bit, 96 kHz, low power stereo DAC. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. The DAC offers many features suitable for low power, portable system applications. The DAC output path includes a digital signal processing engine. Tone Control provides bass and treble adjustment of four selectable corner frequencies. The Mixer allows independent volume control for PCM mix, as well as a master digital volume control for the analog output. All volume level changes may be configured to occur on soft ramp and zero cross transitions. The DAC also includes de-emphasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves. The stereo headphone amplifier is powered from a separate positive supply and the integrated charge pump provides a negative supply. This allows a ground-centered analog output with a wide signal swing and eliminates external DC-blocking capacitors. In addition to its many features, the CS43L21 operates from a low-voltage analog and digital core, making this DAC ideal for portable systems that require extremely low power consumption in a minimal amount of space. The CS43L21 is available in a 32-pin QFN package in both Commercial (-10 to +70° C) and Automotive grades (-40 to +85° C). The CS43L21 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 63 for complete details. 2 DS723A1 CS43L21 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9 3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11 SPECIFIED OPERATING CONDITIONS ............................................................................................. 11 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 11 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ...................................................... 12 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ...................................................... 13 LINE OUTPUT VOLTAGE CHARACTERISTICS ................................................................................. 14 HEADPHONE OUTPUT POWER CHARACTERISTICS ...................................................................... 15 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 16 SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 16 SWITCHING SPECIFICATIONS - I²C® CONTROL PORT .................................................................. 18 SWITCHING CHARACTERISTICS - SPI™ CONTROL PORT ............................................................ 19 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 20 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 20 POWER CONSUMPTION .................................................................................................................... 21 4. APPLICATIONS ................................................................................................................................... 22 4.1 Overview ......................................................................................................................................... 22 4.1.1 Architecture ........................................................................................................................... 22 4.1.2 Line & Headphone Outputs ................................................................................................... 22 4.1.3 Signal Processing Engine ..................................................................................................... 22 4.1.4 Beep Generator ..................................................................................................................... 22 4.1.5 Device Control (Hardware or Software Mode) ...................................................................... 22 4.1.6 Power Management .............................................................................................................. 22 4.2 Hardware Mode .............................................................................................................................. 23 4.3 Analog Outputs ............................................................................................................................... 24 4.3.1 De-Emphasis Filter ................................................................................................................ 24 4.3.2 Volume Controls .................................................................................................................... 25 4.3.3 Mono Channel Mixer ............................................................................................................. 25 4.3.4 Beep Generator ..................................................................................................................... 25 4.3.5 Tone Control .......................................................................................................................... 26 4.3.6 Limiter .................................................................................................................................... 26 4.3.7 Line-Level Outputs and Filtering ........................................................................................... 27 4.3.8 On-Chip Charge Pump .......................................................................................................... 28 4.4 Serial Port Clocking ........................................................................................................................ 28 4.4.1 Slave ..................................................................................................................................... 29 4.4.2 Master ................................................................................................................................... 29 4.4.3 High-Impedance Digital Output ............................................................................................. 30 4.4.4 Quarter- and Half-Speed Mode ............................................................................................. 30 4.5 Digital Interface Formats ................................................................................................................ 30 4.6 Initialization ..................................................................................................................................... 31 4.7 Recommended Power-Up Sequence ............................................................................................. 31 4.8 Recommended Power-Down Sequence ........................................................................................ 32 4.9 Software Mode ............................................................................................................................... 33 4.9.1 SPI Control ............................................................................................................................ 33 4.9.2 I²C Control ............................................................................................................................. 33 4.9.3 Memory Address Pointer (MAP) ............................................................................................ 35 4.9.3.1 Map Increment (INCR) ............................................................................................... 35 5. REGISTER QUICK REFERENCE ........................................................................................................ 36 6. REGISTER DESCRIPTION .................................................................................................................. 39 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 39 DS723A1 3 CS43L21 6.2 Power Control 1 (Address 02h) ...................................................................................................... 39 6.3 Speed Control (Address 03h) ......................................................................................................... 40 6.4 Interface Control (Address 04h) ..................................................................................................... 41 6.5 DAC Output Control (Address 08h) ................................................................................................ 41 6.6 DAC Control (Address 09h) ............................................................................................................ 42 6.7 PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h) ..................................................................................... 44 6.8 Beep Frequency & Timing Configuration (Address 12h) ................................................................ 45 6.9 Beep Off Time & Volume (Address 13h) ........................................................................................ 46 6.10 Beep Configuration & Tone Configuration (Address 14h) ............................................................ 47 6.11 Tone Control (Address 15h) ......................................................................................................... 48 6.12 AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h) ................................................................................. 49 6.13 PCM Channel Mixer (Address 18h) .............................................................................................. 49 6.14 Limiter Threshold SZC Disable (Address 19h) ............................................................................. 50 6.15 Limiter Release Rate Register (Address 1Ah) .............................................................................. 51 6.16 Limiter Attack Rate Register (Address 1Bh) ................................................................................. 52 6.17 Status (Address 20h) (Read Only) ............................................................................................... 52 6.18 Charge Pump Frequency (Address 21h) ...................................................................................... 53 7. ANALOG PERFORMANCE PLOTS .................................................................................................... 54 7.1 Headphone THD+N versus Output Power Plots ............................................................................ 54 7.2 Headphone Amplifier Efficiency ...................................................................................................... 56 8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 57 8.1 Auto Detect Enabled ....................................................................................................................... 57 8.2 Auto Detect Disabled ...................................................................................................................... 58 9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 59 9.1 Power Supply, Grounding ............................................................................................................... 59 9.2 QFN Thermal Pad .......................................................................................................................... 59 10. DIGITAL FILTERS .............................................................................................................................. 60 11. PARAMETER DEFINITIONS .............................................................................................................. 61 12. PACKAGE DIMENSIONS ................................................................................................................. 62 THERMAL CHARACTERISTICS ........................................................................................................ 62 13. ORDERING INFORMATION ............................................................................................................. 63 14. REFERENCES .................................................................................................................................... 63 15. REVISION HISTORY ......................................................................................................................... 63 4 DS723A1 CS43L21 LIST OF FIGURES Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9 Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10 Figure 3.Headphone Output Test Load ..................................................................................................... 15 Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 17 Figure 5.Serial Audio Interface Master Mode Timing ................................................................................ 17 Figure 6.Control Port Timing - I²C ............................................................................................................. 18 Figure 7.Control Port Timing - SPI Format ................................................................................................ 19 Figure 8.Output Architecture ..................................................................................................................... 24 Figure 9.De-Emphasis Curve .................................................................................................................... 25 Figure 10.Beep Configuration Options ...................................................................................................... 26 Figure 11.Peak Detect & Limiter ............................................................................................................... 27 Figure 12.Master Mode Timing ................................................................................................................. 29 Figure 13.Tri-State SCLK/LRCK ............................................................................................................... 30 Figure 14.I²S Format ................................................................................................................................. 30 Figure 15.Left-Justified Format ................................................................................................................. 31 Figure 16.Right-Justified Format (DAC only) ............................................................................................ 31 Figure 17.Initialization Flow Chart ............................................................................................................. 32 Figure 18.Control Port Timing in SPI Mode .............................................................................................. 33 Figure 19.Control Port Timing, I²C Write ................................................................................................... 34 Figure 20.Control Port Timing, I²C Read ................................................................................................... 34 Figure 21.THD+N vs. Output Power per Channel at 1.8 V (16 Ω load) .................................................... 54 Figure 22.THD+N vs. Output Power per Channel at 2.5 V (16 Ω load) .................................................... 54 Figure 23.THD+N vs. Output Power per Channel at 1.8 V (32 Ω load) .................................................... 55 Figure 24.THD+N vs. Output Power per Channel at 2.5 V (32 Ω load) .................................................... 55 Figure 25.Power Dissipation vs. Output Power into Stereo 16 Ω ......................................................................56 Figure 26.Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail) .......................................... 56 Figure 27.Passband Ripple ....................................................................................................................... 60 Figure 28.Stopband ................................................................................................................................... 60 Figure 29.Transition Band ......................................................................................................................... 60 Figure 30.Transition Band (Detail) ............................................................................................................ 60 LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Hardware Mode Feature Summary ............................................................................................. 23 Table 3. MCLK/LRCK Ratios .................................................................................................................... 29 DS723A1 5 CS43L21 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE TSTO(M/S) DGND MCLK SCLK SDIN VD 32 31 30 29 28 27 26 VL LRCK SDA/CDIN (MCLKDIV2) SCL/CCLK (I²S/LJ) ADO/CS (DEM) VA_HP FLYP GND_HP FLYN RESET 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 TSTO TSTO TSTO TSTO TSTO TSTO TSTO TSTO CS43L21 21 20 19 18 17 AOUTA VSS_HP AOUTB AGND Pin Name LRCK SDA/CDIN (MCLKDIV2) # 1 Pin Description Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the control port interface in SPI Mode. MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry. Serial Control Port Clock (Input) - Serial clock for the serial control port. 2 SCL/CCLK (I²S/LJ) 3 Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface formats for the DAC. Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS is the chip-select signal for SPI format. De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter. AD0/CS (DEM) VA_HP FLYP GND_HP FLYN VSS_HP 4 5 6 7 8 9 Analog Power For Headphone (Input) - Positive power for the internal analog headphone section. Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor. Analog Ground (Input) - Ground reference for the internal headphone/charge pump section. Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor. Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog headphone section. 6 FILT+ NIC VA VQ DS723A1 CS43L21 AOUTB AOUTA VA AGND FILT+ VQ NIC TSTO TSTO TSTO TSTO TSTO TSTO RESET VL VD DGND TSTO (M/S) MCLK SCLK SDIN Thermal Pad 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table Analog Power (Input) - Positive power for the internal analog section. Analog Ground (Input) - Ground reference for the internal analog section. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Not Internally Connected - This pin is not connected internal to the device and may be connected to ground or left “floating”. No other external connection should be made to this pin. Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no connection external to the pin). Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no connection external to the pin). Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no connection external to the pin). Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no connection external to the pin). Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no connection external to the pin). Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no connection external to the pin). Reset (Input) - The device enters a low power mode when this pin is driven low. Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port. Refer to the Recommended Operating Conditions for appropriate voltages. Digital Power (Input) - Positive power for the internal digital section. Digital Ground (Input) - Ground reference for the internal digital section. Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no connection external to the pin). Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and Slave Mode for the serial port. 30 31 32 Master Clock (Input) - Clock source for the delta-sigma modulators. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 59. 29 DS723A1 7 CS43L21 1.1 Digital I/O Pin Characteristics The logic level for each input should not exceed the maximum ratings for the VL power supply. Pin Name SW/(HW) RESET SCL/CCLK (I²S/LJ) SDA/CDIN (MCLKDIV2) AD0/CS (DEM) MCLK LRCK SCLK TSTO (M/S) SDIN I/O Input Input Input/Output Input Input Input/Output Input/Output Input/Output Input Driver 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS Table 1. I/O Power Rails Receiver 1.8 V - 3.3 V 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 8 DS723A1 CS43L21 2. TYPICAL CONNECTION DIAGRAMS +1.8 V or +2.5 V 1 µF 0.1 µF 0.1 µF 0.1 µF See Note 3 +1.8 V or +2.5 V 1 µF Note 3: Series resistance in the path of the power supplies must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output . VD VA VA_HP AOUTB 1.5 µF See Note 4 ** 1 µF ** FLYP FLYN VSS_HP AOUTA 0.022 µF 51.1 Ω Headphone Out Left & Right 1.5 µF ** 1 µF ** GND_HP * *Use low ESR ceramic capacitors. 470 Ω C Rext Line Level Out Left & Right See Note 2 CS43L21 470 Ω C Rext Speaker Driver Note 4 : Larger capacitors, such as 1.5 µF, improves the charge pump performance (and subsequent THD+N) at the full scale output power achieved with gain (G) settings greater than default. Note 2 : For best response to Fs/2 : C= MCLK SCLK LRCK Digital Audio Processor SDIN RESET SCL/CCLK SDA/CDIN AD0/CS Rext + 470 4πFs(Rext × 470 ) This circuitry is intended for applications where the CS43L21 connects directly to an unbalanced output of the device. For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations. 2k Ω 2k Ω +1.8 V, +2.5 V or +3.3 V See Note 1 VL 0.1 µF Note 1: Resistors are required for I²C control port operation FILT+ 1 µF AGND 1 µF VQ DGND Figure 1. Typical Connection Diagram (Software Mode) DS723A1 9 CS43L21 +1.8V or +2.5V 1 µF 0.1 µF 0.1 µF 0.1 µF 1 µF See Note 1 +1.8V or +2.5V VD VA VA_HP AOUTB Note 1: Series resistance in the path of the power supplies (typically used for added filtering) must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output . 1 µF ** FLYP FLYN AOUTA 0.022 µF 51.1 Ω Headphone Out Left & Right 1 µF ** VSS_HP GND_HP 470Ω C Rext Line Level Out Left & Right See Note 2 * *Use low ESR ceramic capacitors. CS43L21 470Ω C Rext MCLK SCLK LRCK SDIN VL or DGND Digital Audio Processor 47 kΩ See Note 3 Speaker Driver TSTO/M/S RESET I²S/LJ MCLKDIV2 DEM AGND 1 µF FILT+ 1 µF +1.8V, 2.5 V or +3.3V 0.1 µF VL VQ DGND kΩ Note 3: Pull-up to VL (47 kΩ  Master Mode. Pullfor down to DGND for Slave Mode. Note 2 : This circuitry is intended for applications where the CS 43L21 connects directly to an unbalanced output of the device . For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations . For best response to Fs/2 : C= Rext + 470 4πFs (Rext × 470 ) Figure 2. Typical Connection Diagram (Hardware Mode) 10 DS723A1 CS43L21 3. CHARACTERISTIC AND SPECIFICATION TABLES (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) Parameters DC Power Supply (Note 1) Analog Core Headphone Amplifier Digital Core Serial/Control Port Interface Ambient Temperature Commercial - CNZ Automotive - DNZ VA VA_HP VD VL TA 1.65 2.37 1.65 2.37 1.65 2.37 1.65 2.37 3.14 -10 -40 1.8 2.5 1.8 2.5 1.8 2.5 1.8 2.5 3.3 1.89 2.63 1.89 2.63 1.89 2.63 1.89 2.63 3.47 +70 +85 V V V V V V V V V °C °C Symbol Min Nom Max Units ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Symbol Min -0.3 -0.3 -0.3 -0.3 -50 -65 Max 3.0 3.0 4.0 ±10 VL+ 0.4 +115 +150 Units V V V mA V °C °C Analog VA, VA_HP VD Digital VL Serial/Control Port Interface (Note 2) Iin VIND TA Tstg Input Current Digital Input Voltage (Note 3) Ambient Operating Temperature (power applied) Storage Temperature WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. The device will operate properly over the full range of the analog, headphone amplifier, digital core and serial/control port interface supplies. 2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current. DS723A1 11 CS43L21 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) (Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF for the line output (see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.) Parameter (Note 4) VA = 2.5V (nominal) VA = 1.8V (nominal) Min Typ Max Min Typ Max Unit R L = 10 k Ω Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB -86 -75 -35 -86 -73 -33 -78 -88 -72 -32 -88 -70 -30 -82 dB dB dB dB dB dB A-weighted unweighted A-weighted unweighted 92 89 98 95 96 93 89 86 95 92 93 90 dB dB dB dB 16-Bit R L = 16 Ω Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Modulation Index (MI) Analog Gain Multiplier (G) -75 -75 -35 -75 -73 -33 -69 -75 -72 -32 -75 -70 -30 -69 dB dB dB dB dB dB A-weighted unweighted A-weighted unweighted 92 89 98 95 96 93 89 86 95 92 93 90 dB dB dB dB 16-Bit Other Characteristics for RL = 16 Ω or 10 kΩ Output Parameters (Note 5) 0.6787 0.6787 0.6047 0.6047 Refer to Table “Line Output Voltage Characteristics” on page 14 Refer to Table “Headphone Output Power Characteristics” on page 15 80 80 95 93 (Note 6) (Note 6) 16 0.1 ±100 0.25 150 16 0.1 ±100 0.25 150 Full-scale Output Voltage (2•G•MI•VA) (Note 5) Full-scale Output Power (Note 5) Interchannel Isolation (1 kHz) Interchannel Gain Mismatch Gain Drift AC-Load Resistance (RL) Load Capacitance (CL) 16 Ω 10 kΩ Vpp mW dB dB dB ppm/° C Ω pF 12 DS723A1 CS43L21 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) (Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load RL = 10 kΩ, CL = 10 pF for the line output (see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.) Parameter (Note 4) VA = 2.5V (nominal) Min Typ Max VA = 1.8V (nominal) Min Typ Max Unit RL = 1 0 k Ω Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB -86 -75 -35 -86 -73 -33 -73 -88 -72 -32 -88 -70 -30 -80 dB dB dB dB dB dB A-weighted unweighted A-weighted unweighted 90 87 98 95 96 93 87 84 95 92 93 90 dB dB dB dB 16-Bit RL = 1 6 Ω Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Modulation Index (MI) Analog Gain Multiplier (G) -75 -75 -35 -75 -73 -33 -67 -75 -72 -32 -75 -70 -30 -67 dB dB dB dB dB dB A-weighted unweighted A-weighted unweighted 90 87 98 95 96 93 87 84 95 92 93 90 dB dB dB dB 16-Bit Other Characteristics for RL = 16 Ω or 10 kΩ Output Parameters (Note 5) 0.6787 0.6787 0.6047 0.6047 Refer to Table “Line Output Voltage Characteristics” on page 14 Refer to Table “Headphone Output Power Characteristics” on page 15 80 80 95 93 (Note 6) (Note 6) 16 0.1 ±100 0.25 150 16 0.1 ±100 0.25 150 Full-scale Output Voltage (2•G•MI•VA) (Note 5) Full-scale Output Power (Note 5) Interchannel Isolation (1 kHz) Interchannel Gain Mismatch Gain Drift AC-Load Resistance (RL) Load Capacitance (CL) 16 Ω 10 kΩ Vpp mW dB dB dB ppm/° C Ω pF DS723A1 13 CS43L21 LINE OUTPUT VOLTAGE CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF (see Figure 3). Parameter VA = 2.5V (nominal) Min Typ Max Analog Gain (G) 0.3959 0.4571 0.5111 0.6047 0.7099 0.8399 1.0000 1.1430 VA_HP 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.95 1.34 1.34 1.55 1.55 1.73 1.73 2.05 2.05 2.41 2.41 2.85 2.85 3.39 3.39 (See (Note 7) 3.88 2.15 - VA = 1.8V (nominal) Min Typ Max Unit AOUTx Voltage Into RL = 10 kΩ HP_GAIN[2:0] 000 001 010 011 (default) 100 101 110 111 1.41 - 0.97 0.97 1.12 1.12 1.25 1.25 1.48 1.48 1.73 1.73 2.05 2.05 2.44 2.44 2.79 2.79 1.55 - Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp 14 DS723A1 CS43L21 HEADPHONE OUTPUT POWER CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 16 Ω, CL = 10 pF (see Figure 3). Parameter VA = 2.5V (nominal) Min Typ Max Analog Gain (G) 0.3959 0.4571 0.5111 0.6047 0.7099 0.8399 1.0000 1.1430 VA = 1.8V (nominal) Min Typ Max Unit AOUTx Power Into RL = 16 Ω HP_GAIN[2:0] 000 001 010 011 (default) 100 101 110 111 VA_HP 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 14 14 19 19 23 23 (Note 7) 32 (Note 7) 44 (Note 5, 7) 7 7 10 10 12 12 17 17 23 23 (Note 5) 32 mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms 4. One-half LSB of triangular PDF dither is added to data. 5. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog Gain (HP_GAIN[2:0])” on page 41. High gain settings at certain VA and VA_HP supply levels may cause clipping when the audio signal approaches full-scale, maximum power output, as shown in Figures 21 - 24 on page 55. 6. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recommended 150 pF can cause the internal op-amp to become unstable. 7. VA_HP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC may not achieve the full THD+N performance at full-scale output voltage and power. AOUTx 51 Ω 0.022 µ F C L R L AGND Figure 3. Headphone Output Test Load DS723A1 15 CS43L21 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter (Note 8) Frequency Response 10 Hz to 20 kHz Passband StopBand StopBand Attenuation (Note 9) Group Delay De-emphasis Error Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.05 dB corner to -3 dB corner Min -0.01 0 0 0.5465 50 - Typ 10.4/Fs - Max +0.08 0.4780 0.4996 +1.5/+0 +0.05/-0.25 -0.2/-0.4 Unit dB Fs Fs Fs dB s dB dB dB Notes: 8. Response is clock dependent and will scale with Fs. Note that the response plots (Figure 27 to Figure 30 on page 60) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 9. Measurement Bandwidth is from Stopband to 3 Fs. SWITCHING SPECIFICATIONS - SERIAL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL.) Parameters RESET pin Low Pulse Width MCLK Frequency MCLK Duty Cycle (Note 11) (Note 10) Symbol Min 1 1.024 45 Max 38.4 55 Units ms MHz % Slave Mode Input Sample Rate (LRCK) Quarter-Speed Mode Half-Speed Mode Single-Speed Mode Double-Speed Mode Fs Fs Fs Fs 1/tP ts(LK-SK) ts(SD-SK) th 4 8 4 50 45 45 40 20 20 12.5 25 50 100 55 64•Fs 55 kHz kHz kHz kHz % Hz % ns ns ns LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Setup Time Before SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge 16 DS723A1 CS43L21 // LRCK ts(LK-SK) // // // ts(SD-SK) th MSB-1 tP SCLK SDIN // MSB // Figure 4. Serial Audio Interface Slave Mode Timing Parameters Master Mode (Note 12) Output Sample Rate (LRCK) LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Edge to SDIN MSB Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge All Speed Modes Symbol Min Max Units Fs 45 MCLK ---------------128 55 64•Fs 55 52 Hz % Hz % ns ns ns 1/tP td(MSB) ts(SD-SK) th 45 20 20 - 10. After powering up the CS43L21, RESET should be held low after the power supplies and clocks are settled. 11. See “Example System Clock Frequencies” on page 57 for typical MCLK frequencies. 12. See “Master” on page 29 // LRCK // tP // // td(MSB) ts(SD-SK) // MSB // th MSB-1 SCLK SDIN Figure 5. Serial Audio Interface Master Mode Timing DS723A1 17 CS43L21 SWITCHING SPECIFICATIONS - I²C® CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF) Parameter SCL Clock Frequency Symbol fscl tirs tbuf thdst tlow thigh tsust (Note 13) thdd tsud trc tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 3450 Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns RESET Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling 13. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. RST t irs Stop SDA t buf SCL Repeated Start Start Stop t hdst t high t hdst tf t susp t low t hdd t sud t sust tr Figure 6. Control Port Timing - I²C 18 DS723A1 CS43L21 SWITCHING CHARACTERISTICS - SPI™ CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL) Parameter CCLK Clock Frequency Symbol fsck tsrs tcss tcsh tscl tsch tdsu (Note 14) (Note 15) (Note 15) tdh tr2 tf2 Min 0 20 20 1.0 66 66 40 15 - Max 6.0 100 100 Units MHz ns ns µs ns ns ns ns ns ns RESET Rising Edge to CS Falling CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN 14. Data must be held for sufficient time to bridge the transition time of CCLK. 15. For fsck