CDB47L85-M-1

CS47L85 Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub Features • Class D speaker, and digital (PDM) output interfaces • 900 MIPS, 900MMAC multicore audio-signal processor • SLIMbus® audio and control interface • Sensor hub capability, with event time-stamp functions • Four full digital audio interfaces • Programmable wideband, multimic audio processing — Standard sample rates from 8 to 192 kHz — Cirrus Logic® adaptive ambient noise cancelation — Multichannel TDM support on AIF1 and AIF2 — Transmit-path noise reduction and echo cancelation • Flexible clocking, derived from MCLKn, AIFn, or SLIMbus — Wind noise, sidetone, and other programmable filters • Multichannel asynchronous sample rate conversion • Low-power frequency-locked loops (FLLs) support reference clocks down to 32 kHz • Integrated multichannel 24-bit hi-fi audio hub codec • Configurable functions on up to 40 GPIO pins — Six ADCs, 100-dB SNR mic input (48 kHz) • Integrated regulators and charge pumps — Eight DACs, 121-dB SNR headphone playback (48 kHz) • Small W-CSP package, 0.4-mm staggered ball array • Up to 9 analog or 12 digital microphone inputs Applications • Multipurpose headphone/earpiece/line output drivers • Smartphones and multimedia handsets JACKDET1 JACKDET2 MICDET1 HPDETL HPDETR SPKVDDL SPKGNDLP SPKGNDLN SPKVDDR SPKGNDRP SPKGNDRN SUBGND LDOVDD LDOVOUT LDOENA DCVDD DBVDD1 DBVDD2 DBVDD3 DBVDD4 DGND FLLVDD CPVDD1 CPVDD2 CPGND • Tablets and Mobile Internet Devices (MIDs) CP2CA CP2CB CP1C1A CP1C1B CP1VOUT1P CP1VOUT1N CP1C2A CP1C2B CP1VOUT2P CP1VOUT2N CP2VOUT MICVDD — 30 mW into 32-Ω load at 0.1% THD+N CS47L85 MICBIAS1 MICBIAS2 MICBIAS3 MICBIAS4 LDO and MICBIAS Generators AVDD AGND VREFC Reference Generator Advanced always-on buffering Trigger word detection & ASR assist Speaker protection 6 x ADC 3 x Stereo Digital Mic Interface HPOUTnR DAC SPKOUTLP SPKOUTLN DAC SPKOUTRP SPKOUTRN PDM Driver PWM signal generator Haptic control signal generator x3 DAC 5-Band equaliser (EQ) Dynamic range control (DRC) Low-Pass / High-Pass Filter (LHPF) Asynchronous sample rate conversion Automatic sample rate detection Digital Mic Interface GPIO AEC (Echo Cancellation) Loopback SPKCLKn SPKDATn x2 GPSWP GPSWN GPIOn x8 SYSCLK, ASYNCCLK, DSPCLK Copyright  Cirrus Logic, Inc., 2014-2017 (All Rights Reserved) MIF1SCLK MIF1SDA MIF2SCLK MIF2SDA MIF3SCLK MIF3SDA CIF3MISO CIF3MOSI CIF3SCLK CIF3SS CIF2SCLK CIF2SDA Control Interfaces (2 x SPI, 1 x I2C) Master Interface (3 x I2C) CIF1MISO CIF1MOSI CIF1SCLK CIF1SS SLIMbus Interface AIF4TXDAT AIF4RXDAT AIF4BCLK AIF4LRCLK AIF3TXDAT AIF3RXDAT AIF3BCLK AIF3LRCLK AIF2TXDAT AIF2RXDAT AIF2BCLK AIF2LRCLK Digital Audio Interfaces AIF1, AIF2, AIF3, AIF4 SLIMCLK SLIMDAT Clocking Control RESET AIFnBCLK AIFnLRCLK SLIMCLK http://www.cirrus.com Programmable multicore DSP sensor hub Stereo adaptive RX ambient noise cancelation Advanced multimic TX noise reduction Advanced multimic acoustic-echo cancelation Input Select MCLK1 MCLK2 HPOUTnL DAC HPOUTnFB AIF1TXDAT AIF1RXDAT AIF1BCLK AIF1LRCLK x3 DMICCLKn DMICDATn Accessory Detect LDO1 Digital Core IRQ IN1ALN/DMICCLK1, IN1BN IN1ALP, IN1BP IN1RN/DMICDAT1 IN1RP IN2ALN/DMICCLK2, IN2BLN IN2ALP, IN2BLP IN2ARN/DMICDAT2 IN2ARP, IN2BR IN3LN/DMICCLK3 IN3LP IN3RN/DMICDAT3 IN3RP Charge Pumps Rev 4.2 JAN ‘17 CS47L85 Description The CS47L85 is a highly integrated, low-power audio and sensor hub system for smartphones, tablets and other portable audio devices. It combines an advanced DSP feature set with a flexible, high-performance audio hub codec. The CS47L85 combines seven programmable DSP cores with a variety of power-efficient fixed-function audio processors. Extensive GPIO and I2C master interfaces enable powerful sensor fusion functions to be integrated. The DSP cores support multiple concurrent audio features, including multimic wideband noise reduction, highperformance acoustic-echo cancellation (AEC), stereo ambient noise cancellation (ANC), speech enhancement, advanced media enhancement, and many more. The CS47L85 sensor hub technology enables applications to support increased contextual awareness, including advanced motion sensing and pedestrian navigation functionality. The DSP cores are supported by a fully flexible, all-digital mixing and routing engine with sample rate converters, for wide use-case flexibility. Support for third-party DSP programming provides far-reaching opportunities for product differentiation. A SLIMbus interface supports multi-channel audio paths and host control register access. Four further digital audio interfaces are provided, each supporting a wide range of standard audio sample rates and serial interface formats. Automatic sample rate detection enables seamless wideband/narrowband voice-call handover. Three stereo headphone drivers each provide stereo ground-referenced or mono BTL outputs. 121dB SNR, and noise levels as low as 0.8 μVRMS, offer hi-fi quality line or headphone output. The CS47L85 also features a stereo pair of 2.5-W Class D outputs, four channels of stereo PDM output, and an IEC-60958-3–compatible S/PDIF transmitter. A signal generator for controlling haptics devices is included; vibe actuators can connect directly to the Class D speaker output or via an external driver on the PDM output interface. All inputs, outputs, and system interfaces can function concurrently. The CS47L85 supports up to 9 analog inputs, and up to 12 PDM digital inputs. Microphone activity detection with interrupt is available. A smart accessory interface supports most standard 3.5mm accessories. Impedance sensing and measurement is provided for external accessory and push-button detection. The CS47L85 is configured using the SLIMbus, SPI™, or I2C interfaces. Three integrated FLLs provide support for a wide range of system clock frequencies. The device is powered from 1.8- and 1.2-V supplies. (A separate 4.2-V battery supply is typically required for the Class D speaker drivers). The power, clocking and output driver architectures are all designed to maximise battery life in voice, music and standby modes. Low-power (10µA) ‘Sleep’ is supported, with configurable wake-up events. 2 Rev 4.2 CS47L85 TABLE OF CONTENTS PIN CONFIGURATION ......................................................................................................................... 7 ORDERING INFORMATION ................................................................................................................ 8 PIN DESCRIPTION .............................................................................................................................. 8 ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 15 RECOMMENDED OPERATING CONDITIONS ................................................................................. 16 ELECTRICAL CHARACTERISTICS .................................................................................................. 17 TERMINOLOGY ............................................................................................................................................... 28 THERMAL CHARACTERISTICS ....................................................................................................... 29 TYPICAL PERFORMANCE................................................................................................................ 30 TYPICAL POWER CONSUMPTION ................................................................................................................ 30 TYPICAL SIGNAL LATENCY .......................................................................................................................... 31 SIGNAL TIMING REQUIREMENTS ................................................................................................... 32 SYSTEM CLOCK & FREQUENCY LOCKED LOOP (FLL) .............................................................................. 32 AUDIO INTERFACE TIMING ........................................................................................................................... 34 DIGITAL MICROPHONE (DMIC) INTERFACE TIMING ................................................................................................................................................ 34 DIGITAL SPEAKER (PDM) INTERFACE TIMING ......................................................................................................................................................... 35 DIGITAL AUDIO INTERFACE - MASTER MODE ......................................................................................................................................................... 36 DIGITAL AUDIO INTERFACE - SLAVE MODE ............................................................................................................................................................. 37 DIGITAL AUDIO INTERFACE - TDM MODE................................................................................................................................................................. 38 CONTROL INTERFACE TIMING ..................................................................................................................... 39 2-WIRE (I2C) CONTROL MODE ................................................................................................................................................................................... 39 4-WIRE (SPI) CONTROL MODE ................................................................................................................................................................................... 40 SLIMBUS INTERFACE TIMING ...................................................................................................................... 41 JTAG INTERFACE TIMING ............................................................................................................................. 43 DEVICE DESCRIPTION ..................................................................................................................... 44 INTRODUCTION .............................................................................................................................................. 44 HI-FI AUDIO CODEC ..................................................................................................................................................................................................... 44 DIGITAL AUDIO CORE ................................................................................................................................................................................................. 45 DIGITAL INTERFACES ................................................................................................................................................................................................. 45 OTHER FEATURES ...................................................................................................................................................................................................... 45 INPUT SIGNAL PATH ...................................................................................................................................... 47 ANALOGUE MICROPHONE INPUT.............................................................................................................................................................................. 49 ANALOGUE LINE INPUT .............................................................................................................................................................................................. 50 DIGITAL MICROPHONE INPUT.................................................................................................................................................................................... 50 INPUT SIGNAL PATH ENABLE .................................................................................................................................................................................... 52 INPUT SIGNAL PATH SAMPLE RATE CONTROL ....................................................................................................................................................... 53 INPUT SIGNAL PATH CONFIGURATION .................................................................................................................................................................... 54 INPUT SIGNAL PATH DIGITAL VOLUME CONTROL .................................................................................................................................................. 61 INPUT SIGNAL PATH ANC CONTROL ........................................................................................................................................................................ 67 DIGITAL MICROPHONE PIN CONFIGURATION ......................................................................................................................................................... 67 DIGITAL CORE ................................................................................................................................................ 68 DIGITAL CORE MIXERS ............................................................................................................................................................................................... 70 DIGITAL CORE INPUTS................................................................................................................................................................................................ 74 DIGITAL CORE OUTPUT MIXERS ............................................................................................................................................................................... 75 5-BAND PARAMETRIC EQUALISER (EQ) ................................................................................................................................................................... 78 DYNAMIC RANGE CONTROL (DRC) ........................................................................................................................................................................... 82 LOW PASS / HIGH PASS DIGITAL FILTER (LHPF) ..................................................................................................................................................... 94 DIGITAL CORE DSP ..................................................................................................................................................................................................... 96 SPDIF OUTPUT GENERATOR ..................................................................................................................................................................................... 97 TONE GENERATOR ..................................................................................................................................................................................................... 99 NOISE GENERATOR .................................................................................................................................................................................................. 100 Rev 4.2 3 CS47L85 HAPTIC SIGNAL GENERATOR .................................................................................................................................................................................. 101 PWM GENERATOR..................................................................................................................................................................................................... 104 SAMPLE RATE CONTROL ......................................................................................................................................................................................... 106 ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) ....................................................................................................................................... 116 ISOCHRONOUS SAMPLE RATE CONVERTER (ISRC) ............................................................................................................................................ 120 DSP FIRMWARE CONTROL ......................................................................................................................... 127 DSP FIRMWARE MEMORY AND REGISTER MAPPING .......................................................................................................................................... 127 DSP FIRMWARE CONTROL....................................................................................................................................................................................... 130 DSP DIRECT MEMORY ACCESS (DMA) CONTROL ................................................................................................................................................ 134 DSP INTERRUPTS ...................................................................................................................................................................................................... 137 DSP DEBUG SUPPORT.............................................................................................................................................................................................. 139 VIRTUAL DSP REGISTERS ........................................................................................................................................................................................ 139 DSP PERIPHERAL CONTROL ..................................................................................................................... 140 MASTER INTERFACES .............................................................................................................................................................................................. 140 EVENT LOGGERS ...................................................................................................................................................................................................... 146 GENERAL PURPOSE TIMERS ................................................................................................................................................................................... 155 DSP GPIO .................................................................................................................................................................................................................... 159 AMBIENT NOISE CANCELLATION .............................................................................................................. 165 DIGITAL AUDIO INTERFACE ....................................................................................................................... 166 MASTER AND SLAVE MODE OPERATION ............................................................................................................................................................... 167 AUDIO DATA FORMATS............................................................................................................................................................................................. 167 AIF TIMESLOT CONFIGURATION ............................................................................................................................................................................. 169 TDM OPERATION BETWEEN THREE OR MORE DEVICES .................................................................................................................................... 171 DIGITAL AUDIO INTERFACE CONTROL ..................................................................................................... 173 AIF SAMPLE RATE CONTROL ................................................................................................................................................................................... 173 AIF PIN CONFIGURATION ......................................................................................................................................................................................... 173 AIF MASTER / SLAVE CONTROL .............................................................................................................................................................................. 174 AIF SIGNAL PATH ENABLE........................................................................................................................................................................................ 177 AIF BCLK AND LRCLK CONTROL ............................................................................................................................................................................. 180 AIF DIGITAL AUDIO DATA CONTROL ....................................................................................................................................................................... 185 AIF TDM AND TRI-STATE CONTROL ........................................................................................................................................................................ 189 SLIMBUS INTERFACE .................................................................................................................................. 191 SLIMBUS DEVICES..................................................................................................................................................................................................... 191 SLIMBUS FRAME STRUCTURE................................................................................................................................................................................. 191 CONTROL SPACE ...................................................................................................................................................................................................... 191 DATA SPACE .............................................................................................................................................................................................................. 192 SLIMBUS CONTROL SEQUENCES ............................................................................................................. 193 DEVICE MANAGEMENT & CONFIGURATION .......................................................................................................................................................... 193 INFORMATION MANAGEMENT ................................................................................................................................................................................. 193 VALUE MANAGEMENT (INCLUDING REGISTER ACCESS) .................................................................................................................................... 194 FRAME & CLOCKING MANAGEMENT ...................................................................................................................................................................... 194 DATA CHANNEL CONFIGURATION .......................................................................................................................................................................... 194 SLIMBUS INTERFACE CONTROL ............................................................................................................... 195 SLIMBUS DEVICE PARAMETERS ............................................................................................................................................................................. 195 SLIMBUS MESSAGE SUPPORT ................................................................................................................................................................................ 195 SLIMBUS PORT NUMBER CONTROL ....................................................................................................................................................................... 198 SLIMBUS SAMPLE RATE CONTROL......................................................................................................................................................................... 198 SLIMBUS SIGNAL PATH ENABLE ............................................................................................................................................................................. 199 SLIMBUS CONTROL REGISTER ACCESS ............................................................................................................................................................... 200 SLIMBUS CLOCKING CONTROL ............................................................................................................................................................................... 202 OUTPUT SIGNAL PATH ................................................................................................................................ 204 OUTPUT SIGNAL PATH ENABLE .............................................................................................................................................................................. 206 OUTPUT SIGNAL PATH SAMPLE RATE CONTROL ................................................................................................................................................. 208 OUTPUT SIGNAL PATH CONTROL ........................................................................................................................................................................... 208 OUTPUT SIGNAL PATH DIGITAL FILTER CONTROL .............................................................................................................................................. 210 OUTPUT SIGNAL PATH DIGITAL VOLUME CONTROL ............................................................................................................................................ 212 4 Rev 4.2 CS47L85 OUTPUT SIGNAL PATH NOISE GATE CONTROL .................................................................................................................................................... 218 OUTPUT SIGNAL PATH AEC LOOPBACK ................................................................................................................................................................ 220 HEADPHONE OUTPUTS AND MONO MODE ........................................................................................................................................................... 221 SPEAKER OUTPUTS (ANALOGUE) .......................................................................................................................................................................... 222 SPEAKER OUTPUTS (DIGITAL PDM) ....................................................................................................................................................................... 224 EXTERNAL ACCESSORY DETECTION ....................................................................................................... 227 JACK DETECT............................................................................................................................................................................................................. 227 JACK POP SUPPRESSION (MICDET CLAMP AND GP SWITCH) ............................................................................................................................ 229 CONTROL SEQUENCE FOR JACK DETECT & MICDET CLAMP ............................................................................................................................ 232 MICROPHONE DETECT ............................................................................................................................................................................................. 233 HEADPHONE DETECT ............................................................................................................................................................................................... 238 LOW POWER SLEEP CONFIGURATION ..................................................................................................... 243 GENERAL PURPOSE INPUT / OUTPUT ...................................................................................................... 245 GPIO CONTROL.......................................................................................................................................................................................................... 245 GPIO FUNCTION SELECT.......................................................................................................................................................................................... 247 PIN-SPECIFIC ALTERNATIVE FUNCTION ................................................................................................................................................................ 250 BUTTON DETECT (GPIO INPUT) ............................................................................................................................................................................... 251 LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT) ................................................................................................................................................ 251 DSP GPIO (LOW LATENCY DSP INPUT/OUTPUT) .................................................................................................................................................. 251 INTERRUPT (IRQ) STATUS OUTPUT ........................................................................................................................................................................ 251 FREQUENCY LOCKED LOOP (FLL) CLOCK OUTPUT ............................................................................................................................................. 252 FREQUENCY LOCKED LOOP (FLL) STATUS OUTPUT ........................................................................................................................................... 253 OPCLK AND OPCLK_ASYNC CLOCK OUTPUT ....................................................................................................................................................... 253 PULSE WIDTH MODULATION (PWM) SIGNAL OUTPUT ......................................................................................................................................... 254 SPDIF AUDIO OUTPUT .............................................................................................................................................................................................. 254 ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) LOCK STATUS OUTPUT ............................................................................................. 255 OVER-TEMPERATURE, SHORT CIRCUIT PROTECTION, AND SPEAKER SHUTDOWN STATUS OUTPUT ....................................................... 255 GENERAL PURPOSE TIMER STATUS OUTPUT ...................................................................................................................................................... 255 EVENT LOGGER FIFO BUFFER STATUS OUTPUT ................................................................................................................................................. 256 GENERAL PURPOSE SWITCH .................................................................................................................................................................................. 256 INTERRUPTS ................................................................................................................................................ 257 CLOCKING AND SAMPLE RATES ............................................................................................................... 287 SYSTEM CLOCKING................................................................................................................................................................................................... 287 SAMPLE RATE CONTROL ......................................................................................................................................................................................... 287 AUTOMATIC SAMPLE RATE DETECTION ................................................................................................................................................................ 288 SYSCLK AND ASYNCCLK CONTROL ....................................................................................................................................................................... 289 DSPCLK CONTROL .................................................................................................................................................................................................... 291 MISCELLANEOUS CLOCK CONTROLS .................................................................................................................................................................... 292 BCLK AND LRCLK CONTROL .................................................................................................................................................................................... 300 CONTROL INTERFACE CLOCKING .......................................................................................................................................................................... 300 FREQUENCY LOCKED LOOP (FLL) .......................................................................................................................................................................... 301 FREE-RUNNING FLL MODE....................................................................................................................................................................................... 313 SPREAD SPECTRUM FLL CONTROL ....................................................................................................................................................................... 314 FLL INTERRUPTS AND GPIO OUTPUT..................................................................................................................................................................... 316 EXAMPLE FLL CALCULATION ................................................................................................................................................................................... 316 EXAMPLE FLL SETTINGS .......................................................................................................................................................................................... 317 CONTROL INTERFACE ................................................................................................................................ 319 4-WIRE (SPI) CONTROL MODE ................................................................................................................................................................................. 320 2-WIRE (I2C) CONTROL MODE ................................................................................................................................................................................. 321 CONTROL WRITE SEQUENCER ................................................................................................................. 324 INITIATING A SEQUENCE .......................................................................................................................................................................................... 324 AUTOMATIC SAMPLE RATE DETECTION SEQUENCES ........................................................................................................................................ 328 DRC SIGNAL DETECT SEQUENCES ........................................................................................................................................................................ 329 MICDET CLAMP SEQUENCES .................................................................................................................................................................................. 330 EVENT LOGGER SEQUENCES ................................................................................................................................................................................. 331 BOOT SEQUENCE ...................................................................................................................................................................................................... 332 Rev 4.2 5 CS47L85 SEQUENCER STATUS AND READBACK .................................................................................................................................................................. 332 PROGRAMMING A SEQUENCE................................................................................................................................................................................. 333 SEQUENCER MEMORY DEFINITION ........................................................................................................................................................................ 334 CHARGE PUMPS, REGULATORS AND VOLTAGE REFERENCE ............................................................. 335 CHARGE PUMPS AND LDO2 REGULATOR ............................................................................................................................................................. 335 MICROPHONE BIAS (MICBIAS) CONTROL .............................................................................................................................................................. 335 VOLTAGE REFERENCE CIRCUIT ............................................................................................................................................................................. 336 LDO1 REGULATOR AND DCVDD SUPPLY ............................................................................................................................................................... 336 BLOCK DIAGRAM AND CONTROL REGISTERS ...................................................................................................................................................... 337 JTAG INTERFACE ......................................................................................................................................... 341 THERMAL SHUTDOWN AND SHORT CIRCUIT PROTECTION ................................................................. 341 POWER-ON RESET (POR) ........................................................................................................................... 343 HARDWARE RESET, SOFTWARE RESET, WAKE-UP, AND DEVICE ID................................................... 346 REGISTER MAP ............................................................................................................................... 348 APPLICATIONS INFORMATION ..................................................................................................... 349 RECOMMENDED EXTERNAL COMPONENTS ........................................................................................... 349 ANALOGUE INPUT PATHS ........................................................................................................................................................................................ 349 DIGITAL MICROPHONE INPUT PATHS .................................................................................................................................................................... 349 MICROPHONE BIAS CIRCUIT ................................................................................................................................................................................... 350 HEADPHONE DRIVER OUTPUT PATH ..................................................................................................................................................................... 351 SPEAKER DRIVER OUTPUT PATH ........................................................................................................................................................................... 353 POWER SUPPLY / REFERENCE DECOUPLING ...................................................................................................................................................... 355 CHARGE PUMP COMPONENTS ............................................................................................................................................................................... 356 EXTERNAL ACCESSORY DETECTION COMPONENTS .......................................................................................................................................... 356 RECOMMENDED EXTERNAL COMPONENTS DIAGRAM ....................................................................................................................................... 358 RESETS SUMMARY ..................................................................................................................................... 359 OUTPUT SIGNAL DRIVE STRENGTH CONTROL ....................................................................................... 360 DIGITAL AUDIO INTERFACE CLOCKING CONFIGURATIONS .................................................................. 364 PCB LAYOUT CONSIDERATIONS ............................................................................................................... 367 PACKAGE DIMENSIONS ................................................................................................................ 368 6 Rev 4.2 CS47L85 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A NC MICBIAS2 MICBIAS1 MICVDD CPVDD1 CP1C2B CP1VOUT2N HPOUT3R HPOUT3L HPOUT2R HPOUT2L HPOUT1R HPOUT1L NC B IN1RN/ DMICDAT1 IN1RP MICBIAS4 MICBIAS3 CPGND CP1C2A CP1VOUT2P CPVDD2 HPOUT3FB NC HPOUT2FB HPDETR HPDETL MICDET1/ HPOUT1FB2 C IN2ARN/ DMICDAT2 IN2ARP IN1ALP IN1ALN/ DMICCLK1 CP1C1A CP1C1B CP1VOUT1N CP1VOUT1P NC NC JACKDET1 JACKDET2 HPOUT1FB1 /MICDET2 AVDD2 D IN3RN/ DMICDAT3 IN3RP IN2ALP IN2ALN/ DMICCLK2 CP2VOUT CP2CB CP2CA NC NC NC GPSWP GPSWN SUBGND AGND2 E IN1BN IN1BP IN3LP IN3LN/ DMICCLK3 NC NC LDOENA LDOVOUT F IN2BLP IN2BLN IN2BR NC NC NC NC NC IRQ MCLK1 RESET LDOVDD G VREFC SPKTST1 SPKTST2 NC GPIO5 NC TRST GPIO1 AIF1TXDAT/ GPIO15 AIF1RXDAT/ GPIO17 FLLVDD DGND H SUBGND AGND1 AVDD1 NC GPIO7 GPIO4 TCK TDO CIF1SS AIF1LRCLK/ GPIO18 AIF1BCLK/ GPIO16 DGND J SPKVDDR SPKVDDR NC GPIO3 GPIO8 GPIO2 TMS TDI CIF1MOSI CIF1MISO CIF1SCLK DCVDD K SPKOUTRN SPKOUTRP NC AIF3LRCLK/ GPIO26 CIF2SCLK MIF1SCLK/ GPIO9 CIF2SDA DGND L SPKGNDRN SPKGNDRP NC AIF3TXDAT/ GPIO23 MIF3SDA/ GPIO14 CIF3MISO AIF4TXDAT/ GPIO27 DMICCLK6/ GPIO35 MIF2SDA/ GPIO12 AIF2LRCLK/ GPIO22 AIF2TXDAT/ GPIO19 MIF1SDA/ GPIO10 SLIMDAT DBVDD1 M SPKGNDLN SPKGNDLP NC AIF3BCLK/ GPIO24 MIF3SCLK/ GPIO13 CIF3SS AIF4BCLK/ GPIO28 DMICDAT6/ GPIO36 DMICDAT4/ GPIO32 MIF2SCLK/ GPIO11 SPKDAT1/ GPIO39 AIF2BCLK/ GPIO20 MCLK2 SLIMCLK N SPKOUTLN SPKOUTLP NC AIF3RXDAT/ GPIO25 GPIO6 CIF3MOSI CIF3SCLK AIF4LRCLK/ GPIO30 DMICCLK5/ GPIO33 DMICCLK4/ GPIO31 SPKDAT2/ GPIO40 SPKCLK1/ GPIO37 AIF2RXDAT/ GPIO21 DCVDD P SPKVDDL SPKVDDL NC DBVDD3 DCVDD DGND DGND AIF4RXDAT/ GPIO29 DMICDAT5/ GPIO34 DBVDD4 SPKCLK2/ GPIO38 DGND DBVDD2 DGND Rev 4.2 TOP VIEW – CS47L85 7 CS47L85 ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE CS47L85-CWZR -40C to +85C PACKAGE W-CSP (Pb-free, Tape and reel) MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE MSL1 260C Note: Reel quantity = 4500 PIN DESCRIPTION A description of each pin on the CS47L85 is provided below. Note that a table detailing the associated power domain for every input and output pin is provided on the following page. Note that, where multiple pins share a common name, these pins should be tied together on the PCB. All Digital Output pins are CMOS outputs, unless otherwise stated. PIN NO 8 NAME TYPE DESCRIPTION AGND1 Supply Analogue ground (Return path for AVDD1) D14 AGND2 Supply Analogue ground (Return path for AVDD2) H13 AIF1BCLK/ GPIO16 Digital Input / Output Audio interface 1 bit clock / GPIO16. GPIO output is selectable CMOS or Open Drain; BCLK output is CMOS. H12 AIF1LRCLK/ GPIO18 Digital Input / Output Audio interface 1 left / right clock / GPIO18. GPIO output is selectable CMOS or Open Drain; LRCLK output is CMOS. G12 AIF1RXDAT/ GPIO17 Digital Input / Output Audio interface 1 RX digital audio data / GPIO17. GPIO output is selectable CMOS or Open Drain. G11 AIF1TXDAT/ GPIO15 Digital Input / Output Audio interface 1 TX digital audio data / GPIO15. GPIO output is selectable CMOS or Open Drain; TXDAT output is CMOS. M12 AIF2BCLK/ GPIO20 Digital Input / Output Audio interface 2 bit clock / GPIO20. GPIO output is selectable CMOS or Open Drain; BCLK output is CMOS. L10 AIF2LRCLK/ GPIO22 Digital Input / Output Audio interface 2 left / right clock / GPIO22. GPIO output is selectable CMOS or Open Drain; LRCLK output is CMOS. N13 AIF2RXDAT/ GPIO21 Digital Input / Output Audio interface 2 RX digital audio data / GPIO21. GPIO output is selectable CMOS or Open Drain. L11 AIF2TXDAT/ GPIO19 Digital Input / Output Audio interface 2 TX digital audio data / GPIO19. GPIO output is selectable CMOS or Open Drain; TXDAT output is CMOS. M4 AIF3BCLK/ GPIO24 Digital Input / Output Audio interface 3 bit clock / GPIO24. GPIO output is selectable CMOS or Open Drain; BCLK output is CMOS. K4 AIF3LRCLK/ GPIO26 Digital Input / Output Audio interface 3 left / right clock / GPIO26. GPIO output is selectable CMOS or Open Drain; LRCLK output is CMOS. N4 AIF3RXDAT/GPIO2 5 Digital Input / Output Audio interface 3 RX digital audio data / GPIO25. GPIO output is selectable CMOS or Open Drain. L4 AIF3TXDAT/GPIO2 3 Digital Input / Output Audio interface 3 TX digital audio data / GPIO23. GPIO output is selectable CMOS or Open Drain; TXDAT output is CMOS. M7 AIF4BCLK/ GPIO28 Digital Input / Output Audio interface 4 bit clock / GPIO28. GPIO output is selectable CMOS or Open Drain; BCLK output is CMOS. N8 AIF4LRCLK/ GPIO30 Digital Input / Output Audio interface 4 left / right clock / GPIO30. GPIO output is selectable CMOS or Open Drain; LRCLK output is CMOS. H2 Rev 4.2 CS47L85 PIN NO NAME TYPE DESCRIPTION P8 AIF4RXDAT/ GPIO29 Digital Input / Output Audio interface 4 RX digital audio data / GPIO29. GPIO output is selectable CMOS or Open Drain. L7 AIF4TXDAT/ GPIO27 Digital Input / Output Audio interface 4 TX digital audio data / GPIO27. GPIO output is selectable CMOS or Open Drain; TXDAT output is CMOS. H3 AVDD1 Supply Analogue supply C14 AVDD2 Supply Analogue supply J12 CIF1MISO Digital Output Control interface 1 (SPI) Master In Slave Out data. The CIFMISO is high impedance when CIF1SS ¯¯¯¯¯¯ is not asserted. J11 CIF1MOSI Digital Input Control interface 1 (SPI) Master Out Slave In data J13 CIF1SCLK Digital Input Control interface 1 (SPI) clock input H11 CIF1SS ¯¯¯¯¯¯ Digital Input Control interface 1 (SPI) Slave Select (SS) K11 CIF2SCLK Digital Input Control interface 2 (I2C) clock input K13 CIF2SDA Digital Input / Output Control interface 2 (I2C) data input and output. The SDA output is Open Drain. L6 CIF3MISO Digital Output Control interface 3 (SPI) Master In Slave Out data. The CIFMISO is high impedance when CIF3SS ¯¯¯¯¯¯ is not asserted. N6 CIF3MOSI Digital Input Control interface 3 (SPI) Master Out Slave In data N7 CIF3SCLK Digital Input Control interface 3 (SPI) clock input M6 CIF3SS ¯¯¯¯¯¯ Digital Input Control interface 3 (SPI) Slave Select (SS) C5 CP1C1A Analogue Output Charge pump 1 fly-back capacitor 1 pin C6 CP1C1B Analogue Output Charge pump 1 fly-back capacitor 1 pin B6 CP1C2A Analogue Output Charge pump 1 fly-back capacitor 2 pin A6 CP1C2B Analogue Output Charge pump 1 fly-back capacitor 2 pin C7 CP1VOUT1N Analogue Output Charge pump 1 negative output 1 decoupling pin C8 CP1VOUT1P Analogue Output Charge pump 1 positive output 1 decoupling pin A7 CP1VOUT2N Analogue Output Charge pump 1 negative output 2 decoupling pin B7 CP1VOUT2P Analogue Output Charge pump 1 positive output 2 decoupling pin D7 CP2CA Analogue Output Charge pump 2 fly-back capacitor pin D6 CP2CB Analogue Output Charge pump 2 fly-back capacitor pin D5 CP2VOUT Analogue Output Charge pump 2 output decoupling pin / Supply for LDO2 B5 CPGND Supply Charge pump ground (Return path for CPVDD1, CPVDD2) A5 CPVDD1 Supply Supply for Charge Pumps 1 & 2 B8 CPVDD2 Supply Secondary supply for Charge Pump 1 L14 DBVDD1 Supply Digital buffer (I/O) supply (core functions, AIF1, CIF1, CIF2, SLIMbus, MIF1, GPIO1) P13 DBVDD2 Supply Digital buffer (I/O) supply (AIF2, PDM, MIF2, MCLK2, GPIO2, JTAG) P4 DBVDD3 Supply Digital buffer (I/O) supply (AIF3, AIF4, CIF3, MIF3, GPIO3-8) P10 DBVDD4 Supply Digital buffer (I/O) supply (DMIC4, DMIC5, DMIC6) J14, N14, P5 DCVDD Supply Digital core supply G14, H14, K14, P6, P7, P12, P14 DGND Supply Digital ground (Return path for DCVDDn and DBVDDn) N10 DMICCLK4/ GPIO31 Digital Input / Output Digital MIC clock output 4 / GPIO31. GPIO output is selectable CMOS or Open Drain; DMICCLK output is CMOS. M9 DMICDAT4/ GPIO32 Digital Input / Output Digital MIC data input 4 / GPIO32. GPIO output is selectable CMOS or Open Drain. N9 DMICCLK5/ GPIO33 Digital Input / Output Digital MIC clock output 5 / GPIO33. GPIO output is selectable CMOS or Open Drain; DMICCLK output is CMOS. P9 DMICDAT5/ GPIO34 Digital Input / Output Digital MIC data input 5 / GPIO34. GPIO output is selectable CMOS or Open Drain. Rev 4.2 9 CS47L85 PIN NO 10 NAME TYPE DESCRIPTION L8 DMICCLK6/ GPIO35 Digital Input / Output Digital MIC clock output 6 / GPIO35. GPIO output is selectable CMOS or Open Drain; DMICCLK output is CMOS. M8 DMICDAT6/ GPIO36 Digital Input / Output Digital MIC data input 6 / GPIO36. GPIO output is selectable CMOS or Open Drain. G13 FLLVDD Supply Analogue supply (FLL1, FLL2) G9 GPIO1 Digital Input / Output General Purpose pin GPIO1. The output configuration is selectable CMOS or Open Drain. J7 GPIO2 Digital Input / Output General Purpose pin GPIO2. The output configuration is selectable CMOS or Open Drain. J4 GPIO3 Digital Input / Output General Purpose pin GPIO3. The output configuration is selectable CMOS or Open Drain. H7 GPIO4 Digital Input / Output General Purpose pin GPIO4. The output configuration is selectable CMOS or Open Drain. G6 GPIO5 Digital Input / Output General Purpose pin GPIO5. The output configuration is selectable CMOS or Open Drain. N5 GPIO6 Digital Input / Output General Purpose pin GPIO6. The output configuration is selectable CMOS or Open Drain. H6 GPIO7 Digital Input / Output General Purpose pin GPIO7. The output configuration is selectable CMOS or Open Drain. J6 GPIO8 Digital Input / Output General Purpose pin GPIO8. The output configuration is selectable CMOS or Open Drain. D11 GPSWP Analogue Input / Output General Purpose bi-directional switch contact D12 GPSWN Analogue Input / Output General Purpose bi-directional switch contact B13 HPDETL Analogue Input Headphone left (HPOUT1L) sense input B12 HPDETR Analogue Input Headphone right (HPOUT1R) sense input C13 HPOUT1FB1/ MICDET2 Analogue Input HPOUT1L and HPOUT1R ground feedback pin 1/ Microphone & accessory sense input 2 A13 HPOUT1L Analogue Output Left headphone 1 output A12 HPOUT1R Analogue Output Right headphone 1 output B11 HPOUT2FB Analogue Input HPOUT2L and HPOUT2R ground loop noise rejection feedback A11 HPOUT2L Analogue Output Left headphone 2 output A10 HPOUT2R Analogue Output Right headphone 2 output B9 HPOUT3FB Analogue Input HPOUT3L and HPOUT3R ground loop noise rejection feedback A9 HPOUT3L Analogue Output Left headphone 3 output A8 HPOUT3R Analogue Output Right headphone 3 output C4 IN1ALN/ DMICCLK1 Analogue Input / Digital Output Left channel negative differential Mic/Line input / Digital MIC clock output 1 C3 IN1ALP Analogue Input Left channel single-ended Mic/Line input / Left channel positive differential Mic/Line input E1 IN1BN Analogue Input Negative differential Mic/Line input. Also suitable for connection to external accessory interfaces. E2 IN1BP Analogue Input Single-ended Mic/Line input / Positive differential Mic/Line input. Also suitable for connection to external accessory interfaces. B1 IN1RN/ DMICDAT1 Analogue input / Digital Input Right channel negative differential Mic/Line input / Digital MIC data input 1 B2 IN1RP Analogue Input Right channel single-ended Mic/Line input / Right channel positive differential Mic/Line input D4 IN2ALN/ DMICCLK2 Analogue Input / Digital Output Left channel negative differential Mic/Line input / Digital MIC clock output 2 D3 IN2ALP Analogue Input Left channel single-ended Mic/Line input / Left channel positive differential Mic/Line input C1 IN2ARN/ DMICDAT2 Analogue input / Digital Input Right channel negative differential Mic/Line input / Digital MIC data input 2 Rev 4.2 CS47L85 PIN NO NAME TYPE C2 IN2ARP Analogue Input Right channel single-ended Mic/Line input / Right channel positive differential Mic/Line input F2 IN2BLN Analogue Input Left channel negative differential Mic/Line input. Also suitable for connection to external accessory interfaces. F1 IN2BLP Analogue Input Left channel single-ended Mic/Line input / Left channel positive differential Mic/Line input. Also suitable for connection to external accessory interfaces. F3 IN2BR Analogue Input Right channel single-ended Mic/Line input. Also suitable for connection to external accessory interfaces. E4 IN3LN/ DMICCLK3 Analogue Input / Digital Output Left channel negative differential Mic/Line input / Digital MIC clock output 3 E3 IN3LP Analogue Input Left channel single-ended Mic/Line input / Left channel positive differential Mic/Line input D1 IN3RN/ DMICDAT3 Analogue input / Digital Input Right channel negative differential Mic/Line input / Digital MIC data input 3 D2 IN3RP Analogue Input Right channel single-ended Mic/Line input / Right channel positive differential Mic/Line input F11 IRQ ¯¯¯ Digital Output Interrupt Request (IRQ) output (default is active low). The pin configuration is selectable CMOS or Open Drain. C11 JACKDET1 Analogue Input Jack detect input 1 C12 JACKDET2 Analogue Input Jack detect input 2 LDOENA Digital Input Enable pin for LDO1 (generates DCVDD supply). Logic 1 input enables LDO1. If using external DCVDD supply, then LDO1 is not used, and LDOENA must be held at logic 0. Supply Supply for LDO1 Analogue Output LDO1 output. If using external DCVDD, then LDOVOUT must be left floating. E13 F14 LDOVDD E14 LDOVOUT DESCRIPTION F12 MCLK1 Digital Input Master clock 1 M13 MCLK2 Digital Input Master clock 2 A3 MICBIAS1 Analogue Output Microphone bias 1 A2 MICBIAS2 Analogue Output Microphone bias 2 B4 MICBIAS3 Analogue Output Microphone bias 3 B3 MICBIAS4 Analogue Output Microphone bias 4 B14 MICDET1/ HPOUT1FB2 Analogue Input Microphone & accessory sense input 1/ HPOUT1L and HPOUT1R ground feedback pin 2 A4 MICVDD Analogue Output LDO2 output decoupling pin (generated internally by CS47L85). (Can also be used as reference/supply for external microphones.) K12 MIF1SCLK/ GPIO9 Digital Input / Output Master (I2C) Interface 1 clock output / GPIO9. GPIO output is selectable CMOS or Open Drain; SCLK output is Open Drain. L12 MIF1SDA/ GPIO10 Digital Input / Output Master (I2C) Interface 1 data input and output / GPIO10. GPIO output is selectable CMOS or Open Drain; SDA output is Open Drain. M10 MIF2SCLK/ GPIO11 Digital Input / Output Master (I2C) Interface 2 clock output / GPIO11. GPIO output is selectable CMOS or Open Drain; SCLK output is Open Drain. L9 MIF2SDA/ GPIO12 Digital Input / Output Master (I2C) Interface 2 data input and output / GPIO12. GPIO output is selectable CMOS or Open Drain; SDA output is Open Drain. M5 MIF3SCLK/ GPIO13 Digital Input / Output Master (I2C) Interface 3 clock output / GPIO13. GPIO output is selectable CMOS or Open Drain; SCLK output is Open Drain. L5 MIF3SDA/ GPIO14 Digital Input / Output Master (I2C) Interface 3 data input and output / GPIO14. GPIO output is selectable CMOS or Open Drain; SDA output is Open Drain. Digital Input Digital Reset input (active low) Digital Input / Output SLIM Bus Clock input / output F13 RESET ¯¯¯¯¯¯ M14 SLIMCLK Rev 4.2 11 CS47L85 PIN NO NAME TYPE DESCRIPTION L13 SLIMDAT Digital Input / Output SLIM Bus Data input / output N12 SPKCLK1/ GPIO37 Digital Input / Output Digital speaker (PDM) 1 clock output / GPIO37. GPIO output is selectable CMOS or Open Drain; SPKCCLK output is CMOS. M11 SPKDAT1/ GPIO39 Digital Input / Output Digital speaker (PDM) 1 data output / GPIO39. GPIO output is selectable CMOS or Open Drain; SPKDAT output is CMOS. P11 SPKCLK2/ GPIO38 Digital Input / Output Digital speaker (PDM) 2 clock output / GPIO38. GPIO output is selectable CMOS or Open Drain; SPKCLK output is CMOS. N11 SPKDAT2/ GPIO40 Digital Input / Output Digital speaker (PDM) 2 data output / GPIO40. GPIO output is selectable CMOS or Open Drain; SPKDAT output is CMOS. M1 SPKGNDLN Supply Left speaker driver ground (Return path for SPKVDDL). See note. M2 SPKGNDLP Supply Left speaker driver ground (Return path for SPKVDDL). See note. L1 SPKGNDRN Supply Right speaker driver ground (Return path for SPKVDDR). See note. L2 SPKGNDRP Supply Right speaker driver ground (Return path for SPKVDDR). See note. N1 SPKOUTLN Analogue Output Left speaker negative output N2 SPKOUTLP Analogue Output Left speaker positive output K1 SPKOUTRN Analogue Output Right speaker negative output K2 SPKOUTRP Analogue Output Right speaker positive output G2 SPKTST1 Analogue Output Test function (recommend no external connection) G3 SPKTST2 Analogue Output Test function (recommend no external connection) P1, P2 SPKVDDL Supply Left speaker driver supply J1, J2 SPKVDDR Supply Right speaker driver supply D13, H1 SUBGND Supply Substrate ground H8 TCK Digital Input JTAG clock input. Internal pull-down holds this pin at logic 0 for normal operation. J9 TDI Digital Input JTAG data input. Internal pull-down holds this pin at logic 0 for normal operation. H9 TDO Digital Output JTAG data output J8 TMS Digital Input JTAG mode select input. Internal pull-down holds this pin at logic 0 for normal operation. G8 TRST Digital Input JTAG Test Access Port reset (active low). Internal pull-down holds this pin at logic 0 for normal operation. External connection to DGND is recommended, if the JTAG interface function is not required. G1 VREFC Analogue Output Bandgap reference external capacitor connection Note: Separate P/N ground connections are provided for each speaker driver channel; this provides flexible support for current monitoring and output protection circuits. If this option is not used, then the respective ground connections should be tied together on the PCB. 12 Rev 4.2 CS47L85 The following table identifies the power domain and ground reference associated with each of the input / output pins. PIN NO NAME POWER DOMAIN GROUND DOMAIN H13 AIF1BCLK/GPIO16 DBVDD1 DGND H12 AIF1LRCLK/GPIO18 DBVDD1 DGND G12 AIF1RXDAT/GPIO17 DBVDD1 DGND G11 AIF1TXDAT/GPIO15 DBVDD1 DGND M12 AIF2BCLK/GPIO20 DBVDD2 DGND L10 AIF2LRCLK/GPIO22 DBVDD2 DGND N13 AIF2RXDAT/GPIO21 DBVDD2 DGND AIF2TXDAT/GPIO19 DBVDD2 DGND M4 AIF3BCLK/GPIO24 DBVDD3 DGND K4 AIF3LRCLK/GPIO26 DBVDD3 DGND N4 AIF3RXDAT/GPIO25 DBVDD3 DGND L4 AIF3TXDAT/GPIO23 DBVDD3 DGND M7 AIF4BCLK/GPIO28 DBVDD3 DGND N8 AIF4LRCLK/GPIO30 DBVDD3 DGND P8 AIF4RXDAT/GPIO29 DBVDD3 DGND L7 AIF4TXDAT/GPIO27 DBVDD3 DGND J12 CIF1MISO DBVDD1 DGND J11 CIF1MOSI DBVDD1 DGND J13 CIF1SCLK DBVDD1 DGND H11 CIF1SS ¯¯¯¯¯¯ DBVDD1 DGND K11 CIF2SCLK DBVDD1 DGND K13 CIF2SDA DBVDD1 DGND L6 CIF3MISO DBVDD3 DGND N6 CIF3MOSI DBVDD3 DGND L11 N7 CIF3SCLK DBVDD3 DGND M6 CIF3SS ¯¯¯¯¯¯ DBVDD3 DGND N10 DMICCLK4/GPIO31 DBVDD4 DGND N9 DMICCLK5/GPIO33 DBVDD4 DGND L8 DMICCLK6/GPIO35 DBVDD4 DGND M9 DMICDAT4/GPIO32 DBVDD4 DGND P9 DMICDAT5/GPIO34 DBVDD4 DGND M8 DMICDAT6/GPIO36 DBVDD4 DGND G9 GPIO1 DBVDD1 DGND J7 GPIO2 DBVDD2 DGND J4 GPIO3 DBVDD3 DGND H7 GPIO4 DBVDD3 DGND G6 GPIO5 DBVDD3 DGND N5 GPIO6 DBVDD3 DGND H6 GPIO7 DBVDD3 DGND GPIO8 DBVDD3 DGND J6 B13 HPDETL AVDD AGND B12 HPDETR AVDD AGND C4 IN1ALN/ DMICCLK1 MICVDD (analogue) / MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 (digital) The DMICCLK1 power domain is selectable using IN1_DMIC_SUP AGND C3 IN1ALP MICVDD AGND E1 IN1BN MICVDD AGND E2 IN1BP MICVDD AGND B1 IN1RN/ DMICDAT1 MICVDD (analogue) / MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 (digital) The DMICDAT1 power domain is selectable using IN1_DMIC_SUP AGND B2 IN1RP MICVDD AGND Rev 4.2 13 CS47L85 PIN NO D4 IN2ALN/ DMICCLK2 POWER DOMAIN GROUND DOMAIN MICVDD (analogue) / MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 (digital) The DMICCLK2 power domain is selectable using IN2_DMIC_SUP AGND MICVDD AGND MICVDD (analogue) / MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 (digital) The DMICDAT2 power domain is selectable using IN2_DMIC_SUP AGND D3 IN2ALP C1 IN2ARN/ DMICDAT2 C2 IN2ARP MICVDD AGND F2 IN2BLN MICVDD AGND F1 IN2BLP MICVDD AGND F3 IN2BR MICVDD AGND MICVDD (analogue) / MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 (digital) The DMICCLK3 power domain is selectable using IN3_DMIC_SUP AGND MICVDD AGND MICVDD (analogue) / MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 (digital) The DMICDAT3 power domain is selectable using IN3_DMIC_SUP AGND E4 IN3LN/ DMICCLK3 E3 IN3LP D1 IN3RN/ DMICDAT3 D2 IN3RP MICVDD AGND F11 IRQ ¯¯¯ DBVDD1 DGND C11 JACKDET1 AVDD AGND C12 JACKDET2 AVDD AGND E13 LDOENA DBVDD1 DGND MCLK1 DBVDD1 DGND M13 MCLK2 DBVDD2 DGND K12 MIF1SCLK/GPIO9 DBVDD1 DGND L12 MIF1SDA/GPIO10 DBVDD1 DGND M10 MIF2SCLK/GPIO11 DBVDD2 DGND L9 MIF2SDA/GPIO12 DBVDD2 DGND M5 MIF3SCLK/GPIO13 DBVDD3 DGND L5 MIF3SDA/GPIO14 DBVDD3 DGND F12 14 NAME F13 RESET ¯¯¯¯¯¯ DBVDD1 DGND M14 SLIMCLK DBVDD1 DGND L13 SLIMDAT DBVDD1 DGND N12 SPKCLK1/GPIO37 DBVDD2 DGND P11 SPKCLK2/GPIO38 DBVDD2 DGND M11 SPKDAT1/GPIO39 DBVDD2 DGND N11 SPKDAT2/GPIO40 DBVDD2 DGND H8 TCK DBVDD2 DGND J9 TDI DBVDD2 DGND H9 TDO DBVDD2 DGND J8 TMS DBVDD2 DGND G8 TRST DBVDD2 DGND Rev 4.2 CS47L85 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Cirrus Logic tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at 200mV Minimum Bias Voltage VMICBIAS Maximum Bias Voltage Bias Voltage output step size Regulator mode (MICBn_BYPASS=0) Load current ≤ 1.0mA Bias Voltage accuracy Output Noise Density Integrated noise voltage Load capacitance Rev 4.2 V 0.1 PSRR V +5% V Regulator mode (MICBn_BYPASS=0), VMICVDD - VMICBIAS >200mV 2.4 mA Bypass mode (MICBn_BYPASS=1) 5.0 Regulator mode (MICBn_BYPASS=0), MICBn_LVL = 4h, Load current = 1mA, Measured at 1kHz 50 nV/Hz Regulator mode (MICBn_BYPASS=0), MICBn_LVL = 4h, Load current = 1mA, 100Hz to 7kHz, A-weighted 4 µVrms 100mV (peak-peak) 217Hz 90 dB 100mV (peak-peak) 10kHz 80 Regulator mode (MICBn_BYPASS=0), MICBn_EXT_CAP=0 Regulator mode (MICBn_BYPASS=0), MICBn_EXT_CAP=1 Output discharge resistance V 2.8 -5% Bias Current Power Supply Rejection Ratio (DBVDDn, LDOVDD, CPVDD1, AVDD) 1.5 MICBn_ENA=0, MICBn_DISCH=1 50 1.8 pF 4.7 µF 2 kΩ 25 CS47L85 Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = DBVDD4 = CPVDD1 = AVDD = LDOVDD = 1.8V, CPVDD2 = 1.2V DCVDD = FLLVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT HP_IMPEDANCE_ RANGE=00 4 30 HP_IMPEDANCE_ RANGE=01 8 100 HP_IMPEDANCE_ RANGE=10 100 1000 HP_IMPEDANCE_ RANGE=11 1000 10000 400 6000 Ω HP_IMPEDANCE_ RANGE=01 or 10 -5 +5 % HP_IMPEDANCE_ RANGE=00 or 11 -10 +10 -20 +20 % Ω External Accessory Detect Load impedance detection range Detection via HPDETL pin (ACCDET_MODE=001) or HPDETR pin (ACCDET_MODE=010) Load impedance detection range Detection via MICDET1 or MICDET2 pin (ACCDET_MODE=100) Load impedance detection accuracy (result derived from HP_DACVAL, ACCDET_MODE=001 or 010) Load impedance detection accuracy (result derived from HP_LVL, ACCDET_MODE= 001, 010 or 100) Load impedance detection range Detection via MICDET1 or MICDET2 pin (ACCDET_MODE=000). 2.2kΩ (2%) MICBIAS resistor. Note these characteristics assume no other component is connected to MICDETn. Jack Detection input threshold voltage (JACKDETn) 26 VJACKDET for MICD_LVL[0] = 1 0 3 for MICD_LVL[1] = 1 17 21 for MICD_LVL[2] = 1 36 44 for MICD_LVL[3] = 1 62 88 for MICD_LVL[4] = 1 115 160 for MICD_LVL[5] = 1 207 381 for MICD_LVL[8] = 1 475 30000 Jack insertion 0.9 Jack removal 1.5 Ω V Rev 4.2 CS47L85 Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = DBVDD4 = CPVDD1 = AVDD = LDOVDD = 1.8V, CPVDD2 = 1.2V DCVDD = FLLVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX 0.9 2.7 3.3 UNIT MICVDD Charge Pump and Regulator (CP2 and LDO2) Output voltage VMICVDD Programmable output voltage step size LDO2_VSEL=00h to 14h (0.9V to 1.4V) 25 LDO2_VSEL=14h to 27h (1.4V to 3.3V) 100 4.7µF on MICVDD 1.5 Maximum output current 8 Start-up time V mV mA 2.5 ms MHz Frequency Locked Loop (FLL1, FLL2, FLL3) Output frequency Lock Time FLL output as SYSCLK or ASYNCCLK source 90 98.3 FLL output as DSPCLK source 135 150 FREF = 32kHz, FOUT = 147.456MHz 10 FREF = 12MHz, FOUT = 147.456MHz 1 ms RESET pin Input RESET input pulse width (To trigger a Hardware Reset, the RESET input must be asserted for longer than this duration) 1 µs Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. Device Reset Thresholds AVDD Reset Threshold VAVDD VAVDD rising VAVDD falling DCVDD Reset Threshold VDCVDD VDCVDD rising VDCVDD falling DBVDD1 Reset Threshold VDBVDD1 1.66 1.06 1.04 0.49 VDBVDD1 rising VDBVDD1 falling V 0.66 1.66 1.06 V 1.44 V 1.44 Note that the reset thresholds are derived from simulations only, across all operational and process corners. Device performance is not assured outside the voltage ranges defined in the “Recommended Operating Conditions” section. Refer to this section for the CS47L85 power-up sequencing requirements. Rev 4.2 27 CS47L85 TERMINOLOGY 1. 2. 3. 4. 5. 6. 7. 8. 9. 28 Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum full scale output signal and the output with no input signal applied. Total Harmonic Distortion (dB) – THD is the ratio of the RMS sum of the harmonic distortion products in the specified bandwidth (see note below) relative to the RMS amplitude of the fundamental (i.e., test frequency) output. Total Harmonic Distortion plus Noise (dB) – THD+N is the ratio of the RMS sum of the harmonic distortion products plus noise in the specified bandwidth (see note below) relative to the RMS amplitude of the fundamental (i.e., test frequency) output. Power Supply Rejection Ratio (dB) - PSRR is the ratio of a specified power supply variation relative to the output signal that results from it. PSRR is measured under quiescent signal path conditions. Common Mode Rejection Ratio (dB) – CMRR is the ratio of a specified input signal (applied to both sides of a differential input), relative to the output signal that results from it. Channel Separation (L/R) (dB) – left-to-right and right-to-left channel separation is the difference in level between the active channel (driven to maximum full scale output) and the measured signal level in the idle channel at the test signal frequency. The active channel is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the associated idle channel. Multi-Path Crosstalk (dB) – is the difference in level between the output of the active path and the measured signal level in the idle path at the test signal frequency. The active path is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the specified idle path. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with mute applied. All performance measurements are specified with a 20kHz low pass ‘brick-wall’ filter and, where noted, an A-weighted filter. Failure to use these filters will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The low pass filter removes out-of-band noise. Rev 4.2 CS47L85 THERMAL CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNIT ΘJA 30.6 °C/W Junction-to-board thermal resistance ΘJB 13.8 °C/W Junction-to-case thermal resistance ΘJC 0.44 °C/W Junction-to-board thermal characterisation parameter ΨJB 16.8 °C/W Junction-to-top thermal characterisation parameter ΨJT 0.02 °C/W Junction-to-ambient thermal resistance Notes: 1. The Thermal Characteristics data is based on simulated test results, with reference to JEDEC JESD51 standards. 2. The thermal resistance (Θ) parameters describe the thermal behaviour in a standardised measurement environment. 3. The thermal characterisation (Ψ) parameters describe the thermal behaviour in the environment of a typical application. Rev 4.2 29 CS47L85 TYPICAL PERFORMANCE TYPICAL POWER CONSUMPTION Typical power consumption data is provided below for a number of different operating conditions. Test Conditions: DBVDD1 = DBVDD2 = DBVDD3 = DBVDD4 = CPVDD1 = AVDD = LDOVDD = 1.8V, CPVDD2 = DCVDD = FLLVDD = 1.2V, SPKVDDL = SPKVDDR = 4.2V, MICVDD = 2.5V (powered from LDO2), TA = +25ºC, PGA gain = 0dB, fs = 48kHz, 24-bit audio data, I2S Slave Mode, SYSCLK = 24.576 MHz (direct MCLK1) unless otherwise OPERATING MODE TEST CONDITIONS SUPPLY CURRENT (1.2V) SUPPLY CURRENT (1.8V) SUPPLY CURRENT (4.2V) TOTAL POWER Quiescent 2.2mA 0.7mA 0.0mA 3.9mW 1kHz sine wave, PO=10mW 37.7mA 1.9mA 0.0mA 48.66mW Quiescent 1.5mA 0.8mA 0.0mA 3.24mW 1kHz sine wave, PO=30mW 61.8mA 1.8mA 0.0mA 77.4mW Quiescent 2.0mA 2.1mA 0.0mA 6.18mW 1kHz sine wave, PO=700mW 2.0mA 2.1mA 382mA 1610mW 1kHz sine wave, -1dBFS out 2.1mA 2.4mA 0.0mA 6.84mW 0.00mA 0.01mA 0.000mA 0.018mW Music Playback to Headphone AIF1 to DAC to HPOUT (stereo) Load = 32 Music Playback to Earpiece AIF1 to DAC to HPOUT (mono) Load = 32, BTL Music Playback to Speaker AIF1 to DAC to SPKOUT (stereo) Load = 8, 22µH, BTL Stereo Line Record Analogue Line to ADC to AIF1 MICVDD=1.8V (CP2/LDO2 bypass) Sleep Mode Accessory detect enabled (JD1_ENA=1) 30 Rev 4.2 CS47L85 TYPICAL SIGNAL LATENCY OPERATING MODE TEST CONDITIONS INPUT OUTPUT LATENCY DIGITAL CORE AIF to DAC Stereo Path Digital input (AIFn) to analogue output (HPOUT). fs = 192kHz fs = 192kHz Synchronous 235µs fs = 96kHz fs = 96kHz Synchronous 261µs fs = 48kHz fs = 48kHz Synchronous 335µs fs = 44.1kHz fs = 44.1kHz Synchronous 361µs fs = 16kHz fs = 16kHz Synchronous 552µs fs = 8kHz fs = 8kHz Synchronous 1080µs 1720µs fs = 8kHz fs = 48kHz Isochronous fs = 16kHz fs = 48kHz Isochronous 995µs fs = 8kHz fs = 44.1kHz Asynchronous 1790µs fs = 16kHz fs = 44.1kHz Asynchronous 1067µs fs = 192kHz fs = 192kHz Synchronous 59µs fs = 96kHz fs = 96kHz Synchronous 98µs fs = 48kHz fs = 48kHz Synchronous 220µs fs = 44.1kHz fs = 44.1kHz Synchronous 235µs fs = 16kHz fs = 16kHz Synchronous 656µs fs = 8kHz fs = 8kHz Synchronous 1325µs 1805µs ADC to AIF Stereo Path Analogue input (INn) to digital output (AIFn). Input path High Pass Filter (HPF) enabled. fs = 8kHz fs = 48kHz Isochronous fs = 16kHz fs = 48kHz Isochronous 997µs fs = 44.1kHz fs = 8kHz Asynchronous 1369µs fs = 44.1kHz fs = 16kHz Asynchronous 883µs Notes Signal is routed via the digital core ISRC function in the isochronous test cases only. Signal is routed via the digital core ASRC function in the asynchronous test cases only. Rev 4.2 31 CS47L85 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK & FREQUENCY LOCKED LOOP (FLL) tMCLKY VIH VIL MCLK tMCLKL tMCLKH Figure 1 Master Clock Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Master Clock Timing (MCLK1, MCLK2) MCLK cycle time MCLK as input to FLL, FLLn_REFCLK_DIV=00 74 MCLK as input to FLL, FLLn_REFCLK_DIV=01 37 MCLK as input to FLL, FLLn_REFCLK_DIV=10 18 MCLK as input to FLL, FLLn_REFCLK_DIV=11 12.5 MCLK as direct SYSCLK or ASYNCCLK source 40 MCLK as input to FLL 80:20 20:80 MCLK as direct SYSCLK or ASYNCCLK source 60:40 40:60 FLLn_REFCLK_DIV=00 0.032 13.5 FLLn_REFCLK_DIV=01 0.064 27 FLLn_REFCLK_DIV=10 0.128 54 MCLK duty cycle ns % Frequency Locked Loops (FLL1, FLL2) FLL input frequency FLL synchroniser input frequency 32 FLLn_REFCLK_DIV=11 0.256 80 FLLn_SYNCCLK_DIV=00 0.032 13.5 FLLn_SYNCCLK_DIV=01 0.064 27 FLLn_SYNCCLK_DIV=10 0.128 54 FLLn_SYNCCLK_DIV=11 0.256 80 MHz MHz Rev 4.2 CS47L85 Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Internal Clocking SYSCLK frequency ASYNCCLK frequency SYSCLK_FREQ=000, SYSCLK_FRAC=0 -1% 6.144 +1% SYSCLK_FREQ=000, SYSCLK_FRAC=1 -1% 5.6448 +1% SYSCLK_FREQ=001, SYSCLK_FRAC=0 -1% 12.288 +1% SYSCLK_FREQ=001, SYSCLK_FRAC=1 -1% 11.2896 +1% SYSCLK_FREQ=010, SYSCLK_FRAC=0 -1% 24.576 +1% SYSCLK_FREQ=010, SYSCLK_FRAC=1 -1% 22.5792 +1% SYSCLK_FREQ=011, SYSCLK_FRAC=0 -1% 49.152 +1% SYSCLK_FREQ=011, SYSCLK_FRAC=1 -1% 45.1584 +1% SYSCLK_FREQ=100, SYSCLK_FRAC=0 -1% 98.304 +1% SYSCLK_FREQ=100, SYSCLK_FRAC=1 -1% 90.3168 +1% ASYNC_CLK_FREQ=000 -1% 6.144 +1% -1% 5.6448 +1% -1% 12.288 +1% -1% 11.2896 +1% -1% 24.576 +1% -1% 22.5792 +1% -1% 49.152 +1% -1% 45.1584 +1% -1% 98.304 +1% -1% 90.3168 +1% ASYNC_CLK_FREQ=001 ASYNC_CLK_FREQ=010 ASYNC_CLK_FREQ=011 ASYNC_CLK_FREQ=100 DSPCLK frequency 5 150 MHz MHz MHz Note: When MCLK1 or MCLK2 is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the frequency must be within 1% of the applicable SYSCLK_FREQ or ASYNCCLK_FREQ register setting. Rev 4.2 33 CS47L85 AUDIO INTERFACE TIMING DIGITAL MICROPHONE (DMIC) INTERFACE TIMING tCY DMICCLK (output) VOH VOL tr tf tRSU tRH DMICDAT (input) tLSU (right data) tLH VIH VIL (left data) Figure 2 Digital Microphone Interface Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Digital Microphone Interface Timing DMICCLKn cycle time tCY DMICCLKn duty cycle 160 163 1432 ns 45 55 % DMICCLKn rise/fall time (25pF load, 1.8V supply - see note) tr , tf 5 30 ns DMICDATn (Left) setup time to falling DMICCLK edge tLSU 15 ns DMICDATn (Left) hold time from falling DMICCLK edge tLH 0 ns DMICDATn (Right) setup time to rising DMICCLK edge tRSU 15 ns DMICDATn (Right) hold time from rising DMICCLK edge tRH 0 ns Notes: DMICDATn and DMICCLKn are each referenced to a selectable supply, VSUP. The applicable supply is selected using the INn_DMIC_SUP registers. The voltage reference for the IN1, IN2 and IN3 digital microphone interfaces is selectable, using the INn_DMIC_SUP registers - each interface may be referenced to MICVDD, or to the MICBIAS1, MICBIAS2 or MICBIAS3 levels. The voltage reference for the IN4, IN5 and IN6 digital microphone interfaces is DBVDD4. 34 Rev 4.2 CS47L85 DIGITAL SPEAKER (PDM) INTERFACE TIMING tCY SPKCLK (output) VOH VOL tr tf tLH SPKDAT (output) tRH (left data) (right data) tLSU tRSU VOH VOL Figure 3 Digital Speaker (PDM) Interface Timing - Mode A Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT PDM Audio Interface Timing SPKCLKn cycle time tCY 160 SPKCLKn duty cycle 358 ns 45 163 55 % 8 ns SPKCLKn rise/fall time (25pF load) tr , tf 2 SPKDATn set-up time to SPKCLKn rising edge (Left channel) tLSU 30 ns SPKDATn hold time from SPKCLKn rising edge (Left channel) tLH 30 ns SPKDATn set-up time to SPKCLKn falling edge (Right channel) tRSU 30 ns SPKDATn hold time from SPKCLKn falling edge (Right channel) tRH 30 ns tCY SPKCLK (output) VOH VOL tr tLEN SPKDAT (output) tf tREN (left data) VOH VOL (right data) tLDIS tRDIS Figure 4 Digital Speaker (PDM) Interface Timing - Mode B Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT 358 ns PDM Audio Interface Timing SPKCLKn cycle time tCY SPKCLKn duty cycle SPKCLKn rise/fall time (25pF load) tr , tf 160 163 45 55 % 2 8 ns SPKDATn enable from SPKCLK rising edge (Right channel) tREN 15 ns SPKDATn disable to SPKCLK falling edge (Right channel) tRDIS 5 ns SPKDATn enable from SPKCLK falling edge (Left channel) tLEN 15 ns SPKDATn disable to SPKCLK rising edge (Left channel) tLDIS 5 ns Rev 4.2 35 CS47L85 DIGITAL AUDIO INTERFACE - MASTER MODE tBCY BCLK (output) tBCH tBCL LRCLK (output) tLRD TXDAT (output) tDD RXDAT (input) tDSU tDH Figure 5 Audio Interface Timing - Master Mode Note that BCLK and LRCLK outputs can be inverted if required; Figure 5 shows the default, non-inverted polarity. Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. CLOAD = 15pF to 25pF (output pins). BCLK slew (10% to 90%) = 3.7ns to 5.6ns. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Master Mode AIFnBCLK cycle time tBCY 40 ns AIFnBCLK pulse width high tBCH 18 ns AIFnBCLK pulse width low tBCL 18 AIFnLRCLK propagation delay from BCLK falling edge tLRD 0 8.3 ns AIFnTXDAT propagation delay from BCLK falling edge tDD 0 5 ns AIFnRXDAT setup time to BCLK rising edge tDSU 11 ns AIFnRXDAT hold time from BCLK rising edge tDH 0 ns AIFnLRCLK setup time to BCLK rising edge tLRSU 14 ns AIFnLRCLK hold time from BCLK rising edge tLRH 0 ns ns Audio Interface Timing - Master Mode, Slave LRCLK Note: The descriptions above assume non-inverted polarity of AIFnBCLK. 36 Rev 4.2 CS47L85 DIGITAL AUDIO INTERFACE - SLAVE MODE tBCY BCLK (input) tBCH tBCL LRCLK (input) tLRH tLRSU TXDAT (output) tDD RXDAT (input) tDSU tDH Figure 6 Audio Interface Timing - Slave Mode Note that BCLK and LRCLK inputs can be inverted if required; Figure 6 shows the default, non-inverted polarity. Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Slave Mode AIFnBCLK cycle time AIFnBCLK pulse width high BCLK as direct SYSCLK or ASYNCCLK source tBCY 40 ns tBCH 16 ns All other conditions AIFnBCLK pulse width low BCLK as direct SYSCLK or ASYNCCLK source 14 tBCL All other conditions 16 ns 14 Audio Interface Timing - Slave Mode CLOAD = 15pF (output pins). BCLK slew (10% to 90%) = 3ns. AIFnLRCLK set-up time to BCLK rising edge tLRSU 7 AIFnLRCLK hold time from BCLK rising edge tLRH 0 AIFnTXDAT propagation delay from BCLK falling edge tDD 0 AIFnRXDAT set-up time to BCLK rising edge tDSU 2 ns AIFnRXDAT hold time from BCLK rising edge tDH 0 ns AIFnLRCLK set-up time to BCLK rising edge tLRSU 7 ns AIFnLRCLK hold time from BCLK rising edge tLRH 0 AIFnTXDAT propagation delay from BCLK falling edge tDD 0 AIFnRXDAT set-up time to BCLK rising edge tDSU 2 ns AIFnRXDAT hold time from BCLK rising edge tDH 0 ns ns ns 12.2 ns Audio Interface Timing - Slave Mode CLOAD = 25pF (output pins). BCLK slew (10% to 90%) = 6ns. ns 14.2 ns Audio Interface Timing - Slave Mode, Master LRCLK AIFnLRCLK propagation delay from BCLK falling edge CLOAD = 15pF (output pins). BCLK slew (10% to 90%) = 3ns. AIFnLRCLK propagation delay from BCLK falling edge CLOAD = 25pF (output pins). BCLK slew (10% to 90%) = 6ns. tLRD 14.8 ns 15.9 Notes: The descriptions above assume non-inverted polarity of AIFnBCLK. When AIFnBCLK or AIFnLRCLK is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the frequency must be within 1% of the applicable SYSCLK_FREQ or ASYNCCLK_FREQ register setting. Rev 4.2 37 CS47L85 DIGITAL AUDIO INTERFACE - TDM MODE When TDM operation is used on the AIFnTXDAT pins, it is important that two devices do not attempt to drive the AIFnTXDAT pin simultaneously. To support this requirement, the AIFnTXDAT pins can be configured to be tri-stated when not outputting data. The timing of the AIFnTXDAT tri-stating at the start and end of the data transmission is described in Figure 7 below. BCLK TXDAT AIFnTXDAT undriven (tri-state) AIFnTXDAT valid (CODEC output) AIFnTXDAT enable time AIFnTXDAT valid AIFnTXDAT undriven (tri-state) AIFnTXDAT disable time Figure 7 Audio Interface Timing - TDM Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. PARAMETER MIN TYP MAX UNIT TDM Timing - Master Mode CLOAD (AIFnTXDAT) = 15pF to 25pF. BCLK slew (10% to 90%) = 3.7ns to 5.6ns. AIFnTXDAT enable time from BCLK falling edge 0 AIFnTXDAT disable time from BCLK falling edge ns 6 ns TDM Timing - Slave Mode CLOAD (AIFnTXDAT) = 15pF). BCLK slew (10% to 90%) = 3ns. AIFnTXDAT enable time from BCLK falling edge 2 AIFnTXDAT disable time from BCLK falling edge ns 12.2 ns TDM Timing - Slave Mode CLOAD (AIFnTXDAT) = 25pF). BCLK slew (10% to 90%) = 6ns AIFnTXDAT enable time from BCLK falling edge AIFnTXDAT disable time from BCLK falling edge 38 2 ns 14.2 ns Rev 4.2 CS47L85 CONTROL INTERFACE TIMING 2-WIRE (I2C) CONTROL MODE START t1 t2 STOP t6 SCLK (input) t4 t7 t3 t8 SDA t5 t9 t10 Figure 8 Control Interface Timing - 2-wire (I2C) Control Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL MIN SCLK Frequency TYP MAX 3400 UNIT kHz SCLK Low Pulse-Width t1 160 ns SCLK High Pulse-Width t2 100 ns Hold Time (Start Condition) t3 160 ns Setup Time (Start Condition) t4 160 SDA, SCLK Rise Time (10% to 90%) t6 SDA, SCLK Fall Time (90% to 10%) SCLK frequency > 1.7MHz ns 80 SCLK frequency > 1MHz 160 SCLK frequency ≤ 1MHz 2000 SCLK frequency > 1.7MHz t7 60 SCLK frequency > 1MHz ns ns 160 SCLK frequency ≤ 1MHz 200 Setup Time (Stop Condition) t8 160 ns SDA Setup Time (data input) t5 40 ns SDA Hold Time (data input) t9 0 SDA Valid Time (data/ACK output) t10 SCLK slew (90% to 10%) = 20ns, CLOAD (SDA) = 15pF SCLK slew (90% to 10%) = 60ns, CLOAD (SDA) = 100pF 130 SCLK slew (90% to 10%) = 160ns, CLOAD (SDA) = 400pF 190 SCLK slew (90% to 10%) = 200ns, CLOAD (SDA) = 550pF 220 Pulse width of spikes that will be suppressed Rev 4.2 ns 40 tps 0 25 ns ns 39 CS47L85 4-WIRE (SPI) CONTROL MODE tSHO tSSU SS (input) tSCY SCLK (input) tSCH MOSI (input) tSCL tDSU tDHO Figure 9 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle) SS (input) SCLK (input) MISO (output) tDL Figure 10 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle) Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL MIN TYP MAX UNIT SS ¯¯ falling edge to SCLK rising edge tSSU 2.6 ns SCLK falling edge to SS ¯¯ rising edge tSHO 0 ns SCLK pulse cycle time tSCY 50.0 ns SYSCLK disabled (SYSCLK_ENA=0) SYSCLK_ENA=1 and SYSCLK_FREQ = 000 76.8 SYSCLK_ENA=1 and SYSCLK_FREQ > 000 38.4 SCLK pulse width low tSCL 15.3 ns SCLK pulse width high tSCH 15.3 ns MOSI to SCLK set-up time tDSU 1.5 ns tDHO 1.7 tDL 0 MOSI to SCLK hold time SCLK falling edge to MISO transition 40 SCLK slew (90% to 10%) = 5ns, CLOAD (MISO) = 25pF ns 12.6 ns Rev 4.2 CS47L85 SLIMBUS INTERFACE TIMING VIH, VOH VIL, VOL SLIMCLK TCLKL TCLKH VIH VIL SLIMDAT TDV TSETUP TH VIL, VIH are the 35%/65% levels of the respective inputs. VOL, VOH are the 20%/80% levels of the respective outputs. The SLIMDAT output delay (TDV) is with respect to the input pads of all receiving devices. Figure 11 SLIMbus Interface Timing The signal timing information shown in Figure 11 describe the timing requirements of the SLIMbus interface as a whole, not just the CS47L85 device. Accordingly, the following should be noted:  TDV is the propagation delay from the rising SLIMCLK edge (at CS47L85 input) to the SLIMDAT output being achieved at the input to all devices across the bus.  TSETUP is the set-up time for SLIMDAT input (at CS47L85), relative to the falling SLIMCLK edge (at CS47L85).  TH is the hold time for SLIMDAT input (at CS47L85) relative to the falling SLIMCLK edge (at CS47L85). For more details of the interface timing, refer to the MIPI Alliance Specification for Serial Low-power Inter-chip Media Bus (SLIMbus). Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL MIN TYP MAX UNIT SLIMCLK Input SLIMCLK cycle time 35 ns SLIMCLK pulse width high TCLKH 12 ns SLIMCLK pulse width low TCLKL 12 ns SLIMCLK Output SLIMCLK cycle time 40 ns SLIMCLK pulse width high TCLKH 12 ns SLIMCLK pulse width low TCLKL 12 SRCLK 0.09 x VDBVDD1 0.22 x VDBVDD1 CLOAD = 70pF, SLIMCLK_DRV_STR=0 0.02 x VDBVDD1 0.05 x VDBVDD1 CLOAD = 70pF, SLIMCLK_DRV_STR=1 0.04 x VDBVDD1 0.11 x VDBVDD1 SLIMCLK slew rate (20% to 80%) CLOAD = 15pF, SLIMCLK_DRV_STR=0 ns V/ns SLIMDAT Input SLIMDAT setup time to SLIMCLK falling edge SLIMDAT hold time from SLIMCLK falling edge Rev 4.2 TSETUP 3.5 ns TH 2 ns 41 CS47L85 Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL MIN TYP MAX UNIT 4.7 8.1 ns CLOAD = 15pF, SLIMDAT_DRV_STR=1, DBVDD1=1.71V 4.3 7.3 CLOAD = 30pF, SLIMDAT_DRV_STR=0, DBVDD1=1.71V 6.8 11.8 CLOAD = 30pF, SLIMDAT_DRV_STR=1, DBVDD1=1.71V 5.8 10.0 CLOAD = 50pF, SLIMDAT_DRV_STR=0, DBVDD1=1.71V 9.6 16.6 CLOAD = 50pF, SLIMDAT_DRV_STR=1, DBVDD1=1.71V 7.9 13.7 CLOAD = 70pF, SLIMDAT_DRV_STR=0, DBVDD1=1.71V 12.4 21.5 CLOAD = 70pF, SLIMDAT_DRV_STR=1, DBVDD1=1.71V 10.0 17.4 SLIMDAT Output SLIMDAT time for data output valid (wrt SLIMCLK rising edge) SLIMDAT slew rate (20% to 80%) CLOAD = 15pF, SLIMDAT_DRV_STR=0, DBVDD1=1.71V CLOAD = 15pF, SLIMDAT_DRV_STR=0 TDV SRDATA 0.64 x VDBVDD1 CLOAD = 30pF, SLIMDAT_DRV_STR=0 0.35 x VDBVDD1 CLOAD = 30pF, SLIMDAT_DRV_STR=1 0.46 x VDBVDD1 CLOAD = 70pF, SLIMDAT_DRV_STR=0 0.16 x VDBVDD1 CLOAD = 70pF, SLIMCLK_DRV_STR=1 0.21 x VDBVDD1 V/ns Other Parameters Driver disable time Bus holder output impedance 42 TDD 0.1 x VDBVDD1 < V < 0.9 x VDBVDD1 RDATAS 18 6 ns 50 kΩ Rev 4.2 CS47L85 JTAG INTERFACE TIMING tCCY TCK (input) tCCH tCCL TRST (input) tRSU tRH TMS (input) tMSU tMH tDSU tDH TDI (input) TDO (output) tDD Figure 12 JTAG Interface Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. CLOAD = 25pF (output pins). TCK slew (20% to 80%) = 5ns. PARAMETER SYMBOL MIN TYP MAX UNIT JTAG Interface Timing TCK cycle time TCCY 50 ns TCK pulse width high TCCH 20 ns TCK pulse width low TCCL 20 ns TMS setup time to TCK rising edge TMSU 1 ns TMS hold time from TCK rising edge TMH 2 ns TDI setup time to TCK rising edge TDSU 1 ns TDI hold time from TCK rising edge TDH 2 TDO propagation delay from TCK falling edge TDD 0 TRST setup time to TCK rising edge TRSU 3 ns TRST hold time from TCK rising edge TRH 3 ns 20 ns TRST pulse width low Rev 4.2 ns 17 ns 43 CS47L85 DEVICE DESCRIPTION INTRODUCTION The CS47L85 is a highly integrated low-power audio hub CODEC for mobile telephony and portable devices. It provides flexible, high-performance audio interfacing for handheld devices in a small and cost-effective package. It provides exceptional levels of performance and signal processing capability, suitable for a wide variety of mobile and handheld devices. The CS47L85 digital core incorporates the Cirrus Logic Ambient Noise Cancellation (ANC), and provides an extensive capability for programmable signal processing algorithms, including receive (RX) path noise cancellation, transmit (TX) path noise reduction, and Acoustic Echo Cancellation (AEC) algorithms. The digital core provides signal processing capability for sensor hub functions. The programmable DSP allows many external sensors to be efficiently integrated, enabling increased contextual awareness in a wide variety of advanced user applications. The CS47L85 digital core supports audio enhancements, such as Dynamic Range Control (DRC), Multi-band Compression (MBC), and Virtual Surround Sound (VSS). Highly flexible digital mixing, including stereo full-duplex asynchronous sample rate conversion, provides use-case flexibility across a broad range of system architectures. A signal generator for controlling haptics vibe actuators is included. The CS47L85 provides multiple digital audio interfaces, including SLIMbus, in order to provide independent and fully asynchronous connections to different processors (e.g., application processor, baseband processor and wireless transceiver). A flexible clocking arrangement supports a wide variety of external clock references, including clocking derived from the digital audio interface. Three Frequency Locked Loop (FLL) circuits provide additional flexibility. Unused circuitry can be disabled under software control, in order to save power; low leakage currents enable extended standby/off time in portable battery-powered applications. The CS47L85 ‘Always-On’ circuitry can be used (in conjunction with the Apps Processor) to ‘Wake-Up’ the device following a headphone jack detection event. Versatile GPIO functionality is provided, and support for external accessory / push-button detection inputs. Comprehensive Interrupt (IRQ) logic and status readback are also provided. HI-FI AUDIO CODEC The CS47L85 is a high-performance low-power audio CODEC which uses a simple analogue architecture. Six ADCs are incorporated, with multiplexers to support up to nine analogue inputs. Eight DACs are incorporated, providing a dedicated DAC for each analogue output channel. The analogue outputs comprise three 32mW (121dB SNR) stereo headphone amplifiers with ground-referenced output, and a Class D stereo speaker driver capable of delivering 2.5W per channel into a 4Ω load. Six analogue inputs are provided, each supporting single-ended or differential input modes. In differential mode, the input path SNR is 106dB (16kHz sample rate, i.e., wideband voice mode). The ADC input paths can be bypassed, supporting up to 12 channels of digital microphone input. The audio CODEC is controlled directly via register access. The simple analogue architecture, combined with the integrated tone generator, enables simple device configuration and testing, minimising debug time and reducing software effort. The CS47L85 output drivers are designed to support as many different system architectures as possible. Each output has a dedicated DAC which allows mixing, equalisation, filtering, gain and other audio processing to be configured independently for each channel. This allows each signal path to be individually tailored for the load characteristics. All outputs have integrated pop and click suppression features. The headphone output drivers are ground-referenced, powered from an integrated charge pump, enabling high quality, power efficient headphone playback without any requirement for DC blocking capacitors. Ground loop feedback is incorporated, providing rejection of noise on the ground connections. A mono mode is available on the headphone outputs; this configures the drivers as differential (BTL) outputs, suitable for an earpiece or hearing aid coil. The Class D speaker drivers deliver excellent power efficiency. High PSRR, low leakage and optimised supply voltage ranges enable powering from switching regulators or directly from the battery. Battery current consumption is minimised across a wide variety of voice communication and multimedia playback use cases. The CS47L85 is cost-optimised for a wide range of mobile phone applications, and features two channels of Class D power amplification. For applications requiring more than two channels of power amplification (or when using the integrated Class D path to drive a haptics actuator), the PDM output channels can be used to drive up to four external PDM-input speaker drivers. In applications where stereo loudspeakers are physically widely separated, the PDM outputs can ease layout and EMC by avoiding the need to run the Class-D speaker outputs over long distances and interconnects. 44 Rev 4.2 CS47L85 DIGITAL AUDIO CORE The CS47L85 uses a core architecture based on all-digital signal routing, making digital audio effects available on all signal paths, regardless of whether the source data input is analogue or digital. The digital mixing desk allows different audio effects to be applied simultaneously on many independent paths, whilst also supporting a variety of sample rates concurrently. This helps support many new audio use-cases. Soft mute and un-mute control allows smooth transitions between use-cases without interrupting existing audio streams elsewhere. The CS47L85 digital core provides an extensive capability for programmable signal processing algorithms. The DSP can support functions such as wind noise, side-tone and other programmable filters. A wide range of application-specific filters and audio enhancements can also be implemented, including Dynamic Range Control (DRC), Multi-band Compression (MBC), and Virtual Surround Sound (VSS). These digital effects can be used to improve audibility and stereo imaging while minimising supply current. The digital core also provides signal processing capability for sensor hub functions of the CS47L85. Sensors and accessories can be connected through 3 master I2C interfaces; the programmable DSP, together with peripheral timer and event logging functions, enables applications to use these inputs to support increased contextual awareness, including advanced motion sensing and navigation functionality. The Cirrus Logic Ambient Noise Cancellation (ANC) processor within the CS47L85 provides the capability to improve the intelligibility of a voice call by using destructive interference to reduce the acoustic energy of the ambient sound. The Cirrus Logic ANC technology supports receive (RX) path noise cancellation; Transmit (TX) path noise reduction, and multimic Acoustic Echo Cancellation (AEC) algorithms are also supported. The CS47L85 is ideal for mobile telephony, providing enhanced voice communication quality for both near-end and far-end users in a wide variety of applications. Highly flexible digital mixing, including mixing between audio interfaces, is possible. The CS47L85 performs multi-channel full-duplex asynchronous sample rate conversion, providing use-case flexibility across a broad range of system architectures. Automatic sample rate detection is provided, enabling seamless wideband/narrowband voice call handover. Dynamic Range Controller (DRC) functions are available for optimising audio signal levels. In playback modes, the DRC can be used to maximise loudness, while limiting the signal level to avoid distortion, clipping or battery droop, in particular for high-power output drivers such as speaker amplifiers. In record modes, the DRC assists in applications where the signal level is unpredictable. The 5-band parametric equaliser (EQ) functions can be used to compensate for the frequency characteristics of the output transducers. EQ functions can be cascaded to provide additional frequency control. Programmable high-pass and lowpass filters are also available for general filtering applications such as removal of wind and other low-frequency noise. DIGITAL INTERFACES Four serial digital audio interfaces (AIFs) each support PCM, TDM and I2S data formats for compatibility with most industry-standard chipsets. AIF1 and AIF2 support eight input/output channels; AIF3 and AIF4 support two input/output channels. Bidirectional operation at sample rates up to 192kHz is supported. 12 digital PDM input channels are available (six stereo interfaces); these are typically used for digital microphones, powered from the integrated MICBIAS power supply regulators. Four PDM output channels are also available (two stereo interfaces); these are typically used for external power amplifiers. Embedded mute codes provide a control mechanism for external PDM-input devices. The CS47L85 features a MIPI-compliant SLIMbus interface, providing eight channels of audio input/output. Mixed audio sample rates are supported on the SLIMbus interface. The SLIMbus interface also supports read/write access to the CS47L85 control registers. An IEC-60958-3 compatible S/PDIF transmitter is incorporated, enabling stereo S/PDIF output on a GPIO pin. Standard S/PDIF sample rates of 32kHz up to 192kHz are all supported. Control register access, and high bandwidth data transfer, is supported by two slave SPI interfaces and a slave I2C control interface. The SPI interfaces operate up to 26MHz; the I2C slave interface operates up to 3.4MHz. Full access to the register map is also provided via the SLIMbus port. The CS47L85 incorporates three master I2C interfaces, offering a flexible capability for additional sensor / accessory input. Typical sensors include accelerometers, gyroscopes and magnetometers for motion sensing and navigation applications. Other example accessories include barometers, or ambient light sensors, for environmental awareness. OTHER FEATURES The CS47L85 incorporates two 1kHz tone generators which can be used for ‘beep’ functions through any of the audio signal paths. The phase relationship between the two generators is configurable, providing flexibility in creating differential signals, or for test scenarios. A white noise generator is provided, which can be routed within the digital core. The noise generator can provide ‘comfort noise’ in cases where silence (digital mute) is not desirable. Rev 4.2 45 CS47L85 Two Pulse Width Modulation (PWM) signal generators are incorporated. The duty cycle of each PWM signal can be modulated by an audio source, or can be set to a fixed value using a control register setting. The PWM signal generators can be output directly on a GPIO pin. The CS47L85 supports up to 40 GPIO pins, offering a range of input/output functions for interfacing, detection of external hardware, and to provide logic outputs to other devices. The CS47L85 provides 8 dedicated GPIO pins; a further 32 GPIOs are multiplexed with other functions. Comprehensive Interrupt (IRQ) functionality is also provided for monitoring internal and external event conditions. A signal generator for controlling haptics devices is included, compatible with both Eccentric Rotating Mass (ERM) and Linear Resonant Actuator (LRA) haptic devices. The haptics signal generator is highly configurable, and can execute programmable drive event profiles, including reverse drive control. An external vibe actuator can be driven directly by the Class D speaker output. The CS47L85 incorporates eight general purpose timers, providing support for the sensor hub capability. Sensor event logging, and other real time application functions, allows many advanced functions to be implemented with a high degree of autonomy from a host processor. A smart accessory interface is included, supporting most standard 3.5mm accessories. Jack detection, accessory sensing and impedance measurement is provided, for external accessory and push-button detection. Accessory detection can be used as a ‘Wake-Up’ trigger from low-power standby. Microphone activity detection with interrupt is also available. System clocking can be derived from the MCLK1 or MCLK2 input pins. Alternatively, the SLIMbus interface, or the audio interfaces (configured in Slave mode), can be used to provide a clock reference. Three integrated Frequency Locked Loop (FLL) circuits provide support for a wide range of clocking configurations, including the use of a 32kHz input clock reference. The CS47L85 can be powered from 1.8V and 1.2V external supplies. A separate supply (4.2V) is typically required for the Class D speaker driver. Integrated Charge Pump and LDO Regulators circuits are used to generate supply rails for internal functions and to support powering or biasing of external microphones. 46 Rev 4.2 CS47L85 INPUT SIGNAL PATH The CS47L85 provides flexible input channels, supporting up to 9 analogue inputs or up to 12 digital inputs. Selectable combinations of analogue (mic or line) and digital inputs are multiplexed into 6 stereo input signal paths. Input paths IN1, IN2 and IN3 support analogue and digital inputs; Input paths IN4, IN5 and IN6 support digital inputs only. The analogue input paths support single-ended and differential modes, programmable gain control and are digitised using a high performance 24-bit sigma-delta ADC. The digital input paths interface directly with external digital microphones; a separate microphone interface clock is provided for six separate stereo pairs of digital microphones. Digital delay can be applied to any of the digital input paths; this can be used for phase adjustment of any digital input, including directional control of multiple microphones. Four microphone bias (MICBIAS) generators are available, which provide a low noise reference for biasing electret condenser microphones (ECMs) or for use as a low noise supply for MEMS microphones and digital microphones. Digital volume control is available on all inputs (analogue and digital), with programmable ramp control for smooth, glitchfree operation. Any pair of analogue or digital inputs may be selected as input to the Ambient Noise Cancellation (ANC) processing function. The signal paths and control registers for inputs IN1, IN2 and IN3 are illustrated in Figure 13. The IN4, IN5 and IN6 signal paths supports digital microphone input only. Rev 4.2 47 CS47L85 IN1BP IN1L_SRC [1:0] 00 = Differential IN1ALP – IN1ALN 01 = Single-ended IN1ALP (non-inverting) 10 = Differential IN1BP – IN1BN 11 = Single-ended IN1BP (non-inverting) IN_HPF_CUT [2:0] IN_VD_RAMP [2:0] IN_VI_RAMP [2:0] IN1_MODE - IN1BN IN1ALN/DMICCLK1 ADC + IN1ALP IN1L_PGA_VOL [6:0] IN1L_HPF IN1L_VOL [7:0] IN1L_MUTE IN1L_ENA IN1R_SRC [1:0] 00 = Differential IN1RP – IN1RN 01 = Single-ended IN1RP (non-inverting) 10 = Reserved 11 = Reserved - IN1RN/DMICDAT1 ADC + IN1RP IN1R_PGA_VOL [6:0] DAT Digital Mic Interface CLK IN1_OSR [2:0] IN1_DMIC_SUP [1:0] IN2BLP IN1R_ENA IN1L_DMIC_DLY [5:0] IN1R_DMIC_DLY [5:0] IN2L_SRC [1:0] 00 = Differential IN2ALP – IN2ALN 01 = Single-ended IN2ALP (non-inverting) 10 = Differential IN2BLP – IN2BLN 11 = Single-ended IN2BLP (non-inverting) IN2_MODE IN2ALN/DMICCLK2 ADC + IN2ALP IN2L_PGA_VOL [6:0] IN2L_HPF IN2R_SRC [1:0] 00 = Differential IN2ARP – IN2ARN 01 = Single-ended IN2ARP (non-inverting) 10 = Reserved 11 = Single-ended IN2BR (non-inverting) IN2L_VOL [7:0] IN2L_MUTE IN2L_ENA - IN2BR IN1R_VOL [7:0] IN1R_MUTE - IN2BLN IN1R_HPF IN2ARN/DMICDAT2 ADC + IN2ARP IN2R_PGA_VOL [6:0] DAT Digital Mic Interface CLK IN2_OSR [2:0] IN2_DMIC_SUP [1:0] IN2R_VOL [7:0] IN2R_MUTE IN2R_ENA IN2L_DMIC_DLY [5:0] IN2R_DMIC_DLY [5:0] IN3L_SRC [1:0] 00 = Differential IN3LP – IN3LN 01 = Single-ended IN3LP (non-inverting) 10 = Reserved 11 = Reserved IN3_MODE - IN3LN/DMICCLK3 IN2R_HPF ADC + IN3LP IN3L_PGA_VOL [6:0] IN3L_VOL [7:0] IN3L_MUTE IN3L_ENA - IN3RN/DMICDAT3 IN3L_HPF IN3R_SRC [1:0] 00 = Differential IN3RP – IN3RN 01 = Single-ended IN3RP (non-inverting) 10 = Reserved 11 = Reserved ADC + IN3RP IN3R_PGA_VOL [6:0] DAT CLK Digital Mic Interface IN3_OSR [2:0] IN3_DMIC_SUP [1:0] IN3R_HPF IN3R_VOL [7:0] IN3R_MUTE IN3R_ENA IN3L_DMIC_DLY [5:0] IN3R_DMIC_DLY [5:0] Figure 13 Input Signal Paths 48 Rev 4.2 CS47L85 ANALOGUE MICROPHONE INPUT Up to nine analogue microphones can be connected to the CS47L85, either in single-ended or differential mode. The applicable mode, and input pin selection, is controlled using the INnx_SRC registers, as described later. The CS47L85 includes external accessory detection circuits, which can detect the presence of a microphone, and the status of a hookswitch or other push-buttons. When using this function, it is recommended to use the IN1B or IN2B analogue microphone input paths, to ensure best immunity to electrical transients arising from the push-buttons. For single-ended input, the microphone signal is connected to the non-inverting input of the PGAs (INnLP or INnRP). The inverting inputs of the PGAs are connected to an internal reference in this configuration. For differential input, the non-inverted microphone signal is connected to the non-inverting input of the PGAs (INnLP or INnRP), whilst the inverted (or ‘noisy ground’) signal is connected to the inverting input pins (INnLN or INnRN). The gain of the input PGAs is controlled via register settings, as defined in Table 4. Note that the input impedance of the analogue input paths is fixed across all PGA gain settings. The Electret Condenser Microphone (ECM) analogue input configurations are illustrated in Figure 14 and Figure 15. The integrated MICBIAS generators provide a low noise reference for biasing the ECMs. MICBIAS MICBIAS IN1xP, IN2xP, IN3xP + PGA IN1xN, IN2xN, IN3xN MIC To ADC PGA To ADC - - IN1xN, IN2xN, IN3xN MIC + IN1xP, IN2xP, IN3xP GND VMID VMID GND Figure 14 Single-Ended ECM Input Figure 15 Differential ECM Input Analogue MEMS microphones can be connected to the CS47L85 in a similar manner to the ECM configurations described above; typical configurations are illustrated in Figure 16 and Figure 17. In this configuration, the integrated MICBIAS generators provide a low-noise power supply for the microphones. MICBIAS MEMS Mic MICBIAS IN1xP, IN2xP, IN3xP VDD IN1xP, IN2xP, IN3xP OUT + PGA To ADC MEMS Mic VDD OUT-P OUT-N GND IN1xN, IN2xN, IN3xN PGA To ADC - - IN1xN, IN2xN, IN3xN + GND GND VREF Figure 16 Single-Ended MEMS Input GND VREF Figure 17 Differential MEMS Input Note that the MICVDD pin can also be used (instead of MICBIASn) as a reference or power supply for external microphones. The MICBIAS outputs are recommended, as these offer better noise performance and independent enable/disable control. Rev 4.2 49 CS47L85 ANALOGUE LINE INPUT Line inputs can be connected to the CS47L85 in a similar manner to the microphone inputs described above. Singleended and differential modes are supported on each of the analogue input paths. The applicable mode (single-ended or differential) is selected using the INnx_SRC registers, as described later. The analogue line input configurations are illustrated in Figure 18 and Figure 19. Note that the microphone bias (MICBIAS) is not used for line input connections. IN1xP, IN2xP, IN3xP IN1xP, IN2xP, IN3xP Line Line + IN1xN, IN2xN, IN3xN To ADC PGA To ADC - PGA + - IN1xN, IN2xN, IN3xN GND VMID VMID Figure 18 Single-Ended Line Input Figure 19 Differential Line Input DIGITAL MICROPHONE INPUT Up to 12 digital microphones can be connected to the CS47L85. Digital Microphone (DMIC) operation on Input paths IN1, IN2 and IN3 is selected using the INn_MODE registers, as described later. DMIC operation on Input paths IN4, IN5 and IN6 is implemented on multi-function GPIO pins, which must be configured for the respective DMIC functions when required; see “General Purpose Input / Output” to configure the GPIO pins for DMIC operation. In digital microphone mode, two channels of audio data are multiplexed on the associated DMICDATn pin. Each stereo digital microphone interface is clocked using the respective DMICCLKn pin. When digital microphone input is enabled, the CS47L85 outputs a clock signal on the applicable DMICCLKn pin(s). The DMICCLKn frequency is controlled by the respective INn_OSR register, as described in Table 1. See Table 3 for details of the INn_OSR registers. Note that, if the 384kHz or 768kHz DMICCLKn frequency is selected for one or more of the digital microphone input paths, then the maximum valid Input Path sample rate (all input paths) will be affected as described in Table 1. Note that the DMICCLKn frequencies noted in Table 1 assume that the SYSCLK frequency is a multiple of 6.144MHz (SYSCLK_FRAC=0). If the SYSCLK frequency is a multiple of 5.6448MHz (SYSCLK_FRAC=1), then the DMICCLKn frequencies will be scaled accordingly. CONDITION DMICCLKn FREQUENCY VALID SAMPLE RATES SIGNAL PASSBAND INn_OSR = 010 384kHz up to 48kHz INn_OSR = 011 768kHz up to 96kHz up to 4kHz up to 8kHz INn_OSR = 100 1.536MHz up to 192kHz up to 20kHz INn_OSR =101 3.072MHz up to 192kHz up to 20kHz INn_OSR =110 6.144MHz up to 192kHz up to 96kHz Table 1 DMICCLK Frequency The voltage reference for the IN1, IN2 and IN3 digital microphone interfaces is selectable, using the INn_DMIC_SUP registers - each interface may be referenced to MICVDD, or to the MICBIAS1, MICBIAS2 or MICBIAS3 levels. The voltage reference for each digital input path should be set equal to the applicable power supply of the respective microphone(s). The voltage reference for the IN4, IN5 and IN6 digital microphone interfaces is DBVDD4. The power supply for digital microphones on these input paths (MICBIAS4 is recommended) should be set equal to the DBVDD4 voltage. A pair of digital microphones is connected as illustrated in Figure 20. The microphones must be configured to ensure that the Left mic transmits a data bit when DMICCLK is high, and the Right mic transmits a data bit when DMICCLK is low. The CS47L85 samples the digital microphone data at the end of each DMICCLK phase. Each microphone must tri-state its data output when the other microphone is transmitting. Note that the CS47L85 provides integrated pull-down resistors on the DMICDATn pins. This provides a flexible capability for interfacing with other devices. 50 Rev 4.2 CS47L85 MICVDD or MICBIASn DMICCLKn DMICDATn Digital Microphone Interface The IN1, IN2, IN3 digital inputs are referenced to MICVDD, or MICBIAS1/2/3. VDD VDD CLK DATA VDD Digital Mic The IN4, IN5, IN6 digital inputs are referenced to DBVDD4. CLK DATA The supply for each digital microphone should the same voltage as the applicable reference. Recommended that MICBIAS4 is used with IN4, IN5, IN6 only. Digital Mic CHAN CHAN AGND Figure 20 Digital Microphone Input Two digital microphone channels are interleaved on DMICDATn. The digital microphone interface timing is illustrated in Figure 21. Each microphone must tri-state its data output when the other microphone is transmitting. DMICCLKn pin hi-Z Left Mic output 1 Right Mic output DMICDATn pin (Left & Right channels interleaved) 1 2 1 2 1 2 1 2 2 1 2 Figure 21 Digital Microphone Interface Timing When digital microphone input is enabled, the CS47L85 outputs a clock signal on the applicable DMICCLK pin(s). The DMICCLK frequency is selectable, as described in Table 1. Note that SYSCLK must be present and enabled when using the Digital Microphone inputs; see “Clocking and Sample Rates” for details of SYSCLK and the associated register control fields. Rev 4.2 51 CS47L85 INPUT SIGNAL PATH ENABLE The input signal paths are enabled using the register bits described in Table 2. The respective bit(s) must be enabled for analogue or digital input on the respective input path(s). The input signal paths are muted by default. It is recommended that de-selecting the mute should be the final step of the path enable control sequence. Similarly, the mute should be selected as the first step of the path disable control sequence. The input signal path mute functions are controlled using the register bits described in Table 4. The MICVDD power domain must be enabled when using the analogue input signal path(s). This power domain is provided using an internal Charge Pump (CP2) and LDO Regulator (LDO2). See “Charge Pumps, Regulators and Voltage Reference” for details of these circuits. The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The input signal paths should be kept disabled (INnx_ENA=0) if SYSCLK is not enabled. The ASYNCCLK and 32kHz clock may also be required, depending on the path configuration. See “Clocking and Sample Rates” for details of the system clocks (including requirements for reconfiguring SYSCLK while audio paths are enabled). The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the input signal paths and associated ADCs. If an attempt is made to enable an input signal path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The status bits in Register R769 indicate the status of each of the input signal paths. If an Underclocked Error condition occurs, then these bits provide readback of which input signal path(s) have been successfully enabled. 52 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R768 (0300h) Input_Ena bles 11 IN6L_ENA 0 Input Path 6 (Left) Enable 0 = Disabled 1 = Enabled 10 IN6R_ENA 0 Input Path 6 (Right) Enable 0 = Disabled 1 = Enabled 9 IN5L_ENA 0 Input Path 5 (Left) Enable 0 = Disabled 1 = Enabled 8 IN5R_ENA 0 Input Path 5 (Right) Enable 0 = Disabled 1 = Enabled 7 IN4L_ENA 0 Input Path 4 (Left) Enable 0 = Disabled 1 = Enabled 6 IN4R_ENA 0 Input Path 4 (Right) Enable 0 = Disabled 1 = Enabled 5 IN3L_ENA 0 Input Path 3 (Left) Enable 0 = Disabled 1 = Enabled 4 IN3R_ENA 0 Input Path 3 (Right) Enable 0 = Disabled 1 = Enabled 3 IN2L_ENA 0 Input Path 2 (Left) Enable 0 = Disabled 1 = Enabled 2 IN2R_ENA 0 Input Path 2 (Right) Enable 0 = Disabled 1 = Enabled 1 IN1L_ENA 0 Input Path 1 (Left) Enable 0 = Disabled 1 = Enabled 0 IN1R_ENA 0 Input Path 1 (Right) Enable 0 = Disabled 1 = Enabled Rev 4.2 CS47L85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R769 (0301h) Input_Ena bles_Statu s 11 IN6L_ENA_STS 0 Input Path 6 (Left) Enable Status 0 = Disabled 1 = Enabled 10 IN6R_ENA_STS 0 Input Path 6 (Right) Enable Status 0 = Disabled 1 = Enabled 9 IN5L_ENA_STS 0 Input Path 5 (Left) Enable Status 0 = Disabled 1 = Enabled 8 IN5R_ENA_STS 0 Input Path 5 (Right) Enable Status 0 = Disabled 1 = Enabled 7 IN4L_ENA_STS 0 Input Path 4 (Left) Enable Status 0 = Disabled 1 = Enabled 6 IN4R_ENA_STS 0 Input Path 4 (Right) Enable Status 0 = Disabled 1 = Enabled 5 IN3L_ENA_STS 0 Input Path 3 (Left) Enable Status 0 = Disabled 1 = Enabled 4 IN3R_ENA_STS 0 Input Path 3 (Right) Enable Status 0 = Disabled 1 = Enabled 3 IN2L_ENA_STS 0 Input Path 2 (Left) Enable Status 0 = Disabled 1 = Enabled 2 IN2R_ENA_STS 0 Input Path 2 (Right) Enable Status 0 = Disabled 1 = Enabled 1 IN1L_ENA_STS 0 Input Path 1 (Left) Enable Status 0 = Disabled 1 = Enabled 0 IN1R_ENA_STS 0 Input Path 1 (Right) Enable Status 0 = Disabled 1 = Enabled Table 2 Input Signal Path Enable INPUT SIGNAL PATH SAMPLE RATE CONTROL The input signal paths may be selected as input to the digital mixers or signal processing functions within the CS47L85 digital core. The sample rate for the input signal paths is configured using the IN_RATE register - see Table 22 within the “Digital Core” section. Note that sample rate conversion is required when routing the input signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. Rev 4.2 53 CS47L85 INPUT SIGNAL PATH CONFIGURATION The CS47L85 supports up to 9 analogue inputs or up to 12 digital inputs. Selectable combinations of analogue (mic or line) and digital inputs are multiplexed into 6 stereo input signal paths. Input paths IN1, IN2 and IN3 can be configured as single-ended, differential, or digital microphone configuration. The input signal path configuration is selected using the INn_MODE and INnx_SRC registers. Note that input paths IN4, IN5 and IN6 support digital inputs only. A configurable high pass filter (HPF) is provided on the left and right channels of each input path. The applicable cut-off frequency is selected using the IN_HPF_CUT register. The filter can be enabled on each path independently using the INnx_HPF bits. The analogue input signal paths (single-ended or differential) each incorporate a PGA to provide gain in the range 0dB to +31dB in 1dB steps. Note that these PGAs do not provide pop suppression functions; it is recommended that the gain should not be adjusted whilst the respective signal path is enabled. The analogue input PGA gain is controlled using the INnL_PGA_VOL and INnR_PGA_VOL registers. Note that separate volume control is provided for the Left and Right channels of each stereo pair. When the IN1, IN2 or IN3 input signal path is configured for digital microphone input, the voltage reference for the associated input/output pins is selectable using the INn_DMIC_SUP registers - each interface may be referenced to MICVDD, or to the MICBIAS1, MICBIAS2 or MICBIAS3 levels. The voltage reference for each digital input path should be set equal to the applicable power supply of the respective microphone(s). The voltage reference for the IN4, IN5 and IN6 digital microphone interfaces is DBVDD4. The power supply for digital microphones on these input paths (MICBIAS4 is recommended) should be set equal to the DBVDD4 voltage. When the input signal path is configured for digital microphone input, the respective DMICCLKn frequency can be configured using the INn_OSR register bits. Note that, if a digital microphone path is selected as a source for the Rx ANC function (see Table 6), the respective DMICCLKn frequency will be 3.072MHz, regardless of the INn_OSR setting. A digital delay may be applied to any of the digital microphone input channels. This feature can be used for phase adjustment of any digital input, including directional control of multiple microphones. The delay is controlled using the INnL_DMIC_DLY and INnR_DMIC_DLY registers. The MICVDD voltage is generated by an internal Charge Pump and LDO Regulator. The MICBIAS1, MICBIAS2 and MICBIAS3 outputs are derived from MICVDD - see “Charge Pumps, Regulators and Voltage Reference”. The input signal paths are configured using the register bits described in Table 3. REGISTER ADDRESS BIT DEFAULT DESCRIPTION R780 (030Ch) HPF_Cont rol 2:0 IN_HPF_CUT [2:0] R784 (0310h) IN1L_Cont rol 15 IN1L_HPF 0 Input Path 1 (Left) HPF Enable 0 = Disabled 1 = Enabled IN1_DMIC_SUP [1:0] 00 Input Path 1 DMIC Reference Select (Sets the DMICDAT1 and DMICCLK1 logic levels) 00 = MICVDD 01 = MICBIAS1 10 = MICBIAS2 11 = MICBIAS3 IN1_MODE 00 Input Path 1 Mode 0 = Analogue input 1 = Digital input 12:11 10 54 LABEL 010 Input Path HPF Select Controls the cut-off frequency of the input path HPF circuits. 000 = 2.5Hz 001 = 5Hz 010 = 10Hz 011 = 20Hz 100 = 40Hz All other codes are Reserved Rev 4.2 CS47L85 REGISTER ADDRESS LABEL DEFAULT DESCRIPTION 7:1 IN1L_PGA_VOL [6:0] 40h Input Path 1 (Left) PGA Volume (Applicable to analogue inputs only) 00h to 3Fh = Reserved 40h = 0dB 41h = 1dB 42h = 2dB … (1dB steps) 5F = 31dB 60h to 7Fh = Reserved R785 (0311h) ADC_Digit al_Volume _1L 14:13 IN1L_SRC [1:0] 00 Input Path 1 (Left) Source 00 = Differential (IN1ALP - IN1ALN) 01 = Single-ended (IN1ALP) 10 = Differential (IN1BP-IN1BN) 11 = Single-ended (IN1BP) R786 (0312h) DMIC1L_ Control 10:8 IN1_OSR [2:0] 101 Input Path 1 DMIC Oversample Rate When digital microphone input is selected (IN1_MODE=1), this field controls the sample rate as below: 000 = Reserved 001 = Reserved 010 = 384kHz 011 = 768kHz 100 = 1.536MHz 101 = 3.072MHz 110 = 6.144MHz 111 = Reserved When IN1_OSR=010 or 011, then the maximum Input Path sample rate (all input paths) is 48kHz or 96kHz respectively. If Input Path 1 DMIC is selected as a source for the Rx ANC function, the DMICCLK1 frequency will be set to 3.072MHz. 5:0 IN1L_DMIC_DLY [5:0] 00h Input Path 1 (Left) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN1_OSR.) 15 IN1R_HPF 7:1 IN1R_PGA_VOL [6:0] 40h Input Path 1 (Right) PGA Volume (Applicable to analogue inputs only) 00h to 3Fh = Reserved 40h = 0dB 41h = 1dB 42h = 2dB … (1dB steps) 5F = 31dB 60h to 7Fh = Reserved R789 (0315h) ADC_Digit al_Volume _1R 14:13 IN1R_SRC [1:0] 00 Input Path 1 (Right) Source 00 = Differential (IN1RP - IN1RN) 01 = Single-ended (IN1RP) 10 = Reserved 11 = Reserved R790 (0316h) DMIC1R_ Control 5:0 IN1R_DMIC_DLY [5:0] 00h Input Path 1 (Right) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN1_OSR.) R788 (0314h) IN1R_Con trol Rev 4.2 BIT 0 Input Path 1 (Right) HPF Enable 0 = Disabled 1 = Enabled 55 CS47L85 REGISTER ADDRESS BIT R792 (0318h) IN2L_Cont rol 15 DEFAULT DESCRIPTION IN2L_HPF 0 Input Path 2 (Left) HPF Enable 0 = Disabled 1 = Enabled IN2_DMIC_SUP [1:0] 00 Input Path 2 DMIC Reference Select (Sets the DMICDAT2 and DMICCLK2 logic levels) 00 = MICVDD 01 = MICBIAS1 10 = MICBIAS2 11 = MICBIAS3 10 IN2_MODE 00 Input Path 2 Mode 0 = Analogue input 1 = Digital input 7:1 IN2L_PGA_VOL [6:0] 40h Input Path 2 (Left) PGA Volume (Applicable to analogue inputs only) 00h to 3Fh = Reserved 40h = 0dB 41h = 1dB 42h = 2dB … (1dB steps) 5F = 31dB 60h to 7Fh = Reserved R793 (0319h) ADC_Digit al_Volume _2L 14:13 IN2L_SRC [1:0] 00 Input Path 2 (Left) Source 00 = Differential (IN2ALP - IN2ALN) 01 = Single-ended (IN2ALP) 10 = Differential (IN2BLP-IN2BLN) 11 = Single-ended (IN2BLP) R794 (031Ah) DMIC2L_ Control 10:8 IN2_OSR [2:0] 101 Input Path 2 DMIC Oversample Rate When digital microphone input is selected (IN2_MODE=1), this field controls the sample rate as below: 000 = Reserved 001 = Reserved 010 = 384kHz 011 = 768kHz 100 = 1.536MHz 101 = 3.072MHz 110 = 6.144MHz 111 = Reserved When IN2_OSR=010 or 011, then the maximum Input Path sample rate (all input paths) is 48kHz or 96kHz respectively. If Input Path 2 DMIC is selected as a source for the Rx ANC function, the DMICCLK2 frequency will be set to 3.072MHz. 5:0 IN2L_DMIC_DLY [5:0] 00h Input Path 2 (Left) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN2_OSR.) 15 IN2R_HPF R796 (031Ch) IN2R_Con 56 LABEL 12:11 0 Input Path 2 (Right) HPF Enable 0 = Disabled 1 = Enabled Rev 4.2 CS47L85 REGISTER ADDRESS trol LABEL DEFAULT DESCRIPTION 7:1 IN2R_PGA_VOL [6:0] 40h Input Path 2 (Right) PGA Volume (Applicable to analogue inputs only) 00h to 3Fh = Reserved 40h = 0dB 41h = 1dB 42h = 2dB … (1dB steps) 5F = 31dB 60h to 7Fh = Reserved R797 (0319h) ADC_Digit al_Volume _2R 14:13 IN2R_SRC [1:0] 00 Input Path 2 (Right) Source 00 = Differential (IN2ARP - IN2ARN) 01 = Single-ended (IN2ARP) 10 = Reserved 11 = Single-ended (IN2BR) R798 (031Eh) DMIC2R_ Control 5:0 IN2R_DMIC_DLY [5:0] 00h Input Path 2 (Right) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN2_OSR.) R800 (0320h) IN3L_Cont rol 15 IN3L_HPF 0 Input Path 3 (Left) HPF Enable 0 = Disabled 1 = Enabled IN3_DMIC_SUP [1:0] 00 Input Path 3 DMIC Reference Select (Sets the DMICDAT3 and DMICCLK3 logic levels) 00 = MICVDD 01 = MICBIAS1 10 = MICBIAS2 11 = MICBIAS3 10 IN3_MODE 00 Input Path 3 Mode 0 = Analogue input 1 = Digital input 7:1 IN3L_PGA_VOL [6:0] 40h Input Path 3 (Left) PGA Volume (Applicable to analogue inputs only) 00h to 3Fh = Reserved 40h = 0dB 41h = 1dB 42h = 2dB … (1dB steps) 5F = 31dB 60h to 7Fh = Reserved 14:13 IN3L_SRC [1:0] 00 Input Path 3 (Left) Source 00 = Differential (IN3LP - IN3LN) 01 = Single-ended (IN3LP) 10 = Reserved 11 = Reserved R801 (0321h) ADC_Digit al_Volume _3L Rev 4.2 BIT 12:11 57 CS47L85 REGISTER ADDRESS R802 (0322h) DMIC3L_ Control LABEL DEFAULT DESCRIPTION 10:8 IN3_OSR [2:0] 101 Input Path 3 DMIC Oversample Rate When digital microphone input is selected (IN3_MODE=1), this field controls the sample rate as below: 000 = Reserved 001 = Reserved 010 = 384kHz 011 = 768kHz 100 = 1.536MHz 101 = 3.072MHz 110 = 6.144MHz 111 = Reserved When IN3_OSR=010 or 011, then the maximum Input Path sample rate (all input paths) is 48kHz or 96kHz respectively. If Input Path 3 DMIC is selected as a source for the Rx ANC function, the DMICCLK3 frequency will be set to 3.072MHz. 5:0 IN3L_DMIC_DLY [5:0] 00h Input Path 3 (Left) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN3_OSR.) 15 IN3R_HPF 7:1 IN3R_PGA_VOL [6:0] 40h Input Path 3 (Right) PGA Volume (Applicable to analogue inputs only) 00h to 3Fh = Reserved 40h = 0dB 41h = 1dB 42h = 2dB … (1dB steps) 5F = 31dB 60h to 7Fh = Reserved R805 (0325h) ADC_Digit al_Volume _3R 14:13 IN3R_SRC [1:0] 00 Input Path 3 (Right) Source 00 = Differential (IN3RP - IN3RN) 01 = Single-ended (IN3RP) 10 = Reserved 11 = Reserved R806 (0326h) DMIC3R_ Control 5:0 IN3R_DMIC_DLY [5:0] 00h Input Path 3 (Right) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN3_OSR.) R808 (0328h) IN4L_Cont rol 15 IN4L_HPF R804 (0324h) IN3R_Con trol 58 BIT 0 0 Input Path 3 (Right) HPF Enable 0 = Disabled 1 = Enabled Input Path 4 (Left) HPF Enable 0 = Disabled 1 = Enabled Rev 4.2 CS47L85 REGISTER ADDRESS R810 (032Ah) DMIC4L_ Control LABEL DEFAULT DESCRIPTION 10:8 IN4_OSR [2:0] 101 Input Path 4 DMIC Oversample Rate Controls the DMIC4 sample rate as below: 000 = Reserved 001 = Reserved 010 = 384kHz 011 = 768kHz 100 = 1.536MHz 101 = 3.072MHz 110 = 6.144MHz 111 = Reserved When IN4_OSR=010 or 011, then the maximum Input Path sample rate (all input paths) is 48kHz or 96kHz respectively. If Input Path 4 DMIC is selected as a source for the Rx ANC function, the DMICCLK4 frequency will be set to 3.072MHz. 5:0 IN4L_DMIC_DLY [5:0] 00h Input Path 4 (Left) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN4_OSR.) R812 (032Ch) IN4R_Con trol 15 IN4R_HPF R814 (032Eh) DMIC4R_ Control 5:0 IN4R_DMIC_DLY [5:0] R816 (0330h) IN5L_Cont rol 15 IN5L_HPF R818 (0332h) DMIC5L_ Control 10:8 IN5_OSR [2:0] 101 Input Path 5 DMIC Oversample Rate Controls the DMIC5 sample rate as below: 000 = Reserved 001 = Reserved 010 = 384kHz 011 = 768kHz 100 = 1.536MHz 101 = 3.072MHz 110 = 6.144MHz 111 = Reserved When IN5_OSR=010 or 011, then the maximum Input Path sample rate (all input paths) is 48kHz or 96kHz respectively. If Input Path 5 DMIC is selected as a source for the Rx ANC function, the DMICCLK5 frequency will be set to 3.072MHz. 5:0 IN5L_DMIC_DLY [5:0] 00h Input Path 5 (Left) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN5_OSR.) 15 IN5R_HPF R820 (0334h) IN5R_Con trol Rev 4.2 BIT 0 00h 0 0 Input Path 4 (Right) HPF Enable 0 = Disabled 1 = Enabled Input Path 4 (Right) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN4_OSR.) Input Path 5 (Left) HPF Enable 0 = Disabled 1 = Enabled Input Path 5 (Right) HPF Enable 0 = Disabled 1 = Enabled 59 CS47L85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R822 (0336h) DMIC5R_ Control 5:0 IN5R_DMIC_DLY [5:0] R824 (0338h) IN6L_Cont rol 15 IN6L_HPF R826 (033Ah) DMIC6L_ Control 10:8 IN6_OSR [2:0] 101 Input Path 6 DMIC Oversample Rate Controls the DMIC6 sample rate as below: 000 = Reserved 001 = Reserved 010 = 384kHz 011 = 768kHz 100 = 1.536MHz 101 = 3.072MHz 110 = 6.144MHz 111 = Reserved When IN6_OSR=010 or 011, then the maximum Input Path sample rate (all input paths) is 48kHz or 96kHz respectively. If Input Path 6 DMIC is selected as a source for the Rx ANC function, the DMICCLK6 frequency will be set to 3.072MHz. 5:0 IN6L_DMIC_DLY [5:0] 00h Input Path 6 (Left) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN6_OSR.) R828 (033Ch) IN6R_Con trol 15 IN6R_HPF R830 (033Eh) DMIC6R_ Control 5:0 IN6R_DMIC_DLY [5:0] 00h 0 0 00h Input Path 5 (Right) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN5_OSR.) Input Path 6 (Left) HPF Enable 0 = Disabled 1 = Enabled Input Path 6 (Right) HPF Enable 0 = Disabled 1 = Enabled Input Path 6 (Right) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN6_OSR.) Table 3 Input Signal Path Configuration 60 Rev 4.2 CS47L85 INPUT SIGNAL PATH DIGITAL VOLUME CONTROL A digital volume control is provided on each of the input signal paths, providing -64dB to +31.5dB gain control in 0.5dB steps. An independent mute control is also provided for each input signal path. Whenever the gain or mute setting is changed, the signal path gain is ramped up or down to the new settings at a programmable rate. For increasing gain (or un-mute), the rate is controlled by the IN_VI_RAMP register. For decreasing gain (or mute), the rate is controlled by the IN_VD_RAMP register. Note that the IN_VI_RAMP and IN_VD_RAMP registers should not be changed while a volume ramp is in progress. The IN_VU bits control the loading of the input signal path digital volume and mute controls. When IN_VU is set to 0, the digital volume and mute settings will be loaded into the respective control register, but will not actually change the signal path gain. The digital volume and mute settings on all of the input signal paths are updated when a 1 is written to IN_VU. This makes it possible to update the gain of multiple signal paths simultaneously. Note that, although the digital volume control registers provide 0.5dB steps, the internal circuits provide signal gain adjustment in 0.125dB steps. This allows a very high degree of gain control, and smooth volume ramping under all operating conditions. The 0dBFS level of the IN1-IN6 digital input paths is not equal to the 0dBFS level of the CS47L85 digital core. The maximum digital input signal level is -6dBFS (see “Electrical Characteristics”). Under 0dBFS gain conditions, a -6dBFS input signal corresponds to a 0dBFS input to the CS47L85 digital core functions. The digital volume control register fields are described in Table 4 and Table 5. REGISTER ADDRESS R777 (0309h) Input_Volu me_Ramp R785 (0311h) ADC_Digit al_Volume _1L Rev 4.2 BIT LABEL DEFAULT DESCRIPTION 6:4 IN_VD_RAMP [2:0] 010 Input Volume Decreasing Ramp Rate (seconds/6dB) 000 = 0ms 001 = 0.5ms 010 = 1ms 011 = 2ms 100 = 4ms 101 = 8ms 110 = 15ms 111 = 30ms This register should not be changed while a volume ramp is in progress. 2:0 IN_VI_RAMP [2:0] 010 Input Volume Increasing Ramp Rate (seconds/6dB) 000 = 0ms 001 = 0.5ms 010 = 1ms 011 = 2ms 100 = 4ms 101 = 8ms 110 = 15ms 111 = 30ms This register should not be changed while a volume ramp is in progress. 9 IN_VU 8 IN1L_MUTE Input Signal Paths Volume and Mute Update Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 Input Path 1 (Left) Digital Mute 0 = Un-mute 1 = Mute 61 CS47L85 REGISTER ADDRESS BIT 7:0 R789 (0315h) ADC_Digit al_Volume _1R IN_VU 8 IN1R_MUTE 62 IN1R_VOL [7:0] 9 IN_VU 8 IN2L_MUTE 7:0 R797 (031Dh) ADC_Digit al_Volume _2R IN1L_VOL [7:0] 9 7:0 R793 (0319h) ADC_Digit al_Volume _2L LABEL IN2L_VOL [7:0] 9 IN_VU 8 IN2R_MUTE DEFAULT 80h DESCRIPTION Input Path 1 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Input Signal Paths Volume and Mute Update Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 80h Input Path 1 (Right) Digital Mute 0 = Un-mute 1 = Mute Input Path 1 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Input Signal Paths Volume and Mute Update Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 80h Input Path 2 (Left) Digital Mute 0 = Un-mute 1 = Mute Input Path 2 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Input Signal Paths Volume and Mute Update Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 Input Path 2 (Right) Digital Mute 0 = Un-mute 1 = Mute Rev 4.2 CS47L85 REGISTER ADDRESS BIT 7:0 R801 (0321h) ADC_Digit al_Volume _3L IN_VU 8 IN3L_MUTE Rev 4.2 IN3L_VOL [7:0] 9 IN_VU 8 IN3R_MUTE 7:0 R809 (0329h) ADC_Digit al_Volume _4L IN2R_VOL [7:0] 9 7:0 R805 (0325h) ADC_Digit al_Volume _3R LABEL IN3R_VOL [7:0] 9 IN_VU 8 IN4L_MUTE DEFAULT 80h DESCRIPTION Input Path 2 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Input Signal Paths Volume and Mute Update Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 80h Input Path 3 (Left) Digital Mute 0 = Un-mute 1 = Mute Input Path 3 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Input Signal Paths Volume and Mute Update Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 80h Input Path 3 (Right) Digital Mute 0 = Un-mute 1 = Mute Input Path 3 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Input Signal Paths Volume and Mute Update Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 Input Path 4 (Left) Digital Mute 0 = Un-mute 1 = Mute 63 CS47L85 REGISTER ADDRESS BIT 7:0 R813 (032Dh) ADC_Digit al_Volume _4R IN_VU 8 IN4R_MUTE 64 IN4R_VOL [7:0] 9 IN_VU 8 IN5L_MUTE 7:0 R821 (0335h) ADC_Digit al_Volume _5R IN4L_VOL [7:0] 9 7:0 R817 (0331h) ADC_Digit al_Volume _5L LABEL IN5L_VOL [7:0] 9 IN_VU 8 IN5R_MUTE DEFAULT 80h DESCRIPTION Input Path 4 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Input Signal Paths Volume and Mute Update Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 80h Input Path 4 (Right) Digital Mute 0 = Un-mute 1 = Mute Input Path 4 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Input Signal Paths Volume and Mute Update Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 80h Input Path 5 (Left) Digital Mute 0 = Un-mute 1 = Mute Input Path 5 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Input Signal Paths Volume and Mute Update Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 Input Path 5 (Right) Digital Mute 0 = Un-mute 1 = Mute Rev 4.2 CS47L85 REGISTER ADDRESS BIT 7:0 R825 (0339h) ADC_Digit al_Volume _6L IN5R_VOL [7:0] 9 IN_VU 8 IN6L_MUTE 7:0 R829 (033Dh) ADC_Digit al_Volume _6R LABEL IN6L_VOL [7:0] 9 IN_VU 8 IN6R_MUTE 7:0 IN6R_VOL [7:0] DEFAULT 80h DESCRIPTION Input Path 5 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Input Signal Paths Volume and Mute Update Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 80h Input Path 6 (Left) Digital Mute 0 = Un-mute 1 = Mute Input Path 6 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Input Signal Paths Volume and Mute Update Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 80h Input Path 6 (Right) Digital Mute 0 = Un-mute 1 = Mute Input Path 6 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Table 4 Input Signal Path Digital Volume Control Rev 4.2 65 CS47L85 Input Volume Register Volume (dB) Input Volume Register Volume (dB) Input Volume Register Volume (dB) Input Volume Register Volume (dB) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 00. -64.0 -63.5 -63.0 -62.5 -62.0 -61.5 -61.0 -60.5 -60.0 -59.5 -59.0 -58.5 -58.0 -57.5 -57.0 -56.5 -56.0 -55.5 -55.0 -54.5 -54.0 -53.5 -53.0 -52.5 -52.0 -51.5 -51.0 -50.5 -50.0 -49.5 -49.0 -48.5 -48.0 -47.5 -47.0 -46.5 -46.0 -45.5 -45.0 -44.5 -44.0 -43.5 -43.0 -42.5 -42.0 -41.5 -41.0 -40.5 -40.0 -39.5 -39.0 -38.5 -38.0 -37.5 -37.0 -36.5 -36.0 -35.5 -35.0 -34.5 -34.0 -33.5 -33.0 -32.5 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh -32.0 -31.5 -31.0 -30.5 -30.0 -29.5 -29.0 -28.5 -28.0 -27.5 -27.0 -26.5 -26.0 -25.5 -25.0 -24.5 -24.0 -23.5 -23.0 -22.5 -22.0 -21.5 -21.0 -20.5 -20.0 -19.5 -19.0 -18.5 -18.0 -17.5 -17.0 -16.5 -16.0 -15.5 -15.0 -14.5 -14.0 -13.5 -13.0 -12.5 -12.0 -11.5 -11.0 -10.5 -10.0 -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 22.5 23.0 23.5 24.0 24.5 25.0 25.5 26.0 26.5 27.0 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Table 5 Input Signal Path Digital Volume Range 66 Rev 4.2 CS47L85 INPUT SIGNAL PATH ANC CONTROL The CS47L85 incorporates a stereo Ambient Noise Cancellation (ANC) processor which can provide noise reduction in a variety of different operating conditions. The Left and Right ANC input sources for the Receive Path ANC function are selected using the IN_RXANCL_SEL and IN_RXANCR_SEL registers, as described in Table 6. See “Ambient Noise Cancellation” for further details of the ANC function. REGISTER ADDRESS R3841 (0F01h) ANC_SRC BIT LABEL DEFAULT DESCRIPTION 6:4 IN_RXANCR_SE L [2:0] 000 Right Input source for Rx ANC function 000 = No selection 001 = Input Path 1 010 = Input Path 2 011 = Input Path 3 100 = Input Path 4 101 = Input Path 5 110 = Input Path 6 111 = Reserved 2:0 IN_RXANCL_SE L [2:0] 000 Left Input source for Rx ANC function 000 = No selection 001 = Input Path 1 010 = Input Path 2 011 = Input Path 3 100 = Input Path 4 101 = Input Path 5 110 = Input Path 6 111 = Reserved Table 6 Input Signal Paths ANC Control DIGITAL MICROPHONE PIN CONFIGURATION Digital Microphone (DMIC) operation on Input paths IN1, IN2 and IN3 is selected using the INn_MODE registers, as described in Table 3. When DMIC is selected, the respective DMICCLKn and DMICDATn pins are configured as digital outputs and inputs respectively. DMIC operation on Input paths IN4, IN5 and IN6 is implemented on multi-function GPIO pins, which must be configured for the respective DMIC functions when required. The DMIC connections are pin-specific alternative functions on specific GPIO pins. See “General Purpose Input / Output” to configure the GPIO pins for DMIC operation. The CS47L85 provides integrated pull-down resistors on each of the DMICDATn pins. This provides a flexible capability for interfacing with other devices. The DMICDAT1, DMICDAT2 and DMICDAT3 pull-down resistors can be configured independently using the register bits described in Table 7. Note that, if the DMICDATn digital microphone input paths are disabled, then the pull-down will be disabled on the respective pin. In the case of the DMIC4, DMIC5 and DMIC6 interfaces, integrated pull-up and pull-down resistors are provided as part of the GPIO functionality, and can be configured using the register bits described in Table 94. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R840 (0348h) Dig_Mic_P ad_Ctrl 2 DMICDAT3_PD 0 DMICDAT3 Pull-Down Control 0 = Disabled 1 = Enabled 1 DMICDAT2_PD 0 DMICDAT2 Pull-Down Control 0 = Disabled 1 = Enabled 0 DMICDAT1_PD 0 DMICDAT1 Pull-Down Control 0 = Disabled 1 = Enabled Table 7 Digital Microphone Interface Pull-Down Control Rev 4.2 67 CS47L85 DIGITAL CORE The CS47L85 digital core provides extensive mixing and processing capabilities for multiple signal paths. The configuration is highly flexible, and virtually every conceivable input/output connection can be supported between the available processing blocks. The digital core provides parametric equalisation (EQ) functions, dynamic range control (DRC), low-pass / high-pass filters (LHPF), and programmable DSP capability. The DSP can support functions such as wind noise, side-tone or other programmable filters, also dynamic range control and compression, or virtual surround sound and other audio enhancements. The CS47L85 supports multiple signal paths through the digital core. Stereo full-duplex sample rate conversion is provided to allow digital audio to be routed between input (ADC) paths, output (DAC) paths, Digital Audio Interfaces (AIF1, AIF2, AIF3 and AIF4) and SLIMbus paths operating at different sample rates and/or referenced to asynchronous clock domains. The DSP functions are highly programmable, using application-specific control sequences. It should be noted that the DSP configuration data is lost whenever the DCVDD power domain is removed; the DSP configuration data must be downloaded to the CS47L85 each time the device is powered up. The procedure for configuring the CS47L85 DSP functions is tailored to each customer’s application; please contact your local Cirrus Logic representative for more details. The digital core incorporates a S/PDIF transmitter, which can provide a stereo S/PDIF output on a GPIO pin. Standard S/PDIF sample rates of 32kHz up to 192kHz can be supported. The CS47L85 incorporates two 1kHz tone generators which can be used for ‘beep’ functions through any of the audio signal paths. A white noise generator is incorporated, to provide ‘comfort noise’ in cases where silence (digital mute) is not desirable. A haptic signal generator is provided, for use with external haptic devices (e.g., mechanical vibration actuators). Two Pulse Width Modulation (PWM) signal generators are also provided; the PWM waveforms can be modulated by an audio source within the digital core, and can be output on a GPIO pin. The CS47L85 also incorporates the Cirrus Logic Ambient Noise Cancellation (ANC) functionality; note that this is described in a separate section, see “Ambient Noise Cancellation”. An overview of the digital core mixing and signal processing functions is provided in Figure 22. The control registers associated with the digital core signal paths are shown in Figure 23 through to Figure 39. The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see “Register Map” for further information. Generic register definitions are provided in Table 8. 68 Rev 4.2 Rev 4.2 ASRCn Right ASRCn Left ASRC2 ASRC1 Asynchronous Sample Rate Converter (ASRC) IN6R signal path IN6L signal path IN5R signal path IN5L signal path IN4R signal path IN4L signal path IN3R signal path IN3L signal path IN2R signal path IN2L signal path IN1R signal path IN1L signal path AEC2 Loopback AEC1 Loopback Silence (mute) ASRCn Right ASRCn Left ISRCn DEC4 ISRCn DEC3 ISRCn DEC2 ISRCn DEC1 + Tone Generator White Noise Generator Haptic Signal Generator ISRC2 ISRC1 Isochronous Sample Rate Converter (ISRC) PWM ISRCn INT4 ISRCn INT3 ISRCn INT2 ISRCn INT1 (GPIO pin) (GPIO pin) PWM2 PWM1 S/PDIF Tone Generator 2 Tone Generator 1 Noise Generator Haptic Output ISRCn DEC2 ISRCn DEC1 + Isochronous Sample Rate Converter (ISRC) ISRC4 ISRC3 LHPF LHPF4 LHPF3 LHPF2 LHPF1 + + ISRCn INT2 ISRCn INT1 LHPFn DSP Core + + + DRC DRC2 DRC1 EQ DRCn Right DRCn Left EQn DSPn Channel 6 DSPn Channel 5 DSPn Channel 4 DSPn Channel 3 DSPn Channel 2 DSPn Channel 1 EQ4 EQ3 EQ2 EQ1 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 Stereo Output Paths AIF1 = 8 input, 8 output AIF2 = 8 input, 8 output AIF3 = 2 input, 2 output AIF4 = 2 input, 2 output + + + + AIF4 AIF3 AIF2 AIF1 etc... SLIMBUS SLIMbus = 8 input, 8 output + + OUTnR output OUTnL output AIFn RX.. AIFn RX.. AIFn RX2 AIFn RX1 AIFn TX.. output AIFn TX.. output AIFn TX2 output AIFn TX1 output OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 CS47L85 Figure 22 Digital Core 69 CS47L85 DIGITAL CORE MIXERS The CS47L85 provides an extensive digital mixing capability. The digital core mixing and signal processing blocks are illustrated in Figure 22. A 4-input digital mixer is associated with many of these functions, as illustrated. The digital mixer circuit is identical in each instance, providing up to 4 selectable input sources, with independent volume control on each input. The control registers associated with the digital core signal paths are shown in Figure 23 through to Figure 39. The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see “Register Map” for further information. Further description of the associated control registers is provided below. Generic register definitions are provided in Table 8. The digital mixer input sources are selected using the associated *_SRCn registers; the volume control is implemented via the associated *_VOLn registers. The ASRC, ISRC, and DSP Aux Input functions support selectable input sources, but do not incorporate any digital mixing. The respective input source (*_SRCn) registers are identical to those of the digital mixers. The *_SRCn registers select the input source(s) for the respective mixer or signal processing block. Note that the selected input source(s) must be configured for the same sample rate as the block(s) to which they are connected. Sample rate conversion functions are available to support flexible interconnectivity - see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”. The *_SRCn registers for all digital core functions should be held at 00h if SYSCLK is not enabled – SYSCLK must be present and enabled before selecting other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while digital core mixers are enabled). A status bit associated with each of the configurable input sources provides readback for the respective signal path. If an Underclocked Error condition occurs, then these bits provide readback of which signal path(s) have been successfully enabled. The generic register definition for the digital mixers is provided in Table 8. 70 Rev 4.2 CS47L85 REGISTER ADDRESS R1600 (0640h) BIT 15 LABEL *_STSn DEFAULT 0 [Digital Core function] input n status 0 = Disabled 1 = Enabled 40h [Digital Core mixer] input n volume -32dB to +16dB in 1dB steps 00h to 20h = -32dB 21h = -31dB 22h = -30dB ... (1dB steps) 40h = 0dB ... (1dB steps) 50h = +16dB 51h to 7Fh = +16dB 00h [Digital Core function] input n source select 00h = Silence (mute) 04h = Tone generator 1 05h = Tone generator 2 06h = Haptic generator 08h = AEC loopback 1 09h = AEC loopback 2 0Dh = Noise generator 10h = IN1L signal path 11h = IN1R signal path 12h = IN2L signal path 13h = IN2R signal path 14h = IN3L signal path 15h = IN3R signal path 16h = IN4L signal path 17h = IN4R signal path 18h = IN5L signal path 19h = IN5R signal path 1Ah = IN6L signal path 1Bh = IN6R signal path 20h = AIF1 RX1 21h = AIF1 RX2 22h = AIF1 RX3 23h = AIF1 RX4 24h = AIF1 RX5 25h = AIF1 RX6 26h = AIF1 RX7 27h = AIF1 RX8 28h = AIF2 RX1 29h = AIF2 RX2 2Ah = AIF2 RX3 2Bh = AIF2 RX4 2Ch = AIF2 RX5 2Dh = AIF2 RX6 2Eh = AIF2 RX7 2Fh = AIF2 RX8 30h = AIF3 RX1 31h = AIF3 RX2 34h = AIF4 RX1 35h = AIF4 RX2 Valid for every digital core function input (digital mixers, DSP Aux inputs, ASRC & ISRC inputs). to R3192 (0C78h) 7:1 *_VOLn Valid for every digital mixer input. 7:0 *_SRCn Valid for every digital core function input (digital mixers, DSP Aux inputs, ASRC & ISRC inputs). Rev 4.2 DESCRIPTION 71 CS47L85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 38h = SLIMbus RX1 39h = SLIMbus RX2 3Ah = SLIMbus RX3 3Bh = SLIMbus RX4 3Ch = SLIMbus RX5 3Dh = SLIMbus RX6 3Eh = SLIMbus RX7 3Fh = SLIMbus RX8 50h = EQ1 51h = EQ2 52h = EQ3 53h = EQ4 58h = DRC1 Left 59h = DRC1 Right 5Ah = DRC2 Left 5Bh = DRC2 Right 60h = LHPF1 61h = LHPF2 62h = LHPF3 63h = LHPF4 68h = DSP1 channel 1 69h = DSP1 channel 2 6Ah = DSP1 channel 3 6Bh = DSP1 channel 4 6Ch = DSP1 channel 5 6Dh = DSP1 channel 6 70h = DSP2 channel 1 71h = DSP2 channel 2 72h = DSP2 channel 3 73h = DSP2 channel 4 74h = DSP2 channel 5 75h = DSP2 channel 6 78h = DSP3 channel 1 79h = DSP3 channel 2 7Ah = DSP3 channel 3 7Bh = DSP3 channel 4 7Ch = DSP3 channel 5 7Dh = DSP3 channel 6 80h = DSP4 channel 1 81h = DSP4 channel 2 82h = DSP4 channel 3 83h = DSP4 channel 4 84h = DSP4 channel 5 85h = DSP4 channel 6 88h = DSP5 channel 1 89h = DSP5 channel 2 8Ah = DSP5 channel 3 8Bh = DSP5 channel 4 8Ch = DSP5 channel 5 8Dh = DSP5 channel 6 90h = ASRC1 IN1 Left 91h = ASRC1 IN1 Right 92h = ASRC1 IN2 Left 93h = ASRC1 IN2 Right 94h = ASRC2 IN1 Left 95h = ASRC2 IN1 Right 96h = ASRC2 IN2 Left 97h = ASRC2 IN2 Right A0h = ISRC1 INT1 72 Rev 4.2 CS47L85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION A1h = ISRC1 INT2 A2h = ISRC1 INT3 A3h = ISRC1 INT4 A4h = ISRC1 DEC1 A5h = ISRC1 DEC2 A6h = ISRC1 DEC3 A7h = ISRC1 DEC4 A8h = ISRC2 INT1 A9h = ISRC2 INT2 AAh = ISRC2 INT3 ABh = ISRC2 INT4 ACh = ISRC2 DEC1 ADh = ISRC2 DEC2 AEh = ISRC2 DEC3 AFh = ISRC2 DEC4 B0h = ISRC3 INT1 B1h = ISRC3 INT2 B4h = ISRC3 DEC1 B5h = ISRC3 DEC2 B8h = ISRC4 INT1 B9h = ISRC4 INT2 BCh = ISRC4 DEC1 BDh = ISRC4 DEC2 C0h = DSP6 channel 1 C1h = DSP6 channel 2 C2h = DSP6 channel 3 C3h = DSP6 channel 4 C4h = DSP6 channel 5 C5h = DSP6 channel 6 C8h = DSP7 channel 1 C9h = DSP7 channel 2 CAh = DSP7 channel 3 CBh = DSP7 channel 4 CCh = DSP7 channel 5 CDh = DSP7 channel 6 Table 8 Digital Core Mixer Control Registers Rev 4.2 73 CS47L85 DIGITAL CORE INPUTS The digital core comprises multiple input paths as illustrated in Figure 23. Any of these inputs may be selected as a source to the digital mixers or signal processing functions within the CS47L85 digital core. Note that the outputs from other blocks within the Digital Core may also be selected as input to the digital mixers or signal processing functions within the CS47L85 digital core. Those input sources, which are not shown in Figure 23, are described separately in other sections of the “Digital Core” description. The bracketed numbers in Figure 23, e.g.,”(10h)” indicate the corresponding *_SRCn register setting for selection of that signal as an input to another digital core function. The sample rate for the input signal paths is configured using the applicable IN_RATE, AIFn_RATE or SLIMRXn_RATE register - see Table 22. Note that sample rate conversion is required when routing the input signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. Silence (mute) (00h) AEC1 Loopback (08h) AEC2 Loopback (09h) IN1L signal path (10h) IN1R signal path (11h) IN2L signal path (12h) IN2R signal path (13h) IN3L signal path (14h) IN3R signal path (15h) IN4L signal path (16h) IN4R signal path (17h) IN5L signal path (18h) IN5R signal path (19h) IN6L signal path (1Ah) IN6R signal path (1Bh) AIF1 RX1 (20h) AIF1 RX2 (21h) AIF1 RX3 (22h) AIF1 RX4 (23h) AIF1 RX5 (24h) AIF1 RX6 (25h) AIF1 RX7 (26h) AIF1 RX8 (27h) AIF2 RX1 (28h) AIF2 RX2 (29h) AIF2 RX3 (2Ah) AIF2 RX4 (2Bh) AIF2 RX5 (2Ch) AIF2 RX6 (2Dh) AIF2 RX7 (2Eh) AIF2 RX8 (2Fh) AIF3 RX1 (30h) AIF3 RX2 (31h) AIF4 RX1 (34h) AIF4 RX2 (35h) SLIMbus RX1 (38h) SLIMbus RX2 (39h) SLIMbus RX3 (3Ah) SLIMbus RX4 (3Bh) SLIMbus RX5 (3Ch) SLIMbus RX6 (3Dh) SLIMbus RX7 (3Eh) SLIMbus RX8 (3Fh) Figure 23 Digital Core Inputs 74 Rev 4.2 CS47L85 DIGITAL CORE OUTPUT MIXERS The digital core comprises multiple output paths. The output paths associated with AIF1, AIF2, AIF3 and AIF4 are illustrated in Figure 24. The output paths associated with OUT1, OUT2, OUT3, OUT4, OUT5 and OUT6 are illustrated in Figure 25. The output paths associated with the SLIMbus interface are illustrated in Figure 26. A 4-input mixer is associated with each output. The 4 input sources are selectable in each case, and independent volume control is provided for each path. The AIF1, AIF2, AIF3 and AIF4 output mixer control registers (see Figure 24) are located at register addresses R1792 (700h) through to R1967 (7AEh). The OUT1, OUT2, OUT3, OUT4, OUT5 and OUT6 output mixer control registers (see Figure 25) are located at addresses R1664 (680h) through to R1759 (6DFh). The SLIMbus output mixer control registers (see Figure 26) are located at addresses R1984 (7C0h) through to R2047 (7FFh). The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see “Register Map” for further information. Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the respective mixers. Note that the selected input source(s) must be configured for the same sample rate as the mixer to which they are connected. Sample rate conversion functions are available to support flexible interconnectivity - see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”. The *_SRCn registers for all digital core functions should be held at 00h if SYSCLK is not enabled – SYSCLK must be present and enabled before selecting other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while digital core mixers are enabled). The sample rate for the output signal paths is configured using the applicable OUT_RATE, AIFn_RATE or SLIMTXn_RATE register - see Table 22. Note that sample rate conversion is required when routing the output signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. The OUT_RATE, AIFn_RATE or SLIMTXn_RATE registers should not be changed if any of the respective *_SRCn registers is non-zero. The associated *_SRCn registers should be cleared to 00h before writing new values to OUT_RATE, AIFn_RATE or SLIMTXn_RATE. A minimum delay of 125us should be allowed between clearing the *_SRCn registers and writing to the associated OUT_RATE, AIFn_RATE or SLIMTXn_RATE registers. See Table 22 for further details. The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the output mixer paths. If an attempt is made to enable an output mixer path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled. Rev 4.2 75 CS47L85 AIF1TXnMIX_SRC1 AIF1TXnMIX_SRC2 AIF1TXnMIX_VOL1 AIF1TXnMIX_VOL2 + AIF1 TXn AIF1TXnMIX_SRC3 AIF1TXnMIX_SRC4 AIF1TXnMIX_VOL3 AIF1TXnMIX_VOL4 CS47L85 supports 8 AIF1 Output mixers, ie. n = 1, 2, 3, 4, 5, 6, 7 or 8 AIF2TXnMIX_SRC1 AIF2TXnMIX_SRC2 AIF2TXnMIX_VOL1 AIF2TXnMIX_VOL2 + AIF2 TXn AIF2TXnMIX_SRC3 AIF2TXnMIX_SRC4 AIF2TXnMIX_VOL3 AIF2TXnMIX_VOL4 CS47L85 supports 8 AIF2 Output mixers, ie. n = 1, 2, 3, 4, 5, 6, 7 or 8 AIF3TXnMIX_SRC1 AIF3TXnMIX_SRC2 AIF3TXnMIX_VOL1 AIF3TXnMIX_VOL2 + AIF3 TXn AIF3TXnMIX_SRC3 AIF3TXnMIX_SRC4 AIF3TXnMIX_VOL3 AIF3TXnMIX_VOL4 CS47L85 supports 2 AIF3 Output mixers, ie. n = 1 or 2 AIF4TXnMIX_SRC1 AIF4TXnMIX_SRC2 AIF4TXnMIX_VOL1 AIF4TXnMIX_VOL2 + AIF4 TXn AIF4TXnMIX_SRC3 AIF4TXnMIX_SRC4 AIF4TXnMIX_VOL3 AIF4TXnMIX_VOL4 CS47L85 supports 2 AIF4 Output mixers, ie. n = 1 or 2 Figure 24 Digital Core AIF Outputs 76 Rev 4.2 CS47L85 OUTnLMIX_SRC1 OUTnLMIX_SRC2 OUTnLMIX_VOL1 OUTnLMIX_VOL2 + OUTn Left OUTnLMIX_SRC3 OUTnLMIX_SRC4 OUTnRMIX_SRC1 OUTnRMIX_SRC2 OUTnLMIX_VOL3 OUTnLMIX_VOL4 OUTnRMIX_VOL1 OUTnRMIX_VOL2 + OUTn Right OUTnRMIX_SRC3 OUTnRMIX_SRC4 OUTnRMIX_VOL3 OUTnRMIX_VOL4 CS47L85 supports 6 Stereo Output mixer pairs, ie. n = 1, 2, 3, 4, 5 or 6 Figure 25 Digital Core OUTn Outputs SLIMTXnMIX_SRC1 SLIMTXnMIX_SRC2 SLIMTXnMIX_VOL1 SLIMTXnMIX_VOL2 + SLIMbus TXn SLIMTXnMIX_SRC3 SLIMTXnMIX_SRC4 SLIMTXnMIX_VOL3 SLIMTXnMIX_VOL4 CS47L85 supports 8 SLIMbus output mixers, ie. n = 1, 2, 3, 4, 5, 6, 7 or 8 Figure 26 Digital Core SLIMbus Outputs Rev 4.2 77 CS47L85 5-BAND PARAMETRIC EQUALISER (EQ) The digital core provides four EQ processing blocks as illustrated in Figure 27. A 4-input mixer is associated with each EQ. The 4 input sources are selectable in each case, and independent volume control is provided for each path. Each EQ block supports 1 output. The EQ provides selective control of 5 frequency bands as described below. The low frequency band (Band 1) filter can be configured either as a peak filter or a shelving filter. When configured as a shelving filter, is provides adjustable gain below the Band 1 cut-off frequency. As a peak filter, it provides adjustable gain within a defined frequency band that is centred on the Band 1 frequency. The mid frequency bands (Band 2, Band 3, Band 4) filters are peak filters, which provide adjustable gain around the respective centre frequency. The high frequency band (Band 5) filter is a shelving filter, which provides adjustable gain above the Band 5 cut-off frequency. EQnMIX_SRC1 EQnMIX_SRC2 EQnMIX_SRC3 EQnMIX_SRC4 EQnMIX_VOL1 EQnMIX_VOL2 EQnMIX_VOL3 + EQ 5-band Equaliser EQ1 (50h) EQ2 (51h) EQ3 (52h) EQ4 (53h) EQnMIX_VOL4 CS47L85 supports 4 EQ blocks, ie. n = 1, 2, 3 or 4 Figure 27 Digital Core EQ Blocks The EQ1, EQ2, EQ3 and EQ4 mixer control registers (see Figure 27) are located at register addresses R2176 (880h) through to R2207 (89Fh). The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see “Register Map” for further information. Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the respective EQ processing blocks. Note that the selected input source(s) must be configured for the same sample rate as the EQ to which they are connected. Sample rate conversion functions are available to support flexible interconnectivity - see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”. The bracketed numbers in Figure 27, e.g.,”(50h)” indicate the corresponding *_SRCn register setting for selection of that signal as an input to another digital core function. The EQ blocks should be kept disabled (EQn_ENA=0) if SYSCLK is not enabled. The *_SRCn registers for all digital core functions should be held at 00h if SYSCLK is not enabled. SYSCLK must be present and enabled before selecting other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while digital core functions are enabled). The sample rate for the EQ function is configured using the FX_RATE register - see Table 22. Note that the EQ, DRC and LHPF functions must all be configured for the same sample rate. Sample rate conversion is required when routing the EQ signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. The FX_RATE register should not be changed if any of the associated *_SRCn registers is non-zero. The associated *_SRCn registers should be cleared to 00h before writing a new value to FX_RATE. A minimum delay of 125us should be allowed between clearing the *_SRCn registers and writing to the FX_RATE register. See Table 22 for further details. The control registers associated with the EQ functions are described in Table 10. The cut-off or centre frequencies for the 5-band EQ are set using the coefficients held in the registers identified in Table 9. These coefficients are derived using tools provided in Cirrus Logic’s WISCE™ evaluation board control software; please contact your local Cirrus Logic representative for more details. 78 Rev 4.2 CS47L85 EQ REGISTER ADDRESSES EQ1 R3602 (0E10h) to R3620 (0E24h) EQ2 R3624 (0E28h) to R3642 (0E3Ah) EQ3 R3646 (0E3Eh) to R3664 (0E53h) EQ4 R3668 (0E54h) to R3686 (0E66h) Table 9 EQ Coefficient Registers REGISTER ADDRESS R3585 (0E01h) FX_Ctrl2 BIT 15:4 LABEL FX_STS [11:0] DEFAULT 00h DESCRIPTION LHPF, DRC, EQ Enable Status Indicates the status of each of the respective signal processing functions. [11] = EQ4 [10] = EQ3 [9] = EQ2 [8] = EQ1 [7] = DRC2 (Right) [6] = DRC2 (Left) [5] = DRC1 (Right) [4] = DRC1 (Left) [3] = LHPF4 [2] = LHPF3 [1] = LHPF2 [0] = LHPF1 Each bit is coded as: 0 = Disabled 1 = Enabled R3600 (0E10h) EQ1_1 15:11 EQ1_B1_GAIN [4:0] 01100 EQ1 Band 1 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 10:6 EQ1_B2_GAIN [4:0] 01100 EQ1 Band 2 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 5:1 EQ1_B3_GAIN [4:0] 01100 EQ1 Band 3 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 0 R3601 (0E11h) EQ1_2 Rev 4.2 EQ1_ENA 0 EQ1 Enable 0 = Disabled 1 = Enabled 15:11 EQ1_B4_GAIN [4:0] 01100 EQ1 Band 4 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 10:6 EQ1_B5_GAIN [4:0] 01100 EQ1 Band 5 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 0 EQ1_B1_MODE 0 R3602 (0E12h) to R3620 (E24h) 15:0 EQ1_B1_* EQ1_B2_* EQ1_B3_* EQ1_B4_* EQ1_B5_* R3622 (0E26h) EQ2_1 15:11 EQ2_B1_GAIN [4:0] EQ1 Band 1 Mode 0 = Shelving filter 1 = Peak filter EQ1 Frequency Coefficients Refer to WISCE evaluation board control software for the derivation of these field values. 01100 EQ2 Band 1 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 79 CS47L85 REGISTER ADDRESS BIT DESCRIPTION EQ2_B2_GAIN [4:0] 01100 EQ2 Band 2 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 5:1 EQ2_B3_GAIN [4:0] 01100 EQ2 Band 3 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) EQ2_ENA 0 EQ2 Enable 0 = Disabled 1 = Enabled 15:11 EQ2_B4_GAIN [4:0] 01100 EQ2 Band 4 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 10:6 EQ2_B5_GAIN [4:0] 01100 EQ2 Band 5 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 0 EQ2_B1_MODE 0 EQ2 Band 1 Mode 0 = Shelving filter 1 = Peak filter R3624 (0E28h) to R3642 (E3Ah) 15:0 EQ2_B1_* EQ2_B2_* EQ2_B3_* EQ2_B4_* EQ2_B5_* R3644 (0E3Ch) EQ3_1 15:11 EQ3_B1_GAIN [4:0] 01100 EQ3 Band 1 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 10:6 EQ3_B2_GAIN [4:0] 01100 EQ3 Band 2 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 5:1 EQ3_B3_GAIN [4:0] 01100 EQ3 Band 3 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 0 R3645 (0E3Dh) EQ3_2 80 DEFAULT 10:6 0 R3623 (0E27h) EQ2_2 LABEL EQ3_ENA EQ2 Frequency Coefficients Refer to WISCE evaluation board control software for the deriviation of these field values. 0 EQ3 Enable 0 = Disabled 1 = Enabled 15:11 EQ3_B4_GAIN [4:0] 01100 EQ3 Band 4 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 10:6 EQ3_B5_GAIN [4:0] 01100 EQ3 Band 5 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 0 EQ3_B1_MODE 0 EQ3 Band 1 Mode 0 = Shelving filter 1 = Peak filter R3646 (0E3Eh) to R3664 (E50h) 15:0 EQ3_B1_* EQ3_B2_* EQ3_B3_* EQ3_B4_* EQ3_B5_* EQ3 Frequency Coefficients Refer to WISCE evaluation board control software for the derivation of these field values. R3666 (0E52h) EQ4_1 15:11 EQ4_B1_GAIN [4:0] 01100 EQ4 Band 1 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 10:6 EQ4_B2_GAIN [4:0] 01100 EQ4 Band 2 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) Rev 4.2 CS47L85 REGISTER ADDRESS BIT 5:1 0 R3667 (0E53h) EQ4_2 R3668 (0E54h) to R3686 (E66h) LABEL EQ4_B3_GAIN [4:0] EQ4_ENA DEFAULT 01100 DESCRIPTION EQ4 Band 3 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) EQ4 Enable 0 = Disabled 1 = Enabled 0 15:11 EQ4_B4_GAIN [4:0] 01100 EQ4 Band 4 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 10:6 EQ4_B5_GAIN [4:0] 01100 EQ4 Band 5 Gain -12dB to +12dB in 1dB steps (see Table 11 for gain range) 0 EQ4_B1_MODE 0 15:0 EQ4_B1_* EQ4_B2_* EQ4_B3_* EQ4_B4_* EQ4_B5_* EQ4 Band 1 Mode 0 = Shelving filter 1 = Peak filter EQ4 Frequency Coefficients Refer to WISCE evaluation board control software for the derivation of these field values. Table 10 EQ Enable and Gain Control EQ GAIN SETTING GAIN (dB) EQ GAIN SETTING GAIN (dB) 00000 -12 01101 +1 00001 -11 01110 +2 00010 -10 01111 +3 00011 -9 10000 +4 00100 -8 10001 +5 00101 -7 10010 +6 00110 -6 10011 +7 00111 -5 10100 +8 01000 -4 10101 +9 01001 -3 10110 +10 01010 -2 10111 +11 01011 -1 11000 +12 01100 0 11001 to 11111 Reserved Table 11 EQ Gain Control Range The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded EQ and digital mixing functions. If an attempt is made to enable an EQ signal path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The FX_STS field in Register R3585 indicates the status of each of the EQ, DRC and LHPF signal paths. If an Underclocked Error condition occurs, then this register provides readback of which EQ, DRC or LHPF signal path(s) have been successfully enabled. The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled. Rev 4.2 81 CS47L85 DYNAMIC RANGE CONTROL (DRC) The digital core provides two stereo Dynamic Range Control (DRC) processing blocks as illustrated in Figure 28. A 4-input mixer is associated with each DRC input channel. The 4 input sources are selectable in each case, and independent volume control is provided for each path. The stereo DRC blocks support 2 outputs each. The function of the DRC is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording from microphones built into a handheld system, or to restrict the dynamic range of an output signal path. The DRC can apply Compression and Automatic Level Control to the signal path. It incorporates ‘anti-clip’ and ‘quick release’ features for handling transients in order to improve intelligibility in the presence of loud impulsive noises. The DRC also incorporates a Noise Gate function, which provides additional attenuation of very low-level input signals. This means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these conditions. A Signal Detect function is provided within the DRC; this can be used to detect the presence of an audio signal, and used to trigger other events. The Signal Detect function can be used as an Interrupt event, or used to trigger the Control Write Sequencer (note - DRC1 only). DRCnLMIX_SRC1 DRCnLMIX_SRC2 DRCnLMIX_SRC3 DRCnLMIX_SRC4 DRCnRMIX_SRC1 DRCnRMIX_SRC2 DRCnRMIX_SRC3 DRCnRMIX_SRC4 DRCnLMIX_VOL1 DRCnLMIX_VOL2 + DRC Dynamic Range Controller DRCnLMIX_VOL3 DRC1 Left (58h) DRC2 Left (5Ah) DRCnLMIX_VOL4 DRCnRMIX_VOL1 DRCnRMIX_VOL2 + DRCnRMIX_VOL3 DRC Dynamic Range Controller DRC1 Right (59h) DRC2 Right (5Bh) DRCnRMIX_VOL4 CS47L85 supports 2 Stereo DRC blocks, ie. n = 1 or 2 Figure 28 Dynamic Range Control (DRC) Block The DRC1 and DRC2 mixer control registers (see Figure 28) are located at register addresses R2240 (8C0h) through to R2271 (08DFh). The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see “Register Map” for further information. Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the respective DRC processing blocks. Note that the selected input source(s) must be configured for the same sample rate as the DRC to which they are connected. Sample rate conversion functions are available to support flexible interconnectivity - see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”. The bracketed numbers in Figure 28, e.g.,”(58h)” indicate the corresponding *_SRCn register setting for selection of that signal as an input to another digital core function. The DRC blocks should be kept disabled (DRCnx_ENA=0) if SYSCLK is not enabled. The *_SRCn registers for all digital 82 Rev 4.2 CS47L85 core functions should be held at 00h if SYSCLK is not enabled. SYSCLK must be present and enabled before selecting other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while digital core functions are enabled). The sample rate for the DRC function is configured using the FX_RATE register - see Table 22. Note that the EQ, DRC and LHPF functions must all be configured for the same sample rate. Sample rate conversion is required when routing the DRC signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. The FX_RATE register should not be changed if any of the associated *_SRCn registers is non-zero. The associated *_SRCn registers should be cleared to 00h before writing a new value to FX_RATE. A minimum delay of 125us should be allowed between clearing the *_SRCn registers and writing to the FX_RATE register. See Table 22 for further details. The DRC functions are enabled using the control registers described in Table 12. REGISTER ADDRESS R3712 (0E80h) DRC1_ctrl1 R3720 (0E88h) DRC2_ctrl1 BIT LABEL DEFAULT DESCRIPTION 1 DRC1L_ENA 0 DRC1 (Left) Enable 0 = Disabled 1 = Enabled 0 DRC1R_ENA 0 DRC1 (Right) Enable 0 = Disabled 1 = Enabled 1 DRC2L_ENA 0 DRC2 (Left) Enable 0 = Disabled 1 = Enabled 0 DRC2R_ENA 0 DRC2 (Right) Enable 0 = Disabled 1 = Enabled Table 12 DRC Enable The following description of the DRC is applicable to each of the DRCs. The associated register control fields are described in Table 14 and Table 15 for DRC1 and DRC2 respectively. DRC COMPRESSION / EXPANSION / LIMITING The DRC supports two different compression regions, separated by a “Knee” at a specific input amplitude. In the region above the knee, the compression slope DRCn_HI_COMP applies; in the region below the knee, the compression slope DRCn_LO_COMP applies. (Note that ‘n’ identifies the applicable DRC 1 or 2.) The DRC also supports a noise gate region, where low-level input signals are heavily attenuated. This function can be enabled or disabled according to the application requirements. The DRC response in this region is defined by the expansion slope DRCn_NG_EXP. For additional attenuation of signals in the noise gate region, an additional “knee” can be defined (shown as “Knee2” in Figure 29). When this knee is enabled, this introduces an infinitely steep drop-off in the DRC response pattern between the DRCn_LO_COMP and DRCn_NG_EXP regions. The overall DRC compression characteristic in “steady state” (i.e. where the input amplitude is near-constant) is illustrated in Figure 29. Rev 4.2 83 CS47L85 DRCn Output Amplitude (dB) (Y0) Knee1 DRCn_KNEE_OP DRC DR _ Cn MP _ CO n_ HI P OM _C O L Knee2 DR Cn _N G_ EX P DRCn_KNEE2_OP DRCn_KNEE2_IP 0dB DRCn_KNEE_IP DRCn Input Amplitude (dB) Figure 29 DRC Response Characteristic The slope of the DRC response is determined by register fields DRCn_HI_COMP and DRCn_LO_COMP. A slope of 1 indicates constant gain in this region. A slope less than 1 represents compression (i.e. a change in input amplitude produces only a smaller change in output amplitude). A slope of 0 indicates that the target output amplitude is the same across a range of input amplitudes; this is infinite compression. When the noise gate is enabled, the DRC response in this region is determined by the DRCn_NG_EXP register. A slope of 1 indicates constant gain in this region. A slope greater than 1 represents expansion (i.e., a change in input amplitude produces a larger change in output amplitude). When the DRCn_KNEE2_OP knee is enabled (“Knee2” in Figure 29), this introduces the vertical line in the response pattern illustrated, resulting in infinitely steep attenuation at this point in the response. The DRC parameters are listed in Table 13. REF PARAMETER DESCRIPTION 1 DRCn_KNEE_IP Input level at Knee1 (dB) 2 DRCn_KNEE_OP Output level at Knee2 (dB) 3 DRCn_HI_COMP Compression ratio above Knee1 4 DRCn_LO_COMP Compression ratio below Knee1 5 DRCn_KNEE2_IP Input level at Knee2 (dB) 6 DRCn_NG_EXP Expansion ratio below Knee2 7 DRCn_KNEE2_OP Output level at Knee2 (dB) Table 13 DRC Response Parameters The noise gate is enabled when the DRCn_NG_ENA register is set. When the noise gate is not enabled, parameters 5, 6, 7 above are ignored, and the DRCn_LO_COMP slope applies to all input signal levels below Knee1. The DRCn_KNEE2_OP knee is enabled when the DRCn_KNEE2_OP_ENA register is set. When this bit is not set, then parameter 7 above is ignored, and the Knee2 position always coincides with the low end of the DRCn_LO_COMP region. The “Knee1” point in Figure 29 is determined by register fields DRCn_KNEE_IP and DRCn_KNEE_OP. Parameter Y0, the output level for a 0dB input, is not specified directly, but can be calculated from the other parameters, using the equation: Y0 = DRCn_KNEE_OP - (DRCn_KNEE_IP x DRCn_HI_COMP) 84 Rev 4.2 CS47L85 GAIN LIMITS The minimum and maximum gain applied by the DRC is set by register fields DRCn_MINGAIN, DRCn_MAXGAIN and DRCn_NG_MINGAIN. These limits can be used to alter the DRC response from that illustrated in Figure 29. If the range between maximum and minimum gain is reduced, then the extent of the dynamic range control is reduced. The minimum gain in the Compression regions of the DRC response is set by DRCn_MINGAIN. The mimimum gain in the Noise Gate region is set by DRCn_NG_MINGAIN. The minimum gain limit prevents excessive attenuation of the signal path. The maximum gain limit set by DRCn_MAXGAIN prevents quiet signals (or silence) from being excessively amplified. DYNAMIC CHARACTERISTICS The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note that the DRC responds to the average (RMS) signal amplitude over a period of time. The DRCn_ATK determines how quickly the DRC gain decreases when the signal amplitude is high. The DRCn_DCY determines how quickly the DRC gain increases when the signal amplitude is low. These register fields are described in Table 14. Note that the register defaults are suitable for general purpose microphone use. ANTI-CLIP CONTROL The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip feature is enabled using the DRCn_ANTICLIP bit. Note that the feed-forward processing increases the latency in the input signal path. Note that the Anti-Clip feature operates entirely in the digital domain. It cannot be used to prevent signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be prevented by reducing the analogue signal gain or by adjusting the source signal. QUICK RELEASE CONTROL The DRC includes a Quick-Release feature to handle short transient peaks that are not related to the intended source signal. For example, in handheld microphone recording, transient signal peaks sometimes occur due to user handling, key presses or accidental tapping against the microphone. The Quick Release feature ensures that these transients do not cause the intended signal to be masked by the longer time constant of DRCn_DCY. The Quick-Release feature is enabled by setting the DRCn_QR bit. When this bit is enabled, the DRC measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a transient peak that may not be related to the intended source signal. If the crest factor exceeds the level set by DRCn_QR_THR, then the normal decay rate (DRCn_DCY) is ignored and a faster decay rate (DRCn_QR_DCY) is used instead. Rev 4.2 85 CS47L85 SIGNAL ACTIVITY DETECT The DRC incorporates a configurable signal detect function, allowing the signal level at the DRC input to be monitored and to be used to trigger other events. This can be used to detect the presence of a microphone signal on an ADC or digital mic channel, or can be used to detect an audio signal received over the digital audio interface. The DRC Signal Detect function is enabled by setting DRCn_SIG_DET register bit. (Note that the respective DRCn must also be enabled.) The detection threshold is either a Peak level (Crest Factor) or an RMS level, depending on the DRCn_SIG_DET_MODE register bit. When Peak level is selected, the threshold is determined by DRCn_SIG_DET_PK, which defines the applicable Crest Factor (Peak to RMS ratio) threshold. If RMS level is selected, then the threshold is set using DRCn_SIG_DET_RMS. The DRC Signal Detect function is an input to the Interrupt control circuit and can be used to trigger an Interrupt event see “Interrupts”. The Control Write Sequencer can be triggered by the DRC1 Signal Detect function. This is enabled using the DRC1_WSEQ_SIG_DET_ENA register bit. See “Control Write Sequencer” for further details. Note that signal detection is supported on DRC1 and DRC2, but the triggering of the Control Write Sequencer is available on DRC1 only. DRC REGISTER CONTROLS The DRC control registers are described in Table 14 and Table 15 for DRC1 and DRC2 respectively. REGISTER ADDRESS R3585 (0E01h) FX_Ctrl2 BIT 15:4 LABEL FX_STS [11:0] DEFAULT 00h DESCRIPTION LHPF, DRC, EQ Enable Status Indicates the status of each of the respective signal processing functions. [11] = EQ4 [10] = EQ3 [9] = EQ2 [8] = EQ1 [7] = DRC2 (Right) [6] = DRC2 (Left) [5] = DRC1 (Right) [4] = DRC1 (Left) [3] = LHPF4 [2] = LHPF3 [1] = LHPF2 [0] = LHPF1 Each bit is coded as: 0 = Disabled 1 = Enabled R3712 (0E80h) DRC1_ctrl1 86 15:11 DRC1_SIG_DET _RMS [4:0] 00h DRC1 Signal Detect RMS Threshold. This is the RMS signal level for signal detect to be indicated when DRC1_SIG_DET_MODE=1. 00h = -30dB 01h = -31.5dB …. (1.5dB steps) 1Eh = -75dB 1Fh = -76.5dB Rev 4.2 CS47L85 REGISTER ADDRESS R3713 (0E81h) DRC1_ctrl2 Rev 4.2 BIT LABEL DEFAULT DESCRIPTION 10:9 DRC1_SIG_DET _PK [1:0] 00 DRC1 Signal Detect Peak Threshold. This is the Peak/RMS ratio, or Crest Factor, level for signal detect to be indicated when DRC1_SIG_DET_MODE=0. 00 = 12dB 01 = 18dB 10 = 24dB 11 = 30dB 8 DRC1_NG_ENA 0 DRC1 Noise Gate Enable 0 = Disabled 1 = Enabled 7 DRC1_SIG_DET _MODE 0 DRC1 Signal Detect Mode 0 = Peak threshold mode 1 = RMS threshold mode 6 DRC1_SIG_DET 0 DRC1 Signal Detect Enable 0 = Disabled 1 = Enabled 5 DRC1_KNEE2_ OP_ENA 0 DRC1 KNEE2_OP Enable 0 = Disabled 1 = Enabled 4 DRC1_QR 1 DRC1 Quick-release Enable 0 = Disabled 1 = Enabled 3 DRC1_ANTICLI P 1 DRC1 Anti-clip Enable 0 = Disabled 1 = Enabled 2 DRC1_WSEQ_S IG_DET_ENA 0 DRC1 Signal Detect Write Sequencer Select 0 = Disabled 1 = Enabled 12:9 DRC1_ATK [3:0] 0100 DRC1 Gain attack rate (seconds/6dB) 0000 = Reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100 to 1111 = Reserved 87 CS47L85 REGISTER ADDRESS R3714 (0E82h) DRC1_ctrl3 88 BIT LABEL DEFAULT DESCRIPTION 8:5 DRC1_DCY [3:0] 1001 DRC1 Gain decay rate (seconds/6dB) 0000 = 1.45ms 0001 = 2.9ms 0010 = 5.8ms 0011 = 11.6ms 0100 = 23.25ms 0101 = 46.5ms 0110 = 93ms 0111 = 186ms 1000 = 372ms 1001 = 743ms 1010 = 1.49s 1011 = 2.97s 1100 to1111 = Reserved 4:2 DRC1_MINGAIN [2:0] 100 DRC1 Minimum gain to attenuate audio signals 000 = 0dB 001 = -12dB 010 = -18dB 011 = -24dB 100 = -36dB 101 = Reserved 11X = Reserved 1:0 DRC1_MAXGAI N [1:0] 11 DRC1 Maximum gain to boost audio signals (dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 36dB 15:12 DRC1_NG_MIN GAIN [3:0] 0000 DRC1 Minimum gain to attenuate audio signals when the noise gate is active. 0000 = -36dB 0001 = -30dB 0010 = -24dB 0011 = -18dB 0100 = -12dB 0101 = -6dB 0110 = 0dB 0111 = 6dB 1000 = 12dB 1001 = 18dB 1010 = 24dB 1011 = 30dB 1100 = 36dB 1101 to 1111 = Reserved 11:10 DRC1_NG_EXP [1:0] 00 DRC1 Noise Gate slope 00 = 1 (no expansion) 01 = 2 10 = 4 11 = 8 9:8 DRC1_QR_THR [1:0] 00 DRC1 Quick-release threshold (crest factor in dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 30dB Rev 4.2 CS47L85 REGISTER ADDRESS R3715 (0E83h) DRC1_ctrl4 R3716 (0E84h) DRC1_ctrl5 Rev 4.2 BIT LABEL DEFAULT DESCRIPTION 7:6 DRC1_QR_DCY [1:0] 00 DRC1 Quick-release decay rate (seconds/6dB) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = Reserved 5:3 DRC1_HI_COM P [2:0] 011 DRC1 Compressor slope (upper region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = Reserved 111 = Reserved 2:0 DRC1_LO_COM P [2:0] 000 DRC1 Compressor slope (lower region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = Reserved 11X = Reserved 10:5 DRC1_KNEE_IP [5:0] 000000 DRC1 Input signal level at the Compressor ‘Knee’. 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB … (-0.75dB steps) 111100 = -45dB 111101 = Reserved 11111X = Reserved 4:0 DRC1_KNEE_O P [4:0] 00000 DRC1 Output signal at the Compressor ‘Knee’. 00000 = 0dB 00001 = -0.75dB 00010 = -1.5dB … (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved 9:5 DRC1_KNEE2_I P [4:0] 00000 DRC1 Input signal level at the Noise Gate threshold ‘Knee2’. 00000 = -36dB 00001 = -37.5dB 00010 = -39dB … (-1.5dB steps) 11110 = -81dB 11111 = -82.5dB Only applicable when DRC1_NG_ENA = 1. 89 CS47L85 REGISTER ADDRESS BIT 4:0 LABEL DRC1_KNEE2_ OP [4:0] DEFAULT 00000 DESCRIPTION DRC1 Output signal at the Noise Gate threshold ‘Knee2’. 00000 = -30dB 00001 = -31.5dB 00010 = -33dB … (-1.5dB steps) 11110 = -75dB 11111 = -76.5dB Only applicable when DRC1_KNEE2_OP_ENA = 1. Table 14 DRC1 Control Registers REGISTER ADDRESS R3585 (0E01h) FX_Ctrl2 BIT 15:4 LABEL FX_STS [11:0] DEFAULT 00h DESCRIPTION LHPF, DRC, EQ Enable Status Indicates the status of each of the respective signal processing functions. [11] = EQ4 [10] = EQ3 [9] = EQ2 [8] = EQ1 [7] = DRC2 (Right) [6] = DRC2 (Left) [5] = DRC1 (Right) [4] = DRC1 (Left) [3] = LHPF4 [2] = LHPF3 [1] = LHPF2 [0] = LHPF1 Each bit is coded as: 0 = Disabled 1 = Enabled R3720 (0E88h) DRC2_ctrl1 90 15:11 DRC2_SIG_DET _RMS [4:0] 00h DRC2 Signal Detect RMS Threshold. This is the RMS signal level for signal detect to be indicated when DRC2_SIG_DET_MODE=1. 00h = -30dB 01h = -31.5dB …. (1.5dB steps) 1Eh = -75dB 1Fh = -76.5dB 10:9 DRC2_SIG_DET _PK [1:0] 00 DRC2 Signal Detect Peak Threshold. This is the Peak/RMS ratio, or Crest Factor, level for signal detect to be indicated when DRC2_SIG_DET_MODE=0. 00 = 12dB 01 = 18dB 10 = 24dB 11 = 30dB 8 DRC2_NG_ENA 0 DRC2 Noise Gate Enable 0 = Disabled 1 = Enabled Rev 4.2 CS47L85 REGISTER ADDRESS R3721 (0E89h) DRC2_ctrl2 Rev 4.2 BIT LABEL DEFAULT DESCRIPTION 7 DRC2_SIG_DET _MODE 0 DRC2 Signal Detect Mode 0 = Peak threshold mode 1 = RMS threshold mode 6 DRC2_SIG_DET 0 DRC2 Signal Detect Enable 0 = Disabled 1 = Enabled 5 DRC2_KNEE2_ OP_ENA 0 DRC2 KNEE2_OP Enable 0 = Disabled 1 = Enabled 4 DRC2_QR 1 DRC2 Quick-release Enable 0 = Disabled 1 = Enabled 3 DRC2_ANTICLI P 1 DRC2 Anti-clip Enable 0 = Disabled 1 = Enabled 12:9 DRC2_ATK [3:0] 0100 DRC2 Gain attack rate (seconds/6dB) 0000 = Reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100 to 1111 = Reserved 8:5 DRC2_DCY [3:0] 1001 DRC2 Gain decay rate (seconds/6dB) 0000 = 1.45ms 0001 = 2.9ms 0010 = 5.8ms 0011 = 11.6ms 0100 = 23.25ms 0101 = 46.5ms 0110 = 93ms 0111 = 186ms 1000 = 372ms 1001 = 743ms 1010 = 1.49s 1011 = 2.97s 1100 to1111 = Reserved 4:2 DRC2_MINGAIN [2:0] 100 DRC2 Minimum gain to attenuate audio signals 000 = 0dB 001 = -12dB (default) 010 = -18dB 011 = -24dB 100 = -36dB 101 = Reserved 11X = Reserved 91 CS47L85 REGISTER ADDRESS R3722 (0E8Ah) DRC2_ctrl3 92 BIT LABEL DEFAULT DESCRIPTION 1:0 DRC2_MAXGAI N [1:0] 11 DRC2 Maximum gain to boost audio signals (dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 36dB 15:12 DRC2_NG_MIN GAIN [3:0] 0000 DRC2 Minimum gain to attenuate audio signals when the noise gate is active. 0000 = -36dB 0001 = -30dB 0010 = -24dB 0011 = -18dB 0100 = -12dB 0101 = -6dB 0110 = 0dB 0111 = 6dB 1000 = 12dB 1001 = 18dB 1010 = 24dB 1011 = 30dB 1100 = 36dB 1101 to 1111 = Reserved 11:10 DRC2_NG_EXP [1:0] 00 DRC2 Noise Gate slope 00 = 1 (no expansion) 01 = 2 10 = 4 11 = 8 9:8 DRC2_QR_THR [1:0] 00 DRC2 Quick-release threshold (crest factor in dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 30dB 7:6 DRC2_QR_DCY [1:0] 00 DRC2 Quick-release decay rate (seconds/6dB) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = Reserved 5:3 DRC2_HI_COM P [2:0] 011 DRC2 Compressor slope (upper region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = Reserved 111 = Reserved 2:0 DRC2_LO_COM P [2:0] 000 DRC2 Compressor slope (lower region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = Reserved 11X = Reserved Rev 4.2 CS47L85 REGISTER ADDRESS R3723 (0E8Bh) DRC2_ctrl4 R3724 (0E8Ch) DRC2_ctrl5 BIT LABEL DEFAULT DESCRIPTION 10:5 DRC2_KNEE_IP [5:0] 000000 DRC2 Input signal level at the Compressor ‘Knee’. 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB … (-0.75dB steps) 111100 = -45dB 111101 = Reserved 11111X = Reserved 4:0 DRC2_KNEE_O P [4:0] 00000 DRC2 Output signal at the Compressor ‘Knee’. 00000 = 0dB 00001 = -0.75dB 00010 = -1.5dB … (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved 9:5 DRC2_KNEE2_I P [4:0] 00000 DRC2 Input signal level at the Noise Gate threshold ‘Knee2’. 00000 = -36dB 00001 = -37.5dB 00010 = -39dB … (-1.5dB steps) 11110 = -81dB 11111 = -82.5dB Only applicable when DRC2_NG_ENA = 1. 4:0 DRC2_KNEE2_ OP [4:0] 00000 DRC2 Output signal at the Noise Gate threshold ‘Knee2’. 00000 = -30dB 00001 = -31.5dB 00010 = -33dB … (-1.5dB steps) 11110 = -75dB 11111 = -76.5dB Only applicable when DRC2_KNEE2_OP_ENA = 1. Table 15 DRC2 Control Registers The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded DRC and digital mixing functions. If an attempt is made to enable a DRC signal path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The FX_STS field in Register R3585 indicates the status of each of the EQ, DRC and LHPF signal paths. If an Underclocked Error condition occurs, then this register provides readback of which EQ, DRC or LHPF signal path(s) have been successfully enabled. The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled. Rev 4.2 93 CS47L85 LOW PASS / HIGH PASS DIGITAL FILTER (LHPF) The digital core provides four Low Pass Filter (LPF) / High Pass Filter (HPF) processing blocks as illustrated in Figure 30. A 4-input mixer is associated with each filter. The 4 input sources are selectable in each case, and independent volume control is provided for each path. Each Low/High Pass Filter (LHPF) block supports 1 output. The Low Pass Filter / High Pass Filter can be used to remove unwanted ‘out of band’ noise from a signal path. Each filter can be configured either as a Low Pass filter or High Pass filter. LHPFnMIX_SRC1 LHPFnMIX_SRC2 LHPFnMIX_SRC3 LHPFnMIX_SRC4 LHPFnMIX_VOL1 LHPFnMIX_VOL2 LHPFnMIX_VOL3 + LHPF Low-Pass filter (LPF) / High-Pass filter (HPF) LHPF1 (60h) LHPF2 (61h) LHPF3 (62h) LHPF4 (63h) LHPFnMIX_VOL4 CS47L85 supports 4 LHPF blocks, ie. n = 1, 2, 3 or 4 Figure 30 Digital Core LPF/HPF Blocks The LHPF1, LHPF2, LHPF3 and LHPF4 mixer control registers (see Figure 30) are located at register addresses R2304 (900h) through to R2335 (91Fh). The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see “Register Map” for further information. Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the respective LHPF processing blocks. Note that the selected input source(s) must be configured for the same sample rate as the LHPF to which they are connected. Sample rate conversion functions are available to support flexible interconnectivity - see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”. The bracketed numbers in Figure 30, e.g.,”(60h)” indicate the corresponding *_SRCn register setting for selection of that signal as an input to another digital core function. The LHPF blocks should be kept disabled (LHPFn_ENA=0) if SYSCLK is not enabled. The *_SRCn registers for all digital core functions should be held at 00h if SYSCLK is not enabled. SYSCLK must be present and enabled before selecting other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while digital core functions are enabled). The sample rate for the LHPF function is configured using the FX_RATE register - see Table 22. Note that the EQ, DRC and LHPF functions must all be configured for the same sample rate. Sample rate conversion is required when routing the LHPF signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. The FX_RATE register should not be changed if any of the associated *_SRCn registers is non-zero. The associated *_SRCn registers should be cleared to 00h before writing a new value to FX_RATE. A minimum delay of 125us should be allowed between clearing the *_SRCn registers and writing to the FX_RATE register. See Table 22 for further details. The control registers associated with the LHPF functions are described in Table 16. The cut-off frequencies for the LHPF blocks are set using the coefficients held in registers R3777, R3781, R3785 and R3789 for LHPF1, LHPF2, LHPF3 and LHPF4 respectively. These coefficients are derived using tools provided in Cirrus Logic’s WISCE evaluation board control software; please contact your local Cirrus Logic representative for more details. 94 Rev 4.2 CS47L85 REGISTER ADDRESS R3585 (0E01h) FX_Ctrl2 BIT 15:4 LABEL FX_STS [11:0] DEFAULT 00h DESCRIPTION LHPF, DRC, EQ Enable Status Indicates the status of each of the respective signal processing functions. [11] = EQ4 [10] = EQ3 [9] = EQ2 [8] = EQ1 [7] = DRC2 (Right) [6] = DRC2 (Left) [5] = DRC1 (Right) [4] = DRC1 (Left) [3] = LHPF4 [2] = LHPF3 [1] = LHPF2 [0] = LHPF1 Each bit is coded as: 0 = Disabled 1 = Enabled Rev 4.2 R3776 (0EC0h) HPLPF1_ 1 1 LHPF1_MODE 0 Low/High Pass Filter 1 Mode 0 = Low-Pass 1 = High-Pass 0 LHPF1_ENA 0 Low/High Pass Filter 1 Enable 0 = Disabled 1 = Enabled R3777 (0EC1h) HPLPF1_ 2 15:0 LHPF1_COEFF [15:0] 0000h R3780 (0EC4h) HPLPF2_ 1 1 LHPF2_MODE 0 Low/High Pass Filter 2 Mode 0 = Low-Pass 1 = High-Pass 0 LHPF2_ENA 0 Low/High Pass Filter 2 Enable 0 = Disabled 1 = Enabled R3781 (0EC5h) HPLPF2_ 2 15:0 LHPF2_COEFF [15:0] 0000h R3784 (0EC8h) HPLPF3_ 1 1 LHPF3_MODE 0 Low/High Pass Filter 3 Mode 0 = Low-Pass 1 = High-Pass 0 LHPF3_ENA 0 Low/High Pass Filter 3 Enable 0 = Disabled 1 = Enabled R3785 (0EC9h) HPLPF3_ 2 15:0 LHPF3_COEFF [15:0] 0000h R3788 (0ECCh) HPLPF4_ 1 1 LHPF4_MODE 0 Low/High Pass Filter 4 Mode 0 = Low-Pass 1 = High-Pass 0 LHPF4_ENA 0 Low/High Pass Filter 4 Enable 0 = Disabled 1 = Enabled Low/High Pass Filter 1 Frequency Coefficient Refer to WISCE evaluation board control software for the derivation of this field value. Low/High Pass Filter 2 Frequency Coefficient Refer to WISCE evaluation board control software for the derivation of this field value. Low/High Pass Filter 3 Frequency Coefficient Refer to WISCE evaluation board control software for the derivation of this field value. 95 CS47L85 REGISTER ADDRESS R3789 (0ECDh) HPLPF4_ 2 BIT 15:0 LABEL LHPF4_COEFF [15:0] DEFAULT 0000h DESCRIPTION Low/High Pass Filter 4 Frequency Coefficient Refer to WISCE evaluation board control software for the derivation of this field value. Table 16 Low Pass Filter / High Pass Filter Control The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded LHPF and digital mixing functions. If an attempt is made to enable an LHPF signal path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The FX_STS field in Register R3585 indicates the status of each of the EQ, DRC and LHPF signal paths. If an Underclocked Error condition occurs, then this register provides readback of which EQ, DRC or LHPF signal path(s) have been successfully enabled. The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled. DIGITAL CORE DSP The digital core provides seven programmable DSP processing blocks as illustrated in Figure 31. Each block supports 8 inputs (Left, Right, Aux1, Aux2, … Aux6). A 4-input mixer is associated with the Left and Right inputs, providing further expansion of the number of input paths. Each of the input sources is selectable, and independent volume control is provided for Left and Right input mixer channels. Each DSP block supports 6 outputs. The functionality of the DSP processing blocks is not fixed, and a wide range of audio enhancements algorithms may be performed. The procedure for configuring the CS47L85 DSP functions is tailored to each customer’s application; please contact your local Cirrus Logic representative for more details. For details of the DSP Firmware requirements relating to clocking, register access, and code execution, refer to the “DSP Firmware Control” section. DSPnLMIX_SRC1 DSPnLMIX_SRC2 DSPnLMIX_SRC3 DSPnLMIX_SRC4 DSPnLMIX_VOL1 DSPnLMIX_VOL2 + DSPn Channel 1 DSPnLMIX_VOL3 DSPn Channel 2 DSPnLMIX_VOL4 DSPn Channel 3 DSP DSPn Channel 4 DSP2 Outputs: (70h, 71h, 72h, 73h, 74h, 75h) DSP3 Outputs: (78h, 79h, 7Ah, 7Bh, 7Ch, 7Dh) DSP4 Outputs: (80h, 81h, 82h, 83h, 84h, 85h) DSPnRMIX_VOL3 DSP5 Outputs: (88h, 89h, 8Ah, 8Bh, 8Ch, 8Dh) DSPnAUX6_SRC DSPnAUX5_SRC DSPnRMIX_VOL4 DSPnAUX1_SRC DSPnRMIX_SRC4 + DSPnAUX4_SRC DSPnRMIX_SRC3 DSPn Channel 6 DSPnRMIX_VOL2 DSPnAUX3_SRC DSPnRMIX_SRC2 DSPn Channel 5 DSPnRMIX_VOL1 DSPnAUX2_SRC DSPnRMIX_SRC1 DSP1 Outputs: (68h, 69h, 6Ah, 6Bh, 6Ch, 6Dh) DSP6 Outputs: (C0h, C1h, C2h, C3h, C4h, C5h) DSP7 Output: (C8h, C9h, CAh, CBh, CCh, CDh) CS47L85 supports 7 DSP blocks, ie. n = 1, 2, 3, 4, 5, 6 or 7 Figure 31 Digital Core DSP Blocks 96 Rev 4.2 CS47L85 The DSPn mixer / input control registers (see Figure 31) are located at register addresses R2368 (940h) through to R2676 (A74h). The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see “Register Map” for further information. Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the respective DSP processing blocks. Note that the selected input source(s) must be configured for the same sample rate as the DSP to which they are connected. Sample rate conversion functions are available to support flexible interconnectivity - see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”. The bracketed numbers in Figure 31, e.g.,”(68h)” indicate the corresponding *_SRCn register setting for selection of that signal as an input to another digital core function. The *_SRCn registers for all digital core functions should be held at 00h if SYSCLK is not enabled – SYSCLK must be present and enabled before selecting other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while digital core mixers are enabled). The sample rate for each of the DSP functions is configured using the respective DSPn_RATE registers - see Table 22. Sample rate conversion is required when routing the DSPn signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. The DSPn_RATE registers should not be changed if any of the respective *_SRCn registers is non-zero. The associated *_SRCn registers should be cleared to 00h before writing new values to DSPn_RATE. A minimum delay of 125us should be allowed between clearing the *_SRCn registers and writing to the associated DSPn_RATE registers. See Table 22 for further details. The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded DSP mixing functions. If an attempt is made to enable a DSP mixer path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled. SPDIF OUTPUT GENERATOR The CS47L85 incorporates an IEC-60958-3 compatible S/PDIF output generator, as illustrated in Figure 32; this provides a stereo S/PDIF output on a GPIO pin. The S/PDIF transmitter allows full control over the S/PDIF validity bits and channel status information. The input sources to the S/PDIF transmitter are selectable for each channel, and independent volume control is provided for each path. The *TX1 and *TX2 registers control channels ‘A’ and ‘B’ (respectively) of the S/PDIF output. The S/PDIF signal can be output directly on a GPIO pin. See “General Purpose Input / Output” to configure a GPIO pin for this function. Note that the S/PDIF signal cannot be selected as input to the digital mixers or signal processing functions within the CS47L85 digital core. SPDIF1TX1_SRC Channel ‘A’ SPDIF1TX1_VOL S/PDIF SPDIF1TX2_SRC Channel ‘B’ SPDIF1TX2_VOL GPIO (GPn_FN = 4Ch) SPD1_ENA SPD1_RATE Figure 32 Digital Core S/PDIF Output Generator Rev 4.2 97 CS47L85 The S/PDIF input control registers (see Figure 32) are located at register addresses R2048 (800h) through to R2057 (809h). The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see “Register Map” for further information. Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the two S/PDIF channels. Note that the selected input source(s) must be synchronised to the SYSCLK clocking domain, and configured for the same sample rate as the S/PDIF generator. Sample rate conversion functions are available to support flexible interconnectivity - see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”. The S/PDIF output generator should be kept disabled (SPD1_ENA=0) if SYSCLK is not enabled. The *_SRCn registers for all digital core functions should be held at 00h if SYSCLK is not enabled. SYSCLK must be present and enabled before selecting other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while digital core functions are enabled). The sample rate of the S/PDIF generator is configured using the SPD1_RATE register - see Table 22. The S/PDIF transmitter supports sample rates in the range 32kHz up to 192kHz. Note that sample rate conversion is required when linking the S/PDIF generator to any signal chain that is asynchronous and/or configured for a different sample rate. The SPD1_RATE register should not be changed if any of the associated *_SRCn registers is non-zero. The associated *_SRCn registers should be cleared to 00h before writing new values to SPD1_RATE. A minimum delay of 125us should be allowed between clearing the *_SRCn registers and writing to the SPD1_RATE register. See Table 22 for further details. The S/PDIF generator is enabled using the SPD1_ENA register bit, as described in Table 17. The S/PDIF output contains audio data derived from the selected sources. Audio samples up to 24-bit width can be accommodated. The Validity bits and the Channel Status bits in the S/PDIF data are configured using the corresponding fields in registers R1474 (5C2h) to R1477 (5C5h). Refer to S/PDIF specification (IEC 60958-3) for full details of the S/PDIF protocol and configuration parameters. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1474 (05C2h) SPD1_TX_ Control 13 SPD1_VAL2 0 S/PDIF validity (Subframe B) 12 SPD1_VAL1 0 S/PDIF validity (Subframe A) 0 SPD1_ENA 0 S/PDIF Generator Enable 0 = Disabled 1 = Enabled R1475 (05C3h) SPD1_TX_ Channel_St atus_1 15:8 SPD1_CATCODE [7:0] 7:6 5:3 00h S/PDIF Category code SPD1_CHSTMODE [1:0] 00 S/PDIF Channel Status mode SPD1_PREEMPH [2:0] 000 S/PDIF Pre-emphasis mode 2 SPD1_NOCOPY 0 S/PDIF Copyright status 1 SPD1_NOAUDIO 0 S/PDIF Audio / Non-audio indication 0 SPD1_PRO 0 S/PDIF Consumer / Professional Mode R1476 (05C4h) SPD1_TX_ Channel_St atus_2 15:12 SPD1_FREQ [3:0] 0000 S/PDIF Indicated sample frequency 11:8 SPD1_CHNUM2 [3:0] 1011 S/PDIF Channel number (Subframe B) 7:4 SPD1_CHNUM1 [3:0] 0000 S/PDIF Channel number (Subframe A) 3:0 SPD1_SRCNUM [3:0] 0001 S/PDIF Source number R1477 (05C5h) SPD1_TX_ Channel_St atus_3 11:8 SPD1_ORGSAMP [3:0] 0000 S/PDIF Original sample frequency 7:5 SPD1_TXWL [2:0] 000 S/PDIF Audio sample word length SPD1_MAXWL 0 S/PDIF Maximum audio sample word length 3:2 SPD1_SC31_30 [1:0] 00 S/PDIF Channel Status [31:30] 1:0 SPD1_CLKACU [1:0] 00 Transmitted clock accuracy 4 Table 17 S/PDIF Output Generator Control The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the digital mixer paths. If an attempt is made to enable the SPDIF generator, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) 98 Rev 4.2 CS47L85 The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled. TONE GENERATOR The CS47L85 incorporates two 1kHz tone generators which can be used for ‘beep’ functions through any of the audio signal paths. The phase relationship between the two generators is configurable, providing flexibility in creating differential signals, or for test scenarios. 1kHz Tone Generator Tone Generator 1 (04h) Tone Generator 2 (05h) TONE1_ENA TONE2_ENA TONE_OFFSET TONE_RATE TONE1_OVD TONE1_LVL TONE2_OVD TONE2_LVL Figure 33 Digital Core Tone Generator The tone generators can be selected as input to any of the digital mixers or signal processing functions within the CS47L85 digital core. The bracketed numbers in Figure 33, e.g.,”(04h)” indicate the corresponding *_SRCn register setting for selection of that signal as an input to another digital core function. SYSCLK must be present and enabled before setting the TONEn_ENA bits. The tone generators should be kept disabled (TONEn_ENA=0) if SYSCLK is not enabled. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while digital core functions are enabled). The sample rate for the tone generators is configured using the TONE_RATE register - see Table 22. Note that sample rate conversion is required when routing the tone generator output(s) to any signal chain that is asynchronous and/or configured for a different sample rate. The tone generators are enabled using the TONE1_ENA and TONE2_ENA register bits as described in Table 18. The phase relationship is configured using TONE_OFFSET. The tone generators can also provide a configurable DC signal level, for use as a test signal. The DC output is selected using the TONEn_OVD register bits, and the DC signal amplitude is configured using the TONEn_LVL registers, as described in Table 18. REGISTER ADDRESS R32 (0020h) Tone_Gen erator_1 Rev 4.2 BIT LABEL DEFAULT DESCRIPTION TONE_OFFSET [1:0] 00 Tone Generator Phase Offset Sets the phase of Tone Generator 2 relative to Tone Generator 1 00 = 0 degrees (in phase) 01 = 90 degrees ahead 10 = 180 degrees ahead 11 = 270 degrees ahead 5 TONE2_OVD 0 Tone Generator 2 Override 0 = Disabled (1kHz tone output) 1 = Enabled (DC signal output) The DC signal level, when selected, is configured using TONE2_LVL[23:0] 4 TONE1_OVD 0 Tone Generator 1 Override 0 = Disabled (1kHz tone output) 1 = Enabled (DC signal output) The DC signal level, when selected, is configured using TONE1_LVL[23:0] 1 TONE2_ENA 0 Tone Generator 2 Enable 0 = Disabled 1 = Enabled 9:8 99 CS47L85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 TONE1_ENA 0 Tone Generator 1 Enable 0 = Disabled 1 = Enabled R33 (0021h) Tone_Gen erator_2 15:0 TONE1_LVL [23:8] 1000h Tone Generator 1 DC output level TONE1_LVL [23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. The digital core 0dBFS level corresponds to 1000_00h (+1) or F000_00h (-1). R34 (0022h) Tone_Gen erator_3 7:0 TONE1_LVL [7:0] 00h Tone Generator 1 DC output level TONE1_LVL [23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. The digital core 0dBFS level corresponds to 1000_00h (+1) or F000_00h (-1). R35 (0023h) Tone_Gen erator_4 15:0 TONE2_LVL [23:8] 1000h Tone Generator 2 DC output level TONE2_LVL [23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. The digital core 0dBFS level corresponds to 1000_00h (+1) or F000_00h (-1). R36 (0024h) Tone_Gen erator_5 7:0 TONE2_LVL [7:0] 00h Tone Generator 2 DC output level TONE2_LVL [23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. The digital core 0dBFS level corresponds to 1000_00h (+1) or F000_00h (-1). Table 18 Tone Generator Control NOISE GENERATOR The CS47L85 incorporates a white noise generator, which can be routed within the digital core. The main purpose of the noise generator is to provide ‘comfort noise’ in cases where silence (digital mute) is not desirable. White Noise Generator Noise Generator (0Dh) NOISE_GEN_ENA NOISE_GEN_GAIN NOISE_GEN_RATE Figure 34 Digital Core Noise Generator The noise generator can be selected as input to any of the digital mixers or signal processing functions within the CS47L85 digital core. The bracketed number (0Dh) in Figure 34 indicates the corresponding *_SRCn register setting for selection of the noise generator as an input to another digital core function. SYSCLK must be present and enabled before setting the NOISE_GEN_ENA bit. The noise generator should be kept disabled (NOISE_GEN_ENA=0) if SYSCLK is not enabled. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while digital core functions are enabled). The sample rate for the noise generator is configured using the NOISE_GEN_RATE register - see Table 22. Note that sample rate conversion is required when routing the noise generator output to any signal chain that is asynchronous 100 Rev 4.2 CS47L85 and/or configured for a different sample rate. The noise generator is enabled using the NOISE_GEN_ENA register bit as described in Table 19. The signal level is configured using NOISE_GEN_GAIN. REGISTER ADDRESS BIT LABEL DEFAULT R160 (00A0h) Comfort_N oise_Gene rator 5 NOISE_GEN_EN A 0 4:0 NOISE_GEN_GA IN [4:0] 00h DESCRIPTION Noise Generator Enable 0 = Disabled 1 = Enabled Noise Generator Signal Level 00h = -114dBFS 01h = -108dBFS 02h = -102dBFS …(6dB steps) 11h = -6dBFS 12h = 0dBFS All other codes are Reserved Table 19 Noise Generator Control HAPTIC SIGNAL GENERATOR The CS47L85 incorporates a signal generator for use with haptic devices (e.g., mechanical vibration actuators). The haptic signal generator is compatible with both Eccentric Rotating Mass (ERM) and Linear Resonant Actuator (LRA) haptic devices. The haptic signal generator is highly configurable, and includes the capability to execute a programmable event profile comprising three distinct operating phases. The resonant frequency of the haptic signal output (for LRA devices) is selectable, providing support for many different actuator components. The haptic signal generator is a digital signal generator which is incorporated within the digital core of the CS47L85. The haptic signal may be routed, via one of the digital core output mixers, to a Class D speaker output for connection to the external haptic device, as illustrated in Figure 35. (Note that the digital PDM output paths may also be used for haptic signal output.) Digital Core Output Mixer Haptic Signal Generator HAP_ACT HAP_CTRL ONESHOT_TRIG LRA_FREQ HAP_RATE + Haptic Output (06h) Output Volume DAC Class D Speaker Driver DAC Haptic Device OUTnxMIX_SRCn OUTnxMIX_VOLn Figure 35 Digital Core Haptic Signal Generator The bracketed number (06h) in Figure 35 indicates the corresponding *_SRCn register setting for selection of the haptic signal generator as an input to another digital core function. The haptic signal generator is selected as input to one of the digital core output mixers by setting the *_SRCn register of the applicable output mixer to (06h). SYSCLK must be present and enabled before setting HAP_CTRL>00. The haptic signal generator should be kept disabled (HAP_CTRL=00) if SYSCLK is not enabled. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while digital core functions are enabled). The sample rate for the haptic signal generator is configured using the HAP_RATE register - see Table 22. Note that sample rate conversion is required when routing the haptic signal generator output to any signal chain that is asynchronous and/or configured for a different sample rate. The haptic signal generator is configured for an ERM or LRA actuator using the HAP_ACT register bit. The required resonant frequency is configured using the LRA_FREQ field. (Note that the resonant frequency is only applicable to LRA actuators.) Rev 4.2 101 CS47L85 The signal generator can be enabled in Continuous mode or configured for One-Shot mode using the HAP_CTRL register, as described in Table 20. In One-Shot mode, the output is triggered by writing to the ONESHOT_TRIG bit. In One-Shot mode, the signal generator profile comprises the distinct phases (1, 2, 3). The duration and intensity of each output phase is programmable. In Continuous mode, the signal intensity is controlled using the PHASE2_INTENSITY field only. In the case of an ERM actuator (HAP_ACT = 0), the haptic output is a DC signal level, which may be positive or negative, as selected by the *_INTENSITY registers. For an LRA actuator (HAP_ACT = 1), the haptic output is an AC signal; selecting a negative signal level corresponds to a 180 degree phase inversion. In some applications, phase inversion may be desirable during the final phase, to halt the physical motion of the haptic device. REGISTER ADDRESS BIT R144 (0090h) Haptics_C ontrol_1 4 ONESHOT_TRIG 0 Haptic One-Shot Trigger Writing ‘1’ starts the one-shot profile (i.e., Phase 1, Phase 2, Phase 3) 3:2 HAP_CTRL [1:0] 00 Haptic Signal Generator Control 00 = Disabled 01 = Continuous 10 = One-Shot 11 = Reserved HAP_ACT 0 Haptic Actuator Select 0 = Eccentric Rotating Mass (ERM) 1 = Linear Resonant Actuator (LRA) 1 R145 (0091h) Haptics_C ontrol_2 14:0 LABEL LRA_FREQ [14:0] DEFAULT 7FFFh DESCRIPTION Haptic Resonant Frequency Selects the haptic signal frequency (LRA actuator only, HAP_ACT = 1) Haptic Frequency (Hz) = System Clock / (2 x (LRA_FREQ+1)) where System Clock = 6.144MHz or 5.6448MHz, derived by division from SYSCLK or ASYNCCLK. If HAP_RATE=1000, then ASYNCCLK is the clock source, and the applicable System Clock frequency is determined by ASYNCCLK. Valid for Haptic Frequency in the range 100Hz to 250Hz For 6.144MHz System Clock: 77FFh = 100Hz 4491h = 175Hz 2FFFh = 250Hz For 5.6448MHz System Clock: 6E3Fh = 100Hz 3EFFh = 175Hz 2C18h = 250Hz 102 Rev 4.2 CS47L85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R146 (0092h) Haptics_p hase_1_in tensity 7:0 PHASE1_INTEN SITY [7:0] 00h Haptic Output Level (Phase 1) Selects the signal intensity of Phase 1 in one-shot mode. Coded as 2’s complement. Range is +/- Full Scale (FS). For ERM actuator, this selects the DC signal level for the haptic output. For LRA actuator, this selects the AC peak amplitude; Negative values correspond to a 180 degree phase shift. R147 (0093h) Haptics_C ontrol_pha se_1_dura tion 8:0 PHASE1_DURAT ION [8:0] 000h Haptic Output Duration (Phase 1) Selects the duration of Phase 1 in oneshot mode. 000h = 0ms 001h = 0.625ms 002h = 1.25ms … (0.625ms steps) 1FFh = 319.375ms R148 (0094h) Haptics_p hase_2_in tensity 7:0 PHASE2_INTEN SITY [7:0] 00h Haptic Output Level (Phase 2) Selects the signal intensity in Continuous mode or Phase 2 of one-shot mode. Coded as 2’s complement. Range is +/- Full Scale (FS). For ERM actuator, this selects the DC signal level for the haptic output. For LRA actuator, this selects the AC peak amplitude; Negative values correspond to a 180 degree phase shift. R149 (0095h) Haptics_p hase_2_d uration 10:0 PHASE2_DURAT ION [10:0] 000h Haptic Output Duration (Phase 2) Selects the duration of Phase 2 in oneshot mode. 000h = 0ms 001h = 0.625ms 002h = 1.25ms … (0.625ms steps) 7FFh = 1279.375ms R150 (0096h) Haptics_p hase_3_in tensity 7:0 PHASE3_INTEN SITY [7:0] 00h Haptic Output Level (Phase 3) Selects the signal intensity of Phase 3 in one-shot mode. Coded as 2’s complement. Range is +/- Full Scale (FS). For ERM actuator, this selects the DC signal level for the haptic output. For LRA actuator, this selects the AC peak amplitude; Negative values correspond to a 180 degree phase shift. R151 (0097h) Haptics_p hase_3_d uration 8:0 PHASE3_DURAT ION [8:0] 000h Haptic Output Duration (Phase 3) Selects the duration of Phase 3 in oneshot mode. 000h = 0ms 001h = 0.625ms 002h = 1.25ms … (0.625ms steps) 1FFh = 319.375ms R152 (0098h) Haptics_St atus 0 ONESHOT_STS 0 Haptic One-Shot status 0 = One-Shot event not in progress 1 = One-Shot event in progress Table 20 Haptic Signal Generator Control Rev 4.2 103 CS47L85 PWM GENERATOR The CS47L85 incorporates two Pulse Width Modulation (PWM) signal generators as illustrated in Figure 36. The duty cycle of each PWM signal can be modulated by an audio source, or can be set to a fixed value using a control register setting. A 4-input mixer is associated with each PWM generator. The 4 input sources are selectable in each case, and independent volume control is provided for each path. The PWM signal generators can be output directly on a GPIO pin. See “General Purpose Input / Output” to configure a GPIO pin for this function. Note that the PWM signal generators cannot be selected as input to the digital mixers or signal processing functions within the CS47L85 digital core. When PWMn_OVD = 0, the PWM duty cycle is controlled by the respective digital audio mixer. When PWMn_OVD = 1, the PWM duty cycle is set by PWMn_LVL. The PWM sample rate and clocking frequency are selected using PWM_RATE and PWM_CLK_SEL. PWM1MIX_SRC1 PWM1MIX_SRC2 PWM1MIX_SRC3 PWM1MIX_SRC4 PWM1MIX_VOL1 PWM1MIX_VOL2 + PWM1 PWM1_ENA PWM1_OVD PWM1_LVL PWM1MIX_VOL3 GPIO (GPn_FN = 48h) PWM1MIX_VOL4 PWM_RATE PWM_CLK_SEL PWM2MIX_SRC1 PWM2MIX_SRC2 PWM2MIX_SRC3 PWM2MIX_SRC4 PWM2MIX_VOL1 PWM2MIX_VOL2 PWM2MIX_VOL3 + PWM2 PWM2_ENA PWM2_OVD PWM2_LVL GPIO (GPn_FN = 49h) PWM2MIX_VOL4 Figure 36 Digital Core Pulse Width Modulation (PWM) Generator The PWM1 and PWM2 mixer control registers (see Figure 36) are located at register addresses R1600 (640h) through to R1615 (64Fh). The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see “Register Map” for further information. Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the respective mixers. Note that the selected input source(s) must be configured for the same sample rate as the mixer to which they are connected. Sample rate conversion functions are available to support flexible interconnectivity - see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”. The PWM generators should be kept disabled (PWMn_ENA=0) if SYSCLK is not enabled. The *_SRCn registers for all digital core functions should be held at 00h if SYSCLK is not enabled. SYSCLK must be present and enabled before 104 Rev 4.2 CS47L85 selecting other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while digital core functions are enabled). The PWM sample rate (cycle time) is configured using the PWM_RATE register - see Table 22. Note that sample rate conversion is required when linking the PWM generators to any signal chain that is asynchronous and/or configured for a different sample rate. The PWM_RATE register should not be changed if any of the associated *_SRCn registers is non-zero. The associated *_SRCn registers should be cleared to 00h before writing a new value to PWM_RATE. A minimum delay of 125us should be allowed between clearing the *_SRCn registers and writing to the PWM_RATE register. See Table 22 for further details. The PWM generators are enabled using PWM1_ENA and PWM2_ENA respectively, as described in Table 21. Under default conditions (PWMn_OVD = 0), the duty cycle of the PWM generators is controlled by an audio signal path; a 4-input mixer is associated with each PWM generator, as illustrated in Figure 36. When the PWMn_OVD bit is set, the duty cycle of the respective PWM generator is set to a fixed ratio; in this case, the duty cycle ratio is configurable using the PWMn_LVL registers. The PWM generator clock frequency is selected using PWM_CLK_SEL. For best performance, this register should be set to the highest available setting. Note that the PWM generator clock must not be set to a higher frequency than SYSCLK (if PWM_RATE 002h Other GPIO functions DSPGPn_SET6_MASK Mask control DSPGPn_SET7_MASK Input / Output control Logic Level control DSPGPn_SET8_LVL DSPGPn_SET8_DIR DSP GPIO Readback DSPGPn_STS Input / Output control Logic Level control DSPGPn_SET7_LVL DSPGPn_SET7_DIR GPn_LVL Mask control Input / Output control Logic Level control DSPGPn_SET6_LVL DSPGPn_SET6_DIR GPIO Control & Readback Mask control Input / Output control Logic Level control DSPGPn_SET5_LVL DSPGPn_SET5_DIR GPn_FN = 000h GPn_FN = 001h Input / Output control Logic Level control DSPGPn_SET4_LVL DSPGPn_SET4_DIR Pin-Specific Function Mask control Mask control GPn_POL GPn_OP_CFG These bits have no effect if GPn_FN = 000h or 002h GPn_DB Valid for GPn_LVL readback and GPIO IRQ event trigger only GPn_DIR These bits have no effect if GPn_FN = 000h or 002h. Pin direction is set automatically if GPn_FN = 000h. Pin direction is set by DSPGPn_SETx_DIR if GPn_FN = 002h. DSPGPn_SET8_MASK Figure 45 DSP GPIO Control The control registers associated with the DSP GPIO are described in Table 36. 160 Rev 4.2 CS47L85 REGISTER ADDRESS R315392 (4D000h) DSPGP_Status_1 R315394 (4D002h) DSPGP_Status_2 R315424 (4D020h) DSPGP_SET1_Mask_1 BIT LABEL DEFAULT 31 DSPGP32_STS 0 DSPGP32 Status Valid for DSPGP input and output 30 DSPGP31_STS 0 DSPGP31 Status 29 DSPGP30_STS 0 DSPGP30 Status 28 DSPGP29_STS 0 DSPGP29 Status 27 DSPGP28_STS 0 DSPGP28 Status 26 DSPGP27_STS 0 DSPGP27 Status 25 DSPGP26_STS 0 DSPGP26 Status 24 DSPGP25_STS 0 DSPGP25 Status 23 DSPGP24_STS 0 DSPGP24 Status 22 DSPGP23_STS 0 DSPGP23 Status 21 DSPGP22_STS 0 DSPGP22 Status 20 DSPGP21_STS 0 DSPGP21 Status 19 DSPGP20_STS 0 DSPGP20 Status 18 DSPGP19_STS 0 DSPGP19 Status 17 DSPGP18_STS 0 DSPGP18 Status 16 DSPGP17_STS 0 DSPGP17 Status 15 DSPGP16_STS 0 DSPGP16 Status 14 DSPGP15_STS 0 DSPGP15 Status 13 DSPGP14_STS 0 DSPGP14 Status 12 DSPGP13_STS 0 DSPGP13 Status 11 DSPGP12_STS 0 DSPGP12 Status 10 DSPGP11_STS 0 DSPGP11 Status 9 DSPGP10_STS 0 DSPGP10 Status 8 DSPGP9_STS 0 DSPGP9 Status 7 DSPGP8_STS 0 DSPGP8 Status 6 DSPGP7_STS 0 DSPGP7 Status 5 DSPGP6_STS 0 DSPGP6 Status 4 DSPGP5_STS 0 DSPGP5 Status 3 DSPGP4_STS 0 DSPGP4 Status 2 DSPGP3_STS 0 DSPGP3 Status 1 DSPGP2_STS 0 DSPGP2 Status 0 DSPGP1_STS 0 DSPGP1 Status 7 DSPGP40_STS 0 DSPGP40 Status 6 DSPGP39_STS 0 DSPGP39 Status 5 DSPGP38_STS 0 DSPGP38 Status 4 DSPGP37_STS 0 DSPGP37 Status 3 DSPGP36_STS 0 DSPGP36 Status 2 DSPGP35_STS 0 DSPGP35 Status 1 DSPGP34_STS 0 DSPGP34 Status 0 DSPGP33_STS 0 DSPGP33 Status 31 DSPGP32_SETn_MASK 1 DSP SETn GPIO32 Mask Control 0 = Unmasked 1 = Masked A GPIO pin should be unmasked in a maximum of one SET at any time. 30 DSPGP31_SETn_MASK 1 DSP SETn GPIO31 Mask Control 29 DSPGP30_SETn_MASK 1 DSP SETn GPIO30 Mask Control 28 DSPGP29_SETn_MASK 1 DSP SETn GPIO29 Mask Control 27 DSPGP28_SETn_MASK 1 DSP SETn GPIO28 Mask Control 26 DSPGP27_SETn_MASK 1 DSP SETn GPIO27 Mask Control 25 DSPGP26_SETn_MASK 1 DSP SETn GPIO26 Mask Control 24 DSPGP25_SETn_MASK 1 DSP SETn GPIO25 Mask Control 23 DSPGP24_SETn_MASK 1 DSP SETn GPIO24 Mask Control R315456 (4D040h) DSPGP_SET2_Mask_1 R315488 (4D060h) DSPGP_SET3_Mask_1 R315520 (4D080h) DSPGP_SET4_Mask_1 R315552 (4D0A0h) DSPGP_SET5_Mask_1 Rev 4.2 DESCRIPTION 161 CS47L85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 22 DSPGP23_SETn_MASK 1 DSP SETn GPIO23 Mask Control 21 DSPGP22_SETn_MASK 1 DSP SETn GPIO22 Mask Control 20 DSPGP21_SETn_MASK 1 DSP SETn GPIO21 Mask Control 19 DSPGP20_SETn_MASK 1 DSP SETn GPIO20 Mask Control 18 DSPGP19_SETn_MASK 1 DSP SETn GPIO19 Mask Control 17 DSPGP18_SETn_MASK 1 DSP SETn GPIO18 Mask Control 16 DSPGP17_SETn_MASK 1 DSP SETn GPIO17 Mask Control 15 DSPGP16_SETn_MASK 1 DSP SETn GPIO16 Mask Control 14 DSPGP15_SETn_MASK 1 DSP SETn GPIO15 Mask Control 13 DSPGP14_SETn_MASK 1 DSP SETn GPIO14 Mask Control 12 DSPGP13_SETn_MASK 1 DSP SETn GPIO13 Mask Control 11 DSPGP12_SETn_MASK 1 DSP SETn GPIO12 Mask Control 10 DSPGP11_SETn_MASK 1 DSP SETn GPIO11 Mask Control 9 DSPGP10_SETn_MASK 1 DSP SETn GPIO10 Mask Control 8 DSPGP9_SETn_MASK 1 DSP SETn GPIO9 Mask Control 7 DSPGP8_SETn_MASK 1 DSP SETn GPIO8 Mask Control 6 DSPGP7_SETn_MASK 1 DSP SETn GPIO7 Mask Control 5 DSPGP6_SETn_MASK 1 DSP SETn GPIO6 Mask Control 4 DSPGP5_SETn_MASK 1 DSP SETn GPIO5 Mask Control 3 DSPGP4_SETn_MASK 1 DSP SETn GPIO4 Mask Control 2 DSPGP3_SETn_MASK 1 DSP SETn GPIO3 Mask Control 1 DSPGP2_SETn_MASK 1 DSP SETn GPIO2 Mask Control 0 DSPGP1_SETn_MASK 1 DSP SETn GPIO1 Mask Control 7 DSPGP40_SETn_MASK 1 DSP SETn GPIO40 Mask Control 6 DSPGP39_SETn_MASK 1 DSP SETn GPIO39 Mask Control 5 DSPGP38_SETn_MASK 1 DSP SETn GPIO38 Mask Control 4 DSPGP37_SETn_MASK 1 DSP SETn GPIO37 Mask Control 3 DSPGP36_SETn_MASK 1 DSP SETn GPIO36 Mask Control 2 DSPGP35_SETn_MASK 1 DSP SETn GPIO35 Mask Control 1 DSPGP34_SETn_MASK 1 DSP SETn GPIO34 Mask Control 0 DSPGP33_SETn_MASK 1 DSP SETn GPIO33 Mask Control R315432 (4D028h) DSPGP_SET1_Direction_1 31 DSPGP32_SETn_DIR 1 DSP SETn GPIO32 Direction Control 0 = Output 1 = Input R315464 (4D048h) DSPGP_SET2_Direction_1 30 DSPGP31_SETn_DIR 1 DSP SETn GPIO31 Direction Control 29 DSPGP30_SETn_DIR 1 DSP SETn GPIO30 Direction Control 28 DSPGP29_SETn_DIR 1 DSP SETn GPIO29 Direction Control 27 DSPGP28_SETn_DIR 1 DSP SETn GPIO28 Direction Control 26 DSPGP27_SETn_DIR 1 DSP SETn GPIO27 Direction Control 25 DSPGP26_SETn_DIR 1 DSP SETn GPIO26 Direction Control 24 DSPGP25_SETn_DIR 1 DSP SETn GPIO25 Direction Control R315584 (4D0C0h) DSPGP_SET6_Mask_1 R315616 (4D0E0h) DSPGP_SET7_Mask_1 R315648 (4D100h) DSPGP_SET8_Mask_1 R315426 (4D022h) DSPGP_SET1_Mask_2 R315458 (4D042h) DSPGP_SET2_Mask_2 R315490 (4D062h) DSPGP_SET3_Mask_2 R315522 (4D082h) DSPGP_SET4_Mask_2 R315554 (4D0A2h) DSPGP_SET5_Mask_2 R315586 (4D0C2h) DSPGP_SET6_Mask_2 R315618 (4D0E2h) DSPGP_SET7_Mask_2 R315650 (4D102h) DSPGP_SET8_Mask_2 R315496 (4D068h) DSPGP_SET3_Direction_1 R315528 (4D088h) 162 Rev 4.2 CS47L85 REGISTER ADDRESS DSPGP_SET4_Direction_1 BIT LABEL DEFAULT DESCRIPTION 23 DSPGP24_SETn_DIR 1 DSP SETn GPIO24 Direction Control 22 DSPGP23_SETn_DIR 1 DSP SETn GPIO23 Direction Control 21 DSPGP22_SETn_DIR 1 DSP SETn GPIO22 Direction Control 20 DSPGP21_SETn_DIR 1 DSP SETn GPIO21 Direction Control 19 DSPGP20_SETn_DIR 1 DSP SETn GPIO20 Direction Control 18 DSPGP19_SETn_DIR 1 DSP SETn GPIO19 Direction Control 17 DSPGP18_SETn_DIR 1 DSP SETn GPIO18 Direction Control 16 DSPGP17_SETn_DIR 1 DSP SETn GPIO17 Direction Control 15 DSPGP16_SETn_DIR 1 DSP SETn GPIO16 Direction Control 14 DSPGP15_SETn_DIR 1 DSP SETn GPIO15 Direction Control 13 DSPGP14_SETn_DIR 1 DSP SETn GPIO14 Direction Control 12 DSPGP13_SETn_DIR 1 DSP SETn GPIO13 Direction Control 11 DSPGP12_SETn_DIR 1 DSP SETn GPIO12 Direction Control 10 DSPGP11_SETn_DIR 1 DSP SETn GPIO11 Direction Control 9 DSPGP10_SETn_DIR 1 DSP SETn GPIO10 Direction Control 8 DSPGP9_SETn_DIR 1 DSP SETn GPIO9 Direction Control 7 DSPGP8_SETn_DIR 1 DSP SETn GPIO8 Direction Control 6 DSPGP7_SETn_DIR 1 DSP SETn GPIO7 Direction Control 5 DSPGP6_SETn_DIR 1 DSP SETn GPIO6 Direction Control 4 DSPGP5_SETn_DIR 1 DSP SETn GPIO5 Direction Control 3 DSPGP4_SETn_DIR 1 DSP SETn GPIO4 Direction Control 2 DSPGP3_SETn_DIR 1 DSP SETn GPIO3 Direction Control 1 DSPGP2_SETn_DIR 1 DSP SETn GPIO2 Direction Control 0 DSPGP1_SETn_DIR 1 DSP SETn GPIO1 Direction Control 7 DSPGP40_SETn_DIR 1 DSP SETn GPIO40 Direction Control 6 DSPGP39_SETn_DIR 1 DSP SETn GPIO39 Direction Control 5 DSPGP38_SETn_DIR 1 DSP SETn GPIO38 Direction Control 4 DSPGP37_SETn_DIR 1 DSP SETn GPIO37 Direction Control 3 DSPGP36_SETn_DIR 1 DSP SETn GPIO36 Direction Control 2 DSPGP35_SETn_DIR 1 DSP SETn GPIO35 Direction Control 1 DSPGP34_SETn_DIR 1 DSP SETn GPIO34 Direction Control 0 DSPGP33_SETn_DIR 1 DSP SETn GPIO33 Direction Control R315440 (4D030h) DSPGP_SET1_Level_ 31 DSPGP32_SETn_LVL 0 DSP SETn GPIO32 Output Level 0 = Logic 0 1 = Logic 1 R315472 (4D050h) DSPGP_SET2_Level_1 30 DSPGP31_SETn_LVL 0 DSP SETn GPIO31 Output Level 29 DSPGP30_SETn_LVL 0 DSP SETn GPIO30 Output Level 28 DSPGP29_SETn_LVL 0 DSP SETn GPIO29 Output Level 27 DSPGP28_SETn_LVL 0 DSP SETn GPIO28 Output Level 26 DSPGP27_SETn_LVL 0 DSP SETn GPIO27 Output Level 25 DSPGP26_SETn_LVL 0 DSP SETn GPIO26 Output Level R315560 (4D0A8h) DSPGP_SET5_Direction_1 R315592 (4D0C8h) DSPGP_SET6_Direction_1 R315624 (4D0E8h) DSPGP_SET7_Direction_1 R315656 (4D108h) DSPGP_SET8_Direction_1 R315434 (4D02Ah) DSPGP_SET1_Direction_2 R315466 (4D04Ah) DSPGP_SET2_Direction_2 R315498 (4D06Ah) DSPGP_SET3_Direction_2 R315530 (4D08Ah) DSPGP_SET4_Direction_2 R315562 (4D0AAh) DSPGP_SET5_Direction_2 R315594 (4D0CAh) DSPGP_SET6_Direction_2 R315626 (4D0EAh) DSPGP_SET7_Direction_2 R315658 (4D10Ah) DSPGP_SET8_Direction_2 R315504 (4D070h) DSPGP_SET3_Level_1 Rev 4.2 163 CS47L85 REGISTER ADDRESS R315536 (4D090h) DSPGP_SET4_Level_1 R315568 (4D0B0h) DSPGP_SET5_Level_1 R315600 (4D0D0h) DSPGP_SET6_Level_1 R315632 (4D0F0h) DSPGP_SET7_Level_1 R315664 (4D110h) DSPGP_SET8_Level_1 R315442 (4D032h) DSPGP_SET1_Level_2 R315474 (4D052h) DSPGP_SET2_Level_2 R315506 (4D072h) DSPGP_SET3_Level_2 BIT LABEL DEFAULT DESCRIPTION 24 DSPGP25_SETn_LVL 0 DSP SETn GPIO25 Output Level 23 DSPGP24_SETn_LVL 0 DSP SETn GPIO24 Output Level 22 DSPGP23_SETn_LVL 0 DSP SETn GPIO23 Output Level 21 DSPGP22_SETn_LVL 0 DSP SETn GPIO22 Output Level 20 DSPGP21_SETn_LVL 0 DSP SETn GPIO21 Output Level 19 DSPGP20_SETn_LVL 0 DSP SETn GPIO20 Output Level 18 DSPGP19_SETn_LVL 0 DSP SETn GPIO19 Output Level 17 DSPGP18_SETn_LVL 0 DSP SETn GPIO18 Output Level 16 DSPGP17_SETn_LVL 0 DSP SETn GPIO17 Output Level 15 DSPGP16_SETn_LVL 0 DSP SETn GPIO16 Output Level 14 DSPGP15_SETn_LVL 0 DSP SETn GPIO15 Output Level 13 DSPGP14_SETn_LVL 0 DSP SETn GPIO14 Output Level 12 DSPGP13_SETn_LVL 0 DSP SETn GPIO13 Output Level 11 DSPGP12_SETn_LVL 0 DSP SETn GPIO12 Output Level 10 DSPGP11_SETn_LVL 0 DSP SETn GPIO11 Output Level 9 DSPGP10_SETn_LVL 0 DSP SETn GPIO10 Output Level 8 DSPGP9_SETn_LVL 0 DSP SETn GPIO9 Output Level 7 DSPGP8_SETn_LVL 0 DSP SETn GPIO8 Output Level 6 DSPGP7_SETn_LVL 0 DSP SETn GPIO7 Output Level 5 DSPGP6_SETn_LVL 0 DSP SETn GPIO6 Output Level 4 DSPGP5_SETn_LVL 0 DSP SETn GPIO5 Output Level 3 DSPGP4_SETn_LVL 0 DSP SETn GPIO4 Output Level 2 DSPGP3_SETn_LVL 0 DSP SETn GPIO3 Output Level 1 DSPGP2_SETn_LVL 0 DSP SETn GPIO2 Output Level 0 DSPGP1_SETn_LVL 0 DSP SETn GPIO1 Output Level 7 DSPGP40_SETn_LVL 0 DSP SETn GPIO40 Output Level 6 DSPGP39_SETn_LVL 0 DSP SETn GPIO39 Output Level 5 DSPGP38_SETn_LVL 0 DSP SETn GPIO38 Output Level 4 DSPGP37_SETn_LVL 0 DSP SETn GPIO37 Output Level 3 DSPGP36_SETn_LVL 0 DSP SETn GPIO36 Output Level 2 DSPGP35_SETn_LVL 0 DSP SETn GPIO35 Output Level 1 DSPGP34_SETn_LVL 0 DSP SETn GPIO34 Output Level 0 DSPGP33_SETn_LVL 0 DSP SETn GPIO33 Output Level R315538 (4D092h) DSPGP_SET4_Level_2 R315570 (4D0B2h) DSPGP_SET5_Level_2 R315602 (4D0D2h) DSPGP_SET6_Level_2 R315634 (4D0F2h) DSPGP_SET7_Level_2 R315666 (4D112h) DSPGP_SET8_Level_2 Table 36 DSP GPIO Control 164 Rev 4.2 CS47L85 AMBIENT NOISE CANCELLATION The Cirrus Logic Ambient Noise Cancellation (ANC) processor within the CS47L85 provides the capability to improve the intelligibility of a voice call by using destructive interference to reduce the acoustic energy of the ambient sound. The stereo ANC capability supports a wide variety of headset/handset applications. The ANC processor is configured using parameters that are determined during product development and downloaded to the CS47L85. The configuration settings are specific to the acoustic properties of the target application. The primary acoustic elements in an application are typically the microphones and the speaker, but other components such as the plastics and the PCBs also have significant importance to the acoustic coefficient data. Note that the ANC configuration parameters are application-specific, and must be recalculated following any change in the design of the acoustic elements of that application. Any mismatch between the acoustic coefficient data and the target application will give inferior ANC performance. The signal path configuration settings are adjusted during product calibration to compensate for component tolerances. Also, calibration allows DC offsets in the earpiece output path to be measured and compensated, thus reducing power consumption and minimising any pops and clicks in the output signal path. The ANC processor employs stereo digital circuits to process the ambient noise (microphone) signals; the noise input paths (analogue or digital) are selected as described in Table 6. The selected sources are filtered and processed in accordance with the acoustic parameters programmed into the CS47L85. The resulting noise cancellation signals can be mixed with the output signal paths using the register bits described in Table 73. Noise cancellation is applied selectively to different audio frequency bands; a low frequency limiter ensures that the ANC algorithms deliver noise reduction in the most sensitive frequency bands, without introducing distortion in other frequency bands. The ANC processor is adaptive to different ambient noise levels in order to provide the most natural sound at the headphone audio output. The stereo ANC signal processing supports a very high level of noise cancellation capability for a wide variety of headset/handset applications. It also incorporates a noise gating function, which ensures that the noise cancellation performance is optimised across a wide range of input signal conditions. Note that the ANC configuration data is lost whenever the DCVDD power domain is removed; the ANC configuration data must be downloaded to the CS47L85 each time the device is powered up. The procedure for configuring the CS47L85 ANC functions is tailored to each customer’s application; please contact your local Cirrus Logic representative for more details. Rev 4.2 165 CS47L85 DIGITAL AUDIO INTERFACE The CS47L85 provides four audio interfaces, AIF1, AIF2, AIF3 and AIF4. Each of these is independently configurable on the respective transmit (TX) and receive (RX) paths. AIF1 and AIF2 support up to 8 channels of input and output signal paths; AIF3 and AIF4 support up to 2 channels of input and output signal paths. The data source(s) for the audio interface transmit (TX) paths can be selected from any of the CS47L85 input signal paths, or from the digital core processing functions. The audio interface receive (RX) paths can be selected as inputs to any of the digital core processing functions or digital core outputs. See “Digital Core” for details of the digital core routing options. The digital audio interfaces provide flexible connectivity for multiple processors and other audio devices. Typical connections include Applications Processor, Baseband Processor and Wireless Transceiver. Note that the SLIMbus interface also provides digital audio input/output paths, providing options for additional interfaces. A typical configuration is illustrated in Figure 46. The audio interfaces AIF1 and AIF2 are referenced to DBVDD1 and DBVDD2 respectively; interfaces AIF3 and AIF4 are referenced to DBVDD3. This enables the CS47L85 to connect easily between application sub-systems on different voltage domains. Applications Processor SLIMbus interface HDMI Device Audio Interface 1 Baseband Processor Audio Interface 2 Wireless Transceiver Audio Interface 3 CS47L85 Figure 46 Typical AIF Connections In the general case, the digital audio interface uses four pins:  TXDAT: Data output  RXDAT: Data input  BCLK: Bit clock, for synchronisation  LRCLK: Left/Right data alignment clock In master interface mode, the clock signals BCLK and LRCLK are outputs from the CS47L85. In slave mode, these signals are inputs, as illustrated below. 166 Rev 4.2 CS47L85 Four different audio data formats are supported by the digital audio interface:  DSP mode A  DSP mode B  I2S  Left Justified The Left Justified and DSP-B modes are valid in Master mode only (i.e., BCLK and LRCLK are outputs from the CS47L85). These modes cannot be supported in Slave mode. All four of these modes are MSB first. Data words are encoded in 2’s complement format. Each of the audio interface modes is described in the following sections. Refer to the “Signal Timing Requirements” section for timing information. Two variants of DSP mode are supported - ‘Mode A’ and ‘Mode B’. Mono PCM operation can be supported using the DSP modes. MASTER AND SLAVE MODE OPERATION The CS47L85 digital audio interfaces can operate as a master or slave as shown in Figure 47 and Figure 48. The associated control bits are described in “Digital Audio Interface Control”. BCLK BCLK LRCLK CS47L85 TXDAT RXDAT Figure 47 Master Mode LRCLK Processor CS47L85 TXDAT Processor RXDAT Figure 48 Slave Mode AUDIO DATA FORMATS The CS47L85 digital audio interfaces can be configured to operate in I2S, Left-Justified, DSP-A or DSP-B interface modes. Note that Left-Justified and DSP-B modes are valid in Master mode only (i.e., BCLK and LRCLK are outputs from the CS47L85). The digital audio interfaces also provide flexibility to support multiple ‘slots’ of audio data within each LRCLK frame. This flexibility allows multiple audio channels to be supported within a single LRCLK frame. The data formats described in this section are generic descriptions, assuming only one stereo pair of audio samples per LRCLK frame. In these cases, the AIF is configured to transmit (or receive) in the first available position in each frame (i.e., the Slot 0 position). The options for multi-channel operation are described in the following section (“AIF Timeslot Configuration”). The audio data modes supported by the CS47L85 are described below. Note that the polarity of the BCLK and LRCLK signals can be inverted if required; the following descriptions all assume the default, non-inverted polarity of these signals. In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK following a rising edge of LRCLK. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In master mode, the LRCLK output will resemble the frame pulse shown in Figure 49 and Figure 50. In slave mode, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs at least one BCLK period before the rising edge of the next frame pulse. Rev 4.2 167 CS47L85 1/fs LRCLK In Slave mode, the falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK LEFT CHANNEL RXDAT/ TXDAT 1 2 MSB 3 RIGHT CHANNEL n-2 n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 49 DSP Mode A Data Format 1/fs LRCLK In Slave mode, the falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK LEFT CHANNEL RXDAT/ TXDAT 1 2 MSB 3 n-2 RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 50 DSP Mode B Data Format PCM operation is supported in DSP interface mode. CS47L85 data that is output on the Left Channel will be read as mono PCM data by the receiving equipment. Mono PCM data received by the CS47L85 will be treated as Left Channel data. This data may be routed to the Left/Right playback paths using the control fields described in the “Digital Core” section. In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK 1 BCLK RXDAT/ TXDAT 1 MSB 2 1 BCLK 3 n-2 Input Word Length (WL) n-1 n 1 2 3 n-2 n-1 n LSB Figure 51 I2S Data Format (assuming n-bit word length) In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. 168 Rev 4.2 CS47L85 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK RXDAT/ TXDAT 1 MSB 2 3 n-2 n-1 Input Word Length (WL) n 1 2 3 n-2 n-1 n LSB Figure 52 Left Justified Data Format (assuming n-bit word length) AIF TIMESLOT CONFIGURATION Digital audio interfaces AIF1 and AIF2 support multi-channel operation, with up to 8 channels of input and output in each case. A high degree of flexibility is provided to define the position of the audio samples within each LRCLK frame; the audio channel samples may be arranged in any order within the frame. AIF3 and AIF4 also provide flexible configuration options, but these interfaces support only 1 stereo input and 1 stereo output path. Note that, on each interface, all input and output channels must operate at the same sample rate (fs). Each of the audio channels can be enabled or disabled independently on the transmit (TX) and receive (RX) signal paths. For each enabled channel, the audio samples are assigned to one timeslot within the LRCLK frame. In DSP modes, the timeslots are ordered consecutively from the start of the LRCLK frame. In I2S and Left-Justified modes, the even-numbered timeslots are arranged in the first half of the LRCLK frame, and the odd-numbered timeslots are arranged in the second half of the frame. The timeslots are assigned independently for the transmit (TX) and receive (RX) signal paths. There is no requirement to assign every available timeslot to an audio sample; some slots may be unused, if desired. Care is required, however, to ensure that no timeslot is allocated to more than one audio channel. The number of BCLK cycles within a slot is configurable; this is the Slot Length. The number of valid data bits within a slot is also configurable; this is the Word Length. The number of BCLK cycles per LRCLK frame must be configured; it must be ensured that there are enough BCLK cycles within each LRCLK frame to transmit or receive all of the enabled audio channels. Examples of the AIF Timeslot Configurations are illustrated in Figure 53 to Figure 56. One example is shown for each of the four possible data formats. Figure 53 shows an example of DSP Mode A format. Four enabled audio channels are shown, allocated to timeslots 0 through to 3. LRCLK BCLK TXDAT/ RXDAT Slot 0 Slot 1 Channel 1 Slot 0 AIF1[TX1/RX1]_SLOT = 0 Channel 2 Channel 3 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 ... AIF1[TX2/RX2]_SLOT = 1 Slot 2 Channel 4 AIF1[TX3/RX3]_SLOT = 2 Slot 3 AIF1[TX4/RX4]_SLOT = 3 Figure 53 DSP Mode A Example Rev 4.2 169 CS47L85 Figure 54 shows an example of DSP Mode B format. Six enabled audio channels are shown, with timeslots 4 and 5 unused. LRCLK BCLK TXDAT/ RXDAT Slot 0 Slot 1 Channel 1 Slot 2 Slot 3 Slot 2 AIF1[TX1/RX1]_SLOT = 2 Slot 3 Channel 2 Channel 3 Slot 0 Slot 5 Slot 6 Slot 7 ... AIF1[TX2/RX2]_SLOT = 3 AIF1[TX3/RX3]_SLOT = 0 Slot 1 Channel 4 Slot 4 AIF1[TX4/RX4]_SLOT = 1 Slot 6 Channel 5 AIF1[TX5/RX5]_SLOT = 6 Slot 7 Channel 6 AIF1[TX6/RX6]_SLOT = 7 Figure 54 DSP Mode B Example Figure 55 shows an example of I2S format. Four enabled channels are shown, allocated to timeslots 0 through to 3. LRCLK BCLK TXDAT/ RXDAT Slot 0 Slot 2 Channel 1 Slot 0 AIF1[TX1/RX1]_SLOT = 0 Slot 4 ... Channel 2 Channel 3 Slot 2 Channel 4 Slot 1 Slot 3 Slot 5 ... Slot 1 AIF1[TX2/RX2]_SLOT = 1 AIF1[TX3/RX3]_SLOT = 2 Slot 3 AIF1[TX4/RX4]_SLOT = 3 Figure 55 I2S Example 170 Rev 4.2 CS47L85 Figure 56 shows an example of Left Justified format. Six enabled channels are shown. LRCLK BCLK TXDAT/ RXDAT Slot 0 Slot 2 Slot 4 ... Slot 1 Slot 3 Slot 5 Channel 1 Slot 4 Channel 2 Slot 1 AIF1[TX4/RX4]_SLOT = 3 AIF1[TX5/RX5]_SLOT = 0 Slot 2 Channel 6 AIF1[TX1/RX1]_SLOT = 5 AIF1[TX3/RX3]_SLOT = 1 Slot 3 Channel 4 Slot 0 ... AIF1[TX2/RX2]_SLOT = 4 Channel 3 Channel 5 Slot 5 AIF1[TX6/RX6]_SLOT = 2 Figure 56 Left Justifed Example TDM OPERATION BETWEEN THREE OR MORE DEVICES The AIF operation described above illustrates how multiple audio channels can be interleaved on a single TXDAT or RXDAT pin. The interface uses Time Division Multiplexing (TDM) to allocate time periods to each of the audio channels in turn. This form of TDM is implemented between two devices, using the electrical connections illustrated in Figure 47 or Figure 48. It is also possible to implement TDM between three or more devices. This allows one CODEC to receive audio data from two other devices simultaneously on a single audio interface, as illustrated in Figure 57, Figure 58 and Figure 59. The CS47L85 provides full support for TDM operation. The TXDAT pin can be tri-stated when not transmitting data, in order to allow other devices to transmit on the same wire. The behaviour of the TXDAT pin is configurable, to allow maximum flexibility to interface with other devices in this way. Typical configurations of TDM operation between three devices are illustrated in Figure 57, Figure 58 and Figure 59. BCLK BCLK LRCLK CS47L85 LRCLK Processor CS47L85 TXDAT RXDAT RXDAT BCLK CS47L85 or similar CODEC LRCLK TXDAT RXDAT Figure 57 TDM with CS47L85 as Master Rev 4.2 Processor TXDAT BCLK CS47L85 or similar CODEC LRCLK TXDAT RXDAT Figure 58 TDM with Other CODEC as Master 171 CS47L85 BCLK LRCLK CS47L85 Processor TXDAT RXDAT BCLK CS47L85 or similar CODEC LRCLK TXDAT RXDAT Figure 59 TDM with Processor as Master Note: The CS47L85 is a 24-bit device. If the user operates the CS47L85 in 32-bit mode then the 8 LSBs will be ignored on the receiving side and not driven on the transmitting side. It is therefore recommended to add a pull-down resistor if necessary to the RXDAT line and the TXDAT line in TDM mode. 172 Rev 4.2 CS47L85 DIGITAL AUDIO INTERFACE CONTROL This section describes the configuration of the CS47L85 digital audio interface paths. AIF1 and AIF2 support up to 8 input signal paths and up to 8 output signal paths; AIF3 and AIF4 support up to 2 channels of input and output signal paths. The digital audio interfaces can be configured as Master or Slave interfaces; mixed master/slave configurations are also possible. Each input and output signal path can be independently enabled or disabled. The AIF output (TX) and AIF input (RX) paths use shared BCLK and LRCLK control signals. The digital audio interface supports flexible data formats, selectable word-length, configurable timeslot allocations and TDM tri-state control. The audio interfaces can be re-configured whilst enabled, including changes to the LRCLK frame length and the channel timeslot configurations. Care is required to ensure that any ‘on-the-fly’ re-configuration does not cause corruption to the active signal paths. Wherever possible, it is recommended to disable all channels before changing the AIF configuration. As noted in the applicable register descriptions, some of the AIF control fields are locked and cannot be updated whilst AIF channels are enabled; this is to ensure continuity of the respective BCLK and LRCLK signals. AIF SAMPLE RATE CONTROL The AIF RX inputs may be selected as input to the digital mixers or signal processing functions within the CS47L85 digital core. The AIF TX outputs are derived from the respective output mixers. The sample rate for each digital audio interface AIFn is configured using the respective AIFn_RATE register - see Table 22 within the “Digital Core” section. Note that sample rate conversion is required when routing the AIF paths to any signal chain that is asynchronous and/or configured for a different sample rate. AIF PIN CONFIGURATION The external connections associated with each digital audio interface (AIF) are implemented on multi-function GPIO pins, which must be configured for the respective AIF functions when required. The AIF connections are pin-specific alternative functions available on specific GPIO pins. See “General Purpose Input / Output” to configure the GPIO pins for AIF operation. Integrated pull-up and pull-down resistors can be enabled on the AIFnLRCLK, AIFnBCLK and AIFnRXDAT pins. This is provided as part of the GPIO functionality, and provides a flexible capability for interfacing with other devices. Each of the pull-up and pull-down resistors can be configured independently using the register bits described in Table 94. When the pull-up and pull-down resistors are both enabled, the CS47L85 provides a ‘bus keeper’ function on the respective pin. The bus keeper function holds the logic level unchanged whenever the pin is undriven (e.g., if the signal is tri-stated). Rev 4.2 173 CS47L85 AIF MASTER / SLAVE CONTROL The digital audio interfaces can operate in Master or Slave modes and also in mixed master/slave configurations. In Master mode, the BCLK and LRCLK signals are generated by the CS47L85 when any of the respective digital audio interface channels is enabled. In Slave mode, these outputs are disabled by default to allow another device to drive these pins. Master mode is selected on the AIFnBCLK pin using the AIFn_BCLK_MSTR register bit. In Master mode, the AIFnBCLK signal is generated by the CS47L85 when one or more AIFn channels is enabled. When the AIFn_BCLK_FRC bit is set in BCLK master mode, the AIFnBCLK signal is output at all times, including when none of the AIFn channels is enabled. The AIFn_BCLK_FRC bit should be held at 0 if SYSCLK is not enabled. SYSCLK must be present and enabled before setting the AIFn_BCLK_FRC bit. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while AIF clock signals are enabled). The AIFnBCLK signal can be inverted in Master or Slave modes using the AIFn_BCLK_INV register. Master mode is selected on the AIFnLRCLK pin using the AIFn_LRCLK_MSTR register bit. In Master mode, the AIFnLRCLK signal is generated by the CS47L85 when one or more AIFn channels is enabled. When the AIFn_LRCLK_FRC bit is set in LRCLK master mode, the AIFnLRCLK signal is output at all times, including when none of the AIFn channels is enabled. Note that AIFnLRCLK is derived from AIFnBCLK, and an internal or external AIFnBCLK signal must be present to generate AIFnLRCLK. The AIFn_LRCLK_FRC bit should be held at 0 if SYSCLK is not enabled. SYSCLK must be present and enabled before setting the AIFn_LRCLK_FRC bit. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring SYSCLK while AIF clock signals are enabled). The AIFnLRCLK signal can be inverted in Master or Slave modes using the AIFn_LRCLK_INV register. REGISTER ADDRESS BIT R1280 (0500h) AIF1_BCL K_Ctrl 7 AIF1_BCLK_INV 0 AIF1 Audio Interface BCLK Invert 0 = AIF1BCLK not inverted 1 = AIF1BCLK inverted This bit is locked when AIF1 channels are enabled; it can only be changed when all AIF1 channels are disabled. 6 AIF1_BCLK_FRC 0 AIF1 Audio Interface BCLK Output Control 0 = Normal 1 = AIF1BCLK always enabled in Master mode 5 AIF1_BCLK_MST R 0 AIF1 Audio Interface BCLK Master Select 0 = AIF1BCLK Slave mode 1 = AIF1BCLK Master mode This bit is locked when AIF1 channels are enabled; it can only be changed when all AIF1 channels are disabled. 2 AIF1_LRCLK_IN V 0 AIF1 Audio Interface LRCLK Invert 0 = AIF1LRCLK not inverted 1 = AIF1LRCLK inverted This bit is locked when AIF1 channels are enabled; it can only be changed when all AIF1 channels are disabled. 1 AIF1_LRCLK_FR C 0 AIF1 Audio Interface LRCLK Output Control 0 = Normal 1 = AIF1LRCLK always enabled in Master mode 0 AIF1_LRCLK_MS TR 0 AIF1 Audio Interface LRCLK Master Select 0 = AIF1LRCLK Slave mode 1 = AIF1LRCLK Master mode This bit is locked when AIF1 channels are enabled; it can only be changed when all AIF1 channels are disabled. R1282 (0502h) AIF1_Rx_ Pin_Ctrl LABEL DEFAULT DESCRIPTION Table 37 AIF1 Master / Slave Control 174 Rev 4.2 CS47L85 REGISTER ADDRESS BIT R1344 (0540h) AIF2_BCL K_Ctrl 7 AIF2_BCLK_INV 0 AIF2 Audio Interface BCLK Invert 0 = AIF2BCLK not inverted 1 = AIF2BCLK inverted This bit is locked when AIF2 channels are enabled; it can only be changed when all AIF2 channels are disabled. 6 AIF2_BCLK_FRC 0 AIF2 Audio Interface BCLK Output Control 0 = Normal 1 = AIF2BCLK always enabled in Master mode 5 AIF2_BCLK_MST R 0 AIF2 Audio Interface BCLK Master Select 0 = AIF2BCLK Slave mode 1 = AIF2BCLK Master mode This bit is locked when AIF2 channels are enabled; it can only be changed when all AIF2 channels are disabled. 2 AIF2_LRCLK_IN V 0 AIF2 Audio Interface LRCLK Invert 0 = AIF2LRCLK not inverted 1 = AIF2LRCLK inverted This bit is locked when AIF2 channels are enabled; it can only be changed when all AIF2 channels are disabled. 1 AIF2_LRCLK_FR C 0 AIF2 Audio Interface LRCLK Output Control 0 = Normal 1 = AIF2LRCLK always enabled in Master mode 0 AIF2_LRCLK_MS TR 0 AIF2 Audio Interface LRCLK Master Select 0 = AIF2LRCLK Slave mode 1 = AIF2LRCLK Master mode This bit is locked when AIF2 channels are enabled; it can only be changed when all AIF2 channels are disabled. R1346 (0542h) AIF2_Rx_ Pin_Ctrl LABEL DEFAULT DESCRIPTION Table 38 AIF2 Master / Slave Control Rev 4.2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1408 (0580h) AIF3_BCL K_Ctrl 7 AIF3_BCLK_INV 0 AIF3 Audio Interface BCLK Invert 0 = AIF3BCLK not inverted 1 = AIF3BCLK inverted This bit is locked when AIF3 channels are enabled; it can only be changed when all AIF3 channels are disabled. 6 AIF3_BCLK_FRC 0 AIF3 Audio Interface BCLK Output Control 0 = Normal 1 = AIF3BCLK always enabled in Master mode 5 AIF3_BCLK_MST R 0 AIF3 Audio Interface BCLK Master Select 0 = AIF3BCLK Slave mode 1 = AIF3BCLK Master mode This bit is locked when AIF3 channels are enabled; it can only be changed when all AIF3 channels are disabled. 175 CS47L85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1410 (0582h) AIF3_Rx_ Pin_Ctrl 2 AIF3_LRCLK_IN V 0 AIF3 Audio Interface LRCLK Invert 0 = AIF3LRCLK not inverted 1 = AIF3LRCLK inverted This bit is locked when AIF3 channels are enabled; it can only be changed when all AIF3 channels are disabled. 1 AIF3_LRCLK_FR C 0 AIF3 Audio Interface LRCLK Output Control 0 = Normal 1 = AIF3LRCLK always enabled in Master mode 0 AIF3_LRCLK_MS TR 0 AIF3 Audio Interface LRCLK Master Select 0 = AIF3LRCLK Slave mode 1 = AIF3LRCLK Master mode This bit is locked when AIF3 channels are enabled; it can only be changed when all AIF3 channels are disabled. Table 39 AIF3 Master / Slave Control REGISTER ADDRESS BIT R1440 (05A0h) AIF4_BCL K_Ctrl 7 AIF4_BCLK_INV 0 AIF43 Audio Interface BCLK Invert 0 = AIF4BCLK not inverted 1 = AIF4BCLK inverted This bit is locked when AIF4 channels are enabled; it can only be changed when all AIF4 channels are disabled. 6 AIF4_BCLK_FRC 0 AIF4 Audio Interface BCLK Output Control 0 = Normal 1 = AIF4BCLK always enabled in Master mode 5 AIF4_BCLK_MST R 0 AIF4 Audio Interface BCLK Master Select 0 = AIF4BCLK Slave mode 1 = AIF4BCLK Master mode This bit is locked when AIF4 channels are enabled; it can only be changed when all AIF4 channels are disabled. 2 AIF4_LRCLK_IN V 0 AIF4 Audio Interface LRCLK Invert 0 = AIF4LRCLK not inverted 1 = AIF4LRCLK inverted This bit is locked when AIF4 channels are enabled; it can only be changed when all AIF4 channels are disabled. 1 AIF4_LRCLK_FR C 0 AIF4 Audio Interface LRCLK Output Control 0 = Normal 1 = AIF4LRCLK always enabled in Master mode 0 AIF4_LRCLK_MS TR 0 AIF4 Audio Interface LRCLK Master Select 0 = AIF4LRCLK Slave mode 1 = AIF4LRCLK Master mode This bit is locked when AIF4 channels are enabled; it can only be changed when all AIF4 channels are disabled. R1442 (05A2h) AIF4_Rx_ Pin_Ctrl LABEL DEFAULT DESCRIPTION Table 40 AIF4 Master / Slave Control 176 Rev 4.2 CS47L85 AIF SIGNAL PATH ENABLE The AIF1 and AIF2 interfaces support up to 8 input (RX) channels and up to 8 output (TX) channels. Each of these channels can be enabled or disabled using the register bits defined in Table 41 and Table 42. The AIF3 and AIF4 interfaces support up to 2 input (RX) channels and up to 2 output (TX) channels. Each of these channels can be enabled or disabled using the register bits defined in Table 43 and Table 44. The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The AIF signal paths should be kept disabled (AIFnTXm_ENA=0, AIFnRXm_ENA=0) if SYSCLK is not enabled. The ASYNCCLK may also be required, depending on the path configuration. See “Clocking and Sample Rates” for details of the system clocks (including requirements for reconfiguring SYSCLK while audio paths are enabled). The audio interfaces can be re-configured whilst enabled, including changes to the LRCLK frame length and the channel timeslot configurations. Care is required to ensure that this ‘on-the-fly’ re-configuration does not cause corruption to the active signal paths. Wherever possible, it is recommended to disable all channels before changing the AIF configuration. As noted in the applicable register descriptions, some of the AIF control fields are locked and cannot be updated whilst AIF channels are enabled; this is to ensure continuity of the respective BCLK and LRCLK signals. The CS47L85 performs automatic checks to confirm that the SYSCLK and ASYNCCLK frequencies are high enough to support the commanded signal paths and processing functions. If an attempt is made to enable an AIF signal path, and there are insufficient SYSCLK or ASYNCCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) REGISTER ADDRESS BIT R1305 (0519h) AIF1_Tx_ Enables 7 AIF1TX8_ENA 0 AIF1 Audio Interface TX Channel 8 Enable 0 = Disabled 1 = Enabled 6 AIF1TX7_ENA 0 AIF1 Audio Interface TX Channel 7 Enable 0 = Disabled 1 = Enabled 5 AIF1TX6_ENA 0 AIF1 Audio Interface TX Channel 6 Enable 0 = Disabled 1 = Enabled 4 AIF1TX5_ENA 0 AIF1 Audio Interface TX Channel 5 Enable 0 = Disabled 1 = Enabled 3 AIF1TX4_ENA 0 AIF1 Audio Interface TX Channel 4 Enable 0 = Disabled 1 = Enabled 2 AIF1TX3_ENA 0 AIF1 Audio Interface TX Channel 3 Enable 0 = Disabled 1 = Enabled 1 AIF1TX2_ENA 0 AIF1 Audio Interface TX Channel 2 Enable 0 = Disabled 1 = Enabled 0 AIF1TX1_ENA 0 AIF1 Audio Interface TX Channel 1 Enable 0 = Disabled 1 = Enabled 7 AIF1RX8_ENA 0 AIF1 Audio Interface RX Channel 8 Enable 0 = Disabled 1 = Enabled R1306 (051Ah) AIF1_Rx_ Enables Rev 4.2 LABEL DEFAULT DESCRIPTION 177 CS47L85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 6 AIF1RX7_ENA 0 AIF1 Audio Interface RX Channel 7 Enable 0 = Disabled 1 = Enabled 5 AIF1RX6_ENA 0 AIF1 Audio Interface RX Channel 6 Enable 0 = Disabled 1 = Enabled 4 AIF1RX5_ENA 0 AIF1 Audio Interface RX Channel 5 Enable 0 = Disabled 1 = Enabled 3 AIF1RX4_ENA 0 AIF1 Audio Interface RX Channel 4 Enable 0 = Disabled 1 = Enabled 2 AIF1RX3_ENA 0 AIF1 Audio Interface RX Channel 3 Enable 0 = Disabled 1 = Enabled 1 AIF1RX2_ENA 0 AIF1 Audio Interface RX Channel 2 Enable 0 = Disabled 1 = Enabled 0 AIF1RX1_ENA 0 AIF1 Audio Interface RX Channel 1 Enable 0 = Disabled 1 = Enabled Table 41 AIF1 Signal Path Enable 178 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1369 (0559h) AIF2_Tx_ Enables 7 AIF2TX8_ENA 0 AIF2 Audio Interface TX Channel 8 Enable 0 = Disabled 1 = Enabled 6 AIF2TX7_ENA 0 AIF2 Audio Interface TX Channel 7 Enable 0 = Disabled 1 = Enabled 5 AIF2TX6_ENA 0 AIF2 Audio Interface TX Channel 6 Enable 0 = Disabled 1 = Enabled 4 AIF2TX5_ENA 0 AIF2 Audio Interface TX Channel 5 Enable 0 = Disabled 1 = Enabled 3 AIF2TX4_ENA 0 AIF2 Audio Interface TX Channel 4 Enable 0 = Disabled 1 = Enabled 2 AIF2TX3_ENA 0 AIF2 Audio Interface TX Channel 3 Enable 0 = Disabled 1 = Enabled Rev 4.2 CS47L85 REGISTER ADDRESS R1370 (055Ah) AIF2_Rx_ Enables BIT LABEL DEFAULT DESCRIPTION 1 AIF2TX2_ENA 0 AIF2 Audio Interface TX Channel 2 Enable 0 = Disabled 1 = Enabled 0 AIF2TX1_ENA 0 AIF2 Audio Interface TX Channel 1 Enable 0 = Disabled 1 = Enabled 7 AIF2RX8_ENA 0 AIF2 Audio Interface RX Channel 8 Enable 0 = Disabled 1 = Enabled 6 AIF2RX7_ENA 0 AIF2 Audio Interface RX Channel 7 Enable 0 = Disabled 1 = Enabled 5 AIF2RX6_ENA 0 AIF2 Audio Interface RX Channel 6 Enable 0 = Disabled 1 = Enabled 4 AIF2RX5_ENA 0 AIF2 Audio Interface RX Channel 5 Enable 0 = Disabled 1 = Enabled 3 AIF2RX4_ENA 0 AIF2 Audio Interface RX Channel 4 Enable 0 = Disabled 1 = Enabled 2 AIF2RX3_ENA 0 AIF2 Audio Interface RX Channel 3 Enable 0 = Disabled 1 = Enabled 1 AIF2RX2_ENA 0 AIF2 Audio Interface RX Channel 2 Enable 0 = Disabled 1 = Enabled 0 AIF2RX1_ENA 0 AIF2 Audio Interface RX Channel 1 Enable 0 = Disabled 1 = Enabled Table 42 AIF2 Signal Path Enable REGISTER ADDRESS BIT R1433 (0599h) AIF3_Tx_ Enables 1 AIF3TX2_ENA 0 AIF3 Audio Interface TX Channel 2 Enable 0 = Disabled 1 = Enabled 0 AIF3TX1_ENA 0 AIF3 Audio Interface TX Channel 1 Enable 0 = Disabled 1 = Enabled 1 AIF3RX2_ENA 0 AIF3 Audio Interface RX Channel 2 Enable 0 = Disabled 1 = Enabled R1434 (059Ah) AIF3_Rx_ Enables Rev 4.2 LABEL DEFAULT DESCRIPTION 179 CS47L85 REGISTER ADDRESS BIT 0 LABEL AIF3RX1_ENA DEFAULT 0 DESCRIPTION AIF3 Audio Interface RX Channel 1 Enable 0 = Disabled 1 = Enabled Table 43 AIF3 Signal Path Enable REGISTER ADDRESS BIT R1465 (05B9h) AIF4_Tx_ Enables 1 AIF4TX2_ENA 0 AIF4 Audio Interface TX Channel 2 Enable 0 = Disabled 1 = Enabled 0 AIF4TX1_ENA 0 AIF4 Audio Interface TX Channel 1 Enable 0 = Disabled 1 = Enabled 1 AIF4RX2_ENA 0 AIF4 Audio Interface RX Channel 2 Enable 0 = Disabled 1 = Enabled 0 AIF4RX1_ENA 0 AIF4 Audio Interface RX Channel 1 Enable 0 = Disabled 1 = Enabled R1466 (05BAh) AIF4_Rx_ Enables LABEL DEFAULT DESCRIPTION Table 44 AIF4 Signal Path Enable AIF BCLK AND LRCLK CONTROL The AIFnBCLK frequency is selected by the AIFn_BCLK_FREQ register. For each value of this register, the actual frequency depends upon whether AIFn is configured for a 48kHz-related sample rate or a 44.1kHz-related sample rate, as described below. If AIFn_RATE475 ohm detection [6] = Not used - must be set to 0 [5] = Not used - must be set to 0 [4] = Enable 375 ohm detection [3] = Enable 155 ohm detection [2] = Enable 73 ohm detection [1] = Enable 40 ohm detection [0] = Enable 18 ohm detection Note that the impedance values quoted assume that a microphone (475ohm30kohm) is also present on the MICDET pin. Only valid when ACCDET_MODE=000. R677 (02A5h) Mic_Detect_ 3 10:2 MICD_LVL [8:0] 0_0000_ 0000 Mic Detect Level (indicates the measured impedance) [8] = >475 ohm, 00)  PWM generator enabled (PWMn_ENA=1)  ASRC channel enabled (ASRCn_INmL_ENA=1, ASRCn_INmR_ENA=1)  ISRC channel enabled (ISRCn_INTm_ENA=1, ISRCn_DECm_ENA=1)  Digital audio interface path enabled (AIFnTXm_ENA=1, AIFnRXm_ENA=1)  Digital audio interface clocks enabled (AIFn_BCLK_FRC=1, AIFn_LRCLK_FRC=1)  SLIMbus framer mode enabled (note - only applies if SLIMCLK_SRC=0)  SLIMbus data channel enabled (SLIMTXn_ENA=1, SLIMRXn_ENA=1)  DSP Core firmware requires access to registers below 0x40000  Timer enabled, with SYSCLK as clock source (TIMERn_RUNNING_STS=1 and TIMERn_REFCLK_SRC=8h)  ANC processor enabled (CLK_L_ENA_SET=1, CLK_NG_ENA=1, CLK_R_ENA_SET=1)  OPCLK enabled for GPIO output (OPCLK_ENA=1) Rev 4.2 CS47L85 If reconfiguration of the SYSCLK source or frequency is required, and it is not possible to disable all of the SYSCLKdependent subsystems, then the Control Write Sequencer must be used for the reconfiguration of SYSCLK. The control sequence should apply the following actions:  Clear SYSCLK_ENA to 0  Write updates to SYSCLK_SRC, SYSCLK_FREQ, and SYSCLK_FRAC  Set SYSCLK_ENA to 1 The ASYNC_CLK_SRC register is used to select the ASYNCCLK source, as described in Table 105. The source may be MCLKn, AIFnBCLK or FLLn. If one of the Frequency Locked Loop (FLL) circuits is selected as the source, then the relevant FLL must be enabled and configured, as described later. The ASYNC_CLK_FREQ register is set according to the frequency of the selected ASYNCCLK source. Note that the FLLn output frequency is divided by three, when used as the ASYNCCLK source. The FLLs can support ASYNCCLK frequencies in the range 90MHz to 100MHz. The ASYNCCLK-referenced circuits within the digital core are clocked at a dynamically-controlled rate, limited by the ASYNCCLK frequency itself. For maximum signal mixing and processing capacity, it is recommended that the highest possible ASYNCCLK frequency is configured. The ASYNC_SAMPLE_RATE_n registers are set according to the sample rate(s) of any audio interface that is not synchronised to the SYSCLK clock domain. The ASYNCCLK signal is enabled by the register bit ASYNC_CLK_ENA. The applicable clock source (MCLKn, AIFnBCLK or FLLn) must be enabled before setting ASYNC_CLK_ENA=1. This bit must be cleared to 0 when reconfiguring the ASYNCCLK source or frequency. The ASYNC_CLK_ENA bit should also be cleared to 0 before stopping or removing the applicable clock source. The SYSCLK (and ASYNCCLK, when applicable) clocks must be configured and enabled before any audio path is enabled. The CS47L85 performs automatic checks to confirm that the SYSCLK and ASYNCCLK frequencies are high enough to support the commanded signal paths and processing functions. If an attempt is made to enable a signal path or processing function, and there are insufficient SYSCLK or ASYNCCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) DSPCLK CONTROL The DSPCLK clock may be provided directly from external inputs (MCLK, or slave mode BCLK inputs). Alternatively, DSPCLK can be derived using the integrated FLL(s), with MCLK, BCLK, LRCLK or SLIMCLK as a reference. Note that a configurable clock divider is provided for each DSP Core, allowing the DSP clocking (and power consumption) to be optimised according to the applicable processing requirements of each DSP Core. See “DSP Firmware Control” for further details. The DSP Cores are clocked at the DSPCLK rate (or supported divisions of the DSPCLK frequency). The DSPCLK configuration must ensure that sufficient clock cycles are available for the processing requirements of each DSP Core. The requirements will vary, according to the particular software that is in use. The DSP_CLK_SRC register is used to select the DSPCLK source, as described in Table 105. The source may be MCLKn, AIFnBCLK or FLLn. If one of the Frequency Locked Loop (FLL) circuits is selected as the source, then the relevant FLL must be enabled and configured, as described later. In most cases, the FLL output frequency is divided by two, when used as the DSPCLK source; this enables DSPCLK frequencies in the range 135MHz to 150MHz. For FLL1 only, a ‘divide by 6’ option is also available, supporting low power DSP operation with DSPCLK frequencies in the range 45MHz to 50MHz. The DSPCLK signal is enabled by the register bit DSP_CLK_ENA. The applicable clock source (MCLKn, AIFnBCLK or FLLn) must be enabled before setting DSP_CLK_ENA=1. This bit must be cleared to 0 when reconfiguring the clock sources. The DSP_CLK_FREQ_RANGE register must be configured for the applicable DSPCLK frequency. Note that, if the DSPCLK frequency is equal to one of the threshold frequencies quoted, then the higher range setting should be selected. For example, if the DSPCLK frequency is 37.5MHz, then DSP_CLK_FREQ_RANGE should be set to 011. In a typical application, DSPCLK and SYSCLK are derived from a single FLL source. In this case, one of the nominal DSPCLK frequencies is likely to be applicable (see Table 105). Note that there is no requirement for DSPCLK to be synchronised to SYSCLK or ASYNCCLK. The DSPCLK controls the Rev 4.2 291 CS47L85 software execution in the DSP Cores; audio outputs from the DSP Cores may be synchronised either to SYSCLK or ASYNCCLK, regardless of the applicable DSPCLK rate. The DSPCLK signal is the reference clock for the DSP cores and DSP peripherals on the CS47L85. All of the DSPCLKdependent functions should be disabled if DSPCLK is not enabled. The DSPCLK_ENA bit must be set to 1 before enabling any DSPCLK-dependent function, and all the dependent functions should be disabled before clearing the DSPCLK_ENA bit to 0. The DSPCLK-dependent subsystems are referenced below; if one or more of the following conditions is met, then the DSPCLK signal is required, and should not be interrupted or reconfigured.  DSP core enabled (DSPn_CORE_ENA=1)  DSP DMA function enabled (DSPn_[WDMA/RDMA]_CHANNEL_ENABLE>00h)  DSP core in JTAG mode  Master Interface active (MIFn_BUSY_STS=1)  Timer enabled (TIMERn_RUNNING_STS=1) If reconfiguration of the DSPCLK source or frequency is required, and it is not possible to disable all of the DSPCLKdependent functions, then the following control requirements must be applied to reconfigure DSPCLK:  Clear DSP_CLK_ENA to 0  Wait 34us (only required if a Timer is enabled)  Update DSP_CLK_SRC and DSP_CLK_FREQ_RANGE, and set DSP_CLK_ENA=1. (These must be applied in a single register write operation)  If a DSP core is enabled, DMA function is enabled, DSP core is in JTAG mode, or a Master Interface is active, then no other register read/write actions (either by Control Interface or by DSP firmware access) can be permitted during this control sequence.  If a Timer is enabled, but no DSP core, DMA, JTAG, or MIF is active, then DSPCLK can be stopped at any time. The minimum wait time of 34us is required before changing DSP_CLK_SRC or DSP_CLK_FREQ_RANGE, but there are no other constraints on configuring DSPCLK in these circumstances. If DSPCLK is the Timer clock source, the Timer pauses when DSPCLK stops, and resumes operation when DSPCLK restarts. If DSPCLK is not the clock source, the Timer operation continues when DSPCLK stops, but the Timer no longer synchronises to DSPCLK. MISCELLANEOUS CLOCK CONTROLS The CS47L85 incorporates a 32kHz clock circuit, which is required for input signal de-bounce, Microphone/Accessory detect, and for the Charge Pump 2 (CP2) circuits. The 32kHz clock must be configured and enabled whenever any of these features are in use. The 32kHz clock can be generated automatically from SYSCLK, or may be input directly as MCLK1 or MCLK2. The 32kHz clock source is selected using the CLK_32K_SRC register. The 32kHz clock is enabled using the CLK_32K_ENA register. A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. See “General Purpose Input / Output” to configure a GPIO pin for this function. A clock output (OPCLK_ASYNC) derived from ASYNCCLK can be output on a GPIO pin. See “General Purpose Input / Output” to configure a GPIO pin for this function. The CS47L85 provides integrated pull-down resistors on the MCLK1 and MCLK2 pins. This provides a flexible capability for interfacing with other devices. The clocking scheme for the CS47L85 is illustrated in Figure 74. 292 Rev 4.2 CS47L85 32k Clock CLK_32K_ENA CLK_32K_SRC Divider (Auto) OPCLK OPCLK_ENA Divider MCLK1 MCLK2 OPCLK_SEL OPCLK_DIV AIF1BCLK AIF2BCLK AIF3BCLK AIF4BCLK SYSCLK SYSCLK_ENA SYSCLK_SRC OPCLK_ASYNC OPCLK_ASYNC_ENA Divider OPCLK_ASYNC_SEL OPCLK_ASYNC_DIV ASYNCCLK ASYNC_CLK_ENA ASYNC_CLK_SRC Divide by 3 Divide by 3 Divide by 3 DSPCLK DSP_CLK_ENA DSP_CLK_SRC Divide by 2 Divide by 2 Divide by 2 Divide by 6 FLL1 GPIO Divider FLL1_GPCLK_ENA FLL1_GPCLK_DIV FLL1_REFCLK_SRC FLL2 GPIO Divider FLL2_GPCLK_ENA FLL2_GPCLK_DIV FLL2_REFCLK_SRC Automatic Clocking Control FLL3 GPIO Divider FLL3_GPCLK_ENA FLL3_REFCLK_SRC FLLn, AIFnLRCLK, and SLIMCLK can also be selected as FLLn input reference. FLL3_GPCLK_DIV SYSCLK_FREQ [2:0] SYSCLK_FRAC SAMPLE_RATE_1 [4:0] SAMPLE_RATE_2 [4:0] SAMPLE_RATE_3 [4:0] ASYNC_CLK_FREQ [2:0] ASYNC_SAMPLE_RATE_1 [4:0] ASYNC_SAMPLE_RATE_2 [4:0] DSP_CLK_FREQ_RANGE [2:0] Figure 74 System Clocking Rev 4.2 293 CS47L85 The CS47L85 clocking control registers are described in Table 105. REGISTER ADDRESS BIT R256 (0100h) Clock_32k _1 6 CLK_32K_ENA 0 32kHz Clock Enable 0 = Disabled 1 = Enabled 1:0 CLK_32K_SRC [1:0] 10 32kHz Clock Source 00 = MCLK1 (direct) 01 = MCLK2 (direct) 10 = SYSCLK (automatically divided) 11 = Reserved 15 SYSCLK_FRAC 0 SYSCLK Frequency 0 = SYSCLK is a multiple of 6.144MHz 1 = SYSCLK is a multiple of 5.6448MHz 10:8 SYSCLK_FREQ [2:0] 101 SYSCLK Frequency 000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) 100 = 98.304MHz (90.3168MHz) All other codes are Reserved The frequencies in brackets apply for 44.1kHz-related sample rates only (i.e., SAMPLE_RATE_n = 01XXX). R257 (0101h) System_Cl ock_1 294 LABEL DEFAULT 6 SYSCLK_ENA 0 3:0 SYSCLK_SRC [3:0] 0100 DESCRIPTION SYSCLK Control 0 = Disabled 1 = Enabled SYSCLK should only be enabled after the applicable clock source has been configured and enabled. Set this bit to 0 when reconfiguring the clock sources. All SYSCLK-dependent functions should be disabled before clearing SYSCLK_ENA=0. Specific control sequences must be followed if reconfiguring SYSCLK while dependent functions are enabled. SYSCLK Source 0000 = MCLK1 0001 = MCLK2 0100 = FLL1 0101 = FLL2 0110 = FLL3 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1011 = AIF4BCLK All other codes are Reserved Rev 4.2 CS47L85 REGISTER ADDRESS Rev 4.2 BIT LABEL DEFAULT DESCRIPTION R258 (0102h) Sample_ra te_1 4:0 SAMPLE_RATE_ 1 [4:0] 10001 Sample Rate 1 Select 00h = None 01h = 12kHz 02h = 24kHz 03h = 48kHz 04h = 96kHz 05h = 192kHz 09h = 11.025kHz 0Ah = 22.05kHz 0Bh = 44.1kHz 0Ch = 88.2kHz 0Dh = 176.4kHz 11h = 8kHz 12h = 16kHz 13h = 32kHz All other codes are Reserved R259 (0103h) Sample_ra te_2 4:0 SAMPLE_RATE_ 2 [4:0] 10001 Sample Rate 2 Select Register coding is same as SAMPLE_RATE_1. R260 (0104h) Sample_ra te_3 4:0 SAMPLE_RATE_ 3 [4:0] 10001 Sample Rate 3 Select Register coding is same as SAMPLE_RATE_1. R266 (010Ah) Sample_ra te_1_statu s 4:0 SAMPLE_RATE_ 1_STS [4:0] 00000 Sample Rate 1 Status (Read only) Register coding is same as SAMPLE_RATE_1. R267 (010Bh) Sample_ra te_2_statu s 4:0 SAMPLE_RATE_ 2_STS [4:0] 00000 Sample Rate 2 Status (Read only) Register coding is same as SAMPLE_RATE_1. R268 (010Ch) Sample_ra te_3_statu s 4:0 SAMPLE_RATE_ 3_STS [4:0] 00000 Sample Rate 3 Status (Read only) Register coding is same as SAMPLE_RATE_1. R274 (0112h) Async_clo ck_1 10:8 ASYNC_CLK_FR EQ [2:0] 011 6 ASYNC_CLK_EN A 0 ASYNCCLK Frequency 000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) 100 = 98.304MHz (90.3168MHz) All other codes are Reserved The frequencies in brackets apply for 44.1kHz-related sample rates only (i.e., ASYNC_SAMPLE_RATE_n = 01XXX). ASYNCCLK Control 0 = Disabled 1 = Enabled ASYNCCLK should only be enabled after the applicable clock source has been configured and enabled. Set this bit to 0 when reconfiguring the clock sources. 295 CS47L85 REGISTER ADDRESS 296 BIT LABEL DEFAULT DESCRIPTION 3:0 ASYNC_CLK_SR C [3:0] 0101 ASYNCCLK Source 0000 = MCLK1 0001 = MCLK2 0010 = Reserved 0011 = Reserved 0100 = FLL1 0101 = FLL2 0110 = FLL3 0111 = Reserved 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1011 = AIF4BCLK All other codes are Reserved R275 (0113h) Async_sa mple_rate _1 4:0 ASYNC_SAMPL E_RATE_1 [4:0] 10001 ASYNC Sample Rate 1 Select 00h = None 01h = 12kHz 02h = 24kHz 03h = 48kHz 04h = 96kHz 05h = 192kHz 09h = 11.025kHz 0Ah = 22.05kHz 0Bh = 44.1kHz 0Ch = 88.2kHz 0Dh = 176.4kHz 11h = 8kHz 12h = 16kHz 13h = 32kHz All other codes are Reserved R276 (0114h) Async_sa mple_rate _2 4:0 ASYNC_SAMPL E_RATE_2 [4:0] 10001 ASYNC Sample Rate 2 Select Register coding is same as ASYNC_SAMPLE_RATE_1. R283 (011Bh) Async_sa mple_rate _1_status 4:0 ASYNC_SAMPL E_RATE_1_STS [4:0] 00000 ASYNC Sample Rate 1 Status (Read only) Register coding is same as ASYNC_SAMPLE_RATE_1. R284 (011Ch) Async_sa mple_rate _2_status 4:0 ASYNC_SAMPL E_RATE_2_STS [4:0] 00000 ASYNC Sample Rate 2 Status (Read only) Register coding is same as ASYNC_SAMPLE_RATE_1. R288 (0120h) DSP_Cloc k_1 10:8 DSP_CLK_FREQ _RANGE [2:0] 000 DSPCLK Frequency 000=5.5MHz to 9.375MHz (9.216MHz) 001=9.375MHz to 18.75MHz (18.432MHz) 010=18.75MHz to 37.5MHz (36.864MHz) 011=37.5MHz to 75MHz (73.728MHz) 100=75MHz to 150MHz (147.456MHz) All other codes are Reserved The frequencies in brackets are the nominal (or typical) frequencies for each setting. If the DSPCLK frequency is equal to one of the threshold frequencies quoted (e.g., 37.5MHz), then the higher range setting (e.g., 011) should be selected. Rev 4.2 CS47L85 REGISTER ADDRESS R329 (0149h) Output_sy stem_cloc k R330 (014Ah) Output_as Rev 4.2 BIT LABEL DEFAULT DESCRIPTION 6 DSP_CLK_ENA 0 3:0 DSP_CLK_SRC [3:0] 0101 15 OPCLK_ENA 7:3 OPCLK_DIV [4:0] 00h OPCLK Divider 02h = Divide by 2 04h = Divide by 4 06h = Divide by 6 … (even numbers only) 1Eh = Divide by 30 Note that only even numbered divisions (2, 4, 6, etc.) are valid selections. All other codes are Reserved when the OPCLK signal is enabled. 2:0 OPCLK_SEL [2:0] 000 OPCLK Source Frequency 000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) All other codes are Reserved The frequencies in brackets apply for 44.1kHz-related SYSCLK rates only (i.e., SAMPLE_RATE_n = 01XXX). The OPCLK Source Frequency must be less than or equal to the SYSCLK frequency. 15 OPCLK_ASYNC_ ENA 0 0 DSPCLK Control 0 = Disabled 1 = Enabled DSPCLK should only be enabled after the applicable clock source has been configured and enabled. Set this bit to 0 when reconfiguring the clock sources. All DSPCLK-dependent functions should be disabled before clearing DSP_CLK_ENA=0. Specific control sequences must be followed if reconfiguring DSPCLK while dependent functions are enabled. DSPCLK Source 0000 = MCLK1 0001 = MCLK2 0100 = FLL1 0101 = FLL2 0110 = FLL3 0111 = FLL1 DIV6 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1011 = AIF4BCLK All other codes are Reserved OPCLK Enable 0 = Disabled 1 = Enabled OPCLK_ASYNC Enable 0 = Disabled 1 = Enabled 297 CS47L85 REGISTER ADDRESS ync_clock BIT DEFAULT DESCRIPTION 7:3 OPCLK_ASYNC_ DIV [4:0] 00h OPCLK_ASYNC Divider 02h = Divide by 2 04h = Divide by 4 06h = Divide by 6 … (even numbers only) 1Eh = Divide by 30 Note that only even numbered divisions (2, 4, 6, etc.) are valid selections. All other codes are Reserved when the OPCLK_ASYNC signal is enabled. 2:0 OPCLK_ASYNC_ SEL [2:0] 000 OPCLK_ASYNC Source Frequency 000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) All other codes are Reserved The frequencies in brackets apply for 44.1kHz-related ASYNCCLK rates only (i.e., ASYNC_SAMPLE_RATE_n = 01XXX). The OPCLK_ASYNC Source Frequency must be less than or equal to the ASYNCCLK frequency. R334 (014Eh) Clock_Ge n_Pad_Ctr l 8 MCLK2_PD 0 MCLK2 Pull-Down Control 0 = Disabled 1 = Enabled 7 MCLK1_PD 0 MCLK1 Pull-Down Control 0 = Disabled 1 = Enabled R338 (0152h) Rate_Esti mator_1 4 TRIG_ON_STAR TUP 0 Automatic Sample Rate Detection StartUp select 0 = Do not trigger Write Sequence on initial detection 1 = Always trigger the Write Sequencer on sample rate detection 000 Automatic Sample Rate Detection source 000 = AIF1LRCLK 001 = Reserved 010 = AIF2LRCLK 011 = Reserved 100 = AIF3LRCLK 101 = Reserved 110 = AIF4LRCLK 111 = Reserved 3:1 298 LABEL LRCLK_SRC [2:0] 0 RATE_EST_ENA 0 Automatic Sample Rate Detection control 0 = Disabled 1 = Enabled R339 (0153h) Rate_Esti mator_2 4:0 SAMPLE_RATE_ DETECT_A [4:0] 00h Automatic Detection Sample Rate A (Up to four different sample rates can be configured for automatic detection.) Register coding is same as SAMPLE_RATE_n. R340 (0154h) Rate_Esti mator_3 4:0 SAMPLE_RATE_ DETECT_B [4:0] 00h Automatic Detection Sample Rate B (Up to four different sample rates can be configured for automatic detection.) Register coding is same as SAMPLE_RATE_n. Rev 4.2 CS47L85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R341 (0155h) Rate_Esti mator_4 4:0 SAMPLE_RATE_ DETECT_C [4:0] 00h Automatic Detection Sample Rate C (Up to four different sample rates can be configured for automatic detection.) Register coding is same as SAMPLE_RATE_n. R342 (0156h) Rate_Esti mator_5 4:0 SAMPLE_RATE_ DETECT_D [4:0] 00h Automatic Detection Sample Rate D (Up to four different sample rates can be configured for automatic detection.) Register coding is same as SAMPLE_RATE_n. Table 105 Clocking Control In AIF Slave modes, it is important to ensure the applicable clock domain (SYSCLK or ASYNCCLK) is synchronised with the associated external LRCLK. This can be achieved by selecting an MCLK input that is derived from the same reference as the LRCLK, or can be achieved by selecting the external BCLK or LRCLK signal as a reference input to one of the FLLs, as a source for SYSCLK or ASYNCCLK. If the AIF clock domain is not synchronised with the LRCLK, then clicks arising from dropped or repeated audio samples will occur, due to the inherent tolerances of multiple, asynchronous, system clocks. See “Applications Information” for further details on valid clocking configurations. Rev 4.2 299 CS47L85 BCLK AND LRCLK CONTROL The digital audio interfaces (AIF1, AIF2, AIF3 and AIF4) use BCLK and LRCLK signals for synchronisation. In master mode, these are output signals, generated by the CS47L85. In slave mode, these are input signals to the CS47L85. It is also possible to support mixed master/slave operation. The BCLK and LRCLK signals are controlled as illustrated in Figure 75. See the “Digital Audio Interface Control” section for further details of the relevant control registers. Note that the BCLK and LRCLK signals are synchronised to SYSCLK or ASYNCLK, depending upon the applicable clocking domain for the respective interface. See “Digital Core” for further details. SYSCLK ASYNCCLK AIF1_BCLK_MSTR AIF1_LRCLK_MSTR AIF1_BCLK_FREQ [4:0] AIF1_BCPF [12:0] f/N (see note below) f/N MASTER MODE CLOCK OUTPUTS AIF1BCLK AIF1LRCLK AIF2_BCLK_MSTR AIF2_LRCLK_MSTR AIF2_BCLK_FREQ [4:0] AIF2_BCPF [12:0] f/N (see note below) f/N MASTER MODE CLOCK OUTPUTS AIF2BCLK AIF2LRCLK AIF3_BCLK_MSTR AIF3_LRCLK_MSTR AIF3_BCLK_FREQ [4:0] AIF3_BCPF [12:0] f/N (see note below) f/N MASTER MODE CLOCK OUTPUTS AIF3BCLK AIF3LRCLK AIF4_BCLK_MSTR AIF4_LRCLK_MSTR AIF4_BCLK_FREQ [4:0] AIF4_BCPF [12:0] f/N (see note below) f/N MASTER MODE CLOCK OUTPUTS AIF4BCLK AIF4LRCLK The clock reference for each AIF is SYSCLK or ASYNCCLK AIFn is clocked from SYSCLK if AIFn_RATE < 1000 AIFn is clocked from ASYNCCLK if AIFn_RATE >= 1000 Figure 75 BCLK and LRCLK Control CONTROL INTERFACE CLOCKING Register map access is possible with or without a system clock - there is no requirement for SYSCLK, or any other system clock, to be enabled when accessing the register map. See “Control Interface” for further details of control register access. 300 Rev 4.2 CS47L85 FREQUENCY LOCKED LOOP (FLL) Three integrated FLLs are provided to support the clocking requirements of the CS47L85. These can be enabled and configured independently according to the available reference clocks and the application requirements. The reference clock may be a high frequency (e.g., 12.288MHz) or low frequency (e.g., 32.768kHz). The FLL is tolerant of jitter and may be used to generate a stable output clock from a less stable input reference. The FLL characteristics are summarised in “Electrical Characteristics”. Note that the FLL can be used to generate a free-running clock in the absence of an external reference source. This is described in the “Free-Running FLL Mode” section below. Configurable spread-spectrum modulation can be applied to the FLL outputs, to control EMI effects. Each of the FLLs comprises two sub-systems - the ‘main’ loop and the ‘synchroniser’ loop; these can be used together to maintain best frequency accuracy and noise (jitter) performance across multiple use-cases. The two-loop design enables the FLL to synchronise effectively to an input clock that may be intermittent or noisy, whilst also achieving the performance benefits of a stable clock reference that may be asynchronous to the audio data. The main loop takes a constant and stable clock reference as its input. For best performance, a high frequency (e.g., 12.288MHz) reference is recommended. The main FLL loop will free-run without any clock reference if the input signal is removed; it can also be configured to initiate an output in the absence of any reference signal. The synchroniser loop takes a separate clock reference as its input. The synchroniser input may be intermittent (e.g., during voice calls only). The FLL uses the synchroniser input, when available, as the frequency reference. To achieve the designed performance advantage, the synchroniser input must be synchronous with the audio data. Note that, if only a single clock input reference is used, this must be configured as the main FLL input reference. The synchroniser should be disabled in this case. The synchroniser loop should only be used when the main loop clock reference is present. If the input reference to the main FLL is intermittent, or may be interrupted unexpectedly, then the synchroniser should be disabled. The FLL is enabled using the FLLn_ENA register bit (where n = 1, 2 or 3 for the corresponding FLL). The FLL Synchroniser is enabled using the FLLn_SYNC_ENA register bit. Note that the other FLL registers should be configured before enabling the FLL; the FLLn_ENA bit should be set as the final step of the FLLn enable sequence. The FLL_SYNC_ENA bit should not be changed if FLLn_ENA = 1; the FLLn_ENA bit should be cleared before changing FLLn_SYNC_ENA. The FLL supports configurable free-running operation, using the FLLn_FREERUN register bits described in the next section. Note that, once the FLL output has been established, the FLL will always free-run when the input reference clock is stopped, regardless of the FLLn_FREERUN bits. To disable the FLL while the input reference clock has stopped, the respective FLLn_FREERUN bit must be set to ‘1’, before setting the FLLn_ENA bit to ‘0’. When changing any of the FLL configuration fields, it is recommended that the digital circuit be disabled via FLLn_ENA and then re-enabled after the other register settings have been updated. If the FLL configuration is changed while the FLL is enabled, the respective FLLn_FREERUN bit should be set before updating any other FLL fields. A minimum delay of 32µs should be allowed between setting FLLn_FREERUN and writing to the required FLL register fields. The FLLn_FREERUN bit should remain set until after the FLL has been reconfigured. Note that, if the FLLn_N or FLLn_THETA fields are changed while the FLL is enabled, the FLLn_CTRL_UPD bit must also be written, as described below. As a general rule, however, it is recommended to configure the FLL (and FLL Synchroniser, if applicable), before setting the corresponding _ENA register bit(s). The FLL configuration requirements are illustrated in Figure 76. Rev 4.2 301 CS47L85 Main FLL path MCLK1 MCLK2 Divide by FLLn_REFCLK_DIV FLLn, AIFnBCLK, AIFnLRCLK FREF Multiply by N.K x3 Divide by 1, 2, 4 or 8 FLLn_REFCLK_SRC FLLn_ENA (FLL Enable) Multiply by FLLn_FRATIO FOUT (SYSCLK, ASYNCCLK) Divide by 3 Multiply by 1, 2, 3 … 16 FREF < 13.5MHz FOUT (DSPCLK) Divide by 2 FVCO (270MHz ≤ Fvco ≤ 300MHz) FLL Synchroniser path Divide by FLLn_SYNCCLK_DIV FSYNC Multiply by N.K (Sync) x3 Divide by 1, 2, 4 or 8 SLIMCLK FLLn_SYNCCLK_SRC Automatic Divider SLIMCLK_REF_GEAR Divide by FLLn_GPCLK_DIV Multiply by FLLn_SYNC_ FRATIO FOUT (GPIO) Divide by 7, 8 .. 127 Multiply by 1, 2, 4, 8 or 16 FSYNC < 13.5MHz FLLn_SYNC_ENA (FLL Synchroniser Enable) Synchroniser disabled: N.K = FLLn_N + Synchroniser enabled: N.K = FLLn_N + FLLn_THETA FLLn_LAMBDA FLLn_THETA 65536 N.K (Sync) = FLLn_SYNC_N + FLLn_SYNC_THETA FLLn_SYNC_LAMBDA Figure 76 FLL Configuration The procedure for configuring the FLL is described below. Note that the configuration of the main FLL path and the FLL Synchroniser path are very similar. One or both paths must be configured, depending on the application requirements:  If a single clock input reference is used, then only the main FLL path should be used.  If the input reference to the main FLL is intermittent, or may be interrupted unexpectedly, then only the main FLL path should be used.  If two clock input references are used, then the constant or low-noise clock is configured on the main FLL path, and the high-accuracy clock is configured on the FLL synchroniser path. Note that the synchroniser input must be synchronous with the audio data. The following description is applicable to FLL1, FLL2 and FLL3. The associated register control fields are described in Table 109, Table 110 and Table 111 respectively. The main input reference is selected using FLLn_REFCLK_SRC. The synchroniser input reference is selected using FLLn_SYNCCLK_SRC. The available options in each case comprise MCLK1, MCLK2, SLIMCLK, AIFnBCLK, AIFnLRCLK, or the output from another FLL. The SLIMCLK reference is controlled by an adaptive divider on the external SLIMCLK input. The divider automatically adapts to the SLIMbus Clock Gear, to provide a constant reference frequency for the FLL. See “SLIMbus Interface Control” for details. The FLL input reference can be generated directly from the output of another FLL. Note that the reference frequency is equal to FVCO / 3 in this case, with respect to the selected FLL source. The FLLn_REFCLK_DIV field controls a programmable divider on the main input reference. The FLLn_SYNCCLK_DIV field controls a programmable divider on the synchroniser input reference. Each input can be divided by 1, 2, 4 or 8. These registers should be set to bring each reference down to 13.5MHz or below. For best performance, it is recommended that the highest possible frequency - within the 13.5MHz limit - should be selected. (Note that additional guidelines also apply, as described below.) The FLL output frequency, relative to the main input reference FREF, is a function of: 302  The FLL oscillator frequency, FVCO  The frequency ratio set by FLLn_FRATIO  The real number represented by N.K. (N=integer; K=fractional portion) Rev 4.2 CS47L85 The FVCO frequency must be in the range 270MHz to 300MHz. When the FLL is selected as SYSCLK or ASYNCCLK source, a fixed divider sets the output frequency equal to FVCO / 3. Therefore, FVCO must be exactly 294.912MHz (for 48kHz-related sample rates) or 270.9504MHz (for 44.1kHz-related sample rates). When the FLL is selected as DSPCLK source, a fixed divider sets the output frequency equal to FVCO / 2. This enables DSPCLK frequencies in the range 135MHz to 150MHz. For FLL1 only, a ‘divide by 6’ option is also available, supporting low power DSP operation with DSPCLK frequencies in the range 45MHz to 50MHz. Note that the DSPCLK can be further divided for each DSP. When the FLL is selected as a GPIO output, a programmable divider supports division ratios in the range 7 through to 127, enabling a wide range of GPIO clock output frequencies. Note that the chosen FVCO frequency can be used to support multiple outputs simultaneously (e.g., SYSCLK and DSPCLK); each of the FLL clock output paths is controlled by a separate divider function, as illustrated in Figure 76. The FLLn_FRATIO field selects the frequency division ratio of the FLL input. The FLLn_GAIN field is used to optimise the FLL, according to the input frequency. As a general guide, these fields should be selected as described in Table 106. (Note that additional guidelines also apply, as described below.) REFERENCE FREQUENCY FREF 1MHz - 13.5MHz FLLn_FRATIO FLLn_GAIN 0h (divide by 1) 4h (16x gain) 256kHz - 1MHz 1h (divide by 2) 2h (4x gain) 128kHz - 256kHz 3h (divide by 4) 0h (1x gain) 64kHz - 128kHz 7h (divide by 8) 0h (1x gain) Less than 64kHz Fh (divide by 16) 0h (1x gain) Table 106 Selection of FLLn_FRATIO and FLLn_GAIN The FLL oscillator frequency, FVCO is set according to the following equation: FVCO = (FREF x 3 x N.K x FLLn_FRATIO) The value of N.K can thus be determined as follows: N.K = FVCO / (FLLn_FRATIO x 3 x FREF) Note that, in the above equations: FREF is the input frequency, after division by FLLn_REFCLK_DIV, where applicable FLLn_FRATIO is the FVCO clock ratio (1, 2, 3 … 16) If the above equations produce an integer value for N.K, then the value of FLLn_FRATIO should be adjusted to a different, odd-number division (e.g., divide by 3), and the value of N.K re-calculated. A non-integer value of N.K is recommended for best performance of the FLL. (If possible, the FLLn_FRATIO value should be decreased to the nearest alternative oddnumber division. If a suitable lower value does not exist, FLLn_FRATIO should be increased to the nearest odd-number division instead.) After the value of FLLn_FRATIO has been determined, the input frequency, FREF, must be compared with the maximum frequency limit noted in Table 107. If the input frequency (after division by FLLn_REFCLK_DIV) is higher than the applicable limit, then the FLLn_REFCLK_DIV division ratio should be increased, and the value of N.K re-calculated. (Note that the same value of FLLn_FRATIO as already calculated should be used, when deriving the new value of N.K.) Rev 4.2 303 CS47L85 FLLn_FRATIO 0h (divide by 1) 1h (divide by 2) REFERENCE FREQUENCY FREF - MAXIMUM VALUE 13.5 MHz 6.144 MHz 2h (divide by 3) 3h (divide by 4) 3.072 MHz 4h (divide by 5) 5h (divide by 6) 2.8224 MHz 6h (divide by 7) 7h (divide by 8) 1.536 MHz 8h (divide by 9) 9h (divide by 10) Ah (divide by 11) Bh (divide by 12) Ch (divide by 13) Dh (divide by 14) Eh (divide by 15) Fh (divide by 16) 768 kHz Table 107 Maximum FLL input frequency (function of FLLn_FRATIO) The value of N is held in the FLLn_N register field. The value of K is determined by the FLLn_THETA and FLLn_LAMBDA fields, as described later. The FLLn_N, FLLn_THETA and FLLn_LAMBDA fields are all coded as integers (LSB = 1). If the FLLn_N or FLLn_THETA registers are updated while the FLL is enabled (FLLn_ENA=1), then the new values will only be effective when a ‘1’ is written to the FLLn_CTRL_UPD bit. This makes it possible to update the two registers simultaneously, without disabling the FLL. Note that, when the FLL is disabled (FLLn_ENA=0), then the FLLn_N and FLLn_THETA registers can be updated without writing to the FLLn_CTRL_UPD bit. The values of FLLn_THETA and FLLn_LAMBDA can be calculated as described later. A similar procedure applies for the derivation of the FLL Synchroniser parameters - assuming that this function is used. The FLLn_SYNC_FRATIO field selects the frequency division ratio of the FLL synchroniser input. The FLLn_GAIN and FLLn_SYNC_DFSAT fields are used to optimise the FLL, according to the input frequency. These fields should be set as described in Table 108. Note that the FLLn_SYNC_FRATIO register coding is not the same as the FLLn_FRATIO register. SYNCHRONISER FREQUENCY FSYNC 1MHz - 13.5MHz FLLn_SYNC_FRATIO FLLn_SYNC_GAIN FLLn_SYNC_DFSAT 0h (divide by 1) 4h (16x gain) 0 (wide bandwidth) 256kHz - 1MHz 1h (divide by 2) 2h (4x gain) 0 (wide bandwidth) 128kHz - 256kHz 2h (divide by 4) 0h (1x gain) 0 (wide bandwidth) 64kHz - 128kHz 3h (divide by 8) 0h (1x gain) 1 (narrow bandwidth) Less than 64kHz 4h (divide by 16) 0h (1x gain) 1 (narrow bandwidth) Table 108 Selection of FLLn_SYNC_FRATIO, FLLn_SYNC_GAIN, FLLn_SYNC_DFSAT The FLL oscillator frequency, FVCO, is the same frequency calculated as described above. The value of N.K (Sync) can then be determined as follows: N.K (Sync) = FVCO / (FLLn_SYNC_FRATIO x 3 x FSYNC) 304 Rev 4.2 CS47L85 Note that, in the above equations: FSYNC is the synchroniser input frequency, after division by FLLn_SYNCCLK_DIV, where applicable FLLn_SYNC_FRATIO is the FVCO clock ratio (1, 2, 4, 8 or 16) The value of N (Sync) is held in the FLLn_SYNC_N register field. The value of K (Sync) is determined by the FLLn_SYNC_THETA and FLLn_SYNC_LAMBDA fields. The FLLn_SYNC_N, FLLn_SYNC_THETA and FLLn_SYNC_LAMBDA fields are all coded as integers (LSB = 1). In Fractional Mode, with the synchroniser disabled (K > 0, and FLLn_SYNC_ENA = 0), the register fields FLLn_THETA and FLLn_LAMBDA can be calculated as described below. The equivalent procedure is also used to derive the FLLn_SYNC_THETA and FLLn_SYNC_LAMBDA register values from the corresponding synchroniser parameters. (This is only required if the synchroniser is enabled.) Calculate GCD(FLL) using the ‘Greatest Common Denominator’ function: GCD(FLL) = GCD(FLLn_FRATIO x FREF, FVCO / 3) where GCD(x, y) is the greatest common denominator of x and y FREF is the input frequency, after division by FLLn_REFCLK_DIV, where applicable. Next, calculate FLLn_THETA and FLLn_LAMBDA using the following equations: FLLn_THETA = ((FVCO / 3) - (FLL_N x FLLn_FRATIO x FREF)) / GCD(FLL) FLLn_LAMBDA = (FLLn_FRATIO x FREF) / GCD(FLL) Note that, in the operating conditions described above, the values of FLLn_THETA and FLLn_LAMBDA must be co-prime (i.e., not divisible by any common integer). The calculation above ensures that the values will be co-prime. The value of K must be a fraction less than 1 (i.e., FLLn_THETA must be less than FLLn_LAMBDA). In Fractional Mode, with the synchroniser enabled (K > 0, and FLLn_SYNC_ENA = 1), the value of FLLn_THETA is calculated as described below. The value of FLLn_LAMBDA is ignored in this case. FLLn_THETA = K x 65536 The FLL control registers are described in Table 109, Table 110 and Table 111. Example settings for a variety of reference frequencies and output frequencies are shown in Table 114. Rev 4.2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R369 (0171h) FLL1_Con trol_1 0 FLL1_ENA 0 FLL1 Enable 0 = Disabled 1 = Enabled This should be set as the final step of the FLL1 enable sequence, i.e., after the other FLL registers have been configured. R370 (0172h) FLL1_Con trol_2 15 FLL1_CTRL_UP D 0 FLL1 Control Update Write ‘1’ to apply the FLL1_N and FLL1_THETA register settings. (Only valid when FLL1_ENA=1) 9:0 FLL1_N [9:0] 008h FLL1 Integer multiply for FREF (LSB = 1) If updated while the FLL is enabled, the new value is only effective when a ‘1’ is written to FLL1_CTRL_UPD. 305 CS47L85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R371 (0173h) FLL1_Con trol_3 15:0 FLL1_THETA [15:0] 0018h FLL1 Fractional multiply for FREF This field sets the numerator (multiply) part of the FLL1_THETA / FLL1_LAMBDA ratio. Coded as LSB = 1. If updated while the FLL is enabled, the new value is only effective when a ‘1’ is written to FLL1_CTRL_UPD. R372 (0174h) FLL1_Con trol_4 15:0 FLL1_LAMBDA [15:0] 007Dh FLL1 Fractional multiply for FREF This field sets the denominator (dividing) part of the FLL1_THETA / FLL1_LAMBDA ratio. Coded as LSB = 1. R373 (0175h) FLL1_Con trol_5 11:8 FLL1_FRATIO [3:0] 0h FLL1 FVCO clock divider 0h = 1 1h = 2 2h = 3 3h = 4 … Fh = 16 R374 (0176h) FLL1_Con trol_6 7:6 FLL1_REFCLK_ DIV [1:0] 00 FLL1 Clock Reference Divider 00 = 1 01 = 2 10 = 4 11 = 8 MCLK (or other input reference) must be divided down to