CDB5321

CDB5321 Evaluation Board for CS5321 and CS5322 Features Description The CDB5321 is an evaluation board that allows laboratory characterization of the CS5321/CS5322 A/D converter chip-set. The chip-set supports seven different selectable word rates: 4 kHz, 2 kHz, 1 kHz, 500 Hz 250 Hz, 125 Hz and 62.5 Hz. Input to the board is 9 volts peak-to-peak. Output is via header connections to the CS5322 serial interface. ORDERING INFORMATION CDB5321 I l DIP switch control of all CS5322 logic pins l Header control of all CS5322 logic pins l Supports manual operation of RESET and SYNC Evaluation Board DIP Switch Selections SYNC +5V Reference Circuitry CS5321 VREF+ MSYNC MCLK MDATA AIN+ AIN AINR 2.048 MHz Oscillator/ Divider +5V Analog +5V Regulator -5V Analog -5V Regulator MFLG CS5322 MSYNC MCLK MDATA MFLG CLKIN 9 8 RESET +5V Headers DIP Switch Selections +5V Digital +15V AGND -15V DGND +5V Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com Copyright © Cirrus Logic, Inc. 1998 (All Rights Reserved) MAR ‘95 DS88DB2 15 CDB5321 +15V +15 V + 47µF 0.1µF C13 3 IN U6 78L05 GND 2 1 OUT +5VA +5VA 0.1µF C14 D2 1N6276 C12 R2 2K 2 + 10 µF C7 0.1µF C11 IN U8 LT1019 4.5V GND 4 OUT 6 5 TRIM 10K R16 OPTIONAL To VREF (4.5 V) Figure 2 -15V -15 V D3 + 1N6276 C16 C17 2 47µF 0.1µF IN U9 79L05 OUT GND 1 3 0.1µF C18 - 5VA - 5VA +5V 6.8V P6KE D1 C3 C4 47µF +5V 0.1µF + DGND Figure 1. Power Supplies 16 DS88DB2 CDB5321 OVERVIEW The CDB5321 evaluation board requires three separate power supplies for proper operation. Figure 1 illustrates the power supply connections. The required power supply input voltages consist of +5V, +15V, and -15V. The CS5322 filter and logic support devices on the board operate from the +5V supply. The +15V and -15V inputs are regulated down to provide +5V and -5V supplies necessary for the CS5321 modulator. Figure 1 also illustrates the LT1019 4.5V reference used with the CS5321 modulator. Figure 2 illustrates the CS5321 modulator circuitry, including the analog BNC input for the test signal source. Most often switch selections on S5 are set to HBR=1, LPWR=0, and +5 VA C26 TANT 10 µF R6 VREF From Figure 1. 200 C50 0.1µF + C22 0.1 µF 2 22 V2+ OFST LPWR HBR 28 27 26 C27 0.1 µF S5 OFST LPWR HBR R7 100k R8 100k R9 100k V1+ 5 VREF+ C20 TANT 68 µF 6 VREF- 8 R1 402 R5 AIN C15 402 NPO 0.1 µF See CS5321 Datasheet C6 NPO 0.1 µF AIN- U2 CS5321 9 MCLK AIN+ MSYNC MDATA AINR MFLG MDATA 1 AGND1 4 AGND2 7 AGND3 11 AGND4 12 AGND5 13 AGND6 14 AGND7 V1-5 VA TEST POINT C29 0.1 µF C19 + 10 µF C40 0.1 µF 3 20 25 18 24 17 23 19 16 15 MCLK MSYNC MDATA MFLG MDATA To Figure 4. 10 DGND1 DGND2 DGND3 DGND4 V221 Figure 2. CS5321 Modulator Input Circuitry. DS88DB2 17 CDB5321 10 +5V R25 10 +5V R3 + 10µF C2 0.1µF 14 74HC74 0.1 C33 14 4 U7 8 3 2 1 S U5A CLK D R Q 6 Q 5 10 11 12 13 S U5B CLK D R Q 9 C1 2.048 MHz OSC 14 pin 7 Q 8 *2.048 MHz exceeds the specified clock frequency for the CS5321 J4 CLK/4 (512 kHz) CLK/2 (1.024 MHz) CLK (2.048 MHz)* CLKIN (To Figure 4) Figure 3. Oscillator / Divider OFST=1. Figure 3 illustrates the 2.048 MHz oscillator and dual D flip flop clock divider. Note that both the oscillator and the divider are separately decoupled from the +5V supply to reduce clock jitter which can be introduced from noisy supplies. Jumper J4 should be set in the CLK/2 position to source 1.024 MHz to the CS5322 chip for normal operation. If operation from 512 kHz clock is desired, the J4 jumper should be changed to the CLK/4 position. The board can be tested at 512 kHz without modification. The digital interface pins to the CS5322 filter chip are all available on the header connectors J1, J2, and J3 as shown in Figures 4, 5, and 6. Note that one row of pins on each of the headers is ground. It is advised that any connections made to control lines be done with twisted pair ribbon cable; with each twisted pair containing one signal and one ground connection. This minimizes radiated noise. CAUTION! Caution is advised when interfacing the evaluation board to any circuitry powered from another source. For example, when interfacing to a computer I/O card be sure that the evaluation board and the computer are both powered up before connecting to the evaluation board headers. Always disconnect header connections when powering down the board but not the computer. Failure to follow this advice may cause damage to either the computer I/O or to the CS5322, because the computer outputs try to power the CDB5321 board. 18 DS88DB2 DS88DB2 19 CLKIN (From Figure 3) CLKIN +5V C9 8 9 21 0.1 µF C8 20 3 1 24 26 22 U3A 2 3 U3B 4 0.1µF C34 TP JP13 SCLK 0.1µF +5V To DRDY SOD Figure 5,6 SCLK VD1+ DGND VD2+ DGND CLKIN 5 To Figure 2 7 10 MDATA 6 MFLG MSYNC MCLK SOD SCLK DRDY J3 +5V 47k SIPS 0.1 DRDY SOD SCLK SID ERROR RSEL CS R/W SYNC SYNC R12 +5VD J1 RST TDATA CSEL H/S PWDN DECC DECB DECA USEOR ORCAL 5K 25 SID 23 ERROR 27 RSEL 1 CS 28 R/W 2 SYNC 100 k R13 RESET TDATA CSEL H/S PWDN DECC DECB DECA USEOR ORCAL 4 11 12 13 14 16 17 18 15 19 100 k R14 DECA DECB DECC PWDN H/S CSEL TDATA CS5322 U1 RESET +5V 5k R11 SW3 USEOR ORCAL SID ERR RSEL CS R/W SW4 CDB5321 Figure 4. CS5322 Filter Interface CDB5321 DECA USEOR ON* OFF ORCAL ON* OFF SID ON Do not use offset register Use offset register Disable offset register calibration Enable offset register calibration Sets SID to Logic 0 PWDN DECC DECB ABC Output Word Rate 000 62.5 Selection 100 125 via hardware 0 1 0 250 pins 110 500 001 1000 101 2000 011 4000 ON* OFF ON Normal Operation Power down active Selects configuration register for operating mode Select hardware pins for operating mode Selects MDATA from modulator Selects TDATA as filter input Sets TDATA input to logic 0 Enables TDATA from J1 header OFF* Allows pull-up on SID line ERR ON Sets ERR to logic 0 OFF* Allows CS5322 ERROR output RSEL ON Select status register H/S OFF* CSEL ON* OFF TDATA ON* OFF OFF* Select conversion data register CS ON* OFF R/W ON Chip select active Chip select inactive Enables write mode via SID pin OFF* Enables read mode via SOD pin OFF = OPEN = 1 *Default to use Figure 6 interface. Table 1. S3 DIP Switch Selections 10 +5V 0.1 C35 R4 + 10 µF C5 DRDY SCLK 1 3 U4A 2 SOD U4B 4 OFF = OPEN = 1 *Default to use Figure 6 interface. Table 2. S4 DIP switch selections JP6 +5V +5V DRDY SCLK SOD DRDY From Figure 4 SCLK U4D 14 9 8 13 11 U4 12 U4F 10 5 U4C 6 SOD 7 U4E U3, U4 = 74HC04 5 13 11 9 6 U3C 12 U3F 10 U3D 8 U3E Figure 5. Serial Latch Interface on CDB5321 (Rev B) board 20 DS88DB2 CDB5321 Figures 5 and 6 illustrate the logic used to drive connections at header JP6 (Rev. B Board) or J2 (Rev. C Board). The Rev. C evaluation board can directly interface to the CDBCAPTURE board through connector J2. A D-type Flip-Flop must be added in the patch area of the Rev. B evaluation board to enable it to interface to the CDBCAPTURE board. The CDBCAPTURE can be used to perform FFT analysis and noise histograms. Tables 1 and 2 illustrate the DIP switch positions of switches S3 and S4. The switch positions with asterisks indicate preferred settin gs fo r driving the interface on the CDBCAPTURE system. The CS5322 filter should be set up for hardware mode (H/S on switch S4 open). DIP switch S4 can then be used to select the desired output word rate. After the selection on the DECA, DECB, and DECC positions of the S4 DIP switch, the S2 RESET switch must be activated, 10 +5 V R4 + 10 µF C5 +5 8 5 6 2 3 From Figure 4 7 SCLK SCLK 13 12 1 2 SOD SOD 11 10 3 4 4 +5 10 +5 U10 74HC74 14 D CL 1 Q +5 5 12 D 13 Q DRDYD J2 +5V +5V DRDYD SCLK SOD followed by the S1 SYNC switch (unless these signals are controlled via the J1 and J3 header signals). Figure 7 illustrates the component layout of the board while figures 8 and 9 illustrate the board layout (not to scale). Using the Evaluation Board Connect the appropriate power supplies to the binding posts of the board. Twist the +5V digital supply lead with the digital ground lead from the board to the supply. Also twist the supply leads for the analog voltages. Use a high quality power supply which is low in noise and line frequency(50/60 Hz) interference. Power up the supplies. Then connect a coaxial cable from the analog BNC to the signal source. Note that the performance of the A/D converter chip set will exceed the capability of most signal generators, with respect to noise, distortion, and line frequency interference. DRDY 9 14 11 CL U4 74HC04 Figure 6. Serial Latch Interface on CDB5321 (Rev C) board. DS88DB2 21 CDB5321 Once power has been applied to the board, connect the ribbon cable to the appropriate headers (J1, J2, and/or J3). The reset and the sync signals to the CS5322 must be applied before normal operation can commence. This can be done by using the S2 RESET switch and the S1 SYNC switch or by interfacing to these signals via the J1 and J3 headers. 22 DS88DB2 CDB5321 Figure 7. CDB5321 (Rev. C) Silk Screen Layout (Not to Scale) DS88DB2 23 CDB5321 Figure 8. CDB5321 (Rev. C) Component Side Layer (Not to Scale) 24 DS88DB2 CDB5321 Figure 9. CDB5321 (Rev. C) Solder Side Layer (Not to Scale) DS88DB2 25