CDB5330A

CDB5330A CDB5331A Evaluation Board for CS5330A / CS5331A Features General Description The CDB5330A/31A evaluation board is an excellent means for quickly evaluating the CS5330A/31A 18-bit, stereo A/D converter. Evaluation requires a digital signal processor, a low distortion analog signal source and a power supply. Analog inputs are provided via RCA connectors for both channels. Also included is a CS8402A digital audio interface transmitter which generates AES/EBU, S/PDIF, and EIAJ-340 compatible audio data. The digital audio data is available via RCA phono, and optical connectors. The evaluation board may also be configured to accept external timing signals for operation in a user application during system development. ORDERING INFORMATION: CDB5330A, CDB5331A • Demonstrates recommended layout and grounding arrangements • CS8402A Generates AES/EBU, S/PDIF, & EIAJ-340 Compatible Digital Audio • Buffered Serial Output Interface • Digital and Analog Patch Areas • On-board or externally supplied system timing Analog Filter CS5330A/31A CS8402A Digital Audio Interface Digital Audio Output I/O for Clocks and Data Cirrus Logic, Inc. Crystal Semiconductor Product Division P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 http://www.crystal.com Copyright © Cirrus Logic, Inc. 1997 (All Rights Reserved) OCT ’97 DS138DB2 17 CDB5330A / CDB5331A CDB5330A/31A System Overview The CDB5330A/31A evaluation board is an excellent means of quickly evaluating the CS5330A/31A. The CS8402A digital audio interface transmitter provides an easy interface to digital audio signal processors, including the majority of digital audio test equipment. The evaluation board has been designed to accept an analog input, and provide a digital output that is either optical or coax. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system development. The CDB5330A/31A schematic has been partitioned into 5 schematics shown in Figures 2 through 6. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the the system diagram also includes the interconnections between the partitioned schematics. CS5330A/31A Analog to Digital Converter A description of the CS5330A/31A is included in the CS5330A/31A data sheet. CS8402A Digital Audio Interface Figure 4 shows the CS8402A circuitry which implements AES/EBU, S/PDIF and EIAJ CP340 digital audio interface standards. The CS8402A circuit is hardware configured for consumer mode. SW2 provides 8 DIP switches to select various modes and bits for the CS8402A, Tables 4-5. See the CS8401A/CS8402A data sheet for detailed information on the operation of the CS8402A and the digital audio standards. The operation of the CS8402A and a discussion of the digital audio interface are included in the 1994 Crystal Semiconductor Audio Data Book. CS8402A Data Format The CS8402A data format can be set with jumpers M0, M1, and M2. These formats are shown in the CS8402A datasheet found in the 1994 Crystal Semiconductor Audio Data Book. The format selected must be compatible with the corresponding data format of the CS5330A/31A shown in Figures 2 and 3 of the CS5330A/31A datasheet. The default settings for M0-M2 on the evaluation board are given in Tables 2 and 3. The compatible data formats for the CS8402A and CS5330A/31A are: CS8402A format 1;CS5330A CS8402A format 4;CS5331A Analog input buffer The recommended input filter required for the CS5330A/31A has been combined with a unity gain input buffer (see Figure 2). The analog input filter uses a Motorola MC33202 single supply, dual op-amp. Power Supply Circuitry Power is supplied to the evaluation board by two binding posts (GND, +5V), Figure 6. The +5V input supplies power to the +5 Volt digital circuitry (VD+), and the +5V analog circuitry (VA+). The analog supply is derived from the +5V binding post through a ferrite bead. Input/Output for Clocks and Data The evaluation board has been designed to allow the interface to external systems via the 10-pin CLOCK I/O header, HDR2. This header allows the evaluation board to accept externally generated clocks. The schematic for the clock/data I/O is shown in Figure 5. The 74HC243 transceiver functions as an I/O buffer where the MASTER/SLAVE jumper determines if the transceiver operates as a transmitter or receiver. DS138DB2 18 CDB5330A / CDB5331A The transceiver operates as a transmitter with the MASTER/SLAVE jumper in the MASTER position. LRCK, SDATA, and SCLK from the CS5330A/31A will be available on HDR2. HDR22 must be in the 0 position and HDR23 must be in the 1 position for MCLK to be an output and to avoid bus contention on MCLK. The transceiver operates as a receiver with the MASTER/SLAVE jumper in the SLAVE position. LRCK and SCLK on HDR2 become inputs. However, the recommended mode of operation is to generate MCLK on the evaluation board with HDR23 in the 0 position and HDR22 in the 1 position. These default settings allow MCLK to be an output, with LRCK and SCLK as inputs. MCLK is always an output from the evaluation board. Grounding and Power Supply Decoupling The CS5330A/31A requires careful attention to power supply and grounding arrangements to optimize performance. Figure 2 shows the recommended power arrangements. The CS5330A/31A is positioned over the analog ground plane, near the digital/analog ground plane split, to minimize the distance that the clocks travel. The series resistors are present on the clock lines to reduce the effects of transient currents when driving a capacitive load in master mode, and reduce clock overshoot when applying external clocks to the CS5330A/31A in slave mode. This layout technique is used to minimize digital noise and to insure proper power supply matching/sequencing. The decoupling capacitors are located as close to the CS5330A/31A as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yield large reductions in radiated noise effects. CONNECTOR +5V GND AINL AINR MCLK, SCLK, LRCK, SDATA Digital Output Optical Output INPUT/OUTPUT input input input input input/output output output SIGNAL PRESENT (VD+) for CS8402A and digital section (VA+) for CS5330A/31A and Analog input filter op-amp ground connection from power supply left channel analog input right channel analog input I/O for master, serial, left/right clocks, and serial DATA digital audio interface output via coax digital audio interface output via optical Table 1. System Connections DS138DB2 19 CDB5330A / CDB5331A JUMPER HDR1 PURPOSE CS5330A/31A SCLK Selection for CS8402A Master/Slave Mode Selection Selects source of system clocks Clock I/O Selects 256× or 512× MCLK for CS8402A POSITION *5330A 5331A *High Low *High Low *0 *1 *256 512 *Low *Low *High FUNCTION SELECTED CS5330A Selected CS5331A Selected MASTER Mode SLAVE Mode MASTER Mode (5330A Clocks) SLAVE Mode (External Clocks) See Input/Output for Clocks and Data section of text See CS8402A data sheet for details See CS8402A data sheet for details HDR10 HDR9 HDR22 HDR23 HDR6 HDR5 (M2) CS8402A mode select HDR4 (M1) HDR3 (M0) * Default setting from factory Table 2. CDB5330A Jumper Selectable Options JUMPER HDR1 PURPOSE CS5330A/31A SCLK Selection for CS8402A Master/Slave Mode Selection Selects source of system clocks Clock I/O Selects 256× or 512× MCLK for CS8402A POSITION 5330A *5331A *High Low *High Low *0 *1 *256 512 *High *Low *Low FUNCTION SELECTED CS5330A Selected CS5331A Selected MASTER Mode SLAVE Mode MASTER Mode (5331A Clocks) SLAVE Mode (External Clocks) See Input/Output for Clocks and Data section of text See CS8402A data sheet for details See CS8402A data sheet for details HDR10 HDR9 HDR22 HDR23 HDR6 HDR5 (M2) CS8402A mode select HDR4 (M1) HDR3 (M0) * Default setting from factory Table 3. CDB5331A Jumper Selectable Options 20 DS138DB2 CDB5330A / CDB5331A 0=Closed, 1=Open PRO=0 FC1, FC0 0 0 *0 1 1 0 1 1 C3 2 *1 0 5 C2 1 *0 6 C15 1 *0 8,7 C8, C9 1 1 1 0 0 1 *0 0 * Default setting from factory Switch# 3 1,4 Comment Consumer Mode C0=0 C24,C25,C26,C27 - Sample Frequency 0000 - 44.1 kHz 0100 - 48 kHz 1100 - 32 kHz 0000 - 44.1 kHz, CD Mode C3,C4,C5 - Emphasis (1 of 3 bits) 000 - None 100 - 50/15 µs C2 - Copy/Copyright 0 - Copy Inhibited/Copyright Asserted 1 - Copy Permitted/Copyright Not Asserted C15 - Generation Status 0 - Definition is based on category code. 1 - See CS8402A Data Sheet, App. A C8-C14 - Category Code (2 of 7 bits) 0000000 - General 0100000 - PCM encoder/decoder 1000000 - Compact Disk - CD 1100000 - Digital Audio Tape - DAT Table 4. CS8402A Switch Definitions - Consumer Mode Switch# 3 1 default 2,5 default 4 default 6 default 8,7 default 0=Closed, 1=Open PRO=0 CRE 0 1 C6, C7 1 1 1 0 0 1 0 0 C1 1 0 C9 1 0 EM1, EM0 1 1 1 0 0 1 0 0 Comment Professional Mode C0=1(default) Local Sample Address Counter & Reliability Flags Disabled Internally Generated C6,C7 - Sample Frequency 00 - Not Indicated - Default to 48 kHz 01 - 48 kHz 10 - 44.1 kHz 11 - 32 kHz C1 - Audio 0 - Normal Audio 1 - Non-Audio C8,C9,C10,C11 - Channel Mode (1 of 4 bits) 0000 - Not indicated - Default to 2-channel 0100 - Stereophonic C2,C3,C4 - Emphasis (2 of 3 bits) 000 - Not Indicated - default to none 100 - No emphasis 110 - 50/15 µs 111 - CCITT J.17 Table 5. CS8402A Switch Definitions - Professional Mode DS138DB2 21 CDB5330A / CDB5331A Figure 1. System Block Diagram and Signal Flow 22 DS138DB2 DS138DB2 CDB5330A / CDB5331A Figure 2. CS5330A/31A and Connections 23 CDB5330A / CDB5331A Figure 3. MCLK Generation and Power Down 24 DS138DB2 DS138DB2 CDB5330A / CDB5331A Figure 4. CS8402A Digital Audio Transmitter Connections Optional Toshiba Part TOTX123 available through Insight Electronics Schott Corp. Transformer Part 121960-602 available through Schott Corp., Wayzata, MN. 25 CDB5330A / CDB5331A Figure 5. I/O Interface for Clocks and Data Figure 6. Power Supply 26 DS138DB2 CDB5330A / CDB5331A Figure 7. CDB5330A/31A Component Side Silkscreen DS138DB2 27 CDB5330A / CDB5331A Figure 8. CDB5330A/31A Component Side (top) 28 DS138DB2 CDB5330A / CDB5331A Figure 9. CDB5330A/31A Solder Side (bottom) DS138DB2 29