CS5351
108 dB, 192 kHz, Multi-bit Audio A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture 24-bit Conversion 108 dB Dynamic Range -98 dB THD+N System Sampling Rates up to 192 kHz 135 mW Power Consumption High-Pass Filter and DC Offset Calibration Supports Logic Levels Between 5 and 2.5 V Single-Ended Analog Inputs Overflow Detection Pin Compatible with the CS5361
General Description
The CS5351 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analogto-digital conversion, and anti-alias filtering. The device generates 24-bit values for both left and right inputs in serial form at sample rates up to 192 kHz per channel. The CS5351 uses a 5th-order, multi-bit, delta-sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The ADC uses a differential architecture which provides excellent noise rejection. The CS5351 is ideal for audio systems requiring wide dynamic range, negligible distortion, and low noise. Such applications include A/V receivers, DVD-R, CD-R, digital mixing consoles, and effects processors. ORDERING INFORMATION CS5351-KSZ, Lead Free -10° to 70°C 24-pin SOIC CS5351-KZZ, Lead Free -10° to 70°C 24-pin TSSOP CS5351-DZZ, Lead Free -40° to 85°C 24-pin TSSOP CDB5351 Evaluation Board
VQ3 VQ1VQ2 REFGND
OVFL
VL SCLK
LRCK SDOUT
MCLK
FILT+
Voltage Reference
Serial Output Interface
RST I²S/LJ M/S High Pass Filter HPF MDIV
AINL S/H
+ -
LP Filter
ΔΣ
Digital Decimation Filter
DAC AINR S/H + LP Filter ΔΣ Digital Decimation Filter High Pass Filter MODE0 MODE1
DAC
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved)
MAY '07 DS565F2
CS5351
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4 SPECIFIED OPERATING CONDITIONS .............................................................................................. 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4 ANALOG CHARACTERISTICS (CS5351-KSZ/KZZ) ............................................................................. 5 ANALOG CHARACTERISTICS (CS5351-DZZ) .................................................................................... 6 DIGITAL FILTER CHARACTERISTICS ................................................................................................. 7 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 10 DIGITAL CHARACTERISTICS ............................................................................................................ 10 THERMAL CHARACTERISTICS ......................................................................................................... 10 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT .............................................................. 11 2. PIN DESCRIPTIONS ............................................................................................................................ 14 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 15 4. APPLICATIONS ................................................................................................................................... 16 4.1 Operational Mode/Sample Rate Range Select .............................................................................. 16 4.2 System Clocking ............................................................................................................................ 16 4.2.1 Slave Mode ........................................................................................................................... 16 4.2.2 Master Mode ......................................................................................................................... 17 4.3 Power-Up Sequence ...................................................................................................................... 17 4.4 Analog Connections ....................................................................................................................... 18 4.5 High-Pass Filter and DC Offset Calibration ................................................................................... 18 4.6 Overflow Detection ......................................................................................................................... 19 4.6.1 OVFL Output Timing ............................................................................................................. 19 4.7 Grounding and Power Supply Decoupling ..................................................................................... 19 4.8 Synchronization of Multiple Devices .............................................................................................. 19 5. PARAMETER DEFINITIONS ................................................................................................................ 20 6. PACKAGE DIMENSIONS ................................................................................................................. 21 7. REVISION HISTORY ............................................................................................................................ 23
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LIST OF FIGURES
Figure 1. Single-Speed Mode Stopband Rejection ..................................................................................... 8 Figure 2. Single-Speed Mode Transition Band ........................................................................................... 8 Figure 3. Single-Speed Mode Transition Band (Detail) ............................................................................... 8 Figure 4. Single-Speed Mode Passband Ripple ......................................................................................... 8 Figure 5. Double-Speed Mode Stopband Rejection .................................................................................... 8 Figure 6. Double-Speed Mode Transition Band .......................................................................................... 8 Figure 7. Double-Speed Mode Transition Band (Detail) ............................................................................. 9 Figure 8. Double-Speed Mode Passband Ripple ........................................................................................ 9 Figure 9. Quad-Speed Mode Stopband Rejection ...................................................................................... 9 Figure 10. Quad-Speed Mode Transition Band .......................................................................................... 9 Figure 11. Quad-Speed Mode Transition Band (Detail) .............................................................................. 9 Figure 12. Quad-Speed Mode Passband Ripple ........................................................................................ 9 Figure 13. Master Mode, Left-Justified SAI ............................................................................................... 12 Figure 14. Slave Mode, Left-Justified SAI ................................................................................................. 12 Figure 15. Master Mode, I²S SAI ............................................................................................................... 12 Figure 16. Slave Mode, I²S SAI ................................................................................................................. 12 Figure 17. OVFL Output Timing ................................................................................................................ 12 Figure 18. Left-Justified Serial Audio Interface ......................................................................................... 13 Figure 19. I²S Serial Audio Interface ......................................................................................................... 13 Figure 20. OVFL Output Timing, I²S Format ............................................................................................. 13 Figure 21. OVFL Output Timing, Left-Justified Format ............................................................................. 13 Figure 22. Typical Connection Diagram .................................................................................................... 15 Figure 23. CS5351 Master Mode Clocking ............................................................................................... 17 Figure 24. CS5351 Recommended Analog Input Buffer ........................................................................... 18
LIST OF TABLES
Table 1. CS5351 Mode Control ................................................................................................................. 16 Table 2. CS5351 Slave Mode Clock Ratios .............................................................................................. 16 Table 3. CS5351 Common Master Clock Frequencies ............................................................................. 17
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CS5351 1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.) Parameter
DC Power Supplies: Positive Analog Positive Digital Positive Logic Commercial (-KSZ/-KZZ) Automotive (-DZZ)
Symbol
VA VD VL TAC TAI
Min
4.75 3.1 2.37 -10 -40
Typ
5.0 3.3 3.3 -
Max
5.25 5.25 5.25 70 85
Unit
V V V °C °C
Ambient Operating Temperature
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 1) Parameter
DC Power Supplies: Analog Logic Digital (Note 2) (Note 3) (Note 3)
Symbol VA VL VD Iin VIN VIND TA Tstg
Min -0.3 -0.3 -0.3 -10 GND - 0.7 -0.7 -50 -65
Max +6.0 +6.0 +6.0 +10 VA + 0.7 VL + 0.7 +95 +150
Units V V V mA V V °C °C
Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature
Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current.
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CS5351 ANALOG CHARACTERISTICS (CS5351-KSZ/KZZ)
(Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.) Parameter
Single-Speed Mode Dynamic Range Fs = 48 kHz 102 99 THD+N 102 99 THD+N 102 99 THD+N -2 -100 0.55*VA 7.5 -98 -84 -44 -95 95 0.1 0.56*VA 82 -92 2 100 0 100 .57*VA dB dB dB dB dB dB % ppm/°C LSB LSB Vpp kΩ dB -98 -84 -44 -95 108 105 102 -92 dB dB dB dB dB dB dB -98 -84 -44 108 105 102 -92 dB dB dB dB dB dB 108 105 dB dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB Double-Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Quad-Speed Mode Fs = 192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB
Symbol
Min
Typ
Max
Unit
Dynamic Performance for All Modes
Interchannel Isolation
DC Accuracy
Interchannel Gain Mismatch Gain Error Gain Drift Offset Error
HPF enabled HPF disabled
Analog Input Characteristics
Full-scale Input Voltage Input Impedance Common Mode Rejection Ratio
CMRR
Notes: 4. Referred to the typical full-scale input voltage.
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CS5351 ANALOG CHARACTERISTICS (CS5351-DZZ)
(Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.) Parameter
Single-Speed Mode Dynamic Range Fs = 48 kHz A-weighted unweighted (Note 4) -1 dB -20 dB -60 dB 100 97 THD+N 100 97 THD+N 100 97 THD+N -5 -100 0.53*VA 7.5 -98 -84 -44 -95 95 0.1 0.56*VA 82 -90 5 100 0 100 0.59*VA dB dB dB dB dB dB % ppm/°C LSB LSB Vpp kΩ dB -98 -84 -44 -95 108 105 102 -90 dB dB dB dB dB dB dB -98 -84 -44 108 105 102 -90 dB dB dB dB dB dB 108 105 dB dB
Symbol
Min
Typ
Max
Unit
Total Harmonic Distortion + Noise
Double-Speed Mode Dynamic Range
Fs = 96 kHz
A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Quad-Speed Mode Fs = 192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB
Dynamic Performance for All Modes
Interchannel Isolation
DC Accuracy
Interchannel Gain Mismatch Gain Error Gain Drift Offset Error
HPF enabled HPF disabled
Analog Input Characteristics
Full-scale Input Voltage Input Impedance Common Mode Rejection Ratio
CMRR
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CS5351 DIGITAL FILTER CHARACTERISTICS
Parameter Single-Speed Mode (2 kHz to 51 kHz sample rates)
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Interchannel Phase Deviation tgd (Note 5) (-0.1 dB) (Note 5) 0 -0.1 0.58 -95 (-0.1 dB) (Note 5) (Note 5) tgd 0 -0.1 0.68 -92 (-0.1 dB) (Note 5) (Note 5) tgd 0 -0.1 0.78 -92 -3.0 dB -0.13 dB @ 20 Hz (Note 6) (Note 6) 12/Fs 0.0001 9/Fs 0.0001 5/Fs 0.0001 1 20 10 105/Fs 0.47 0.035 0.45 0.035 0.24 0.035 0 Fs dB Fs dB s Deg Fs dB Fs dB s Deg Fs dB Fs dB s Deg Hz Hz Deg dB s
Symbol
Min
Typ
Max
Unit
Double-Speed Mode (50 kHz to 102 kHz sample rates)
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Interchannel Phase Deviation
Quad-Speed Mode (100 kHz to 204 kHz sample rates)
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Interchannel Phase Deviation
High Pass Filter Characteristics
Frequency Response Phase Deviation Passband Ripple Filter Settling Time
Notes: 5. The filter frequency response scales precisely with Fs. 6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
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0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 1. Single-Speed Mode Stopband Rejection
Figure 2. Single-Speed Mode Transition Band
0 -1 -2
0.10
0.08
0.05
-3
0.03
Amplitude (dB)
Amplitude (dB)
-4 -5 -6 -7
0.00
-0.03
-0.05
-8
-0.08
-9 -10 0.45
-0.10 0.00
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.53
0.54
0.55
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 3. Single-Speed Mode Transition Band (Detail)
Figure 4. Single-Speed Mode Passband Ripple
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
Amplitude (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
0.43
0.45
0.48
0.50
0.53
0.55
0.58
0.60
0.63
0.65
0.68
0.70
Frequency (normalized to Fs)
Figure 5. Double-Speed Mode Stopband Rejection
Figure 6. Double-Speed Mode Transition Band
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0 -1 -2
0.10
0.08
0.05 -3 -4 -5 -6 -7 -0.05 -8 -9 -10 0.40 -0.08 0.03 Amplitude (dB)
Amplitude (dB)
0.00
-0.03
0.43
0.45
0.48 Frequency (normalized to Fs)
0.50
0.53
0.55
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 7. Double-Speed Mode Transition Band (Detail)
Figure 8. Double-Speed Mode Passband Ripple
Amplitude (dB)
Amplitude (dB)
F r e q u e n c y ( n o r m a liz e d t o F s )
F re q u e n c y (n o rm a liz e d to F s )
Figure 9. Quad-Speed Mode Stopband Rejection
Figure 10. Quad-Speed Mode Transition Band
Amplitude (dB)
Amplitude (dB)
F r e q u e n c y ( n o rm a liz e d t o F s )
F re q u e n c y ( n o rm a liz e d to F s )
Figure 11. Quad-Speed Mode Transition Band (Detail)
Figure 12. Quad-Speed Mode Passband Ripple
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CS5351 DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode) Parameter
Power Supply Current (Normal Operation) Power Supply Current (Power-Down Mode) (Note 7) Power Consumption (Normal Operation) VA = 5 V VL,VD = 5 V VL,VD = 3.3 V VA = 5 V VL,VD = 5 V VA, VD, VL = 5 V VA = 5 V, VL, VD = 3.3 V (Power-Down Mode) (Note 8)
Symbol
IA ID ID IA ID PSRR
Min
-
Typ
17.5 22 14.5 100 100 198 135 1 65 2.5 25 0.01 5 15 0.01
Max
21.5 27.5 17 243 161 -
Unit
mA mA mA μA μA mW mW mW dB V kΩ mA V kΩ mA
Power Supply Rejection Ratio (1 kHz) VQ Nominal Voltage
Output Impedance Maximum allowable DC current source/sink Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink
Notes: 7. Power Down Mode is defined as RST = Low with all clocks and data lines held static. 8. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.
DIGITAL CHARACTERISTICS
Parameter
High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io = 100 μA Low-Level Output Voltage at Io = 100 μA OVFL Current Sink Input Leakage Current (all pins except SCLK and LRCK) Input Leakage Current (SCLK and LRCK) (% of VL) (% of VL) (% of VL) (% of VL)
Symbol
VIH VIL VOH VOL Iovfl Iin Iin
Min
70% 70% -10 -25
Typ
-
Max
30% 15% 4.0 10 25
Units
V V V V mA μA μA
THERMAL CHARACTERISTICS
Parameter
Allowable Junction Temperature Junction to Ambient Thermal Impedance (Multi-layer PCB) TSSOP (Multi-layer PCB) SOIC (Single-layer PCB) TSSOP (Single-layer PCB) SOIC
Symbol
Min
-
Typ
70 60 105 80
Max
135 -
Unit °C °C/W °C/W °C/W °C/W
θJA-TM θJA-SM θJA-TS θJA-SS
-
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DS565F2
CS5351 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF) Parameter
Output Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode
Symbol
Fs Fs Fs tsetup thold
Min
2 50 100 16/fsclk 1/fsclk -
Typ
740 680 50 50
Max
51 102 204 1953 60 20 32 -
Unit
kHz kHz kHz s s ms ms ns % ns ns %
OVFL to LRCK edge setup time OVFL to LRCK edge hold time OVFL time-out on overrange condition
Fs = 44.1, 88.2, 176.4 kHz Fs = 48, 96, 192 kHz
MCLK Specifications
MCLK Period MCLK Pulse Duty Cycle tclkw 38 40 tmslr tsdo -20 0 -
Master Mode
SCLK falling to LRCK SCLK falling to SDOUT valid SCLK Duty Cycle
Slave Mode Single-Speed
Output Sample Rate LRCK Duty Cycle SCLK Period SCLK Duty Cycle SCLK falling to SDOUT valid SCLK falling to LRCK edge tdss tslrd Fs tsclkw tdss tslrd Fs tsclkw tdss tslrd tsclkw Fs 2 40 153 45 -20 50 40 153 45 -20 100 40 77 45 -8 50 50 50 50 50 50 51 60 55 32 20 102 60 55 32 20 204 60 55 32 3 kHz % ns % ns ns kHz % ns % ns ns kHz % ns % ns ns
Double-Speed
Output Sample Rate LRCK Duty Cycle SCLK Period SCLK Duty Cycle SCLK falling to SDOUT valid SCLK falling to LRCK edge
Quad-Speed
Output Sample Rate LRCK Duty Cycle SCLK Period SCLK Duty Cycle SCLK falling to SDOUT valid SCLK falling to LRCK edge
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CS5351
SCLK output tmslr LRCK output tsdo SDOUT MSB MSB-1
CLK input t slrd LRCK input t dss SDOUT MSB MSB-1 MSB-2 tsclkw
Figure 13. Master Mode, Left-Justified SAI
Figure 14. Slave Mode, Left-Justified SAI
SCLK input t slrd LRCK input t dss SDOUT MSB MSB-1 tsclkw
SCLK input t slrd LRCK input t dss SDOUT MSB MSB-1 tsclkw
Figure 15. Master Mode, I²S SAI
Figure 16. Slave Mode, I²S SAI
LRCK t setup OVFL t hold
Figure 17. OVFL Output Timing
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CS5351
LRCK SCLK SDATA 23 22
Left Channel
Right Channel
9876543210
23 22
9876543210
23 22
Figure 18. Left-Justified Serial Audio Interface
LRCK SCLK SDATA 23 22
Left Channel
Right Channel
9876543210
23 22
9876543210
23 22
Figure 19. I²S Serial Audio Interface
LRCK
SCLK
O VFL
O VFL_R
O VFL_L
O VFL_R
Figure 20. OVFL Output Timing, I²S Format
LR CK
SCLK
OVFL
O VFL_R
O VFL_L
O VFL_R
Figure 21. OVFL Output Timing, Left-Justified Format
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CS5351 2. PIN DESCRIPTIONS
RST M/S LRCK SCLK MCLK VD GND VL SDOUT MDIV HPF I²S/LJ 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FILT+ REFGND VQ3 AINR VQ2 VA GND VQ1 AINL OVFL M1 M0
Pin Name RST M/S LRCK SCLK MCLK VD GND VL SDOUT MDIV HPF I²S/LJ M0 M1 OVFL AINL AINR VQ1 VQ2 VQ3 VA REF_GND FILT+
# 1 2 3 4 5 6 7 18 8 9 10 11 12 13 14 15 16 21 17 20 22 19 23 24
Pin Description Reset (Input) - The device enters a low power mode when low. Master/Slave Mode (Input) - Selects operation as either clock master or slave. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Digital Power (Input) - Positive power supply for the digital section. Ground (Input) - Ground reference. Must be connected to analog ground. Logic Power (Input) - Positive power for the digital input/output. Serial Audio Data Output (Output) - Output for two’s complement serial audio data. MCLK Divider (Input) - Enables a master clock divide by two function. High Pass Filter Enable (Input) - Enables the Digital High-Pass Filter. Serial Audio Interface Format Select (Input) -Selects either the Left-Justified or I²S format for the SAI. Mode Selection (Input) - Determines the operational mode of the device. Overflow (Output, open drain) - Detects an overflow condition on both left and right channels. Analog Inputs (Input) - The full-scale analog input level is specified in the Analog Characteristics specification table. Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. Analog Power (Input) - Positive power supply for the analog section. Reference Ground (Input) - Ground reference for the internal sampling circuits. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
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CS5351 3. TYPICAL CONNECTION DIAGRAM
+5 V to 3.3 V
1 μF
+
0.01 μF
*
0.01 μF 0.01 μF
+
1 μF
+5V to 2.5V
+5V
+
1 μF
0.01 μF VA
5.1 Ω VD
VL VL 10 kΩ OVFL RST I 2S/LJ M/S HPF M0 M1 MDIV
47 μF
+
FILT+ 0.01 μF REFGND
Analog Input Buffer (Figure 24)
AINL VQ1 VQ3 VQ2 AINR CS5351 A/D CONVERTER
Power Down and Mode Settings
SDOUT
Audio Data Processor
LRCK SCLK MCLK Timing Logic and Clock
GND
GND
* Resistor may only be used if VD is derived from VA. If used, do not drive any other logic from VD
Figure 22. Typical Connection Diagram
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CS5351 4. APPLICATIONS
4.1 Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2 kHz to 204 kHz. The CS5351 must be set to the proper speed mode via the mode pins, M1 and M0. Refer to Table 1. M1 (Pin 14) 0 0 1 1 M0 (Pin 13) 0 1 0 1 MODE
Single-Speed Mode Double-Speed Mode Quad-Speed Mode Reserved
Output Sample Rate (Fs)
2 kHz - 51 kHz 50 kHz - 102 kHz 100 kHz - 204 kHz
Table 1. CS5351 Mode Control
4.2
System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchronously generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks. The device also includes a master clock divider in Master Mode where the master clock will be internally divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV pin needs to be disabled, set to logic 0.
4.2.1
Slave Mode
LRCK and SCLK operate as inputs in Slave Mode. The left/right clock must be synchronously derived from the master clock and be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance. Refer to Table 2 for required clock ratios. Single-Speed Mode Fs = 2 kHz to 51 kHz Double-Speed Mode Fs = 50 kHz to 102 kHz
128x, 256x 32x, 64x
Quad-Speed Mode Fs = 100 kHz to 204 kHz
128x 32x, 64x
MCLK/LRCK Ratio SCLK/LRCK Ratio
256x, 512x 32x, 64x, 128x
Table 2. CS5351 Slave Mode Clock Ratios
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4.2.2 Master Mode
In Master Mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 23. Refer to Table 3 for common master clock frequencies.
÷ 256 ÷ 128 ÷ 64 ÷1 MCLK ÷2 1 ÷4 MDIV ÷2 ÷1 0
Single Speed Double Speed Quad Speed
00 01 10
LRCK Output (Equal to Fs)
M1
Single Speed Double Speed Quad Speed
M0
00 01 10
SCLK Output
Figure 23. CS5351 Master Mode Clocking
SAMPLE RATE (kHz)
32 44.1 48 64 88.2 96 176.4 192
MDIV = 0 MCLK (MHz)
8.192 11.2896 12.288 8.192 11.2896 12.288 11.2896 12.288
MDIV = 1 MCLK (MHz)
16.384 22.5792 24.576 16.384 22.5792 24.576 22.5792 24.576
Table 3. CS5351 Common Master Clock Frequencies
4.3
Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a delay between the release of reset and the generation of valid output due to the finite output impedance of FILT+ and the presence of the external capacitance.
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CS5351
4.4 Analog Connections
The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n × 6.144 MHz) the digital passband frequency, where n=0,1,2,...Refer to Figure 24 which shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity.
634 Ω 470 pF + 100 kΩ 100 kΩ
+
CS5351
91 Ω 2700 pF C0G
C0G
1 μF
AINL VQ1
1 μF 100 kΩ + 100 kΩ 1 μF 470 pF C0G 634 Ω 91 Ω
0.01 μF
VQ3
2700 pF C0G
VQ2 AINR
Figure 24. CS5351 Recommended Analog Input Buffer
4.5
High-Pass Filter and DC Offset Calibration
The operational amplifiers in the input circuitry driving the CS5351 may generate a small DC offset into the A/D converter. The CS5351 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: Running the CS5351 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. Disabling the high pass filter and freezing the stored DC offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS5351.
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4.6 Overflow Detection
The CS5351 includes overflow detection on both the left and right channels. This time multiplexed information is presented as open drain, active low on pin 15, OVFL. The OVFL_L and OVFL_R data will go to a logical low as soon as an overrange condition in either channel is detected. The data will remain low as specified in the Switching Characteristics - Serial Audio Port section. This ensures sufficient time to detect an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and OVFL_R data will return to a logical high if there has not been any other overrange condition detected. Please note that an overrange condition on either channel will restart the timeout period for both channels.
4.6.1
OVFL Output Timing
In Left-Justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I²S format, the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 23 and 24. In both cases the OVFL data can be easily demultiplexed by using the LRCK to latch the data. In left-justified format, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of LRCK would latch the left channel overflow status. In I²S format, the falling edge of LRCK would latch the right channel overflow status and the rising edge of LRCK would latch the left channel overflow status.
4.7
Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS5351 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 22 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.01 µF, must be positioned to minimize the electrical path from FILT+ and REFGND. The CDB5351 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
4.8
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5351’s in the system. If only one master clock source is needed, one solution is to place one CS5351 in Master Mode, and slave all of the other CS5351’s to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5351 reset with the inactive edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.
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CS5351 5. PARAMETER DEFINITIONS
Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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CS5351 6. PACKAGE DIMENSIONS 24L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1 b c D SEATING PLANE e A1 L A
∝
INCHES DIM A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.598 0.291 0.040 0.394 0.016 0° MAX 0.104 0.012 0.020 0.013 0.614 0.299 0.060 0.419 0.050 8°
∝
MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 15.20 15.60 7.40 7.60 1.02 1.52 10.00 10.65 0.40 1.27 0° 8°
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CS5351 24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1 SEATING PLANE A
E b2 SIDE VIEW
123
∝
L
e
END VIEW
TOP VIEW
DIM A A1 A2 b D E E1 e L µ
MIN -0.002 0.03346 0.00748 0.303 0.248 0.169 -0.020 0°
INCHES NOM -0.004 0.0354 0.0096 0.307 0.2519 0.1732 0.026 BSC 0.024 4°
MAX 0.043 0.006 0.037 0.012 0.311 0.256 0.177 -0.028 8°
MIN -0.05 0.85 0.19 7.70 6.30 4.30 -0.50 0°
MILLIMETERS NOM --0.90 0.245 7.80 6.40 4.40 0.65 BSC 0.60 4°
NOTE MAX 1.10 0.15 0.95 0.30 7.90 6.50 4.50 -0.70 8°
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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CS5351 7. REVISION HISTORY
Release
PP2 F1 Preliminary datasheet. Improve Gain Error specification under Analog Characteristics. Specify Full-scale Input Voltage in terms of VA under Analog Characteristics. Update Differential Input Impedance under Analog Characteristics. Increase maximum Power-Supply Current, IA, under DC Electrical Characteristics. Reduce maximum Power Consumption under DC Electrical Characteristics. Update FILT+ Output Impedance specification under DC Electrical Characteristics. Extend maximum Fs in Single-Speed Mode to 51 kHz. Extend maximum Fs in Double-Speed Mode to 102 kHz. Extend maximum Fs in Quad-Speed Mode to 204 kHz. Decrease maximum SCLK falling to LRCK edge specification in Quad-Speed Mode. Replace minimum MCLK high/low timing specifications with duty cycle specification. Replace minimum SCLK high/low timing specifications with duty cycle specification.
Changes
Replace recommended analog input buffer with new input buffer topology.
F2
Updated ordering information.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com.
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