CDBWM8973L-M-1

w WM8973L Stereo CODEC for Portable Audio Applications DESCRIPTION FEATURES The WM8973L is a low power, high quality stereo CODEC designed for portable digital audio applications.    The device integrates complete interfaces to stereo or mono microphones and a stereo headphone. External component requirements are drastically reduced as no separate microphone or headphone amplifiers are required. Advanced on-chip digital signal processing performs graphic equaliser, 3-D sound enhancement and automatic level control for the microphone or line input. The WM8973L can operate as a master or a slave, with various master clock frequencies including 12 or 24MHz for USB devices, or standard 256fs rates like 12.288MHz and 24.576MHz. Different audio sample rates such as 96kHz, 48kHz, 44.1kHz are generated directly from the master clock without the need for an external PLL. The WM8973L operates at supply voltages down to 1.8V, although the digital core can operate at voltages down to 1.42V to save power, and the maximum for all supplies is 3.6 Volts. Different sections of the chip can also be powered down under software control. The WM8973L is supplied in a very small and thin 5x5mm QFN package, ideal for use in hand-held and portable systems.          DAC SNR 98dB (‘A’ weighted), THD –84dB at 48kHz, 3.3V ADC SNR 95dB (‘A’ weighted), THD -82dB at 48kHz, 3.3V Complete Stereo / Mono Microphone Interface - Programmable ALC / Noise Gate On-chip 400mW BTL Speaker Driver (mono) On-chip Headphone Driver - >40mW output power on 16 / 3.3V - THD –80dB at 20mW, SNR 90dB with 16 load - No DC blocking capacitors required (capless mode) Separately mixed mono output Digital Graphic Equaliser Low Power - 7mW stereo playback (1.8V / 1.5V supplies) - 14mW record & playback (1.8V / 1.5V supplies) Low Supply Voltages - Analogue 1.8V to 3.6V - Digital core: 1.42V to 3.6V - Digital I/O: 1.8V to 3.6V 256fs / 384fs or USB master clock rates: 12MHz, 24MHz Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96kHz generated internally from master clock 5x5x0.9mm QFN package APPLICATIONS     MP3 Player / Recorder AAC/WMA/Multi-Format Player / Recorder Minidisc Player / Recorder Portable Digital Music Systems WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Production Data, December 2011, Rev 4.5 Copyright 2011 Wolfson Microelectronics plc WM8973L Production Data BLOCK DIAGRAM w PD, Rev 4.5, December 2011 2 WM8973L Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1  FEATURES ............................................................................................................ 1  APPLICATIONS..................................................................................................... 1  BLOCK DIAGRAM ................................................................................................ 2  TABLE OF CONTENTS ......................................................................................... 3  PIN CONFIGURATION .......................................................................................... 5  ORDERING INFORMATION .................................................................................. 5  PIN DESCRIPTION ................................................................................................ 6  ABSOLUTE MAXIMUM RATINGS ........................................................................ 7  RECOMMENDED OPERATION CONDITIONS ..................................................... 7  ELECTRICAL CHARACTERISTICS ..................................................................... 8  OUTPUT PGA’S LINEARITY ......................................................................................... 10  HEADPHONE OUTPUT THD VERSUS POWER .......................................................... 11  SPEAKER THD AND NOISE VERSUS POWER ........................................................... 12  POWER CONSUMPTION .................................................................................... 13  SIGNAL TIMING REQUIREMENTS .................................................................... 14  SYSTEM CLOCK TIMING .............................................................................................. 14  AUDIO INTERFACE TIMING – MASTER MODE .......................................................... 14  AUDIO INTERFACE TIMING – SLAVE MODE .............................................................. 15  INTERNAL POWER ON RESET CIRCUIT .......................................................... 18  DEVICE DESCRIPTION ...................................................................................... 19  INTRODUCTION ............................................................................................................ 19  INPUT SIGNAL PATH .................................................................................................... 19  AUTOMATIC LEVEL CONTROL (ALC) ......................................................................... 26  OUTPUT SIGNAL PATH ................................................................................................ 30  ANALOGUE OUTPUTS ................................................................................................. 35  ENABLING THE OUTPUTS ........................................................................................... 37  HEADPHONE SWITCH.................................................................................................. 37  THERMAL SHUTDOWN ................................................................................................ 39  HEADPHONE OUTPUT ................................................................................................. 39  DIGITAL AUDIO INTERFACE ........................................................................................ 40  AUDIO INTERFACE CONTROL .................................................................................... 44  CLOCKING AND SAMPLE RATES................................................................................ 46  CONTROL INTERFACE................................................................................................. 48  POWER SUPPLIES ....................................................................................................... 49  POWER MANAGEMENT ............................................................................................... 49  REGISTER MAP .................................................................................................. 52  DIGITAL FILTER CHARACTERISTICS .............................................................. 53  TERMINOLOGY ............................................................................................................. 53  DAC FILTER RESPONSES ........................................................................................... 54  ADC FILTER RESPONSES ........................................................................................... 55  DE-EMPHASIS FILTER RESPONSES .......................................................................... 56  HIGHPASS FILTER ....................................................................................................... 57  APPLICATIONS INFORMATION ........................................................................ 58  RECOMMENDED EXTERNAL COMPONENTS ............................................................ 58  LINE INPUT CONFIGURATION..................................................................................... 59  MICROPHONE INPUT CONFIGURATION .................................................................... 59  MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS.......................................... 59  POWER MANAGEMENT EXAMPLES ........................................................................... 60  w PD, Rev 4.5, December 2011 3 WM8973L Production Data IMPORTANT NOTICE ......................................................................................... 62  ADDRESS ...................................................................................................................... 62  REVISION HISTORY ........................................................................................... 63  w PD, Rev 4.5, December 2011 4 WM8973L Production Data PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8973CLGEFL/V -25C to +85C 32-lead QFN (5x5x0.9mm) (Pb-free) MSL3 260 C WM8973CLGEFL/RV -25C to +85C 32-lead QFN (5x5x0.9mm) (Pb-free, tape and reel) MSL3 260 C o o Note: Reel quantity = 3500 w PD, Rev 4.5, December 2011 5 WM8973L Production Data PIN DESCRIPTION PIN NO NAME 1 MCLK 2 TYPE DESCRIPTION Digital Input Master Clock DCVDD Supply Digital Core Supply 3 DBVDD Supply Digital Buffer (I/O) Supply 4 DGND Supply Digital Ground (return path for both DCVDD and DBVDD) 5 BCLK Digital Input / Output Audio Interface Bit Clock 6 DACDAT Digital Input DAC Digital Audio Data 7 DACLRC Digital Input / Output Audio Interface Left / Right Clock/Clock Out 8 ADCDAT Digital Output ADC Digital Audio Data 9 ADCLRC Digital Input / Output Audio Interface Left / Right Clock 10 MONOOUT Analogue Output Mono Output 11 OUT3 Analogue Output Analogue Output 3 (can be used as Headphone Pseudo Ground) 12 ROUT1 Analogue Output Right Output 1 (Line or Headphone) 13 LOUT1 Analogue Output Left Output 1 (Line or Headphone) 14 HPGND Supply Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2) 15 ROUT2 Analogue Output Right Output 1 (Line or Headphone or Speaker) 16 LOUT2 Analogue Output Left Output 1 (Line or Headphone or Speaker) 17 HPVDD Supply Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2, MONOUT) 18 AVDD Supply Analogue Supply 19 AGND Supply Analogue Ground (return path for both AVDD) 20 VREF Analogue Output Reference Voltage Decoupling Capacitor 21 VMID Analogue Output Midrail Voltage Decoupling Capacitor 22 MICBIAS Analogue Output Microphone Bias 23 RINPUT3 / HPDETECT Analogue Input Right Channel Input 3 or Headphone Plug-in Detection 24 LINPUT3 Analogue Input Left Channel Input 3 25 RINPUT2 Analogue Input Right Channel Input 2 26 LINPUT2 Analogue Input Left Channel Input 2 27 RINPUT1 Analogue Input Right Channel Input 1 28 LINPUT1 Analogue Input Left Channel Input 1 29 MODE Digital Input Control Interface Selection 30 CSB Digital Input Chip Select / Device Address Selection 31 32 SDIN SCLK Digital Input/Output Digital Input Control Interface Data Input / 2-wire Acknowledge output Control Interface Clock Input Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB. w PD, Rev 4.5, December 2011 6 WM8973L Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at 0.584fs -50 dB DAC Filter Type 1 (USB mode, 272fs or Normal mode operation) Passband +/- 0.03dB 0 -6dB 0.4535fs 0.5fs Passband Ripple +/- 0.03 Stopband dB 0.5465fs Stopband Attenuation f > 0.5465fs Table 46 Digital Filter Characteristics DAC FILTERS -50 dB ADC FILTERS Mode Group Delay Mode Group Delay 0 (250 USB) 11/FS 0 (250 USB) 13/FS 1 (256/272) 16/FS 1 (256/272) 23/FS 2 (250 USB, 96k mode) 4/FS 2 (250 USB, 96k mode) 4/FS 3 (256/272, 88.2/96k mode) 3/FS 3 (256/272, 88.2/96k mode) 5/FS Table 47 ADC/DAC Digital Filters Group Delay TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region w PD, Rev 4.5, December 2011 53 WM8973L Production Data DAC FILTER RESPONSES 0.02 0 0.01 0 Response (dB) Response (dB) -20 -40 -60 -0.01 -0.02 -0.03 -0.04 -80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 0.4 0.45 0.5 Figure 28 DAC Digital Filter Frequency Response – Type 0 Figure 29 DAC Digital Filter Ripple – Type 0 0.02 0 0.01 0 Response (dB) Response (dB) -20 -40 -60 -0.01 -0.02 -0.03 -0.04 -80 -0.05 -0.06 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 0 3 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 Figure 30 DAC Digital Filter Frequency Response – Type 1 Figure 31 DAC Digital Filter Ripple – Type 1 0.02 0 0.01 0 Response (dB) Response (dB) -20 -40 -60 -0.01 -0.02 -0.03 -0.04 -80 -0.05 -0.06 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 32 DAC Digital Filter Frequency Response – Type 2 Figure 33 DAC Digital Filter Ripple – Type 2 w PD, Rev 4.5, December 2011 54 WM8973L Production Data 0.25 0 0.2 0.15 -20 Response (dB) Response (dB) 0.1 -40 -60 0.05 0 -0.05 -0.1 -80 -0.15 -100 -0.25 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 34 DAC Digital Filter Frequency Response – Type 3 Figure 35 DAC Digital Filter Ripple – Type 3 ADC FILTER RESPONSES 0.04 0 0.03 0.02 Response (dB) Response (dB) -20 -40 -60 0.01 0 -0.01 -0.02 -80 -0.03 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 -0.04 3 0 Figure 36 ADC Digital Filter Frequency Response – Type 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 37 ADC Digital Filter Ripple – Type 0 0.02 0 0.01 0 Response (dB) Response (dB) -20 -40 -60 -0.01 -0.02 -0.03 -0.04 -80 -0.05 -0.06 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 Figure 38 ADC Digital Filter Frequency Response – Type 1 w 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 39 ADC Digital Filter Ripple – Type 1 PD, Rev 4.5, December 2011 55 WM8973L Production Data 0.25 0 0.2 0.15 -20 Response (dB) Response (dB) 0.1 -40 -60 0.05 0 -0.05 -0.1 -80 -0.15 -100 -0.25 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 Figure 40 ADC Digital Filter Frequency Response – Type 2 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 41 ADC Digital Filter Ripple – Type 2 0.25 0 0.2 0.15 -20 Response (dB) Response (dB) 0.1 -40 -60 0.05 0 -0.05 -0.1 -80 -0.15 -100 -0.25 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 0 3 Figure 42 ADC Digital Filter Frequency Response – Type 2 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 43 ADC Digital Filter Ripple – Type 3 DE-EMPHASIS FILTER RESPONSES 0.4 0 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -0.4 -10 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 Figure 44 De-emphasis Frequency Response (32kHz) w 16000 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000 Figure 45 De-emphasis Error (32kHz) PD, Rev 4.5, December 2011 56 WM8973L Production Data 0.4 0 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -0.4 -10 0 5000 10000 Frequency (Fs) 15000 0 20000 Figure 46 De-emphasis Frequency Response (44.1kHz) 5000 10000 Frequency (Fs) 15000 20000 15000 20000 Figure 47 De-emphasis Error (44.1kHz) 0.4 0 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -0.4 -10 0 5000 10000 Frequency (Fs) 15000 0 20000 Figure 48 De-emphasis Frequency Response (48kHz) 5000 10000 Frequency (Fs) Figure 49 De-emphasis Error (48kHz) HIGHPASS FILTER The WM8973L has a selectable digital highpass filter in the ADC filter path to remove DC offsets. The filter response is characterised by the following polynomial: H(z) = 1 - z-1 1 - 0.9995z-1 Response (dB) 0 -5 -10 -15 0 0.0005 0.001 Frequency (Fs) 0.0015 0.002 Figure 50 ADC Highpass Filter Response w PD, Rev 4.5, December 2011 57 WM8973L Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 51 Recommended External Components Diagram w PD, Rev 4.5, December 2011 58 WM8973L Production Data LINE INPUT CONFIGURATION When LINPUT1/RINPUT1 or LINPUT2/RINPUT2 are used as line inputs, the microphone boost and ALC functions should normally be disabled. In order to avoid clipping, the user must ensure that the input signal does not exceed AVDD. This may require a potential divider circuit in some applications. It is also recommended to remove RF interference picked up on any cables using a simple first-order RC filter, as high-frequency components in the input signal may otherwise cause aliasing distortion in the audio band. AC signals with no DC bias should be fed to the WM8973L through a DC blocking capacitor, e.g. 1F. MICROPHONE INPUT CONFIGURATION MICBIAS R1 680 Ohm to 2.2kOhm check microphone's specification FROM MICROPHONE C2 1uF LINPUT1/2/3 RINPUT1/2/3 AGND R2 47kOhm AGND C1 220pF AGND Figure 52 Recommended Circuit for Line Input For interfacing to a microphone, the ALC function should be enabled and the microphone boost switched on. Microphones held close to a speaker’s mouth would normally use the 13dB gain setting, while tabletop or room microphones would need a 29dB boost. The recommended application circuit is shown above. R1 and R2 form part of the biasing network (refer to Microphone Bias section). R1 connected to MICBIAS is necessary only for electret type microphones that require a voltage bias. R2 should always be present to prevent the microphone input from charging to a high voltage which may damage the microphone on connection. R1 and R2 should be large so as not to attenuate the signal from the microphone, which can have source impedance greater than 2kOhm. C1 together with the source impedance of the microphone and the WM8973L input impedance forms an RF filter. C2 is a DC blocking capacitor to allow the microphone to be biased at a different DC voltage to the MICIN signal. MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS To minimise any pop or click noise when the system is powered up or down, the following procedures are recommended. POWER UP  Switch on power supplies. By default the WM8973L is in Standby Mode, the DAC is digitally muted and the Audio Interface, Line outputs and Headphone outputs are all OFF (DACMU = 1 Power Management registers 1 and 2 are all zeros).   Enable Vmid and VREF. Enable DACs as required   Enable line and / or headphone output buffers as required. Set DACMU = 0 to soft-un-mute the audio DACs. POWER DOWN w   Set DACMU = 1 to soft-mute the audio DACs. Disable all output buffers.  Switch off the power supplies. PD, Rev 4.5, December 2011 59 WM8973L Production Data POWER MANAGEMENT EXAMPLES AINL/R POWER MANAGEMENT (1) VREF OPERATION MODE PGAs POWER MANAGEMENT (2) ADCs PGL PGR ADL DACs Output Buffers ADR MBI DAL DAR LO1 RO1 LO2 RO2 MO HPD Stereo Headphone Playback 1 0 0 0 0 0 0 1 1 1 1 0 0 0 x Stereo Line-in Record 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Stereo Microphone Record 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Mono Microphone Record 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 Stereo Line-in to Headphone Out 1 1 0 0 0 0 0 0 0 1 1 0 0 0 x Phone Call 1 1 1 0 0 0 1 0 0 1 1 0 0 1 x Speaker Phone Call [ROUT2INV = 1] 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 Record Phone Call [L channel = mic with boost, R channel = RX, enable mono mix] 1 1 1 1 1 1 1 0 0 1 1 0 0 1 x Table 48 Register Settings for Power Management w PD, Rev 4.5, December 2011 60 WM8973L Production Data PACKAGE DIMENSIONS FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH DM101.A D DETAIL 1 D2 32 25 L 1 24 4 EXPOSED GROUND 6 PADDLE INDEX AREA (D/2 X E/2) E2 17 E 8 2X 16 15 9 b B e 1 bbb M C A B 2X aaa C aaa C TOP VIEW BOTTOM VIEW ccc C A3 A 5 0.08 C C A1 SIDE VIEW SEATING PLANE M M 45° DETAIL 2 0.30 EXPOSED GROUND PADDLE DETAIL 1 W Exposed lead T A3 G H b Half etch tie bar DETAIL 2 Symbols A A1 A3 b D D2 E E2 e G H L T W MIN 0.80 0 0.18 3.30 3.30 0.30 Dimensions (mm) NOM MAX NOTE 0.90 1.00 0.02 0.05 0.203 REF 1 0.30 0.25 5.00 BSC 3.45 5.00 BSC 3.45 0.50 BSC 0.20 0.1 0.40 0.103 3.60 2 3.60 2 0.50 0.15 Tolerances of Form and Position aaa bbb ccc REF: 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VHHD-5. NOTES: 1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220, VARIATION VHHD-5. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002. 5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. 7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. w PD, Rev 4.5, December 2011 61 WM8973L Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. not liable for any unauthorised alteration of such information or for any reliance placed thereon. Wolfson is Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PD, Rev 4.5, December 2011 62 WM8973L Production Data REVISION HISTORY DATE REV ORIGINATOR CHANGES 06/12/11 4.5 JMacD Order codes changed from WM8973LGEFL/V and WM8973LGEFL/RV to WM8973CLGEFL/V and WM8973CLGEFL/RV to reflect change to copper wire bonding. 06/12/11 4.5 JMacD Package diagram changed to DM101.A 06/12/11 4.5 JMacD Important Notice updated w PD, Rev 4.5, December 2011 63