CDBWM8993-M-1

厂商：
CIRRUS(凌云)
封装：
描述：
EVAL BD - WM8993 MINI EVAL BOARD

数据手册：

下载CDBWM8993-M-1.pdf

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数据手册
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CDBWM8993-M-1 数据手册

WM8993 Audio Hub Codec for Multimedia Phones DESCRIPTION FEATURES The WM8993 is a highly integrated ultra-low power hi-fi CODEC designed for portable devices such as multimedia phones.    A stereo 1W/channel speaker driver can operate in class D or AB mode. Low leakage and high PSRR across the audio band enable direct battery connection for the speaker supply. Class W headphone drivers provide a dramatic reduction in playback power and are ground-referenced. Active ground loop noise rejection and DC offset correction help prevent pop noise and ground noise from degrading headphone output quality. Powerful mixing capability allows the device to support a huge range of architectures and use cases. A highly flexible input configuration supports multiple microphone or line inputs (mono or stereo, single-ended or differential). Fully differential internal architecture and on-chip RF noise filters ensure a very high degree of noise immunity. ReTuneTM Mobile parametric EQ with fully programmable coefficients is integrated for optimization of speaker characteristics. Programmable dynamic range control is also available for maximizing loudness, protecting speakers from clipping and preventing premature shutdown due to battery droop. The WM8993 is supplied in very small and thin 48-ball W-CSP package, ideal for portable systems.           APPLICATIONS  AVDD1 VMIDC AGND1 AVDD2 DCVDD DBVDD DGND 100dB SNR during DAC playback (‘A’ weighted) Low power, low noise MIC interface Class D or AB stereo speaker driver - Stereo1W into 8 BTL speaker at SPKVOL->SPKOUT) fs=48kHz DAC to Stereo Speaker D 8ohm (DAC->SPKMIX->SPKVOL->SPKOUT) fs=48kHz ADC Record ADC Record fs=48kHz (IN1LN/P & IN1RN/P->IN1L/IN1R->MIXIN->ADC) Analogue Bypass VRX to Earpiece 16ohm (VRXN/P->HPOUT2) AVDD1 (V) SPKVDD (V) AVDD2 (V) CPVDD (V) DBVDD (V) DCVDD (V) iAVDD1 iSPKVDD iAVDD2 (A) (A) (A) iCPVDD (A) iDBVDD iDCVDD (A) (A) TOTAL (mW) 0.0 0.0 0.0 0.0 0.0 2.7 3.7 4.2 5.0 5.5 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.000 0.000 0.000 0.000 0.000 0.392 0.451 0.514 0.627 0.795 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.001 0.002 0.002 0.003 0.004 2.24 3.0 3.3 2.24 3.0 3.3 2.24 3.0 3.3 2.7 5.0 5.5 2.7 5.0 5.5 2.7 5.0 5.5 1.71 1.8 2.0 1.71 1.8 2.0 1.71 1.8 2.0 1.71 1.8 2.0 1.71 1.8 2.0 1.71 1.8 2.0 1.62 1.8 3.6 1.62 1.8 3.6 1.62 1.8 3.6 1.08 1.2 2.0 1.08 1.2 2.0 1.08 1.2 2.0 4.711 5.919 6.410 4.801 5.673 6.186 4.663 5.737 6.409 0.631 1.463 1.987 0.576 1.454 1.942 0.761 1.467 1.975 4.059 4.215 4.423 23.707 23.977 24.657 23.701 24.029 24.564 4.352 4.223 4.243 4.223 4.251 4.523 3.988 4.132 4.451 4.545 6.352 38.094 4.454 6.359 38.016 6.872 9.075 48.040 0.972 1.015 1.619 0.998 1.045 1.585 201.000 225.000 420.000 0.035 0.053 0.190 0.068 0.088 0.229 0.288 0.362 1.103 2.24 3.0 3.3 2.24 3.0 3.3 2.24 3.0 3.3 2.7 5.0 5.5 2.7 5.0 5.5 2.7 5.0 5.5 1.71 1.8 2.0 1.71 1.8 2.0 1.71 1.8 2.0 1.71 1.8 2.0 1.71 1.8 2.0 1.71 1.8 2.0 1.62 1.8 3.6 1.62 1.8 3.6 1.62 1.8 3.6 1.08 1.2 2.0 1.08 1.2 2.0 1.08 1.2 2.0 (mA) 1.424 1.950 2.165 1.617 2.213 2.457 1.627 2.231 2.476 (mA) 0.000 0.001 0.002 6.083 9.098 10.237 0.577 1.078 1.202 (mA) 0.103 0.149 0.305 0.098 0.119 0.131 0.891 1.190 1.334 (mA) 0.908 1.248 2.637 0.004 0.004 0.004 0.004 0.004 0.005 (mA) 0.007 0.009 0.046 0.007 0.009 0.045 0.007 0.009 0.046 (mA) 0.796 0.888 1.594 0.768 0.857 1.538 0.773 0.863 1.547 (mW) 5.789 9.453 16.392 21.062 53.396 67.922 7.579 15.285 20.717 2.24 3.0 3.3 2.7 5.0 5.5 1.71 1.8 2.0 1.71 1.8 2.0 1.62 1.8 3.6 1.08 1.2 2.0 6.393 7.149 7.430 0.000 0.001 0.002 0.043 0.045 0.048 0.004 0.004 0.004 0.021 0.025 0.075 0.941 1.049 1.890 15.452 22.846 28.685 2.24 3.0 3.3 2.7 5.0 5.5 1.71 1.8 2.0 1.71 1.8 2.0 1.62 1.8 3.6 1.08 1.2 2.0 4.120 5.704 6.335 0.000 0.001 0.002 0.043 0.045 0.048 0.004 0.004 0.004 0.004 0.006 0.038 0.001 0.001 0.002 9.318 17.221 21.161 Notes: 1. Power in the load is included. 2. All figures are quoted at TA = 25°C. 3. All figures are quoted as quiescent current unless otherwise stated. Rev 4.1 24 MICBIAS2 MICBIAS1 GPIO GPIO REFERENCE GENERATOR MICBIAS Current Detect MICBIAS Current Detect IN1RP_TO_IN1R IN1RN_TO_IN1R IN2RP_TO_IN2R IN2RN_TO_IN2R IN2LP_TO_IN2L AVDD2 RXVOICE IN1R_ENA LRCLK IN1R IN1R_MUTE / IN1R_VOL[4:0] FLL + SYSCLK REC R AIFDAC_TDM AIFDAC_TDM_CHAN AIFADC_TDM AIFADC_TDM_CHAN AIF_WL[1:0] AIF_FMT[1:0] LOOPBACK AIFADCL_SRC AIFADCR_SRC ADCL_DATINV ADCR_DATINV ADCL_DAC_SVOL[3:0] ADCR_DAC_SVOL[3:0] ADC_VU ADCL_VOL[7:0] ADCR_VOL[7:0] LR RL A-law and -law Support TDM Support DIGITAL AUDIO INTERFACE + LR RL + MONO MIX AIFDACL_SRC AIFDACR_SRC DACL_DATINV DACR_DATINV IN1LP IN1LN IN2LN/GI7 DACR_TO_HPOUT1R HPOUT1R_MUTE_N HPOUT1R_VOL[5:0] + MIXOUTR_MUTE_N MIXOUTR_VOL[5:0] MIXOUTRVOL_ENA HPOUT1RVOL MIXOUTRVOL MIXOUTL_MUTE_N MIXOUTL_VOL[5:0] MIXOUTLVOL_ENA MIXOUTLVOL DACL_TO_HPOUT1L HPOUT1L_MUTE_N HPOUT1L_VOL[5:0] + HPOUT1LVOL CONTROL INTERFACE HPOUT1L SPKOUTLN SPKOUTLP DC Offset Correction Ground Loop Noise Rejection HPOUT1R HPOUT2N HPOUT2P + + Line Output Ground Loop Noise Rejection Feedback Headphone Ground Loop Noise Rejection Feedback LINEOUT2P_ENA LINEOUTFB HPOUT1FB Speaker Mono / Stereo Mode Select IN1L_TO_LINEOUT2P IN1R_TO_LINEOUT2P MIXOUTR_TO_LINEOUT2PLINEOUT2PMIX Ground Loop Noise Rejection Ground Loop Noise Rejection CHARGE PUMP LINEOUT2N_ENA MIXOUTR_TO_LINEOUT2N CPFB1 CPFB2 CPVOUTP CPVOUTN LINEOUT2P LINEOUT2_MODE LINEOUT2N_MUTE LINEOUT2P_MUTE LINEOUT2_VOL LINEOUT2N SPKOUTRN SPKOUTRP SPKMIXL_TO_SPKOUTR SPKMIXR_TO_SPKOUTR Direct Voice SPKOUTR_BOOST[2:0] VRX_TO_SPKOUTR SPKOUTRBOOST HPOUT1R_ENA LINEOUT1P VRX_TO_HPOUT2 Direct Voice DC Offset Correction Ground Loop Noise Rejection MIXOUTLVOL_TO_HPOUT2 MIXOUTRVOL_TO_HPOUT2 HPOUT2_ENA HPOUT2_MUTE HPOUT2_VOL HPOUT2_IN_ENA + HPOUT2MIX HPOUT1L_ENA LINEOUT1N LINEOUT1_MODE LINEOUT1N_MUTE LINEOUT1P_MUTE LINEOUT1_VOL VRX_TO_SPKOUTL Direct Voice Ground Loop Noise Rejection SPKOUTL_ENA + SPKMIXL_TO_SPKOUTL SPKMIXR_TO_SPKOUTL SPKOUTL_BOOST[2:0] SPKOUTLBOOST LINEOUT1P_ENA MIXOUTL_TO_LINEOUT1PLINEOUT1PMIX IN1L_TO_LINEOUT1P + IN1R_TO_LINEOUT1P MIXOUTR_TO_SPKMIXR / MIXOUTR_SPKMIXR_VOL SPKMIXR + SPKMIXR_VOL[1:0] DACR_TO_SPKMIXR / DACR_SPKMIXR_VOL SPKRVOL IN1RP_TO_SPKMIXR / IN1RP_SPKMIXR_VOL SPKOUTR_ENA + MIXINR_TO_SPKMIXR / MIXINR_SPKMIXR_VOL SPKOUTR_MUTE_N SPKOUTR_VOL[5:0] LINEOUT2NMIX SPKRVOL_ENA MIXOUTL_TO_LINEOUT2N REC R MIXOUTR_ENA MIXINR_TO_MIXOUTR / MIXINR_MIXOUTR_VOL[2:0] MIXOUTR MIXINL_TO_MIXOUTR / MIXINL_MIXOUTR_VOL[2:0] IN1R_TO_MIXOUTR / IN1R_MIXOUTR_VOL[2:0] IN1L_TO_MIXOUTR / IN1L_MIXOUTR_VOL[2:0] IN2RP_TO_MIXOUTR / IN2RP_MIXOUTR_VOL[2:0] + IN2RN_TO_MIXOUTR / IN2RN_MIXOUTR_VOL[2:0] IN2LN_TO_MIXOUTR / IN2LN_MIXOUTR_VOL[2:0] DACR_TO_MIXOUTR / DACR_MIXOUTR_VOL[2:0] Direct DAC R Direct DAC L MIXOUTL_ENA DACL_TO_MIXOUTL / DACL_MIXOUTL_VOL[2:0] MIXOUTL IN2LN_TO_MIXOUTL / IN2LN_MIXOUTL_VOL[2:0] IN2LP_TO_MIXOUTL / IN2LP_MIXOUTL_VOL[2:0] IN2RN_TO_MIXOUTL / IN2RN_MIXOUTL_VOL[2:0] IN1L_TO_MIXOUTL / IN1L_MIXOUTL_VOL[2:0] + IN1R_TO_MIXOUTL / IN1R_MIXOUTL_VOL[2:0] MIXINL_TO_MIXOUTL / MIXINL_MIXOUTL_VOL[2:0] MIXINR_TO_MIXOUTL / MIXINR_MIXOUTL_VOL[2:0] REC L + LINEOUT1N_ENA Ground Loop Noise Rejection Direct Voice LINEOUT1NMIX MIXOUTL_TO_LINEOUT1N MIXOUTR_TO_LINEOUT1N SPKLVOL_ENA SPKMIXL MIXINL_TO_SPKMIXL / MIXINL_SPKMIXL_VOL SPKMIXL_VOL[1:0] IN1LP_TO_SPKMIXL / IN1LP_SPKMIXL_VOL SPKLVOL DACL_TO_SPKMIXL / DACL_SPKMIXL_VOL + MIXOUTL_TO_SPKMIXL / MIXOUTL_SPKMIXL_VOL SPKOUTL_MUTE_N SPKOUTL_VOL[5:0] MIXINR MIXINL IN1R IN1L IN1RP IN1RN IN2RP/VRXP IN2RN/GI8 IN2LP/VRXN DAC_VU DACL_VOL[7:0] DACR_VOL[7:0] DAC_MUTE DAC_BOOST[1:0] DAC_MUTERATE DAC_UNMUTE_RAMP ADC_TO_DACL[1:0] ADC_TO_DACR[1:0] DEEMPH[1:0] DAC_COMP DAC_COMPMODE ADC_COMP ADC_COMPMODE ReTune Mobile Parametric Equalizer DAC R DACL_ENA DACR_ENA DAC L DAC_MONO DAC_SB_FILT Dynamic Range Contoller L/R SWAP Dynamic Range Contoller ADC_HPF ADC_HPF_CUT[1:0] Dynamic Range Control (DRC) available on ADC or DAC channels, not both. ADC R ADCL_ENA ADCR_ENA ADC L SPKVDD SPKGND MIXINR_ENA MIXINR + MIXINL REC L MIXINL_ENA MIXOUTL_MIXINL_VOL[2:0] IN2L_MUTE / IN2L_VOL[4:0] IN1L_TO_MIXINL / IN1L_MIXINL_VOL IN2L_TO_MIXINL / IN2L_MIXINL_VOL IN1LP_MIXINL_VOL[2:0] IN2L VRX_MIXINL_VOL[2:0] IN2L_ENA VRX_MIXINR_VOL[2:0] IN2R_MUTE / IN2R_VOL[4:0] IN1RP_MIXINR_VOL[2:0] IN2R_TO_MIXINR / IN2R_MIXINR_VOL IN1R_TO_MIXINR / IN1R_MIXINR_VOL IN2R MIXOUTR_MIXINR_VOL[2:0] IN2R_ENA - + IN2LN_TO_IN2L IN1L IN1L_ENA - + IN1LP_TO_IN1L - + IN1LN_TO_IN1L IN1L_MUTE / IN1L_VOL[4:0] DBVDD DGND - + DCVDD - Rev 4.1 + IN1LN IN1LP IN2LN/GI7 IN2LP/VRXN IN2RN/GI8 IN2RP/VRXP IN1RN IN1RP WM8993 AUDIO SIGNAL PATHS DIAGRAM CPVDD CPGND SPKMONO SDAT SCLK GPIO1 ADCDAT DACDAT LRCLK BCLK MCLK AVDD1 VMIDC AGND 25 WM8993 SIGNAL TIMING REQUIREMENTS MASTER CLOCK tMCLKY MCLK tMCLKL tMCLKH Figure 2 Master Clock Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT (MCLK as input to FLL) 33.33 ns TMCLKY (FLL not used, MCLK_DIV = 1 40 ns (FLL not used, MCLK_DIV = 0 80 Master Clock Timing MCLK cycle time MCLK duty cycle 60:40 ns 40:60 (= TMCLKH : TMCLKL) Rev 4.1 26 WM8993 AUDIO INTERFACE TIMING MASTER MODE BCLK (Output) tDL LRCLK (Output) t DDA ADCDAT DACDAT t DST tDHT Figure 3 Audio Interface Timing - Master Mode Note that BCLK and LRCLK outputs can be inverted if required; Figure 3 shows the default, noninverted polarity of these signals. Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Master Mode LRCLK propagation delay from BCLK falling edge tDL 20 ns ADCDAT propagation delay from BCLK falling edge tDDA 20 ns DACDAT setup time to BCLK rising edge tDST 20 ns DACDAT hold time from BCLK rising edge tDHT 10 ns Note that the descriptions above assume non-inverted polarity of BCLK and LRCLK. Rev 4.1 27 WM8993 SLAVE MODE tBCY BCLK (input) tBCH tBCL LRCLK (input) tLRH tLRSU ADCDAT (output) tDD DACDAT (input) tDS tDH Figure 4 Audio Interface Timing - Slave Mode Note that BCLK and LRCLK inputs can be inverted if required; Figure 4 shows the default, noninverted polarity. Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set-up time to BCLK rising edge tLRSU 20 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ADCDAT propagation delay from BCLK falling edge tDD DACDAT set-up time to BCLK rising edge tDS Audio Interface Timing - Slave Mode ns 20 20 ns ns Note: BCLK period must always be greater than or equal to MCLK period. Note: the descriptions above assume non-inverted polarity of BCLK and LRCLK. Rev 4.1 28 WM8993 TDM MODE In TDM mode, it is important that two ADC devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8993 ADCDAT tri-stating at the start and end of the data transmission is described below. BCLK ADCDAT set-up time ADCDAT ADCDAT undriven (tri-state) ADCDAT release time ADCDAT valid (CODEC output) ADCDAT valid ADCDAT undriven (tri-state) Figure 5 Audio Interface Timing - TDM Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER CONDITIONS MIN TYP MAX UNIT Audio Data Timing Information ADCDAT setup time from BCLK falling edge ADCDAT release time from BCLK falling edge Rev 4.1 DCVDD =2.0V DBVDD = 3.6V 5 ns DCVDD = 1.08V DBVDD = 1.62V 15 ns DCVDD = 2.0V DBVDD = 3.6V 5 ns DCVDD = 1.08V DBVDD = 1.62V 15 ns 29 WM8993 CONTROL INTERFACE TIMING START STOP SCLK (input) t4 t3 t2 t1 t8 t7 t6 SDAT t9 t5 Figure 6 Control Interface Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN SCLK Frequency TYP MAX UNIT 400 kHz SCLK Low Pulse-Width t1 1300 ns SCLK High Pulse-Width t2 600 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 SDAT, SCLK Rise Time t6 300 ns SDAT, SCLK Fall Time t7 300 ns Setup Time (Stop Condition) t8 Data Hold Time t9 Pulse width of spikes that will be suppressed tps Rev 4.1 ns 600 0 ns 900 ns 5 ns 30 WM8993 DEVICE DESCRIPTION INTRODUCTION The WM8993 is a low power, high quality audio codec designed to interface with a wide range of processors and analogue components. A high level of mixed-signal integration in a very small 3.65 x 3.55mm footprint makes it ideal for portable applications such as mobile phones. Fully differential internal architecture and on-chip RF noise filters ensure a very high degree of noise immunity. Eight highly flexible analogue inputs allow interfacing to up to four microphone inputs (single-ended or differential), plus multiple stereo or mono line inputs. Connections to an external voice CODEC, FM radio, melody IC, line input, handset MIC and headset MIC are all fully supported. Signal routing to the output mixers and within the CODEC has been designed for maximum flexibility to support a wide variety of usage modes. A ‘Direct Voice’ path from a voice CODEC directly to the Speaker or Earpiece output drivers is included. Nine analogue output drivers are integrated, including a stereo pair of high power, high quality Class D/AB switchable speaker drivers; these can support 1W each in stereo mode, or can be coupled to support a 2W mono speaker output. A mono earpiece driver is provided, providing output from the output mixers or from the low-power differential ‘Direct Voice’ path. One pair of ground-reference headphone outputs is provided; these are powered from an integrated Charge Pump, enabling high quality, power efficient headphone playback without any requirement for DC blocking capacitors. A DC Servo circuit is available for DC offset correction, thereby suppressing pops and reducing power consumption. Four line outputs are provided, with multiple configuration options including 4 x single-ended output or 2 x differential outputs. The line outputs are suitable for output to a voice CODEC or an external speaker driver. They are also capable of driving ear speakers and stereo headsets. Ground loop feedback is available on the headphone outputs and the line outputs, providing rejection of noise on the ground connections. All outputs have integrated pop and click suppression features. Internal differential signal routing and amplifier configurations have been optimised to provide the lowest possible power consumption for a wide range of usage scenarios, including voice calls and music playback. The speaker drivers offer low leakage and high PSRR; this enables direct connection to a Lithium battery. The speaker drivers provide eight levels of AC and DC gain to allow output signal levels to be maximised for many commonly-used SPKVDD/AVDD1 combinations. The stereo ADCs and DACs are of hi-fi quality, using a 24-bit low-order oversampling architecture to deliver optimum performance. A flexible clocking arrangement supports mixed ADC and DAC sample rates, whilst an integrated ultra-low power FLL provides additional flexibility. A high pass filter is available in the ADC path for removing DC offsets and suppressing low frequency noise such as mechanical vibration and wind noise. A digital mixing path from the ADC to the DAC provides a sidetone of enhanced quality during voice calls. DAC soft mute and un-mute is available for pop-free music playback. The integrated Dynamic Range Controller (DRC) and ReTune Mobile 5-band parametric equaliser (EQ) provide further processing capability of the digital audio paths. The DRC provides compression and signal level control to improve the handling of unpredictable signal levels. ‘Anti-clip’ and ‘quick release’ algorithms improve intelligibility in the presence of transients and impulsive noises. The EQ provides the capability to tailor the audio path according to the frequency characteristics of an earpiece or loudspeaker, and/or according to user preferences. The WM8993 has a highly flexible digital audio interface, supporting a number of protocols, including I2S, DSP, MSB-first left/right justified, and can operate in master or slave modes. PCM operation is supported in the DSP mode. A-law and -law companding are also supported. Time division multiplexing (TDM) is available to allow multiple devices to stream data simultaneously on the same bus, saving space and power. The system clock (CLK_SYS) provides clocking for the ADCs, DACs, DSP core, digital audio interface and other circuits. CLK_SYS can be derived directly from the MCLK pin or via an integrated FLL, providing flexibility to support a wide range of clocking schemes. Typical portable system MCLK frequencies, and sample rates from 8kHz to 48kHz are all supported. Automatic configuration of the clocking circuits is available, derived from the sample rate and from the MCLK / CLK_SYS ratio. The integrated FLL can be used as a free-running oscillator, enabling autonomous clocking of the Class D drivers, Headphone Charge Pump and DC Servo if required. (Note that hi-fi ADC / DAC operation requires an external crystal.) Rev 4.1 31 WM8993 The WM8993 uses a standard 2-wire control interface, providing full software control of all features, together with device register readback. An integrated Control Write Sequencer enables automatic scheduling of control sequences; commonly-used signal configurations may be selected using readyprogrammed sequences, including time-optimised control of the WM8993 pop suppression features. It is an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. Unused circuitry can be disabled under software control, in order to save power; low leakage currents enable extended standby/off time in portable battery-powered applications. Versatile GPIO functionality is provided, with support for button/accessory detect inputs, or for clock, system status, or programmable logic level output for control of additional external circuitry. Interrupt logic, status readback and de-bouncing options are supported within this functionality. Rev 4.1 32 WM8993 INPUT SIGNAL PATH The WM8993 has eight highly flexible analogue input channels, configurable in a large number of combinations: 1. Up to four fully differential or single-ended microphone inputs 2. Up to eight mono line inputs or 4 stereo line inputs 3. A dedicated mono differential input from external voice CODEC These inputs may be mixed together or independently routed to different combinations of output drivers. An internal record path is provided at the input mixers to allow DAC output to be mixed with the input signal path (e.g. for voice call recording). The WM8993 input signal paths and control registers are illustrated in Figure 7. IN1LN IN1LN IN1LP IN2LN/GI7 IN2LP/VRXN IN2RN/GI8 IN2RP/VRXP IN1RN IN1RP IN1LP IN2LN/GI7 IN2LP/VRXN IN2RN/GI8 IN2RP/VRXP IN1RN IN1RP IN1L IN1R MIXINL MIXINR RXVOICE + IN1L_MUTE / IN1L_VOL[4:0] IN1LN_TO_IN1L IN1LP_TO_IN1L IN1L MIXINL_ENA + IN1L_ENA MIXOUTL_MIXINL_VOL[2:0] IN2L_MUTE / IN2L_VOL[4:0] IN1L_TO_MIXINL / IN1L_MIXINL_VOL IN2L_TO_MIXINL / IN2L_MIXINL_VOL IN1LP_MIXINL_VOL[2:0] IN2L VRX_MIXINL_VOL[2:0] IN2L_ENA VRX_MIXINR_VOL[2:0] IN2R_MUTE / IN2R_VOL[4:0] IN1RP_MIXINR_VOL[2:0] IN2R_TO_MIXINR / IN2R_MIXINR_VOL IN1R_TO_MIXINR / IN1R_MIXINR_VOL IN2R MIXOUTR_MIXINR_VOL[2:0] IN2R_ENA IN2LN_TO_IN2L REC L - IN2LP_TO_IN2L + + IN2RN_TO_IN2R ADC L MIXINL - IN2RP_TO_IN2R + + IN1R_MUTE / IN1R_VOL[4:0] IN1RN_TO_IN1R ADC R MIXINR MIXINR_ENA REC R - IN1RP_TO_IN1R IN1R + IN1R_ENA Buffered VMID reference Vref VMID_BUF_ENA Figure 7 Control Registers for Input Signal Path Rev 4.1 33 WM8993 MICROPHONE INPUTS Up to four microphones can be connected to the WM8993, either in single-ended or differential mode. A dedicated PGA is provided for each microphone input. Two low noise microphone bias circuits are provided, reducing the need for external components. For single-ended microphone inputs, the microphone signal is connected to the inverting input of the PGAs (IN1LN, IN2LN, IN1RN or IN2RN). The non-inverting inputs of the PGAs are internally connected to VMID in this configuration. The non-inverting input pins IN1LP, IN2LP, IN1RP and IN2RP are free to be used as line connections to the input or output mixers in this configuration. For differential microphone inputs, the non-inverted microphone signal is connected to the noninverting input of the PGAs (IN1LP, IN2LP, IN1RP or IN2RP), whilst the inverted (or ‘noisy ground’) signal is connected to the inverting input pins (IN1LN, IN2LN, IN1RN and IN2RN). The gain of the input PGAs is controlled via register settings, as defined in Table 4. Note that the input impedance of both inverting and non-inverting inputs changes with the input PGA gain setting, as described under “Electrical Characteristics”. See also the “Applications Information” for details of input resistance at all PGA Gain settings. The microphone input configurations are illustrated in Figure 8 and Figure 9. Note that any PGA input pin that is used in either microphone configuration is not available for use as a line input path at the same time. MICBIAS - IN1LP, IN2LP, IN1RP, IN2RP PGA To input mixers MIC IN1LN, IN2LN, IN1RN, IN2RN IN1LP, IN2LP, IN1RP, IN2RP - + MIC GND PGA + IN1LN, IN2LN, IN1RN, IN2RN To input mixers GND VMID VMID Line Input MICBIAS Figure 8 Single-Ended Microphone Input Figure 9 Differential Microphone Input MICROPHONE BIAS CONTROL There are two MICBIAS generators which provide low noise reference voltages suitable for biasing electret condenser (ECM) type microphones via an external resistor. Note that an external decoupling capacitor is also required on each of the MICBIAS outputs. A suitable capacitor must be connected whenever the associated MICBIAS output is enabled. Refer to the “Applications Information” section for recommended external components. The MICBIAS voltages can be enabled using the MICB1_ENA and MICB2_ENA control bits; the voltage of each can be selected using the MICB1_LVL and MICB2_LVL register bits as detailed in Table 1. REGISTER ADDRESS BIT R1 (01h) 5 Power Managem ent (1) LABEL MICB2_ENA DEFAULT 0b DESCRIPTION Microphone Bias 2 Enable 0 = OFF (high impedance output) 1 = ON 4 MICB1_ENA 0b Microphone Bias 1 Enable 0 = OFF (high impedance output) 1 = ON Rev 4.1 34 WM8993 REGISTER ADDRESS BIT R58 (3Ah) 1 LABEL MICB2_LVL DEFAULT 0b MICBIAS DESCRIPTION Microphone Bias 2 Voltage Control 0 = 0.9 * AVDD1 1 = 0.65 * AVDD1 0 MICB1_LVL 0b Microphone Bias 1 Voltage Control 0 = 0.9 * AVDD1 1 = 0.65 * AVDD1 Table 1 Microphone Bias Control Note that the maximum source current capability for MICBIAS1 and MICBIAS2 is 2.4mA each. The external biasing resistance must be large enough to limit each MICBIAS current to 2.4mA across the full microphone impedance range. An external capacitor is required on MICBIAS1 and MICBIAS2 in order to ensure accuracy and stability of each regulator. The recommended capacitance is 4.7F in each case. See “Recommended External Components” for further details. Note that, if the MICBIAS1 or MICBIAS2 regulator is not enabled, then no external capacitor is required on the respective MICBIAS pin. MICROPHONE CURRENT DETECT A MICBIAS current detect function allows detection of accessories such as headset microphones. When the MICBIAS load current exceeds one of two programmable thresholds, (e.g. short circuit current or normal operating current), an interrupt or GPIO output can be generated. The current detection circuit is enabled by the JD_ENA bit; the current thresholds are selected by the JD_THR and JD_SCTHR register fields as described in Table 66. See “General Purpose Input/Output” for a full description of these fields. LINE AND VOICE CODEC INPUTS All eight analogue input pins may be used as line inputs. Each line input has different signal path options, providing flexibility, high performance and low power consumption for many different usage modes. IN1LN and IN1RN can operate as single-ended line inputs to the input PGAs IN1L and IN1R respectively. These inputs provide a high gain path if required for low input signal levels. IN2LN and IN2RN can operate as single-ended line inputs to the input PGAs IN2L and IN2R respectively, providing further high gain signal paths. These pins can also be connected to either of the output mixers MIXOUTL and MIXOUTR. IN1LP and IN1RP can operate as single-ended line inputs to the input mixers MIXINL and MIXINR, or to the speaker mixers SPKMIXL and SPKMIXR. These signal paths enable power consumption to be reduced, by allowing the input PGAs and other circuits to be disabled if not required. IN2LP/VRXN and IN2RP/VRXP can operate in three different ways:  Mono differential ’RXVOICE’ input (e.g. from an external voice CODEC) to the input mixers MIXINL and MIXINR.  Single-ended line inputs to either of the output mixers MIXOUTL and MIXOUTR.  Ultra-low power mono differential ‘Direct Voice’ input (e.g. from an external voice CODEC) to the ear speaker driver on HPOUT2, or to either of the speaker drivers on SPKOUTL and SPKOUTR. Signal path configuration to the input PGAs and input mixers is detailed later in this section. Signal path configuration to the output mixers and speaker mixers is described in “Output Signal Path”. Rev 4.1 35 WM8993 The line input and voice CODEC input configurations are illustrated in Figure 10 through to Figure 13. MIXOUTL/R Line Input IN1LN or IN1RN Line Input IN2LN, IN2RN MIXINL/R - PGA + PGA MIXINL/R + VMID VMID Figure 10 IN1LN or IN1RN as Line Inputs Figure 11 IN2LN or IN2RN as Line Inputs PGA IN2LP/VRXN or IN2RP/VRXP + + Line Input Line Input PGA IN1LP, IN1RP VMID ‘Direct Voice’ VMID ‘Rx Voice’ MIXINL/R Bypass SPKMIXL/R Figure 12 IN1LP or IN1RP as Line Inputs SPKOUTL/R or HPOUT2 MIXINL/R MIXOUTL/R Figure 13 IN2LP or IN2RP as Line Inputs INPUT PGA ENABLE The Input PGAs are enabled using register bits IN1L_ENA, IN2L_ENA, IN1R_ENA and IN2R_ENA, as described in Table 2. The Input PGAs must be enabled for microphone input on the respective input pins, or for line input on the inverting input pins IN1LN, IN1RN, IN2LN, IN2RN. REGISTER ADDRESS R2 (02h) Power Management (2) BIT 7 LABEL IN2L_ENA DEFAULT 0b DESCRIPTION IN2L Input PGA Enable 0 = Disabled 1 = Enabled 6 IN1L_ENA 0b IN1L Input PGA Enable 0 = Disabled 1 = Enabled 5 IN2R_ENA 0b IN2R Input PGA Enable 0 = Disabled 1 = Enabled 4 IN1R_ENA 0b IN1R Input PGA Enable 0 = Disabled 1 = Enabled Table 2 Input PGA Enable For normal operation of the input PGAs, the reference voltage VMID and the bias current must also be enabled. See “Reference Voltages and Master Bias” for details of the associated controls VMID_SEL and BIAS_ENA. Rev 4.1 36 WM8993 INPUT PGA CONFIGURATION Each of the Input PGAs can operate in a single-ended or differential mode. In differential mode, both inputs to the PGA are connected to the input source. In single-ended mode, the non-inverting input to the PGA must be connected to VMID. Configuration of the PGA inputs to the WM8993 input pins is controlled using the register bits shown in Table 3. Single-ended microphone operation is configured by connecting the input source to the inverting input of the applicable PGA. The non-inverting input of the PGA must be connected to the buffered VMID reference. Note that the buffered VMID reference must be enabled, using the VMID_BUF_ENA register, as described in “Reference Voltages and Master Bias”. Differential microphone operation is configured by connecting the input source to both inputs of the applicable PGA. Line inputs to the input pins IN1LN, IN2LN, IN1RN and IN2RN must be connected to the applicable PGA. The non-inverting input of the PGA must be connected to VMID. Line inputs to the input pins IN1LP, IN2LP, IN1RP or IN2RP do not connect to the input PGAs. The non-inverting inputs of the associated PGAs must be connected to VMID. The inverting inputs of the associated PGAs may be used as separate mic/line inputs if required. The maximum available attenuation on any of these input paths is achieved by using register bits shown in Table 3 to disconnect the input pins from the applicable PGA. REGISTER ADDRESS R40 (28h) BIT LABEL DEFAULT DESCRIPTION 7 IN2LP_TO_IN2L 0b IN2L PGA Non-Inverting Input Select 0 = Connected to VMID 1 = Connected to IN2LP Note that VMID_BUF_ENA must be set when using IN2L connected to VMID. 6 IN2LN_TO_IN2L 0b 5 IN1LP_TO_IN1L 0b IN2L PGA Inverting Input Select 0 = Not connected 1 = Connected to IN2LN IN1L PGA Non-Inverting Input Select 0 = Connected to VMID 1 = Connected to IN1LP Note that VMID_BUF_ENA must be set when using IN2L connected to VMID. 4 IN1LN_TO_IN1L 0b 3 IN2RP_TO_IN2R 0b 2 IN2RN_TO_IN2R 0b 1 IN1RP_TO_IN1R 0b 0 IN1RN_TO_IN1R 0b Input Mixer2 IN1L PGA Inverting Input Select 0 = Not connected 1 = Connected to IN1LN IN2R PGA Non-Inverting Input Select 0 = Connected to VMID 1 = Connected to IN2RP Note that VMID_BUF_ENA must be set when using IN2L connected to VMID. IN2R PGA Inverting Input Select 0 = Not connected 1 = Connected to IN2RN IN1R PGA Non-Inverting Input Select 0 = Connected to VMID 1 = Connected to IN1RP Note that VMID_BUF_ENA must be set when using IN2L connected to VMID. IN1R PGA Inverting Input Select 0 = Not connected 1 = Connected to IN1RN Table 3 Input PGA Configuration Rev 4.1 37 WM8993 INPUT PGA VOLUME CONTROL Each of the four Input PGAs has an independently controlled gain range of -16.5dB to +30dB in 1.5dB steps. The gains on the inverting and non-inverting inputs to the PGAs are always equal. Each Input PGA can be independently muted using the PGA mute bits as described in Table 4, with maximum mute attenuation achieved by simultaneously disconnecting the corresponding inputs described in Table 3. To prevent "zipper noise", a zero-cross function is provided on the input PGAs. When this feature is enabled, volume updates will not take place until a zero-crossing is detected. In the case of a long period without zero-crossings, a timeout function is provided. When the zero-cross function is enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. The timeout clock is enabled using TOCLK_ENA, the timeout period is set by TOCLK_RATE. See “Clocking and Sample Rates” for more information on these fields. The IN1_VU and IN2_VU bits control the loading of the input PGA volume data. When IN1_VU and IN2_VU are set to 0, the PGA volume data will be loaded into the respective control register, but will not actually change the gain setting. The IN1L and IN1R volume settings are both updated when a 1 is written to IN1_VU; the IN2L and IN2R volume settings are both updated when a 1 is written to IN2_VU. This makes it possible to update the gain of the left and right signal paths simultaneously. The Input PGA Volume Control register fields are described in Table 4 and Table 5. REGISTER ADDRESS R24 (18h) BIT 8 LABEL IN1_VU DEFAULT N/A Left Line Input 1&2 Volume DESCRIPTION Input PGA Volume Update Writing a 1 to this bit will cause IN1L and IN1R input PGA volumes to be updated simultaneously 7 IN1L_MUTE 1b IN1L PGA Mute 0 = Disable Mute 1 = Enable Mute 6 IN1L_ZC 0b IN1L PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 4:0 IN1L_VOL [4:0] 01011b IN1L Volume (0dB) -16.5dB to +30dB in 1.5dB steps IN2_VU N/A (See Table 5 for volume range) R25 (19h) 8 Left Line Input 3&4 Volume Input PGA Volume Update Writing a 1 to this bit will cause IN2L and IN2R input PGA volumes to be updated simultaneously 7 IN2L_MUTE 1b IN2L PGA Mute 0 = Disable Mute 1 = Enable Mute 6 IN2L_ZC 0b IN2L PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 4:0 IN2L_VOL [4:0] 01011b IN2L Volume (0dB) -16.5dB to +30dB in 1.5dB steps (See Table 5 for volume range) Rev 4.1 38 WM8993 REGISTER ADDRESS R26 (1Ah) BIT 8 LABEL IN1_VU DEFAULT N/A DESCRIPTION Input PGA Volume Update Right Line Input 1&2 Volume Writing a 1 to this bit will cause IN1L and IN1R input PGA volumes to be updated simultaneously 7 IN1R_MUTE 1b IN1R PGA Mute 0 = Disable Mute 1 = Enable Mute 6 IN1R_ZC 0b IN1R PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 4:0 IN1R_VOL [4:0] 01011b IN1R Volume (0dB) -16.5dB to +30dB in 1.5dB steps IN2_VU N/A (See Table 5 for volume range) R27 (1Bh) 8 Input PGA Volume Update Right Line Input 3&4 Volume Writing a 1 to this bit will cause IN2L and IN2R input PGA volumes to be updated simultaneously 7 IN2R_MUTE 1b IN2R PGA Mute 0 = Disable Mute 1 = Enable Mute 6 IN2R_ZC 0b IN2R PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 4:0 IN2R_VOL [4:0] 01011b IN2R Volume (0dB) -16.5dB to +30dB in 1.5dB steps (See Table 5 for volume range) Table 4 Input PGA Volume Control Rev 4.1 IN1L_VOL[4:0], IN2L_VOL[4:0], IN1R_VOL[4:0], IN2R_VOL[4:0] VOLUME 00000 -16.5 00001 -15.0 00010 -13.5 00011 -12.0 00100 -10.5 00101 -9.0 00110 -7.5 00111 -6.0 01000 -4.5 01001 -3.0 01010 -1.5 (dB) 01011 0 01100 +1.5 01101 +3.0 01110 +4.5 01111 +6.0 10000 +7.5 10001 +9.0 10010 +10.5 39 WM8993 IN1L_VOL[4:0], IN2L_VOL[4:0], IN1R_VOL[4:0], IN2R_VOL[4:0] VOLUME 10011 +12.0 10100 +13.5 10101 +15.0 10110 +16.5 10111 +18.0 11000 +19.5 11001 +21.0 11010 +22.5 11011 +24.0 11100 +25.5 11101 +27.0 11110 +28.5 11111 +30.0 (dB) Table 5 Input PGA Volume Range INPUT MIXER ENABLE The WM8993 has two analogue input mixers which allow the Input PGAs and Line Inputs to be combined in a number of ways and output to the ADCs, Output Mixers, or directly to the output drivers via bypass paths. The input mixers MIXINL and MIXINR are enabled by the MIXINL_ENA and MIXINR_ENA register bits, as described in Table 6. These control bits also enable the RXVOICE input path, described in the following section. REGISTER ADDRESS R2 (02h) BIT 9 LABEL MIXINL_ENA DEFAULT 0b Power Management (2) DESCRIPTION Left Input Mixer Enable (Enables MIXINL and RXVOICE input to MIXINL) 0 = Disabled 1 = Enabled 8 MIXINR_ENA 0b Right Input Mixer Enable (Enables MIXINR and RXVOICE input to MIXINR) 0 = Disabled 1 = Enabled Table 6 Input Mixer Enable INPUT MIXER CONFIGURATION AND VOLUME CONTROL The left and right channel input mixers MIXINL and MIXINR can be configured to take input from up to five sources: Rev 4.1 1. IN1L or IN1R Input PGA 2. IN2L or IN2R Input PGA 3. IN1LP or IN1RP pin (PGA bypass) 4. RXVOICE mono differential input from IN2LP/VRXN and IN2RP/VRXP 5. MIXOUTL or MIXOUTR Output Mixer (Record path) 40 WM8993 The Input Mixer configuration and volume controls are described in Table 7 for the Left input mixer (MIXINL) and Table 8 for the Right input mixer (MIXINR). The signal levels from the Input PGAs may be set to Mute, 0dB or 30dB boost. Gain controls for the PGA bypass, RXVOICE and Record paths provide adjustment from -12dB to +6dB in 3dB steps. To prevent pop noise, it is recommended that gain and mute controls for the input mixers are not modified while the signal paths are active. If volume control is required on these signal paths, it is recommended that this is implemented using the input PGA volume controls or the ADC volume controls. The ADC volume controls are described in the “Analogue to Digital Converter (ADC)” section. REGISTER ADDRESS BIT R41 (29h) 8 LABEL IN2L_TO_MIXINL DEFAULT 0b Input Mixer3 DESCRIPTION IN2L PGA Output to MIXINL Mute 0 = Mute 1 = Un-Mute 7 IN2L_MIXINL_VOL 0b IN2L PGA Output to MIXINL Gain 0 = 0dB 1 = +30dB 5 IN1L_TO_MIXINL 0b IN1L PGA Output to MIXINL Mute 0 = Mute 1 = Un-Mute 4 IN1L_MIXINL_VOL 0b IN1L PGA Output to MIXINL Gain 0 = 0dB 1 = +30dB 2:0 MIXOUTL_MIXINL_VOL 000b [2:0] (Mute) Record Path MIXOUTL to MIXINL Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB R43 (2Bh) 8:6 Input Mixer5 IN1LP_MIXINL_VOL 000b [2:0] (Mute) IN1LP Pin (PGA Bypass) to MIXINL Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 2:0 VRX_MIXINL_VOL 000b [2:0] (Mute) RXVOICE (VRXN/VRXP) Differential Input to MIXINL Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Table 7 Left Input Mixer (MIXINL) Volume Control Rev 4.1 41 WM8993 REGISTER ADDRESS BIT R42 (2A) 8 LABEL IN2R_TO_MIXINR DEFAULT 0b Input Mixer4 DESCRIPTION IN2R PGA Output to MIXINR Mute 0 = Mute 1 = Un-Mute 7 IN2R_MIXINR_VOL 0b IN2R PGA Output to MIXINR Gain 0 = 0dB 1 = +30dB 5 IN1R_TO_MIXINR 0b IN1R PGA Output to MIXINR Mute 0 = Mute 1 = Un-Mute 4 IN1R_MIXINR_VOL 0b IN1R PGA Output to MIXINR Gain 0 = 0dB 1 = +30dB 2:0 MIXOUTR_MIXINR_VOL 000b [2:0] (Mute) Record Path MIXOUTR to MIXINR Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB R44 (2Ch) 8:6 Input Mixer6 IN1RP_MIXINR_VOL 000b [2:0] (Mute) IN1RP Pin (PGA Bypass) to MIXINR Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 2:0 VRX_MIXINR_VOL 000b [2:0] (Mute) RXVOICE (VRXN/VRXP) Differential Input to MIXINR Gain and Mute 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Table 8 Right Input Mixer (MIXINR) Volume Control Rev 4.1 42 WM8993 ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8993 uses stereo 24-bit, 128x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. An oversample rate of 64x can also be supported - see “Clocking and Sample Rates” for details. The ADC full scale input level is proportional to AVDD1 - see “Electrical Characteristics”. Any input signal greater than full scale may overload the ADC and cause distortion. The ADCs are enabled by the ADCL_ENA and ADCR_ENA register bits. REGISTER ADDRESS R2 (02h) BIT LABEL DEFAULT 1 ADCL_ENA 0 Power Management (2) DESCRIPTION Left ADC Enable 0 = ADC disabled 1 = ADC enabled ADCR_ENA 0 0 Right ADC Enable 0 = ADC disabled 1 = ADC enabled Table 9 ADC Enable Control ADC DIGITAL VOLUME CONTROL The output of the ADCs can be digitally amplified or attenuated over a range from -71.625dB to +17.625dB in 0.375dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit code X is given by: 0.375  (X-192) dB for 1  X  239; MUTE for X = 0 +17.625dB for 239  X  255 The ADC_VU bit controls the loading of digital volume control data. When ADC_VU is set to 0, the ADCL_VOL or ADCR_VOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to ADC_VU. This makes it possible to update the gain of both channels simultaneously. REGISTER ADDRESS R15 (0Fh) BIT 8 LABEL ADC_VU DEFAULT N/A Left ADC Digital Volume DESCRIPTION ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously 7:0 ADCL_VOL [7:0] 1100_0000 (0dB) Left ADC Digital Volume 00h = MUTE 01h = -71.625dB … (0.375dB steps) EFh = +17.625dB (See Table 11 for volume range) R16 (10h) 8 ADC_VU N/A Right ADC Digital Volume ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously 7:0 ADCR_VOL [7:0] 1100_0000 (0dB) Right ADC Digital Volume 00h = MUTE 01h = -71.625dB … (0.375dB steps) EFh = +17.625dB (See Table 11 for volume range) Table 10 ADC Digital Volume Control Rev 4.1 43 WM8993 ADCL_VOL or ADCL_VOL or ADCL_VOL or ADCL_VOL or ADCR_VOL Volume (dB) ADCR_VOL Volume (dB) ADCR_VOL Volume (dB) ADCR_VOL Volume (dB) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh 0.000 0.375 0.750 1.125 1.500 1.875 2.250 2.625 3.000 3.375 3.750 4.125 4.500 4.875 5.250 5.625 6.000 6.375 6.750 7.125 7.500 7.875 8.250 8.625 9.000 9.375 9.750 10.125 10.500 10.875 11.250 11.625 12.000 12.375 12.750 13.125 13.500 13.875 14.250 14.625 15.000 15.375 15.750 16.125 16.500 16.875 17.250 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 Table 11 ADC Digital Volume Range Rev 4.1 44 WM8993 HIGH PASS FILTER A digital high pass filter is applied by default to the ADC path to remove DC offsets. This filter can also be programmed to remove low frequency noise in voice applications (e.g. wind noise or mechanical vibration). This filter is controlled using the ADC_HPF and ADC_HPF_CUT register bits. In hi-fi mode the high pass filter is optimised for removing DC offsets without degrading the bass response and has a cut-off frequency of 3.7Hz at fs=44.1kHz. In voice mode the high pass filter is optimised for voice communication and it is recommended to program the cut-off frequency below 300Hz (e.g. ADC_HPF_CUT=11 at fs=8kHz or ADC_HPF_CUT=10 at fs=16kHz). REGISTER ADDRESS BIT R14 (0Eh) 8 LABEL DEFAULT ADC_HPF 1 ADC CTRL DESCRIPTION ADC Digital High Pass Filter Enable 0 = disabled 1 = enabled 6:5 ADC_HPF_CUT [1:0] 00 ADC Digital High Pass Filter Cut-Off Frequency (fc) 00 = Hi-fi mode (fc=4Hz at fs=48kHz) 01 = Voice mode 1 (fc=127Hz at fs=16kHz) 10 = Voice mode 2 (fc=130Hz at fs=8kHz) 11 = Voice mode 3 (fc=267Hz at fs=8kHz) (Note: fc scales with sample rate. See Table 13 for cut-off frequencies at all supported sample rates) Table 12 ADC High Pass Filter Control Registers Sample Frequency (kHz) ADC_HPF_CUT =00 ADC_HPF_CUT =01 CUT-OFF FREQUENCY (Hz) ADC_HPF_CUT =10 ADC_HPF_CUT =11 8.000 0.7 64 130 267 11.025 0.9 88 178 367 16.000 1.3 127 258 532 22.050 1.9 175 354 733 24.000 2.0 190 386 798 32.000 2.7 253 514 1063 44.100 3.7 348 707 1464 48.000 4.0 379 770 1594 Table 13 ADC High Pass Filter Cut-Off Frequencies The high pass filter characteristics are shown in the "Digital Filter Characteristics" section. Rev 4.1 45 WM8993 DIGITAL MIXING The ADC and DAC data can be combined in various ways to support a range of different usage modes. Data from either of the two ADCs can be routed to either the left or the right channel of the digital audio interface. In addition, data from either of the digital audio interface channels can be routed to either the left or the right DAC. See "Digital Audio Interface" for more information on the audio interface. The WM8993 provides a Dynamic Range Control (DRC) feature, which can apply compression and gain adjustment in the digital domain to either the ADC or DAC signal path. This is effective in controlling signal levels under conditions where input amplitude is unknown or varies over a wide range. The DACs can be configured as a mono mix of the two audio channels. Digital sidetone from the ADCs can also be selectively mixed into the DAC output path. DIGITAL MIXING PATHS Figure 14 shows the digital mixing paths available in the WM8993 digital core. DAC L ADC L DACL_ENA DACR_ENA ADCL_ENA ADCR_ENA ADC_HPF ADC_HPF_CUT[1:0] DAC_SB_FILT DAC R ADC R Dynamic Range Control (DRC) available on ADC or DAC channels, not both. Dynamic Range Controller Dynamic Range Controller ReTune Mobile Parametric Equalizer ADC_VU ADCL_VOL[7:0] ADCR_VOL[7:0] MONO MIX DAC_MONO + ADC_TO_DACL[1:0] ADC_TO_DACR[1:0] + ADCL_DAC_SVOL[3:0] ADCR_DAC_SVOL[3:0] AIFADCL_SRC AIFADCR_SRC ADCL_DATINV ADCR_DATINV DAC_VU DACL_VOL[7:0] DACR_VOL[7:0] DAC_MUTE DAC_BOOST[1:0] DAC_MUTERATE DAC_UNMUTE_RAMP LR RL AIFDAC_TDM AIFDAC_TDM_CHAN AIFADC_TDM AIFADC_TDM_CHAN AIF_WL[1:0] AIF_FMT[1:0] LOOPBACK L/R SWAP DIGITAL AUDIO INTERFACE A-law and -law Support TDM Support LR RL AIFDACL_SRC AIFDACR_SRC DACL_DATINV DACR_DATINV DEEMPH[1:0] DAC_COMP DAC_COMPMODE ADC_COMP ADC_COMPMODE ADCDAT DACDAT LRCLK BCLK Figure 14 Digital Mixing Paths Rev 4.1 46 WM8993 The polarity of each ADC output signal can be changed under software control using the ADCL_DATINV and ADCR_DATINV register bits. The AIFADCL_SRC and AIFADCR_SRC register bits may be used to select which ADC is used for the left and right digital audio interface data. These register bits are described in Table 14. REGISTER ADDRESS BIT R4 (04h) 15 LABEL AIFADCL_SRC DEFAULT 0 Audio Interface (1) DESCRIPTION Left Digital Audio interface source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 14 AIFADCR_SRC 1 Right Digital Audio interface source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel R14 (0Eh) 1 ADCL_DATINV 0 ADC CTRL Left ADC Invert 0 = Left ADC output not inverted 1 = Left ADC output inverted 0 ADCR_DATINV 0 Right ADC Invert 0 = Right ADC output not inverted 1 = Right ADC output inverted Table 14 ADC Routing and Control The input data source for each DAC can be changed under software control using register bits AIFDACL_SRC and AIFDACR_SRC. The polarity of each DAC input may also be modified using register bits DACL_DATINV and DACR_DATINV. These register bits are described in Table 15. REGISTER ADDRESS BIT R5 (05h) 15 LABEL AIFDACL_SRC DEFAULT 0 Audio Interface (2) DESCRIPTION Left DAC Data Source Select 0 = Left DAC outputs left interface data 1 = Left DAC outputs right interface data 14 AIFDACR_SRC 1 Right DAC Data Source Select 0 = Right DAC outputs left interface data 1 = Right DAC outputs right interface data R10 (0Ah) 1 DACL_DATINV 0 DAC CTRL Left DAC Invert 0 = Left DAC output not inverted 1 = Left DAC output inverted 0 DACR_DATINV 0 Right DAC Invert 0 = Right DAC output not inverted 1 = Right DAC output inverted Table 15 DAC Routing and Control Rev 4.1 47 WM8993 DAC INTERFACE VOLUME BOOST A digital gain function is available at the audio interface to boost the DAC volume when a small signal is received on DACDAT. This is controlled using register bits DAC_BOOST[1:0]. To prevent clipping at the DAC input, this function should not be used when the boosted DAC data is expected to be greater than 0dBFS. REGISTER ADDRESS R5 (05h) BIT LABEL DEFAULT 11:10 DAC_BOOST [1:0] 00 Audio Interface (2) DESCRIPTION DAC Input Volume Boost 00 = 0dB 01 = +6dB (Input data must not exceed -6dBFS) 10 = +12dB (Input data must not exceed -12dBFS) 11 = +18dB (Input data must not exceed -18dBFS) Table 16 DAC Interface Volume Boost DIGITAL SIDETONE A digital sidetone is available when ADCs and DACs are operating at the same sample rate. Digital data from either left or right ADC can be mixed with the audio interface data on the left and right DAC channels. Sidetone data is taken from the ADC high pass filter output, to reduce low frequency noise in the sidetone (e.g. wind noise or mechanical vibration). When using the digital sidetone, it is recommended that the ADCs are enabled before un-muting the DACs to prevent pop noise. The DAC volumes and sidetone volumes should be set to an appropriate level to avoid clipping at the DAC input. The digital sidetone is controlled as shown in Table 17. REGISTER ADDRESS BIT R13 (0Dh) 12:9 Digital Side Tone LABEL ADCL_DAC_SVOL [3:0] DEFAULT 0000 DESCRIPTION Left Digital Sidetone Volume 0000 = -36dB 0001 = -33dB …. (3dB steps) 1011 = -3dB 1100 = 0dB (See Table 18 for volume range) 8:5 ADCR_DAC_SVOL [3:0] 0000 Right Digital Sidetone Volume 0000 = -36dB 0001 = -33dB …. (3dB steps) 1011 = -3dB 1100 = 0dB (See Table 18 for volume range) 3:2 ADCL_TO_DACL [1:0] 00 Left DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved 1:0 ADC_TO_DACR [1:0] 00 Right DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved Table 17 Digital Sidetone Control Rev 4.1 48 WM8993 ADCL_DAC_SVOL or ADCR_DAC_SVOL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SIDETONE VOLUME (dB) -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 0 0 0 Table 18 Digital Sidetone Volume DYNAMIC RANGE CONTROL (DRC) The dynamic range controller (DRC) is a circuit which can be enabled in the digital data path of either the ADCs or the DACs. The function of the DRC is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording from microphones built into a handheld system. The DRC can apply Compression and Automatic Level Control to the signal path. It incorporates ‘anti-clip’ and ‘quick release’ features for handling transients in order to improve intelligibility in the presence of loud impulsive noises. The DRC is enabled as shown in Table 19. It can be enabled in the ADC digital path or in the DAC digital path, under the control of the DRC_DAC_PATH register bit. Note that the DRC can only be active in one of these paths at any time. REGISTER ADDRESS R123 (7Bh) BIT 15 LABEL DRC_ENA DEFAULT 0 DRC Control 1 DESCRIPTION DRC enable 0 = disabled 1 = enabled 14 DRC_DAC_PAT H 0 DRC path select 0 = ADC path 1 = DAC path Table 19 DRC Enable COMPRESSION/LIMITING CAPABILITIES The DRC supports two different compression regions, specified by R0 and R1, separated by a “knee” at input amplitude T. For signals above the knee, the compression slope R0 applies; for signals below the knee, the compression slope R1 applies. The overall DRC compression characteristic in “steady state” (i.e. where the input amplitude is nearconstant) is illustrated in Figure 15. Rev 4.1 49 WM8993 DRC Output Amplitude (dB) (Y0) “knee” R0 YT R1 T 0dB DRC Input Amplitude (dB) Figure 15 DRC Compression Characteristic The slope of R0 and R1 are determined by register fields DRC_R0_SLOPE_COMP and DRC_R1_SLOPE_COMP respectively. A slope of 1 indicates constant gain in this region. A slope less than 1 represents compression (i.e. a change in input amplitude produces only a smaller change in output amplitude). A slope of 0 indicates that the target output amplitude is the same across a range of input amplitudes; this is infinite compression. The “knee” in Figure 15 is represented by T and Y, which are determined by register fields DRC_THRESH_COMP and DRC_AMP_COMP respectively. Parameter Y0, the output level for a 0dB input, is not specified directly, but can be calculated from the other parameters, using the equation Y0 = YT – (T * R0) The DRC Compression parameters are defined in Table 20. REGISTER ADDRESS R124 (7Ch) DRC Control 2 BIT LABEL DEFAULT 7:2 DRC_THRESH_ COMP [5:0] 000000 DESCRIPTION Compressor threshold T (dB) 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB … (-0.75dB steps) 111100 = -45dB 111101 = Reserved 11111X = Reserved Rev 4.1 50 WM8993 REGISTER ADDRESS R125 (7Dh) BIT 15:11 DRC Control 3 LABEL DRC_AMP_CO MP [4:0] DEFAULT DESCRIPTION 00000 Compressor amplitude at threshold YT (dB) 00000 = 0dB 00001 = -0.75dB 00010 = -1.5dB … (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved 10:8 DRC_R0_SLOP E_COMP [2:0] 100 Compressor slope R0 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = Reserved 111 = Reserved R126 (7Eh) 15:13 DRC Control 4 DRC_R1_SLOP E_COMP [2:0] 000 Compressor slope R1 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = Reserved 11X = Reserved Table 20 DRC Compression Control GAIN LIMITS The minimum and maximum gain applied by the DRC is set by register fields DRC_MINGAIN and DRC_MAXGAIN. These limits can be used to alter the DRC response from that illustrated in Figure 15. If the range between maximum and minimum gain is reduced, then the extent of the dynamic range control is reduced. The maximum gain prevents quiet signals (or silence) from being excessively amplified. REGISTER ADDRESS R123 (7Bh) BIT 3:2 DRC Control 1 LABEL DRC_MINGAIN [1:0] DEFAULT 00 DESCRIPTION Minimum gain the DRC can use to attenuate audio signals 00 = 0dB (default) 01 = -6dB 10 = -12dB 11 = -18dB 1:0 DRC_MAXGAIN [1:0] 01 Maximum gain the DRC can use to boost audio signals 00 = 12dB 01 = 18dB (default) 10 = 24dB 11 = 36dB Table 21 DRC Gain Limits Rev 4.1 51 WM8993 DYNAMIC CHARACTERISTICS The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note that the DRC responds to the average (RMS) signal amplitude over a period of time. The DRC_ATTACK_RATE determines how quickly the DRC gain decreases when the signal amplitude is high. The DRC_DECAY_RATE determines how quickly the DRC gain increases when the signal amplitude is low. These register fields are described in Table 22. For general purpose microphone use, the settings DRC_ATTACK_RATE = 0100 and DRC_DECAY_RATE = 0010 are suitable for many applications. Note that the default setting of DRC_ATTACK_RATE is Reserved and should not be used. REGISTER ADDRESS R124 (7Ch) BIT LABEL DEFAULT 15:12 DRC_ATTACK_ RATE [3:0] 0000 DRC Control 2 DESCRIPTION Gain attack rate (seconds/6dB) 0000 = Reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100-1111 = Reserved 11:8 DRC_DECAY_R ATE [3:0] 0000 Gain decay rate (seconds/6dB) 0000 = 186ms 0001 = 372ms 0010 = 743ms 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0111 = 23.78s 1000 = 47.56s 1001-1111 = Reserved Table 22 DRC Time Constants ANTI-CLIP CONTROL The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip feature is enabled using the DRC_ANTICLIP_ENA bit. Note that the feed-forward processing increases the latency in the input signal path. For low-latency applications (e.g. telephony), it may be desirable to reduce the delay, although this will also reduce the effectiveness of the anti-clip feature. The latency is determined by the DRC_FF_DELAY bit. If necessary, the latency can be minimised by disabling the anti-clip feature altogether. The DRC Anti-Clip control bits are described in Table 23. Rev 4.1 52 WM8993 REGISTER ADDRESS BIT LABEL DEFAULT R125 (7Dh) DRC Control 3 7 DRC_FF_DELAY 1 DESCRIPTION Feed-forward delay for anti-clip feature 0 = 5 samples 1 = 9 samples Time delay can be calculated as 5/fs or 9/ fs, where fs is the sample rate. R123 (7Bh) DRC Control 1 9 DRC_ANTICLIP_ ENA 1 Anti-clip enable 0 = disabled 1 = enabled Table 23 DRC Anti-Clip Control Note that the Anti-Clip feature operates entirely in the digital domain. It cannot be used to prevent signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be prevented by reducing the analogue signal gain or by adjusting the source signal. QUICK RELEASE CONTROL The DRC includes a Quick-Release feature to handle short transient peaks that are not related to the intended source signal. For example, in handheld microphone recording, transient signal peaks sometimes occur due to user handling, key presses or accidental tapping against the microphone. The Quick Release feature ensures that these transients do not cause the intended signal to be masked by the longer time constants of DRC_DECAY_RATE. The Quick-Release feature is enabled by setting the DRC_QR_ENA bit. When this bit is enabled, the DRC measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a transient peak that may not be related to the intended source signal. If the crest factor exceeds the level set by DRC_THRESH_QR, then the normal decay rate (DRC_DECAY_RATE) is ignored and a faster decay rate (DRC_RATE_QR) is used instead. The DRC Quick-Release control bits are described in Table 24. REGISTER ADDRESS R123 (7Bh) BIT 10 LABEL DRC_QR_ENA DEFAULT 1 DRC Control 1 DESCRIPTION Quick release enable 0 = disabled 1 = enabled R125 (7Dh) 3:2 DRC Control 3 DRC_THRESH_ QR [1:0] 01 Quick release crest factor threshold 00 = 12dB 01 = 18dB (default) 10 = 24dB 11 = 30dB 1:0 DRC_RATE_QR [1:0] 00 Quick release decay rate (seconds/6dB) 00 = 0.725ms (default) 01 = 1.45ms 10 = 5.8ms 11 = Reserved Table 24 DRC Quick-Release Control GAIN SMOOTHING The DRC includes a gain smoothing filter in order to prevent gain ripples. A programmable level of hysteresis is also used to control the DRC gain. This improves the handling of very low frequency input signals whose period is close to the DRC attack/decay time. DRC Gain Smoothing is enabled by default and it is recommended to use the default register settings. Rev 4.1 53 WM8993 The extent of the gain smoothing filter may be adjusted or disabled using the control fields described in Table 25. REGISTER ADDRESS R123 (7Bh) BIT LABEL DEFAULT 11 DRC_SMOOTH_ ENA 1 DRC_HYST_EN A 1 DRC_THRESH_ HYST [1:0] 01 DRC Control 1 DESCRIPTION Gain smoothing enable 0 = disabled 1 = enabled 8 Gain smoothing hysteresis enable 0 = disabled 1 = enabled 5:4 Gain smoothing hysteresis threshold 00 = Low 01 = Medium (recommended) 10 = High 11 = Reserved Table 25 DRC Gain Smoothing INITIALISATION When the DRC is initialised, the gain is set to the level determined by the DRC_STARTUP_GAIN register field. The default setting is 0dB, but values from -3dB to +6dB are available, as described in Table 26. REGISTER ADDRESS R126 (7Eh) DRC Control 4 BIT LABEL DEFAULT 12:8 DRC_STARTUP_ GAIN [4:0] 00110 DESCRIPTION Initial gain at DRC startup 00000 = -18dB 00001 = -15dB 00010 = -12dB 00011 = -9dB 00100 = -6dB 00101 = -3dB 00110 = 0dB (default) 00111 = 3dB 01000 = 6dB 01001 = 9dB 01010 = 12dB 01011 = 15dB 01100 = 18dB 01101 = 21dB 01110 = 24dB 01111 = 27dB 10000 = 30dB 10001 = 33dB 10010 = 36dB 10011 to 11111 = Reserved Table 26 DRC Initialisation Rev 4.1 54 WM8993 RETUNE MOBILE PARAMETRIC EQUALIZER (EQ) The ReTune Mobile Parametric EQ is a circuit which can be enabled in the DAC path. The function of the EQ is to adjust the frequency characteristic of the output in order to compensate for unwanted frequency characteristics in the loudspeaker (or other output transducer). It can also be used to tailor the response according to user preferences, for example to accentuate or attenuate specific frequency bands to emulate different sound profiles or environments e.g. concert hall, rock etc. The EQ is enabled as shown in Table 27. REGISTER ADDRESS R98 (62h) BIT 0 LABEL DEFAULT EQ_ENA DESCRIPTION EQ Enable 0b EQ1 0 = EQ disabled 1 = EQ enabled Table 27 ReTune Mobile Parametric EQ Enable The EQ can be configured to operate in two modes - “Default” mode or “ReTune Mobile” mode. DEFAULT MODE (5-BAND PARAMETRIC EQ) In default mode, the cut-off / centre frequencies are fixed as per Table 28. The filter bandwidths are also fixed in default mode. The gain of the individual bands (-12dB to +12dB) can be controlled as described in Table 29. Note that the cut-off / centre frequencies noted in Table 28 are applicable to a DAC Sample Rate of 48kHz. When using other sample rates, these frequencies will be scaled in proportion to the selected sample rate. EQ BAND CUT-OFF/CENTRE FREQUENCY 1 100 Hz 2 300 Hz 3 875 Hz 4 2400 Hz 5 6900 Hz Table 28 EQ Band Cut-off / Centre Frequencies REGISTER ADDRESS R99 (63h) BIT 4:0 EQ2 LABEL EQ_B1_GAIN [4:0] DEFAULT 01100b (0dB) DESCRIPTION EQ Band 1 Gain -12dB to +12dB in 1dB steps (see Table 30 for gain range) R100 (64h) 4:0 EQ3 EQ_B2_GAIN [4:0] 01100b (0dB) EQ Band 2 Gain -12dB to +12dB in 1dB steps (see Table 30 for gain range) R101 (65h) 4:0 EQ4 EQ_B3_GAIN [4:0] 01100b (0dB) EQ Band 3 Gain -12dB to +12dB in 1dB steps (see Table 30 for gain range) R102 (66h) 4:0 EQ5 EQ_B4_GAIN [4:0] 01100b (0dB) EQ Band 4 Gain -12dB to +12dB in 1dB steps (see Table 30 for gain range) R103 (67h) EQ6 4:0 EQ_B5_GAIN [4:0] 01100b (0dB) EQ Band 5 Gain -12dB to +12dB in 1dB steps (see Table 30 for gain range) Table 29 EQ Band Gain Control Rev 4.1 55 WM8993 EQ GAIN SETTING GAIN (DB) 00000 -12 00001 -11 00010 -10 00011 -9 00100 -8 00101 -7 00110 -6 00111 -5 01000 -4 01001 -3 01010 -2 01011 -1 01100 0 01101 +1 01110 +2 01111 +3 10000 +4 10001 +5 10010 +6 10011 +7 10100 +8 10101 +9 10110 +10 10111 +11 11000 +12 11001 to 11111 Reserved Table 30 EQ Gain Control RETUNE MOBILE MODE ReTune Mobile mode provides a comprehensive facility for the user to define the cut-off/centre frequencies and filter bandwidth for each EQ band, in addition to the gain controls already described. This enables the EQ to be accurately customised for a specific transducer characteristic or desired sound profile. The EQ enable and EQ gain controls are the same as defined for the default mode. The additional coefficients used in ReTune Mobile mode are held in registers R104 to R121. These coefficients are derived using tools provided in WISCE™ evaluation board control software. Please contact your local Cirrus Logic representative for more details. EQ FILTER CHARACTERISTICS The filter characteristics for each frequency band are shown in Figure 16 to Figure 20. These figures show the frequency response for all available gain settings, using default cut-off/centre frequencies and bandwidth. Rev 4.1 56 15 15 10 10 5 5 Gain (dB) Gain (dB) WM8993 0 0 -5 -5 -10 -10 -15 -15 1 10 100 1000 10000 100000 1 10 Frequency (Hz) 1000 10000 100000 Frequency (Hz) Figure 16 EQ Band 1 – Low Freq Shelf Filter Response Figure 17 EQ Band 2 – Peak Filter Response 15 15 10 10 5 5 Gain (dB) Gain (dB) 100 0 0 -5 -5 -10 -10 -15 -15 1 10 100 1000 10000 100000 Frequency (Hz) 1 10 100 1000 10000 100000 Frequency (Hz) Figure 18 EQ Band 3 – Peak Filter Response Figure 19 EQ Band 4 – Peak Filter Response 15 10 Gain (dB) 5 0 -5 -10 -15 1 10 100 1000 10000 100000 Frequency (Hz) Figure 20 EQ Band 5 – High Freq Shelf Filter Response Rev 4.1 57 WM8993 DIGITAL TO ANALOGUE CONVERTER (DAC) The WM8993 DACs receive digital input data from the DACDAT pin and via the digital sidetone path. The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion. The analogue outputs from the DACs can be mixed with analogue line/mic inputs using the line output mixers MIXOUTL / MIXOUTR and the speaker output mixers SPKMIXL / SPKMIXR. The DACs are enabled by the DACL_ENA and DACR_ENA register bits. Note that the CLK_DSP clock must be enabled and present whenever the DACs are enabled. See “Clocking and Sample Rates” for details of this clock. REGISTER ADDRESS R3 (03h) BIT LABEL DEFAULT 1 DACL_ENA 0 Power Management (3) DESCRIPTION Left DAC Enable 0 = DAC disabled 1 = DAC enabled 0 DACR_ENA 0 Right DAC Enable 0 = DAC disabled 1 = DAC enabled Table 31 DAC Enable Control DAC DIGITAL VOLUME CONTROL The output level of each DAC can be controlled digitally over a range from -71.625dB to 0dB in 0.375dB steps. The level of attenuation for an eight-bit code X is given by: 0.375  (X-192) dB for 1  X  192; MUTE for X = 0 0dB for 192  X  255 The DAC_VU bit controls the loading of digital volume control data. When DAC_VU is set to 0, the DACL_VOL or DACR_VOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to DAC_VU. This makes it possible to update the gain of both channels simultaneously. REGISTER ADDRESS R11 (0Bh) BIT 8 LABEL DAC_VU DEFAULT N/A Left DAC Digital Volume DESCRIPTION DAC Volume Update Writing 1 causes the left and right DAC volume to be updated simultaneously 7:0 DACL_VOL [7:0] 1100_0000 (0dB) Left DAC Digital Volume 00h = MUTE 01h = -71.625dB … (0.375dB steps) C0h = 0dB (See Table 33 for volume range) R12 (0Ch) 8 DAC_VU N/A Right DAC Digital Volume DAC Volume Update Writing 1 causes the left and right DAC volume to be updated simultaneously 7:0 DACR_VOL [7:0] 1100_0000 (0dB) Right DAC Digital Volume 00h = MUTE 01h = -71.625dB … (0.375dB steps) C0h = 0dB (See Table 33 for volume range) Table 32 DAC Digital Volume Control Rev 4.1 58 WM8993 DACL_VOL or DACL_VOL or DACL_VOL or DACL_VOL or DACR_VOL Volume (dB) DACR_VOL Volume (dB) DACR_VOL Volume (dB) DACR_VOL Volume (dB) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 Table 33 DAC Digital Volume Range Rev 4.1 59 WM8993 DAC SOFT MUTE AND SOFT UN-MUTE The WM8993 has a soft mute function which, when enabled, gradually attenuates the volume of the DAC output. When soft mute is disabled, the gain will either gradually ramp back up to the digital gain setting, or return instantly to the digital gain setting, depending on the DAC_UNMUTE_RAMP register bit. The DAC is soft-muted by default (DAC_MUTE = 1). To play back an audio signal, this function must first be disabled by setting DAC_MUTE to 0. Soft Mute Mode would typically be enabled (DAC_UNMUTE_RAMP = 1) when using DAC_MUTE during playback of audio data so that when DAC_MUTE is subsequently disabled, the sudden volume increase will not create pop noise by jumping immediately to the previous volume level (e.g. resuming playback after pausing during a track). Soft Mute Mode would typically be disabled (DAC_UNMUTE_RAMP = 0) when un-muting at the start of a music file, in order that the first part of the track is not attenuated (e.g. when starting playback of a new track, or resuming playback after pausing between tracks). DAC muting and un-muting using volume control bits DACL_VOL and DACR_VOL = 00000000 DACL_VOL or DACR_VOL = [non-zero] = [non-zero] DAC muting and un-muting using soft mute bit DAC_MUTE. Soft mute mode not enabled (DAC_UNMUTE_RAMP = 0). DAC_UNMUTE_RAMP = 0 DAC_MUTE = 0 DAC_MUTE = 1 DAC_MUTE = 0 DAC muting and un-muting using soft mute bit DAC_MUTE. Soft mute mode enabled (DAC_UNMUTE_RAMP = 1). DAC_UNMUTE_RAMP = 1 DAC_MUTE = 0 DAC_MUTE = 1 DAC_MUTE = 0 Figure 21 DAC Soft Mute Control The volume ramp rate during soft mute and un-mute is controlled by the DAC_MUTERATE bit. Ramp rates of fs/32 and fs/2 are selectable as shown in Table 34. The ramp rate determines the rate at which the volume will be increased or decreased. The actual ramp time depends on the extent of the difference between the muted and un-muted volume settings. Rev 4.1 60 WM8993 REGISTER ADDRESS R10 (0Ah) BIT LABEL DEFAULT DAC_MUTERATE 7 DESCRIPTION DAC Soft Mute Ramp Rate 0 DAC CTRL 0 = Fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = Slow ramp (fs/32, maximum ramp time is 171ms at fs=48k) (Note: ramp rate scales with sample rate.) DAC_UNMUTE_RAMP 6 DAC Unmute Ramp select 0 0 = Disabling soft-mute (DAC_MUTE=0) will cause the DAC volume to change immediately to DACL_VOL and DACR_VOL settings 1 = Disabling soft-mute (DAC_MUTE=0) will cause the DAC volume to ramp up gradually to the DACL_VOL and DACR_VOL settings DAC_MUTE 2 DAC Soft Mute Control 1 0 = DAC Un-mute 1 = DAC Mute Table 34 DAC Soft-Mute Control DAC MONO MIX A DAC digital mono-mix mode can be enabled using the DAC_MONO register bit. The mono mix is generated as the sum of the Left and Right channel DAC data. To prevent clipping, a -6dB attenuation is automatically applied to the mono mix. The mono mix is only supported when one or other DAC is disabled. If DACL_ENA and DACR_ENA are both set, then stereo operation applies. REGISTER ADDRESS BIT R10 (0Ah) 9 LABEL DEFAULT DAC_MONO 0 DAC CTRL DESCRIPTION DAC Mono Mix 0 = Disabled 1 = Enabled Only valid when one or other DAC is disabled. Table 35 DAC Mono Mix DAC DE-EMPHASIS Digital de-emphasis can be applied to the DAC playback data; this is appropriate when the data source is a CD where pre-emphasis is used in the recording. De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. See "Digital Filter Characteristics" section for details of de-emphasis filter characteristics. REGISTER ADDRESS R10 (0Ah) DAC CTRL BIT 5:4 LABEL DEEMPH [1:0] DEFAULT 00 DESCRIPTION DAC De-Emphasis Control 00 = No de-emphasis 01 = 32kHz sample rate 10 = 44.1kHz sample rate 11 = 48kHz sample rate Table 36 DAC De-Emphasis Control Rev 4.1 61 WM8993 DAC SLOPING STOPBAND FILTER Two DAC filter types are available, selected by the register bit DAC_SB_FILT. When operating at lower sample rates (e.g. during voice communication) it is recommended that the sloping stopband filter type is selected (DAC_SB_FILT=1) to reduce out-of-band noise which can be audible at low DAC sample rates. See "Digital Filter Characteristics" section for details of DAC filter characteristics. The DAC filter type is determined automatically by the WM8993 in Automatic Clocking Configuration mode. The DAC_SB_FILT register bit is only effective in Manual Clocking Configuration mode. See “Clocking and Sample Rates” for details of the Clocking Configuration mode selection. REGISTER ADDRESS R10 (0Ah) BIT 8 LABEL DAC_SB_FILT DAC CTRL DEFAULT 0 DESCRIPTION Selects DAC filter characteristics 0 = Normal mode 1 = Sloping stopband mode Note - this field is ignored and invalid in Automatic Clocking Configuration mode. Table 37 DAC Sloping Stopband Filter Rev 4.1 62 WM8993 OUTPUT SIGNAL PATH The WM8993 output routing and mixers provide a high degree of flexibility, allowing operation of many simultaneous signal paths through the device to a variety of analogue outputs. The outputs include a ground referenced headphone driver, two switchable class D/AB loudspeaker drivers, an ear speaker driver and four highly flexible line drivers. See “Analogue Outputs” for further details of these outputs. The WM8993 output signal paths and control registers are illustrated in Figure 22. IN1LN IN1LP IN2LN/GI7 IN2LP/VRXN IN2RN/GI8 IN2RP/VRXP IN1RN Direct Voice IN1RP LINEOUT1NMIX MIXOUTL_TO_LINEOUT1N MIXOUTR_TO_LINEOUT1N IN1L + IN1R LINEOUT1N MIXINL LINEOUT1N_ENA MIXINR Ground Loop Noise Rejection MIXOUTL_TO_LINEOUT1PLINEOUT1PMIX IN1L_TO_LINEOUT1P + IN1R_TO_LINEOUT1P MIXINL_TO_SPKMIXL / MIXINL_SPKMIXL_VOL IN1LP_TO_SPKMIXL / IN1LP_SPKMIXL_VOL DACL_TO_SPKMIXL / DACL_SPKMIXL_VOL MIXOUTL_TO_SPKMIXL / MIXOUTL_SPKMIXL_VOL SPKMIXL SPKMIXL_VOL[1:0] + SPKMIXL_TO_SPKOUTL SPKMIXR_TO_SPKOUTL SPKOUTL_BOOST[2:0] SPKOUTLBOOST Direct Voice VRX_TO_SPKOUTL SPKOUTLN SPKOUTLP + REC L DAC L Ground Loop Noise Rejection SPKLVOL SPKOUTL_MUTE_N SPKOUTL_VOL[5:0] DACL_TO_MIXOUTL / DACL_MIXOUTL_VOL[2:0] IN2LN_TO_MIXOUTL / IN2LN_MIXOUTL_VOL[2:0] IN2LP_TO_MIXOUTL / IN2LP_MIXOUTL_VOL[2:0] IN2RN_TO_MIXOUTL / IN2RN_MIXOUTL_VOL[2:0] IN1L_TO_MIXOUTL / IN1L_MIXOUTL_VOL[2:0] IN1R_TO_MIXOUTL / IN1R_MIXOUTL_VOL[2:0] MIXINL_TO_MIXOUTL / MIXINL_MIXOUTL_VOL[2:0] MIXINR_TO_MIXOUTL / MIXINR_MIXOUTL_VOL[2:0] LINEOUT1P LINEOUT1P_ENA SPKLVOL_ENA LINEOUT1_MODE LINEOUT1N_MUTE LINEOUT1P_MUTE LINEOUT1_VOL MIXOUTL SPKOUTL_ENA HPOUT1LVOL + HPOUT1L_ENA + HPOUT1L DACL_TO_HPOUT1L HPOUT1L_MUTE_N HPOUT1L_VOL[5:0] MIXOUTL_ENA DC Offset Correction Ground Loop Noise Rejection MIXOUTLVOL Direct Voice VRX_TO_HPOUT2 MIXOUTL_MUTE_N MIXOUTL_VOL[5:0] MIXOUTLVOL_ENA Direct DAC L HPOUT2MIX HPOUT2N HPOUT2P + Direct DAC R DAC R MIXINR_TO_MIXOUTR / MIXINR_MIXOUTR_VOL[2:0] MIXOUTR MIXINL_TO_MIXOUTR / MIXINL_MIXOUTR_VOL[2:0] IN1R_TO_MIXOUTR / IN1R_MIXOUTR_VOL[2:0] IN1L_TO_MIXOUTR / IN1L_MIXOUTR_VOL[2:0] IN2RP_TO_MIXOUTR / IN2RP_MIXOUTR_VOL[2:0] + IN2RN_TO_MIXOUTR / IN2RN_MIXOUTR_VOL[2:0] IN2LN_TO_MIXOUTR / IN2LN_MIXOUTR_VOL[2:0] DACR_TO_MIXOUTR / DACR_MIXOUTR_VOL[2:0] MIXOUTR_ENA MIXOUTRVOL MIXOUTR_MUTE_N MIXOUTR_VOL[5:0] MIXOUTRVOL_ENA HPOUT1RVOL MIXOUTLVOL_TO_HPOUT2 MIXOUTRVOL_TO_HPOUT2 HPOUT2_ENA HPOUT2_MUTE HPOUT2_IN_ENA HPOUT2_VOL HPOUT1R_ENA + DACR_TO_HPOUT1R HPOUT1R_MUTE_N HPOUT1R_VOL[5:0] REC R HPOUT1R DC Offset Correction Ground Loop Noise Rejection SPKMIXL_TO_SPKOUTR SPKMIXR_TO_SPKOUTR Direct Voice SPKOUTR_BOOST[2:0] VRX_TO_SPKOUTR SPKOUTRBOOST MIXOUTR_TO_SPKMIXR / MIXOUTR_SPKMIXR_VOL SPKMIXR + SPKMIXR_VOL[1:0] DACR_TO_SPKMIXR / DACR_SPKMIXR_VOL SPKRVOL IN1RP_TO_SPKMIXR / IN1RP_SPKMIXR_VOL SPKOUTR_ENA + MIXINR_TO_SPKMIXR / MIXINR_SPKMIXR_VOL SPKOUTR_MUTE_N SPKOUTR_VOL[5:0] LINEOUT2NMIX SPKRVOL_ENA MIXOUTL_TO_LINEOUT2N MIXOUTR_TO_LINEOUT2N + LINEOUT2N_ENA LINEOUT2N Ground Loop Noise Rejection MIXOUTR_TO_LINEOUT2PLINEOUT2PMIX IN1L_TO_LINEOUT2P + IN1R_TO_LINEOUT2P LINEOUT2P_ENA Headphone Ground Loop Noise Rejection Feedback Line Output Ground Loop Noise Rejection Feedback SPKOUTRN SPKOUTRP LINEOUT2_MODE LINEOUT2N_MUTE LINEOUT2P_MUTE LINEOUT2_VOL LINEOUT2P Ground Loop Noise Rejection HPOUT1FB LINEOUTFB Figure 22 Control Registers for Output Signal Path Rev 4.1 63 WM8993 OUTPUT SIGNAL PATHS ENABLE The output mixers and drivers can be independently enabled and disabled as described in Table 38. Note that the headphone outputs HPOUT1L and HPOUT1R have dedicated output PGAs and volume controls. As a result, a low power consumption DAC playback path can be supported without needing to enable the output mixers MIXOUTL / MIXOUTR or the mixer output PGAs MIXOUTLVOL / MIXOUTRVOL. REGISTER ADDRESS R1 (01h) BIT 13 LABEL SPKOUTR_ENA DEFAULT 0b Power Management (1) DESCRIPTION SPKMIXR Mixer, SPKRVOL PGA and SPKOUTR Output Enable 0 = Disabled 1 = Enabled 12 SPKOUTL_ENA 0b SPKMIXL Mixer, SPKLVOL PGA and SPKOUTL Output Enable 0 = Disabled 1 = Enabled 11 HPOUT2_ENA 0b HPOUT2 Output Stage Enable 0 = Disabled 1 = Enabled 9 HPOUT1L_ENA 0b Enables HPOUT1L input stage 0 = Disabled 1 = Enabled Note: When HPOUT1_AUTO_PU is set, the HPOUT1L_ENA bit automatically enables all stages of the left headphone driver 8 HPOUT1R_ENA 0b Enables HPOUT1R input stage 0 = Disabled 1 = Enabled Note: When HPOUT1_AUTO_PU is set, the HPOUT1R_ENA bit automatically enables all stages of the right headphone driver R3 (03h) 13 LINEOUT1N_ENA 0b Power Management (3) LINEOUT1N Line Out and LINEOUT1NMIX Enable 0 = Disabled 1 = Enabled 12 LINEOUT1P_ENA 0b LINEOUT1P Line Out and LINEOUT1PMIX Enable 0 = Disabled 1 = Enabled 11 LINEOUT2N_ENA 0b LINEOUT2N Line Out and LINEOUT2NMIX Enable 0 = Disabled 1 = Enabled 10 LINEOUT2P_ENA 0b LINEOUT2P Line Out and LINEOUT2PMIX Enable 0 = Disabled 1 = Enabled 9 SPKRVOL_ENA 0b SPKMIXR Mixer and SPKRVOL PGA Enable 0 = Disabled 1 = Enabled Note that SPKMIXR and SPKRVOL are also enabled when SPKOUTR_ENA is set. Rev 4.1 64 WM8993 REGISTER ADDRESS BIT 8 LABEL DEFAULT SPKLVOL_ENA 0b DESCRIPTION SPKMIXL Mixer and SPKLVOL PGA Enable 0 = Disabled 1 = Enabled Note that SPKMIXL and SPKLVOL are also enabled when SPKOUTL_ENA is set. 7 MIXOUTLVOL_ENA 0b MIXOUTL Left Volume Control Enable 0 = Disabled 1 = Enabled 6 MIXOUTRVOL_ENA 0b MIXOUTR Right Volume Control Enable 0 = Disabled 1 = Enabled 5 MIXOUTL_ENA 0b MIXOUTL Left Output Mixer Enable 0 = Disabled 1 = Enabled 4 MIXOUTR_ENA 0b MIXOUTR Right Output Mixer Enable 0 = Disabled 1 = Enabled R56 (38h) 6 HPOUT2_IN_ENA 0b AntiPOP1 HPOUT2MIX Mixer and Input Stage Enable 0 = Disabled 1 = Enabled Table 38 Output Signal Paths Enable HEADPHONE SIGNAL PATHS ENABLE The HPOUT1L and HPOUT1R output paths can be actively discharged to AGND through internal resistors if desired. This is desirable at start-up in order to achieve a known output stage condition prior to enabling the VMID reference voltage. This is also desirable in shutdown to prevent the external connections from being affected by the internal circuits. The HPOUT1L and HPOUT1R outputs are shorted to AGND by default; the short circuit is removed on each of these paths by setting the applicable fields HPOUT1L_RMV_SHORT or HPOUT1R_RMV_SHORT. The ground-referenced Headphone output drivers are designed to suppress pops and clicks when enabled or disabled. However, it is necessary to control the drivers in accordance with a defined sequence in start-up and shut-down to achieve the pop suppression. It is also necessary to schedule the DC Servo offset correction at the appropriate point in the sequence (see “DC Servo”). Table 39 and Table 40 describe the recommended sequences for enabling and disabling these output drivers. SEQUENCE Step 1 HEADPHONE ENABLE HPOUT1L_ENA = 1 HPOUT1R_ENA = 1 Step 2 20s delay Step 3 HPOUT1L_DLY = 1 HPOUT1R_DLY = 1 Step 4 DC offset correction Step 5 HPOUT1L_OUTP = 1 HPOUT1L_RMV_SHORT = 1 HPOUT1R_OUTP = 1 HPOUT1R_RMV_SHORT = 1 Table 39 Headphone Output Enable Sequence Rev 4.1 65 WM8993 SEQUENCE Step 1 HEADPHONE DISABLE HPOUT1L_RMV_SHORT = 0 HPOUT1L_DLY = 0 HPOUT1L_OUTP = 0 HPOUT1R_RMV_SHORT = 0 HPOUT1R_DLY = 0 HPOUT1R_OUTP = 0 Step 2 HPOUT1L_ENA = 0 HPOUT1R_ENA = 0 Table 40 Headphone Output Disable Sequence The sequences described above in Table 39 and Table 40 are implemented automatically by the WM8993 when the HPOUT1_AUTO_PU bit is set, which is the default condition. In this mode, the enable sequence is triggered by setting the HPOUT1L_ENA and HPOUT1R_ENA bits in register R1. Note that the Charge Pump is also enabled automatically in this mode. The register bits relating to pop suppression control are defined in Table 41. REGISTER ADDRESS R1 (01h) BIT 9 LABEL HPOUT1L_ENA DEFAULT 0b Power Management (1) DESCRIPTION Enables HPOUT1L input stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set as the first step of the HPOUT1L Enable sequence. Note: When HPOUT1_AUTO_PU is set, the HPOUT1L_ENA bit automatically enables all stages of the left headphone driver 8 HPOUT1R_ENA 0b Enables HPOUT1R input stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set as the first step of the HPOUT1R Enable sequence. Note: When HPOUT1_AUTO_PU is set, the HPOUT1R_ENA bit automatically enables all stages of the right headphone driver R96 (60h) 8 Analogue HP 0 HPOUT1_AUTO_ PU 1b Enables automatic power-up of HPOUT1 by monitoring HPOUT1L_ENA and HPOUT1R_ENA 0 = Disabled 1 = Enabled 7 HPOUT1L_RMV_ SHORT 0b Removes HPOUT1L short 0 = HPOUT1L short enabled 1 = HPOUT1L short removed For normal operation, this bit should be set as the final step of the HPOUT1L Enable sequence. 6 HPOUT1L_OUTP 0b Enables HPOUT1L output stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the DC offset cancellation has been scheduled. Rev 4.1 66 WM8993 REGISTER ADDRESS BIT 5 LABEL DEFAULT DESCRIPTION 0b Enables HPOUT1L intermediate stage HPOUT1L_DLY 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the output signal path has been configured, and before DC offset cancellation is scheduled. This bit should be set with at least 20us delay after HPOUT1L_ENA. 3 HPOUT1R_RMV_ SHORT Removes HPOUT1R short 0b 0 = HPOUT1R short enabled 1 = HPOUT1R short removed For normal operation, this bit should be set as the final step of the HPOUT1R Enable sequence. 2 HPOUT1R_OUTP Enables HPOUT1R output stage 0b 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the DC offset cancellation has been scheduled. 1 HPOUT1R_DLY Enables HPOUT1R intermediate stage 0b 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the output signal path has been configured, and before DC offset cancellation is scheduled. This bit should be set with at least 20us delay after HPOUT1R_ENA. Table 41 Pop Suppression Control OUTPUT MIXER CONTROL The Output Mixer path select and volume controls are described in Table 42 for the Left Channel (MIXOUTL) and Table 43 for the Right Channel (MIXOUTR). The gain of each of input path may be controlled independently in the range described in Table 44. The DAC input levels may also be controlled by the DAC digital volume control - see “Digital to Analogue Converter (DAC)” for further details. REGISTER ADDRESS R45 (2Dh) BIT 5 LABEL IN2RN_TO_MIXOUTL DEFAULT 0b Output Mixer1 DESCRIPTION IN2RN to MIXOUTL Mute 0 = Mute 1 = Un-mute R49 (31h) 8:6 Output Mixer5 IN2RN_MIXOUTL_VOL [2:0] 000b IN2RN to MIXOUTL Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) R45 (2Dh) 4 IN2LN_TO_MIXOUTL 0b Output Mixer1 IN2LN to MIXOUTL Mute 0 = Mute 1 = Un-mute R47 (2Fh) Output Mixer3 8:6 IN2LN_MIXOUTL_VOL [2:0] 000b IN2LN to MIXOUTL Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) Rev 4.1 67 WM8993 REGISTER ADDRESS R45 (2Dh) BIT 2 LABEL IN1L_TO_MIXOUTL DEFAULT 0b Output Mixer1 DESCRIPTION IN1L PGA Output to MIXOUTL Mute 0 = Mute 1 = Un-mute R47 (2Fh) 2:0 Output Mixer3 IN1L_MIXOUTL_VOL [2:0] 000b IN1L PGA Output to MIXOUTL Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) R45 (2Dh) 3 IN1R_TO_MIXOUTL 0 Output Mixer1 IN1R PGA Output to MIXOUTL Mute 0 = Mute 1 = Un-mute R47 (2Fh) 5:3 Output Mixer3 IN1R_MIXOUTL_VOL [2:0] 000b IN1R PGA Output to MIXOUTL Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) R45 (2Dh) 1 IN2LP_TO_MIXOUTL 0b Output Mixer1 IN2LP to MIXOUTL Mute 0 = Mute 1 = Un-mute R47 (2Fh) 11:9 Output Mixer3 IN2LP_MIXOUTL_VOL [2:0] 000b MIXINR_TO_MIXOUTL 0b IN2LP to MIXOUTL Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) R45 (2Dh) 7 Output Mixer1 MIXINR Output (Right ADC bypass) to MIXOUTL Mute 0 = Mute 1 = Un-mute R49 (31h) 5:3 Output Mixer5 MIXINR_MIXOUTL_VO L [2:0] 000b MIXINR Output (Right ADC bypass) to MIXOUTL Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) R45 (2Dh) 6 MIXINL_TO_MIXOUTL 0b Output Mixer1 MIXINL Output (Left ADC bypass) to MIXOUTL Mute 0 = Mute 1 = Un-mute R49 (31h) 2:0 Output Mixer5 MIXINL_MIXOUTL_VOL [2:0] 000b MIXINL Output (Left ADC bypass) to MIXOUTL Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) R45 (2Dh) 0 DACL_TO_MIXOUTL 0b Output Mixer1 Left DAC to MIXOUTL Mute 0 = Mute 1 = Un-mute R49 (31h) Output Mixer5 11:9 DACL_MIXOUTL_VOL [2:0] 000b Left DAC to MIXOUTL Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) Table 42 Left Output Mixer (MIXOUTL) Control Rev 4.1 68 WM8993 REGISTER ADDRESS R46 (2Eh) BIT 5 LABEL IN2LN_TO_MIXOUTR DEFAULT 0b Output Mixer2 R50 (32h) 8:6 IN2LN_MIXOUTR_VOL [2:0] 000b 4 IN2RN_TO_MIXOUTR 0b Output Mixer6 R46 (2Eh) Output Mixer2 R48 (30h) 8:6 Output Mixer4 R46 (2Eh) 3 IN2RN_MIXOUTR_VOL [2:0] IN1L_TO_MIXOUTR 000b 0b Output Mixer2 R48 (30h) 5:3 IN1L_MIXOUTR_VOL [2:0] 000b 2 IN1R_TO_MIXOUTR 0 Output Mixer4 R46 (2Eh) Output Mixer2 R48 (30h) 2:0 IN1R_MIXOUTR_VOL [2:0] 000b 1 IN2RP_TO_MIXOUTR 0b Output Mixer4 R46 (2Eh) Output Mixer2 R48 (30h) 11:9 IN2RP_MIXOUTR_VOL [2:0] 000b 7 MIXINL_TO_MIXOUTR 0b 5:3 MIXINL_MIXOUTR_VO L[2:0] 000b 6 MIXINR_TO_MIXOUTR 0b 2:0 MIXINR_MIXOUTR_VO L [2:0] 000b Output Mixer4 R46 (2Eh) Output Mixer2 R50 (32h) Output Mixer6 R46 (2Eh) Output Mixer2 R50 (32h) Output Mixer6 R46 (2Eh) 0 DACR_TO_MIXOUTR 0b Output Mixer2 R50 (32h) Output Mixer6 11:9 DACR_MIXOUTR_VOL [2:0] 000b DESCRIPTION IN2LN to MIXOUTR Mute 0 = Mute 1 = Un-mute IN2LN to MIXOUTR Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) IN2RN to MIXOUTR Mute 0 = Mute 1 = Un-mute IN2RN to MIXOUTR Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) IN1L PGA Output to MIXOUTR Mute 0 = Mute 1 = Un-mute IN1L PGA Output to MIXOUTR Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) IN1R PGA Output to MIXOUTR Mute 0 = Mute 1 = Un-mute IN1R PGA Output to MIXOUTR Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) IN2RP to MIXOUTR Mute 0 = Mute 1 = Un-mute IN2RP to MIXOUTR Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) MIXINL Output (Left ADC bypass) to MIXOUTR Mute 0 = Mute 1 = Un-mute MIXINL Output (Left ADC bypass) to MIXOUTR Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) MIXINR Output (Right ADC bypass) to MIXOUTR Mute 0 = Mute 1 = Un-mute MIXINR Output (Right ADC bypass) to MIXOUTR Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) Right DAC to MIXOUTR Mute 0 = Mute 1 = Un-mute Right DAC to MIXOUTR Volume 0dB to -21dB in 3dB steps (See Table 44 for Volume Range) Table 43 Right Output Mixer (MIXOUTR) Control Rev 4.1 69 WM8993 VOLUME SETTING VOLUME (dB) 000 0 001 -3 010 -6 011 -9 100 -12 101 -15 110 -18 111 -21 Table 44 MIXOUTL and MIXOUTR Volume Range SPEAKER MIXER CONTROL The Speaker Mixer path select and volume controls are described in Table 45 for the Left Channel (SPKMIXL) and Table 46 for the Right Channel (SPKMIXR). Care should be taken when enabling more than one path to a speaker mixer in order to avoid clipping. The gain of each input path is adjustable using a selectable -3dB control in each path to facilitate this. Each Speaker Mixer output is also controlled by an additional independent volume control. The DAC input levels may also be controlled by the DAC digital volume control - see “Digital to Analogue Converter (DAC)” for further details. REGISTER ADDRESS R54 (36h) BIT 7 LABEL MIXINL_TO_SPKMIXL DEFAULT 0b Speaker Mixer DESCRIPTION MIXINL (Left ADC bypass) to SPKMIXL Mute 0 = Mute 1 = Un-mute 5 IN1LP_TO_SPKMIXL 0b IN1LP to SPKMIXL Mute 0 = Mute 1 = Un-mute 3 MIXOUTL_TO_SPKMIX L 0b Left Mixer Output to SPKMIXL Mute 0 = Mute 1 = Un-mute 1 DACL_TO_SPKMIXL 0b Left DAC to SPKMIXL Mute 0 = Mute 1 = Un-mute R34 (22h) 5 MIXINL_SPKMIXL_VOL 0b SPKMIXL Attenuation MIXINL (Left ADC bypass) to SPKMIXL Fine Volume Control 0 = 0dB 1 = -3dB 4 IN1LP_SPKMIXL_VOL 0b IN1LP to SPKMIXL Fine Volume Control 0 = 0dB 1 = -3dB 3 MIXOUTL_SPKMIXL_V OL 0b Left Mixer Output to SPKMIXL Fine Volume Control 0 = 0dB 1 = -3dB 2 DACL_SPKMIXL_VOL 0b Left DAC to SPKMIXL Fine Volume Control 0 = 0dB 1 = -3dB Rev 4.1 70 WM8993 REGISTER ADDRESS BIT 1:0 LABEL DEFAULT DESCRIPTION 11b Left Speaker Mixer Volume Control SPKMIXL_VOL [1:0] 00 = 0dB 01 = -6dB 10 = -12dB 11 = mute Table 45 Left Speaker Mixer (SPKMIXL) Control REGISTER ADDRESS R54 (36h) BIT 6 LABEL MIXINR_TO_SPKMIXR DEFAULT 0b Speaker Mixer DESCRIPTION MIXINR (Right ADC bypass) to SPKMIXR Mute 0 = Mute 1 = Un-mute 4 IN1RP_TO_SPKMIXR 0b IN1RP to SPKMIXR Mute 0 = Mute 1 = Un-mute 2 MIXOUTR_TO_SPKMIX R 0b Right Mixer Output to SPKMIXR Mute 0 = Mute 1 = Un-mute 0 DACR_TO_SPKMIXR 0b Right DAC to SPKMIXR Mute 0 = Mute 1 = Un-mute R35 (22h) 5 MIXINR_SPKMIXR_VOL 0b SPKMIXR Attenuation MIXINR (Right ADC bypass) to SPKMIXR Fine Volume Control 0 = 0dB 1 = -3dB 4 IN1RP_SPKMIXR_VOL 0b IN1RP to SPKMIXR Fine Volume Control 0 = 0dB 1 = -3dB 3 MIXOUTR_SPKMIXR_V OL 0b Right Mixer Output to SPKMIXR Fine Volume Control 0 = 0dB 1 = -3dB 2 DACR_SPKMIXR_VOL 0b Right DAC to SPKMIXR Fine Volume Control 0 = 0dB 1 = -3dB 1:0 SPKMIXR_VOL [1:0] 11b Right Speaker Mixer Volume Control 00 = 0dB 01 = -6dB 10 = -12dB 11 = mute Table 46 Right Speaker Mixer (SPKMIXR) Control OUTPUT SIGNAL PATH VOLUME CONTROL There are six output PGAs - MIXOUTLVOL, MIXOUTRVOL, HPOUT1LVOL, HPOUT1RVOL, SPKLVOL and SPKRVOL. Each can be independently controlled, with MIXOUTLVOL and MIXOUTRVOL providing volume control to both the earpiece and line drivers, HPOUT1LVOL and HPOUT1RVOL to the headphone driver, and SPKLVOL and SPKRVOL to the speaker drivers. Rev 4.1 71 WM8993 The volume control of each of these output PGAs can be adjusted over a wide range of values. To minimise pop noise, it is recommended that only the MIXOUTLVOL, MIXOUTRVOL, HPOUT1LVOL, HPOUT1RVOL, SPKLVOL and SPKRVOL are modified while the output signal path is active. Other gain controls are provided in the signal paths to provide scaling of signals from different sources, and to prevent clipping when multiple signals are mixed. However, to prevent pop noise, it is recommended that those other gain controls should not be modified while the signal path is active. To prevent "zipper noise", a zero-cross function is provided on the output PGAs. When this feature is enabled, volume updates will not take place until a zero-crossing is detected. In the case of a long period without zero-crossings, a timeout function is provided. When the zero-cross function is enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. The timeout clock is enabled using TOCLK_ENA; the timeout period is set by TOCLK_RATE. See “Clocking and Sample Rates” for more information on these fields. The mixer output PGA controls are shown in Table 47. The MIXOUT_VU bits control the loading of the output mixer PGA volume data. When MIXOUT_VU is set to 0, the volume control data will be loaded into the respective control register, but will not actually change the gain setting. The output mixer PGA volume settings are both updated when a 1 is written to either MIXOUT_VU bit. This makes it possible to update the gain of both output paths simultaneously. REGISTER ADDRESS R32 (20h) BIT 8 LABEL MIXOUT_VU DEFAULT N/A Left OPGA Volume DESCRIPTION Mixer Output PGA Volume Update Writing a 1 to this bit will update MIXOUTLVOL and MIXOUTRVOL volumes simultaneously. 7 MIXOUTL_ZC 0b MIXOUTLVOL (Left Mixer Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled 6 MIXOUTL_MUTE_N 5:0 MIXOUTL_VOL [5:0] 1b 39h (0dB) MIXOUTLVOL (Left Mixer Output PGA) Mute 0 = Mute 1 = Un-mute MIXOUTLVOL (Left Mixer Output PGA) Volume -57dB to +6dB in 1dB steps (See Table 50 for output PGA volume control range) R33 (21h) 8 MIXOUT_VU N/A Right OPGA Volume Mixer Output PGA Volume Update Writing a 1 to this bit will update MIXOUTLVOL and MIXOUTRVOL volumes simultaneously. 7 MIXOUTR_ZC 0b 6 MIXOUTR_MUTE_N 1b 5:0 MIXOUTR_VOL [5:0] 39h (0dB) MIXOUTRVOL (Right Mixer Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled MIXOUTLVOL (Right Mixer Output PGA) Mute 0 = Mute 1 = Un-mute MIXOUTRVOL (Right Mixer Output PGA) Volume -57dB to +6dB in 1dB steps (See Table 50 for output PGA volume control range) Table 47 Mixer Output PGA (MIXOUTLVOL, MIXOUTRVOL) Control The headphone output PGA is configurable between two input sources. The default input to each headphone output PGA is the respective output mixer (MIXOUTL or MIXOUTR). A direct path from the DACL or DACR can be selected using the DACL_TO_HPOUT1L and DACR_TO_HPOUT1R Rev 4.1 72 WM8993 register bits. When these bits are selected, a DAC to Headphone playback path is possible without using the output mixers; this offers reduced power consumption by allowing the output mixers to be disabled in this typical usage case. The headphone output PGA controls are shown in Table 48. The HPOUT1_VU bits control the loading of the headphone PGA volume data. When HPOUT1_VU is set to 0, the volume control data will be loaded into the respective control register, but will not actually change the gain setting. The headphone PGA volume settings are both updated when a 1 is written to either HPOUT1_VU bit. This makes it possible to update the gain of both output paths simultaneously. REGISTER ADDRESS R28 (1Ch) BIT 8 LABEL HPOUT1_VU DEFAULT N/A Left Output Volume DESCRIPTION Headphone Output PGA Volume Update Writing a 1 to this bit will update HPOUT1LVOL and HPOUT1RVOL volumes simultaneously. 7 HPOUT1L_ZC 0b HPOUT1LVOL (Left Headphone Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled 6 HPOUT1L_MUTE_N 1b HPOUT1LVOL (Left Headphone Output PGA) Mute 0 = Mute 1 = Un-mute 5:0 HPOUT1L_VOL [5:0] 2Dh (-12dB) HPOUT1LVOL (Left Headphone Output PGA) Volume -57dB to +6dB in 1dB steps (See Table 50 for output PGA volume control range) R45 (2Dh) 8 DACL_TO_HPOUT1L 0b Output Mixer1 HPOUT1LVOL (Left Headphone Output PGA) Input Select 0 = MIXOUTL 1 = DACL R29 (1Dh) 8 HPOUT1_VU N/A Right Output Volume Headphone Output PGA Volume Update Writing a 1 to this bit will update HPOUT1LVOL and HPOUT1RVOL volumes simultaneously. 7 HPOUT1R_ZC 0b HPOUT1RVOL (Right Headphone Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled 6 HPOUT1R_MUTE_N 1b HPOUT1RVOL (Right Headphone Output PGA) Mute 0 = Mute 1 = Un-mute 5:0 HPOUT1R_VOL [5:0] 2Dh (-12dB) HPOUT1RVOL (Right Headphone Output PGA) Volume -57dB to +6dB in 1dB steps (See Table 50 for output PGA volume control range) R46 (2Eh) Output Mixer2 8 DACR_TO_HPOUT1 R 0b HPOUT1RVOL (Right Headphone Output PGA) Input Select 0 = MIXOUTR 1 = DACR Table 48 Headphone Output PGA (HPOUT1LVOL, HPOUT1RVOL) Control Rev 4.1 73 WM8993 The speaker output PGA controls are shown in Table 49.The SPKOUT_VU bits control the loading of the speaker PGA volume data. When SPKOUT_VU is set to 0, the volume control data will be loaded into the respective control register, but will not actually change the gain setting. The speaker PGA volume settings are both updated when a 1 is written to either SPKOUT_VU bit. This makes it possible to update the gain of both output paths simultaneously. REGISTER ADDRESS R38 (26h) BIT 8 LABEL SPKOUT_VU DEFAULT N/A Speaker Volume Left DESCRIPTION Speaker Output PGA Volume Update Writing a 1 to this bit will update SPKLVOL and SPKRVOL volumes simultaneously. 7 SPKOUTL_ZC 0b SPKLVOL (Left Speaker Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled 6 SPKOUTL_MUTE_N 1b SPKLVOL (Left Speaker Output PGA) Mute 0 = Mute 1 = Un-mute 5:0 SPKOUTL_VOL [5:0] 39h (0dB) SPKLVOL (Left Speaker Output PGA) Volume -57dB to +6dB in 1dB steps (See Table 50 for output PGA volume control range) R39 (27h) 8 SPKOUT_VU N/A Speaker Volume Right Speaker PGA Volume Update Writing a 1 to this bit will update SPKLVOL and SPKRVOL volumes simultaneously. 7 SPKOUTR_ZC 0b SPKRVOL (Right Speaker Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled 6 SPKOUTR_MUTE_N 1b SPKRVOL (Right Speaker Output PGA) Mute 0 = Mute 1 = Un-mute 5:0 SPKOUTR_VOL [5:0] 39h (0dB) SPKRVOL (Right Speaker Output PGA) Volume -57dB to +6dB in 1dB steps (See Table 50 for output PGA volume control range) Table 49 Speaker Output PGA (SPKLVOL, SPKRVOL) Control Rev 4.1 74 WM8993 PGA GAIN SETTING VOLUME (dB) PGA GAIN SETTING VOLUME (dB) 0h -57 20h -25 1h -56 21h -24 2h -55 22h -23 3h -54 23h -22 4h -53 24h -21 5h -52 25h -20 6h -51 26h -19 7h -50 27h -18 8h -49 28h -17 9h -48 29h -16 Ah -47 2Ah -15 Bh -46 2Bh -14 Ch -45 2Ch -13 Dh -44 2Dh -12 Eh -43 2Eh -11 Fh -42 2Fh -10 10h -41 30h -9 11h -40 31h -8 12h -39 32h -7 13h -38 33h -6 14h -37 34h -5 15h -36 35h -4 16h -35 36h -3 17h -34 37h -2 18h -33 38h -1 19h -32 39h 0 1Ah -31 3Ah +1 1Bh -30 3Bh +2 1Ch -29 3Ch +3 1Dh -28 3Dh +4 1Eh -27 3Eh +5 1Fh -26 3Fh +6 Table 50 Output PGA Volume Range Rev 4.1 75 WM8993 SPEAKER BOOST MIXER Each class D/AB speaker driver has its own boost mixer which performs a dual role. It allows the output from the left speaker mixer (via SPKLVOL), right speaker mixer (via SPKRVOL), or the ‘Direct Voice’ path to be routed to either speaker driver. (The ‘Direct Voice’ path is the differential input, VRXN/VRXP, routed directly to the output drivers, providing a low power differential path from baseband voice to loudspeakers.) The speaker boost mixers are controlled using the registers defined in Table 51 below. The second function of the speaker boost mixers is that they provide an additional AC gain (boost) function to shift signal levels between the AVDD1 and SPKVDD voltage domains for maximum output power. The AC gain (boost) function is described in the “Analogue Outputs” section. REGISTER ADDRESS R36 (24h) BIT 5 LABEL VRX_TO_SPKOUTL DEFAULT DESCRIPTION 0b Direct Voice (Differential Input, VRXN/VRXP) to Left Speaker Mute SPKOUT Mixers 0 = Mute 1 = Un-mute 4 SPKMIXL_TO_SPKOU TL 1b SPKMIXL Left Speaker Mixer to Left Speaker Mute 0 = Mute 1 = Un-mute 3 SPKMIXR_TO_SPKO UTL 0b SPKMIXR Right Speaker Mixer to Left Speaker Mute 0 = Mute 1 = Un-mute 2 VRX_TO_SPKOUTR 0b Direct Voice (Differential Input, VRXN/VRXP) to Right Speaker Mute 0 = Mute 1 = Un-mute 1 SPKMIXL_TO_SPKOU TR 0b SPKMIXL Left Speaker Mixer to Right Speaker Mute 0 = Mute 1 = Un-mute 0 SPKMIXR_TO_SPKO UTR 1b SPKMIXR Right Speaker Mixer to Right Speaker Mute 0 = Mute 1 = Un-mute Table 51 Speaker Boost Mixer (SPKOUTLBOOST, SPKOUTRBOOST) Control Rev 4.1 76 WM8993 EARPIECE DRIVER MIXER The earpiece driver has a dedicated mixer, HPOUT2MIX, which is controlled using the registers defined in Table 52. The earpiece driver is configurable to select output from the left output mixer (via MIXOUTLVOL), the right output mixer (via MIXOUTRVOL), or the ‘Direct Voice’ path. (The ‘Direct Voice’ path is the differential input, VRXN/VRXP, routed directly to the output drivers, providing a low power differential path from baseband voice to earpiece.) Care should be taken to avoid clipping when enabling more than one path to the earpiece driver. The HPOUT2VOL volume control can be used to avoid clipping when more than one full scale signal is input to the mixer. REGISTER ADDRESS R31 (1Fh) BIT 5 LABEL DEFAULT HPOUT2_MUTE 1b HPOUT2 Volume DESCRIPTION HPOUT2 (Earpiece Driver) Mute 0 = Un-mute 1 = Mute 4 HPOUT2_VOL 0b HPOUT2 (Earpiece Driver) Volume 0 = 0dB 1 = -6dB R51 (33h) 5 VRX_TO_HPOUT2 0b HPOUT2 Mixer Direct Voice (Differential Input, VRXN/VRXP) to Earpiece Driver 0 = Mute 1 = Un-mute 4 MIXOUTLVOL_TO_HP OUT2 0b MIXOUTLVOL (Left Output Mixer PGA) to Earpiece Driver 0 = Mute 1 = Un-mute 3 MIXOUTRVOL_TO_HP OUT2 0b MIXOUTRVOL (Right Output Mixer PGA) to Earpiece Driver 0 = Mute 1 = Un-mute Table 52 Earpiece Driver Mixer (HPOUT2MIX) Control LINE OUTPUT MIXERS The WM8993 provides two pairs of line outputs, both with highly configurable output mixers. The outputs LINEOUT1N and LINEOUT1P can be configured as two single-ended outputs or as a differential output. In the same manner, LINEOUT2N and LINEOUT2P can be configured either as two single-ended outputs or as a differential output. The respective line output mixers can be configured in single-ended mode or differential mode; each mode supports multiple signal path configurations. LINEOUT1 single-ended mode is selected by setting LINEOUT1_MODE = 1. In single-ended mode, any of three possible signal paths may be enabled:  MIXOUTL (left output mixer) to LINEOUT1P  MIXOUTR (right output mixer) to LINEOUT1N  MIXOUTL (left output mixer) to LINEOUT1N LINEOUT1 differential mode is selected by setting LINEOUT1_MODE = 0. In differential mode, any of three possible signal paths may be enabled: Rev 4.1  MIXOUTL (left output mixer) to LINEOUT1N and LINEOUT1P  IN1L (input PGA) to LINEOUT1N and LINEOUT1P  IN1R (input PGA) to LINEOUT1N and LINEOUT1P 77 WM8993 The LINEOUT1 output mixers are controlled as described in Table 53. Care should be taken to avoid clipping when enabling more than one path to the line output mixers. The LINEOUT1_VOL control can be used to provide -6dB attenuation when more than one full scale signal is applied. When using the LINEOUT1 mixers in single-ended mode, a buffered VMID must be enabled. This is achieved by setting LINEOUT_VMID_BUF_ENA, as described in the “Analogue Outputs” section. REGISTER ADDRESS R30 (1Eh) BIT 6 LABEL LINEOUT1N_MUTE DEFAULT 1b Line Outputs Volume DESCRIPTION LINEOUT1N Line Output Mute 0 = Un-mute 1 = Mute 5 LINEOUT1P_MUTE 1b LINEOUT1P Line Output Mute 0 = Un-mute 1 = Mute 4 LINEOUT1_VOL 0b LINEOUT1 Line Output Volume 0 = 0dB 1 = -6dB Applies to both LINEOUT1N and LINEOUT1P R52 (34h) 6 Line Mixer1 MIXOUTL_TO_LINEO UT1N 0b MIXOUTL to Single-Ended Line Output on LINEOUT1N 0 = Mute 1 = Un-mute (LINEOUT1_MODE = 1) 5 MIXOUTR_TO_LINE OUT1N 0b MIXOUTR to Single-Ended Line Output on LINEOUT1N 0 = Mute 1 = Un-mute (LINEOUT1_MODE = 1) 4 LINEOUT1_MODE 0b LINEOUT1 Mode Select 0 = Differential 1 = Single-Ended 2 IN1R_TO_LINEOUT1 P 0b IN1R Input PGA to Differential Line Output on LINEOUT1 0 = Mute 1 = Un-mute (LINEOUT1_MODE = 0) 1 IN1L_TO_LINEOUT1 P 0b IN1L Input PGA to Differential Line Output on LINEOUT1 0 = Mute 1 = Un-mute (LINEOUT1_MODE = 0) 0 MIXOUTL_TO_LINEO UT1P 0b Differential Mode (LINEOUT1_MODE = 0): MIXOUTL to Differential Output on LINEOUT1 0 = Mute 1 = Un-mute Single Ended Mode (LINEOUT1_MODE = 1): MIXOUTL to Single-Ended Line Output on LINEOUT1P 0 = Mute 1 = Un-mute Table 53 LINEOUT1N and LINEOUT1P Control Rev 4.1 78 WM8993 LINEOUT2 single-ended mode is selected by setting LINEOUT2_MODE = 1. In single-ended mode, any of three possible signal paths may be enabled:  MIXOUTR (right output mixer) to LINEOUT2P  MIXOUTL (left output mixer) to LINEOUT2N  MIXOUTR (right output mixer) to LINEOUT2N LINEOUT2 differential mode is selected by setting LINEOUT2_MODE = 0. In differential mode, any of three possible signal paths may be enabled:  MIXOUTR (right output mixer) to LINEOUT2N and LINEOUT2P  IN1L (input PGA) to LINEOUT2P and LINEOUT2P  IN1R (input PGA) to LINEOUT2N and LINEOUT2P The LINEOUT2 output mixers are controlled as described in Table 54. Care should be taken to avoid clipping when enabling more than one path to the line output mixers. The LINEOUT2_VOL control can be used to provide -6dB attenuation when more than one full scale signal is applied. When using the LINEOUT2 mixers in single-ended mode, a buffered VMID must be enabled. This is achieved by setting LINEOUT_VMID_BUF_ENA, as described in the “Analogue Outputs” section. Rev 4.1 79 WM8993 REGISTER ADDRESS R30 (1Eh) BIT 2 LABEL LINEOUT2N_MUTE DEFAULT 1b Line Outputs Volume DESCRIPTION LINEOUT2N Line Output Mute 0 = Un-mute 1 = Mute 1 LINEOUT2P_MUTE 1b LINEOUT2P Line Output Mute 0 = Un-mute 1 = Mute 0 LINEOUT2_VOL 0b LINEOUT2 Line Output Volume 0 = 0dB 1 = -6dB Applies to both LINEOUT2N and LINEOUT2P R53 (35h) 6 Line Mixer2 MIXOUTR_TO_LINEO UT2N 0b MIXOUTR to Single-Ended Line Output on LINEOUT2N 0 = Mute 1 = Un-mute (LINEOUT2_MODE = 1) 5 MIXOUTL_TO_LINEO UT2N 0b MIXOUTL to Single-Ended Line Output on LINEOUT2N 0 = Mute 1 = Un-mute (LINEOUT2_MODE = 1) 4 LINEOUT2_MODE 0b LINEOUT2 Mode Select 0 = Differential 1 = Single-Ended 2 IN1L_TO_LINEOUT2P 0b IN1L Input PGA to Differential Line Output on LINEOUT2 0 = Mute 1 = Un-mute (LINEOUT2_MODE = 0) 1 IN1R_TO_LINEOUT2P 0b IN1R Input PGA to Differential Line Output on LINEOUT2 0 = Mute 1 = Un-mute (LINEOUT2_MODE = 0) 0 MIXOUTR_TO_LINEO UT2P 0b Differential Mode (LINEOUT2_MODE = 0): MIXOUTR to Differential Output on LINEOUT2 0 = Mute 1 = Un-mute Single-Ended Mode (LINEOUT2_MODE = 0): MIXOUTR to Single-Ended Line Output on LINEOUT2P 0 = Mute 1 = Un-mute Table 54 LINEOUT2N and LINEOUT2P Control Rev 4.1 80 WM8993 CHARGE PUMP The WM8993 incorporates a dual-mode Charge Pump which generates the supply rails for the headphone output drivers, HPOUT1L and HPOUT1R. The Charge Pump has a single supply input, CPVDD, and generates split rails CPVOUTP and CPVOUTN according to the selected mode of operation. The Charge Pump connections are illustrated in Figure 23 (see “Electrical Characteristics” for external component values). An input decoupling capacitor may also be required at CPVDD, depending upon the system configuration. CPFB1 CPFB2 CPVOUTP CPVDD Charge Pump CPVOUTN WM8993 CPGND Figure 23 Charge Pump External Connections The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts the output voltages (CPVOUTP and CPVOUTN) as well as the switching frequency in order to optimise the power consumption according to the operating conditions. This can take two forms, which are selected using the CP_DYN_PWR register bit.  Register control (CP_DYN_PWR = 0)  Dynamic control (CP_DYN_PWR = 1) Under Register control, the HPOUT1L_VOL and HPOUT1R_VOL register settings are used to control the charge pump mode of operation. Under Dynamic control, the audio signal level in the DAC is used to control the charge pump mode of operation. This is the Wolfson ‘Class W’ mode, which allows the power consumption to be optimised in real time, but can only be used if the DAC is the only signal source. This mode should not be used if any of the bypass paths are used to feed analogue inputs into the output signal path. Under the recommended usage conditions of the WM8993, the Charge Pump will be enabled by running the default headphone Start-Up sequence as described in the “Control Write Sequencer” section. (Similarly, it will be disabled by running the Shut-Down sequence.) In these cases, the user does not need to write to the CP_ENA bit. The Charge Pump operating mode defaults to Register control; Dynamic control may be selected by setting the CP_DYN_PWR register bit, if appropriate. Note that the charge pump clock is derived from internal clock CLK_SYS; either MCLK or the FLL output selectable using the SYSCLK_SRC bit. Under normal circumstances an external clock signal must be present for the charge pump to function. However, the FLL has a free-running mode that does not require an external clock but will generate an internal clock suitable for running the charge pump. The clock division from CLK_SYS is handled transparently by the WM8993 without user intervention, as long as CLKSYS and sample rates are set correctly. Refer to the “Clocking and Sample Rates” section for more detail on the FLL and clocking configuration. The Charge Pump control fields are described in Table 55. Rev 4.1 81 WM8993 REGISTER ADDRESS R76 (4Ch) BIT 15 LABEL CP_ENA DEFAULT 0 Charge Pump 1 DESCRIPTION Enable charge-pump digits 0 = disable 1 = enable Note: Default value of R76[14:0] (0x1F25h) must not be changed when enabling/disabling the Charge Pump R81 (51h) 0 CP_DYN_PWR Class W 0 0 Enable dynamic charge pump power control 0 = charge pump controlled by volume register settings (Class G) 1 = charge pump controlled by realtime audio level (Class W) Table 55 Charge Pump Control If the headphone output drivers (HPOUT1L and HPOUT1R) are not used, then the Charge Pump and the associated external components are not required. The Charge Pump and Headphone drivers should not be enabled in this case (CP_ENA=0, HPOUT1L_ENA=0, HPOUT1R_ENA=0). If the Charge Pump is not used, and the associated external components are omitted, then the CPCA and CPCB pins can be left floating; the CPVOUTP and CPVOUTN pins should be grounded as illustrated in Figure 24. Note that, when the Charge Pump is disabled, it is still recommended that the CPVDD pin is kept within its recommended operating conditions (1.71V to 2.0V). CPFB1 CPFB2 CPVOUTP CPVDD Charge Pump CPVOUTN WM8993 CPGND Figure 24 External Configuration when Charge Pump not used Rev 4.1 82 WM8993 DC SERVO The WM8993 provides a DC servo circuit on the headphone outputs HPOUT1L and HPOUT1R in order to remove DC offset from these ground-referenced outputs. When enabled, the DC servo ensures that the DC level of these outputs remains within 1mV of ground. Removal of the DC offset is important because any deviation from GND at the output pin will cause current to flow through the load under quiescent conditions, resulting in increased power consumption. Additionally, the presence of DC offsets can result in audible pops and clicks at power up and power down. The recommended usage of the DC Servo is initialised by running the default Start-Up sequence as described in the “Control Write Sequencer” section. The default Start-Up sequence executes a series of DC offset corrections, after which the measured offset correction is maintained on the headphone output channels. If a different usage is required, eg. if a periodic DC offset correction is required, then the default Start-Up sequence may be modified according to specific requirements. The relevant control fields are described in the following paragraphs and are defined in Table 56. DC SERVO ENABLE AND START-UP The DC Servo circuit is enabled on HPOUT1L and HPOUT1R by setting DCS_ENA_CHAN_0 and DCS_ENA_CHAN_1 respectively. When the DC Servo is enabled, the DC offset correction can be commanded in a number of different ways, including single-shot and periodically recurring events. Writing a logic 1 to DCS_TRIG_STARTUP_n initiates a series of DC offset measurements and applies the necessary correction to the associated output; (‘n’ = 0 for Left channel, 1 for Right channel). On completion, the headphone output will be within 1mV of AGND. This is the DC Servo mode selected by the default Start-Up sequence. Completion of the DC offset correction triggered in this way is indicated by the DCS_STARTUP_COMPLETE field, as described in Table 56. Typically, this operation takes 86ms per channel. For correct operation of the DC Servo Start-Up mode, it is important that there is no active audio signal present on the signal path while the mode is running. The DC Servo Start-Up mode should be scheduled at the correct position within the Headphone Output Enable sequence, as described in the “Output Signal Path” section. All other stages of the analogue signal path should be fully enabled prior to commanding the Start-Up mode; the DAC Digital Mute function should be used, where appropriate, to ensure there is no active audio signal present during the DC Servo measurements. Writing a logic 1 to DCS_TRIG_DAC_WR_n causes the DC offset correction to be set to the value contained in the DCS_DAC_WR_VAL_n fields in Register R87. This mode is useful if the required offset correction has already been determined and stored; it is faster than the DCS_TRIG_STARTUP_n mode, but relies on the accuracy of the stored settings. Completion of the DC offset correction triggered in this way is indicated by the DCS_DAC_WR_COMPLETE field, as described in Table 56. Typically, this operation takes 2ms per channel. For pop-free operation of the DC Servo DAC Write mode, it is important that the mode is scheduled at the correct position within the Headphone Output Enable sequence, as described in the “Output Signal Path” section. When using either of the DC Servo options above, the status of the DC offset correction process is indicated by the DCS_CAL_COMPLETE field; this is the logical OR of the DCS_STARTUP_COMPLETE and DCS_DAC_WR_COMPLETE fields. The DC Servo control fields associated with start-up operation are described in Table 56. It is important to note that, to minimise audible pops/clicks, the Start-Up and DAC Write modes of DC Servo operation should be commanded as part of a control sequence which includes muting and shorting of the headphone outputs; a suitable sequence is defined in the default Start-Up sequence. Rev 4.1 83 WM8993 REGISTER ADDRESS R84 (54h) BIT LABEL DEFAULT DESCRIPTION 5 DCS_TRIG_START UP_1 0 Writing 1 to this bit selects StartUp DC Servo mode for HPOUT1R. DC Servo 0 In readback, a value of 1 indicates that the DC Servo Start-Up correction is in progress. 4 DCS_TRIG_START UP_0 0 Writing 1 to this bit selects StartUp DC Servo mode for HPOUT1L. In readback, a value of 1 indicates that the DC Servo Start-Up correction is in progress. 3 DCS_TRIG_DAC_W R_1 0 Writing 1 to this bit selects DAC Write DC Servo mode for HPOUT1R. In readback, a value of 1 indicates that the DC Servo DAC Write correction is in progress. 2 DCS_TRIG_DAC_W R_0 0 Writing 1 to this bit selects DAC Write DC Servo mode for HPOUT1L. In readback, a value of 1 indicates that the DC Servo DAC Write correction is in progress. 1 DCS_ENA_CHAN_1 0 DC Servo enable for HPOUT1R 0 = disabled 1 = enabled 0 DCS_ENA_CHAN_0 0 DC Servo enable for HPOUT1L 0 = disabled 1 = enabled R87 (57h) 15:8 DC Servo 3 DCS_DAC_WR_VA L1 [7:0] 0000 0000 DC Offset value for HPOUT1Rin DAC Write DC Servo mode. Two’s complement format. LSB is 0.25mV. Range is -32mV to +31.75mV 7:0 DCS_DAC_WR_VA L0 [7:0] 0000 0000 DC Offset value for HPOUT1Lin DAC Write DC Servo mode. Two’s complement format. LSB is 0.25mV. Range is -32mV to +31.75mV Rev 4.1 84 WM8993 REGISTER ADDRESS R88 (58h) BIT 9:8 DC Servo Readback 0 LABEL DCS_CAL_COMPL ETE [1:0] DEFAULT 00 DESCRIPTION DC Servo Complete status 0 = DAC Write or Start-Up DC Servo mode not completed. 1 = DAC Write or Start-Up DC Servo mode complete. Bit [1] = HPOUT1R Bit [0] = HPOUT1L 5:4 DCS_DAC_WR_CO MPLETE [1:0] 00 DC Servo DAC Write status 0 = DAC Write DC Servo mode not completed. 1 = DAC Write DC Servo mode complete. Bit [1] = HPOUT1R Bit [0] = HPOUT1L 1:0 DCS_STARTUP_C OMPLETE [1:0] 00 DC Servo Start-Up status 0 = Start-Up DC Servo mode not completed. 1 = Start-Up DC Servo mode complete. Bit [1] = HPOUT1R Bit [0] = HPOUT1L Table 56 DC Servo Enable and Start-Up Modes DC SERVO ACTIVE MODES The DC Servo modes described above are suitable for initialising the DC offset correction circuit on the Headphone outputs as part of a controlled start-up sequence which is executed before the signal path is fully enabled. Additional modes are available for use whilst the signal path is active; these modes may be of benefit following a large change in signal gain, which can lead to a change in DC offset level. Periodic updates may also be desirable to remove slow drifts in DC offset caused by changes in parameters such as device temperature. The DC Servo circuit is enabled on HPOUT1L and HPOUT1R by setting DCS_ENA_CHAN_0 and DCS_ENA_CHAN_1 respectively, as described earlier in Table 56. Writing a logic 1 to DCS_TRIG_SINGLE_n initiates a single DC offset measurement and adjustment to the associated output; (‘n’ = 0 for Left channel, 1 for Right channel). This will adjust the DC offset correction on the selected channel by no more than 1LSB (0.25mV). Setting DCS_TIMER_PERIOD_01 to a non-zero value will cause a single DC offset measurement and adjustment to be scheduled on a periodic basis. Periodic rates ranging from every 0.52s to in excess of 2hours can be selected. Writing a logic 1 to DCS_TRIG_SERIES_n initiates a series of DC offset measurements and applies the necessary correction to the associated output. The number of DC Servo operations performed is determined by DCS_SERIES_NO_01. A maximum of 128 operations may be selected, though a much lower value will be sufficient in most applications. The DC Servo control fields associated with active modes (suitable for use on a signal path that is in active use) are described in Table 57. Rev 4.1 85 WM8993 REGISTER ADDRESS R84 (54h) BIT LABEL DEFAULT 13 DCS_TRIG_SINGLE _1 0 DC Servo 0 DESCRIPTION Writing 1 to this bit selects a single DC offset correction for HPOUT1R. In readback, a value of 1 indicates that the DC Servo single correction is in progress. 12 DCS_TRIG_SINGLE _0 0 Writing 1 to this bit selects a single DC offset correction for HPOUT1L. In readback, a value of 1 indicates that the DC Servo single correction is in progress. 9 DCS_TRIG_SERIES _1 0 Writing 1 to this bit selects a series of DC offset corrections for HPOUT1R. In readback, a value of 1 indicates that the DC Servo DAC Write correction is in progress. 8 DCS_TRIG_SERIES _0 0 Writing 1 to this bit selects a series of DC offset corrections for HPOUT1L. In readback, a value of 1 indicates that the DC Servo DAC Write correction is in progress. R85 (55h) 11:5 DC Servo 1 DCS_SERIES_NO_ 01 [6:0] 010 1010 Number of DC Servo updates to perform in a series event. 0 = 1 updates 1 = 2 updates ... 127 = 128 updates 3:0 DCS_TIMER_PERI OD_01 [3:0] 1010 Time between periodic updates. Time is calculated as 0.256s x (2^PERIOD) 0000 = Off 0001 = 0.52s 1010 = 266s (4min 26s) 1111 = 8519s (2hr 22s) Table 57 DC Servo Active Modes DC SERVO READBACK The current DC offset value for each Headphone output channel can be read from Registers R89 and R90, as described in Table 58. Note that these values may form the basis of settings that are subsequently used by the DC Servo in DAC Write mode. REGISTER ADDRESS R89 (59h) BIT LABEL DEFAULT 7:0 DCS_INTEG_CHAN _1 0000 0000 DCS_INTEG_CHAN _0 0000 0000 DC Servo Readback 1 R90 (5Ah) DC Servo Readback 2 7:0 DESCRIPTION Readback value for HPOUT1R. Two’s complement format. LSB is 0.25mV. Range is -32mV to +31.75mV Readback value for HPOUT1L. Two’s complement format. LSB is 0.25mV. Range is -32mV to +31.75mV Table 58 DC Servo Readback Rev 4.1 86 WM8993 ANALOGUE OUTPUTS The speaker, headphone, earpiece and line outputs are highly configurable and may be used in many different ways. SPEAKER OUTPUT CONFIGURATIONS The speaker outputs SPKOUTL and SPKOUTR can be driven by either of the speaker mixers, SPKMIXL or SPKMIXR, or by the low power, differential Direct Voice path from IN2LP/VRXN and IN2RP/VRXP. Fine volume control is available on the speaker mixer paths using the SPKLVOL and SPKRVOL PGAs. A boost function is available on both the speaker mixer paths and the Direct Voice path. For information on the speaker mixing options, refer to the “Output Signal Path” section. The speaker outputs SPKOUTL and SPKOUTR operate in a BTL configuration in Class AB or Class D amplifier modes. The default mode is class D but class AB mode can be selected by setting the SPKOUT_CLASSAB_MODE register bit, as defined in Table 60. The speaker outputs may be configured in two ways: 1. Stereo Mode – supports up to 1W into stereo 8 BTL loads 2. Mono Mode – supports up to 2W into a single 4 BTL load Mono mode is selected by applying a logic high input to the SPKMONO pin (E3). For Stereo mode this pin should be connected to GND. Note that SPKMONO is referenced to DBVDD. SPEAKER CONFIGURATION SPKMONO PIN (E3) Stereo Mode GND Mono Mode DBVDD Table 59 SPKMONO Pin Function For mono operation, the P channels, SPKOUTLP and SPKOUTRP should be connected together on the PCB, and similarly with the N channels, SPKOUTLN and SPKOUTRN. Refer to External Components Diagram in the ‘Applications Information’ for more details. In this configuration both left and right speaker drivers should be enabled (SPKOUTL_ENA=1 and SPKOUTR_ENA=1), but path selection and volume controls are available on left channel only (SPKMIXL, SPKLVOL and SPKOUTLBOOST). Note that for applications with a mono 8 speaker it is possible to improve THD performance at higher power levels by configuring the output in mono mode instead of running either the left of right channel in stereo mode. The connections for stereo and mono speaker configurations are shown in Figure 25. SPKOUTLP SPKOUTLN SPKOUTLP SPKOUTLN 8Ω SPKOUTRN SPKOUTRP SPKOUTRN SPKOUTRP 4Ω 8Ω Figure 25 Mono and Stereo Speaker Output Configuration Rev 4.1 87 WM8993 Eight levels of AC signal boost are provided in order to deliver maximum output power for many commonly-used SPKVDD/AVDD1 combinations. These boost options are available in both Class AB and Class D modes. The AC boost levels from 0dB to +12dB are selected using register bits SPKOUTL_BOOST and SPKOUTR_BOOST. To prevent pop noise, SPKOUTL_BOOST and SPKOUTR_BOOST should not be modified while the speaker outputs are enabled. Figure 26 illustrates the speaker outputs and the mixing and gain/boost options available. Ultra-low leakage and high PSRR allow the speaker supply SPKVDD to be directly connected to a lithium battery. Note that an appropriate SPKVDD supply voltage must be provided to prevent waveform clipping when speaker boost is used. DC gain is applied automatically in both class AB and class D modes with a shift from VMID to SPKVDD/2. This provides optimum signal swing for maximum output power. In class AB mode, an ultra-high PSRR mode is available, in which the DC reference for the speaker driver is fixed at VMID. This mode is selected by enabling the SPKAB_REF_SEL bit (see Table 60). In this mode, the output power is limited but the driver will still be capable of driving more than 500mW in 8 while maintaining excellent suppression of noise on SPKVDD (for example, TDMA noise in a GSM phone application). Direct Voice SPKVDD AVDD SPKLMIX SPKOUTL_BOOST[2:0] SPKLVOL[6:0] SPKOUTLP SPKOUTLN -15dB to 0dB, 3dB steps -57dB to +6dB, 1dB steps SPKGND AGND SPKVDD AVDD SPKRMIX SPKOUTR_BOOST[2:0] SPKRVOL[6:0] SPKOUTRP SPKOUTRN -15dB to 0dB, 3dB steps -57dB to +6dB, 1dB steps SPKGND AGND SPKOUTL_BOOST SPKOUTR_BOOST 000 = 1.00x (+0dB) 000 = 1.19x (+1.5dB) 000 = 1.41x (+3.0dB) 000 = 1.68x (+4.5dB) 000 = 2.00x (+6.0dB) 000 = 2.37x (+7.5dB) 000 = 2.81x (+9.0dB) 000 = 3.98x (+12.0dB) SPKVDD AVDD Signal x BOOST SPKVDD/2 VMID AGND Signal x BOOST is automatically centred around SPKVDD/2 Figure 26 Speaker Output Configuration and AC Boost Operation Rev 4.1 88 WM8993 REGISTER ADDRESS BIT R35 (23h) 8 SPKMIXR Attenuation LABEL DEFAULT DESCRIPTION SPKOUT_CLASSAB _MODE 0b Speaker Class AB Mode Enable SPKOUTL_BOOST [2:0] 000b Left Speaker Gain Boost (1.0x) 000 = 1.00x boost (+0dB) 0 = Class D mode 1 = Class AB mode R37 (25h) 5:3 SPKOUT Boost 001 = 1.19x boost (+1.5dB) 010 = 1.41x boost (+3.0dB) 011 = 1.68x boost (+4.5dB) 100 = 2.00x boost (+6.0dB) 101 = 2.37x boost (+7.5dB) 110 = 2.81x boost (+9.0dB) 111 = 3.98x boost (+12.0dB) 2:0 SPKOUTR_BOOST [2:0] 000b Right Speaker Gain Boost (1.0x) 000 = 1.00x boost (+0dB) 001 = 1.19x boost (+1.5dB) 010 = 1.41x boost (+3.0dB) 011 = 1.68x boost (+4.5dB) 100 = 2.00x boost (+6.0dB) 101 = 2.37x boost (+7.5dB) 110 = 2.81x boost (+9.0dB) 111 = 3.98x boost (+12.0dB) R54 (36h) 8 SPKAB_REF_SEL 0b Selects Reference for Speaker in Class AB mode Speaker Mixer 0 = SPKVDD/2 1 = VMID Table 60 Speaker Mode and Boost Control Clocking of the Class D output driver is derived from CLK_SYS. The clocking frequency division is configured automatically, according to the CLK_SYS_RATE and SAMPLE_RATE registers. (See “Clocking and Sample Rates” for further details of the system clocks and control registers.) The Class D switching clock is enabled whenever SPKOUTL_ENA or SPKOUTR_ENA is set, provided also that SPKOUT_CLASSAB_MODE = 0. The frequency is as described in Table 61. Note that the CLK_SYS must be present and enabled when using the speaker outputs in Class D mode. SAMPLE RATE (kHz) 8 11.025 SYSTEM CLOCK RATE (CLK_SYS / fs ratio) 64 128 192 256 384 512 768 1024 1408 1536 352 256 256 256 256 341.3 256 341.3 256 341.3 352.8 352.8 352.8 352.8 352.8 352.8 352.8 352.8 384 12 384 384 384 384 384 384 384 16 256 341.3 384 341.3 384 341.3 384 22.05 352.8 352.8 352.8 352.8 352.8 352.8 24 341.3 384 384 384 384 384 32 341.3 341.3 384 341.3 384 44.1 352.8 352.8 352.8 352.8 384 384 384 384 48 Table 61 Class D Switching Frequency (kHz) Rev 4.1 89 WM8993 HEADPHONE OUTPUT CONFIGURATIONS The headphone outputs HPOUT1L andHPOUT1R are driven by the headphone output PGAs HPOUT1LVOL and HPOUT1RVOL. Each PGA has its own dedicated volume control, as described in the “Output Signal Path” section. The input to these PGAs can be either the output mixers MIXOUTL and MIXOUTR or the direct DAC outputs DACL and DACR. The headphone output driver is capable of driving up to 25mW into a 16Ω or 32Ω load such as a stereo headset or headphones. The outputs are ground-referenced, eliminating any requirement for AC coupling capacitors. This is achieved by having separate positive and negative supply rails powered by an on-chip charge pump. A DC Servo circuit removes any DC offset from the headphone outputs, suppressing ‘pop’ noise and minimising power consumption. The Charge Pump and DC Servo are described separately (see “Charge Pump” and “DC Servo” respectively). It is recommended to connect a zobel network to the headphone output pins HPOUT1L and HPOUT1R for best audio performance in all applications. The components of the zobel network have the effect of dampening high frequency oscillations or instabilities that can arise outside the audio band under certain conditions. Possible sources of these instabilities include the inductive load of a headphone coil or an active load in the form of an external line amplifier. The capacitance of lengthy cables or PCB tracks can also lead to amplifier instability. The zobel network should comprise of a 20 resistor and 100nF capacitor in series with each other, as illustrated in Figure 27. If any ground-referenced headphone output is not used, then the zobel network components can be omitted from the corresponding output pin, and the pin can be left floating. The respective headphone driver(s) should not be enabled in this case. WM8993 HPOUT1L HPOUT1R HPOUT1FB AGND = 0V 100 nF 20Ω 100 nF 20Ω AGND = 0V Figure 27 Zobel Network Components for HPOUT1L and HPOUT1R The headphone output incorporates a common mode, or ground loop, feedback path which provides rejection of system-related ground noise. The return path is via HPOUT1FB. This pin must be connected to ground for normal operation of the headphone output. No register configuration is required. Note that the HPOUT1FB pin should be connected to GND close to the headphone jack, as illustrated in Figure 27. Rev 4.1 90 WM8993 EARPIECE DRIVER OUTPUT CONFIGURATIONS The earpiece driver outputs HPOUT2P and HPOUT2N are driven by the HPOUT2MIX output mixer, which can take inputs from the mixer output PGAs MIXOUTLVOL and MIXOUTRVOL, or from the low power, differential Direct Voice path IN2LP/VRXN and IN2RP/VRXP. Fine volume control is available on the output mixer paths using MIXOUTLVOL and MIXOUTRVOL. A selectable -6dB attenuation is available on the HPOUT2MIX output, as described in Table 52 (refer to the “Output Signal Path” section). The earpiece outputs are designed to operate in a BTL configuration, driving 50mW into a typical 16 ear speaker. For suppression of pop noise there are two separate enables for the earpiece driver; HPOUT2_ENA enables the output stage and HPOUT2_IN_ENA enables the mixer and input stage. HPOUT2_IN_ENA should be enabled a minimum of 50s before HPOUT2_ENA – see “Control Write Sequencer” section for an example power sequence. LINE OUTPUT CONFIGURATIONS The four line outputs LINEOUT1P, LINEOUT1N, LINEOUT2P and LINEOUT2N provide a highly flexible combination of differential and single-ended configurations, each driven by a dedicated output mixer. There is a selectable -6dB gain option in each mixer to avoid clipping when mixing more than one signal into a line output. Additional volume control is available at other locations within each of the supported signal paths. For more information about the line output mixing options, refer to the “Output Signal Path” section. Typical applications for the line outputs (single-ended or differential) are:  Handset or headset microphone output to external voice CODEC  Stereo line output  Output to external speaker driver(s) to support additional loudspeakers (e.g. stereo 2W with external driver plus on-chip mono 2W output) When single-ended mode is selected for either LINEOUT1 or LINEOUT2, a buffered VMID must be enabled as a reference for the outputs. This is enabled by setting the LINEOUT_VMID_BUF_ENA bit as defined in Table 62. REGISTER ADDRESS R56 (38h) AntiPOP1 BIT LABEL DEFAULT 7 LINEOUT_VMID_BUF_E NA 0b DESCRIPTION Enables VMID reference for line outputs in single-ended mode 0 = Disabled 1 = Enabled Table 62 LINEOUT VMID Buffer for Single-Ended Operation Some example line output configurations are listed and illustrated below. Rev 4.1  Differential line output from Mic/Line input on IN1L PGA  Differential line output from Mic/Line input on IN1R PGA  Stereo differential line output from output mixers MIXOUTL and MIXOUTR  Stereo single-ended line output from output mixer to either LINEOUT1 or LINEOUT2  Mono single-ended line output from output mixer 91 WM8993 LINEOUT1NMIX LINEOUT1NMIX MIXOUTLVOL MIXOUTLVOL MIXOUTRVOL MIXOUTRVOL + IN1R LINEOUT1N IN1L Ground Loop Noise Rejection LINEOUT1PMIX LINEOUT1PMIX MIXOUTLVOL + IN1L IN1R 0dB or -6dB LINEOUT1P IN1L + IN1L IN1R IN1R LINEOUT1P 0dB or -6dB Ground Loop Noise Rejection Min = -57dB Max = +6dB Step = 1dB Ground Loop Noise Rejection Min = -57dB Max = +6dB Step = 1dB MIXOUTLVOL MIXOUTLVOL Min = -57dB Max = +6dB Step = 1dB Min = -57dB Max = +6dB Step = 1dB MIXOUTRVOL MIXOUTRVOL LINEOUT2NMIX LINEOUT2NMIX MIXOUTLVOL MIXOUTLVOL MIXOUTRVOL MIXOUTRVOL + IN1R LINEOUT2N Ground Loop Noise Rejection LINEOUT2PMIX IN1L IN1R Ground Loop Noise Rejection 0dB or -6dB LINEOUT2PMIX MIXOUTRVOL IN1L LINEOUT2N IN1L 0dB or -6dB IN1R + IN1R IN1L MIXOUTRVOL + 0dB or -6dB LINEOUT2P IN1L IN1L IN1R IN1R + LINEOUT2P 0dB or -6dB Ground Loop Noise Rejection Ground Loop Noise Rejection LINEOUT1N_MUTE=0, LINEOUT1P_MUTE=0 LINEOUT1N_MUTE=0, LINEOUT1P_MUTE=0 LINEOUT2N_MUTE=0, LINEOUT2P_MUTE=0 LINEOUT2N_MUTE=0, LINEOUT2P_MUTE=0 LINEOUT1_MODE=0 LINEOUT1_MODE=0 LINEOUT2_MODE=0 LINEOUT2_MODE=0 IN1L_TO_LINEOUT1P=1 IN1R_TO_LINEOUT1P=1 IN1R_TO_LINEOUT2P=1 IN1L_TO_LINEOUT2P=1 Figure 28 Differential Line Out from input PGA Figure 29 Differential Line Out from input PGA IN1L (to LINEOUT1) and IN1R (to LINEOUT2) IN1R (to LINEOUT1) and IN1L (to LINEOUT2) LINEOUT1NMIX LINEOUT1NMIX MIXOUTLVOL MIXOUTLVOL MIXOUTRVOL MIXOUTRVOL + IN1R LINEOUT1N IN1R IN1L Ground Loop Noise Rejection 0dB or -6dB LINEOUT1PMIX LINEOUT1N Ground Loop Noise Rejection LINEOUT1PMIX MIXOUTLVOL IN1L MIXOUTLVOL + IN1L IN1R + IN1L 0dB or -6dB IN1R 0dB or -6dB LINEOUT1P IN1L IN1L IN1R IN1R + 0dB or -6dB Ground Loop Noise Rejection Min = -57dB Max = +6dB Step = 1dB LINEOUT1P Ground Loop Noise Rejection Min = -57dB Max = +6dB Step = 1dB MIXOUTLVOL MIXOUTLVOL Min = -57dB Max = +6dB Step = 1dB Min = -57dB Max = +6dB Step = 1dB MIXOUTRVOL MIXOUTRVOL LINEOUT2NMIX LINEOUT2NMIX MIXOUTLVOL MIXOUTLVOL MIXOUTRVOL MIXOUTRVOL + IN1R LINEOUT2N IN1R IN1L Ground Loop Noise Rejection 0dB or -6dB LINEOUT2PMIX IN1L IN1R LINEOUT2N Ground Loop Noise Rejection LINEOUT2PMIX MIXOUTRVOL IN1L IN1R + IN1L 0dB or -6dB MIXOUTRVOL + 0dB or -6dB LINEOUT2P IN1L IN1L IN1R IN1R + 0dB or -6dB Ground Loop Noise Rejection LINEOUT2P Ground Loop Noise Rejection LINEOUT1N_MUTE=0, LINEOUT1P_MUTE=0 LINEOUT1N_MUTE=0, LINEOUT1P_MUTE=0 LINEOUT2N_MUTE=0, LINEOUT2P_MUTE=0 LINEOUT2N_MUTE=0, LINEOUT2P_MUTE=0 LINEOUT1_MODE=0 LINEOUT1_MODE=1 LINEOUT2_MODE=0 MIXOUTL_TO_LINEOUT1P=1 MIXOUTL_TO_LINEOUT1P=1 MIXOUTR_TO_LINEOUT1N=1 MIXOUTR_TO_LINEOUT2P=1 LINEOUT_VMID_BUF_ENA=1 Figure 30 Figure 31 Stereo Differential Line Out from MIXOUTL and MIXOUTR Rev 4.1 Ground Loop Noise Rejection 0dB or -6dB MIXOUTLVOL IN1L LINEOUT1N IN1L 0dB or -6dB IN1R + IN1R Stereo Single-Ended Line Out from MIXOUTL and MIXOUTR to LINEOUT1 92 WM8993 LINEOUT1NMIX LINEOUT1NMIX MIXOUTLVOL MIXOUTLVOL MIXOUTRVOL MIXOUTRVOL + IN1R LINEOUT1N IN1L 0dB or -6dB LINEOUT1PMIX Ground Loop Noise Rejection LINEOUT1PMIX MIXOUTLVOL IN1L LINEOUT1N IN1L Ground Loop Noise Rejection 0dB or -6dB MIXOUTLVOL + IN1L IN1R + IN1R IN1R LINEOUT1P 0dB or -6dB IN1L + IN1L IN1R IN1R 0dB or -6dB Ground Loop Noise Rejection Min = -57dB Max = +6dB Step = 1dB LINEOUT1P Ground Loop Noise Rejection Min = -57dB Max = +6dB Step = 1dB MIXOUTLVOL MIXOUTLVOL Min = -57dB Max = +6dB Step = 1dB Min = -57dB Max = +6dB Step = 1dB MIXOUTRVOL MIXOUTRVOL LINEOUT2NMIX LINEOUT2NMIX MIXOUTLVOL MIXOUTLVOL MIXOUTRVOL MIXOUTRVOL + IN1R LINEOUT2N IN1L 0dB or -6dB LINEOUT2PMIX IN1L IN1R Ground Loop Noise Rejection LINEOUT2PMIX MIXOUTRVOL IN1L LINEOUT2N IN1L Ground Loop Noise Rejection 0dB or -6dB IN1R + IN1R MIXOUTRVOL + LINEOUT2P 0dB or -6dB IN1L IN1L IN1R IN1R + 0dB or -6dB Ground Loop Noise Rejection LINEOUT2P Ground Loop Noise Rejection LINEOUT1N_MUTE=0, LINEOUT1P_MUTE=0 LINEOUT1N_MUTE=0, LINEOUT1P_MUTE=0 LINEOUT2N_MUTE=0, LINEOUT2P_MUTE=0 LINEOUT2N_MUTE=0, LINEOUT2P_MUTE=0 LINEOUT1_MODE=1 LINEOUT1_MODE=1 MIXOUTL_TO_LINEOUT2N=1 LINEOUT2_MODE=1 MIXOUTR_TO_LINEOUT2P=1 MIXOUTL_TO_LINEOUT1N=1 and/or LINEOUT_VMID_BUF_ENA=1 MIXOUTL_TO_LINEOUT1P=1 MIXOUTR_TO_LINEOUT2N=1 and/or MIXOUTR_TO_LINEOUT2P=1 LINEOUT_VMID_BUF_ENA=1 Figure 32 Stereo Single-Ended Line Out from MIXOUTL and MIXOUTR to LINEOUT2 Figure 33 Mono Line Out to LINEOUT1N, LINEOUT1P, LINEOUT2N, LINEOUT2P The line outputs incorporate a common mode, or ground loop, feedback path which provides rejection of system-related ground noise. The return path, via LINEOUTFB, is enabled separately for LINEOUT1 and LINEOUT2 using the LINEOUT1_FB and LINEOUT2_FB bits as defined in Table 63. Ground loop feedback is a benefit to single-ended line outputs only; it is not applicable to differential outputs, which already inherently offer common mode noise rejection. REGISTER ADDRESS R55 (37h) BIT 7 LABEL LINEOUT1_FB DEFAULT 0b Additional Control DESCRIPTION Enable ground loop noise feedback on LINEOUT1 0 = Disabled 1 = Enabled 6 LINEOUT2_FB 0b Enable ground loop noise feedback on LINEOUT2 0 = Disabled 1 = Enabled Table 63 Line Output Ground Loop Feedback Enable Rev 4.1 93 WM8993 GENERAL PURPOSE INPUT/OUTPUT The WM8993 provides a number of GPIO functions to enable interfacing and detection of external hardware and to provide logic outputs to other devices. The input functions can be polled directly or can be used to generate an Interrupt (IRQ) event. The GPIO and Interrupt circuits support the following functions:  Button detect (digital input)  Accessory detection (MICBIAS current detection)  Clock output (CLK_SYS divided by OPCLK_DIV)  FLL Lock status output  Temperature sensor output  Control Write Sequencer status  Logic ‘1’ and logic ‘0’ output  Interrupt event (IRQ) output GPIO1 CONTROL The function of the GPIO1 pin can be selected using the GPIO1_SEL field. The available functions are described individually in the subsequent sections. Internal pull-up and pull-down resistors can be enabled for interfacing with external signal sources or push-buttons. GPIO1 may be configured as an input. In this configuration, the GPIO1 is an input to the Interrupt function, with selectable de-bounce and polarity control. The associated interrupt bit is latched once set and can be polled at any time or used to generate Interrupt events. See “Interrupts” for more details of the Interrupt event handling. The interrupt bit is latched once set; it is reset by writing a logic ‘1’ to the GPIO1_EINT register bit. Debouncing is provided in order to avoid false event triggers. Note that TOCLK must be enabled when this input de-bouncing is required. REGISTER ADDRESS R18 (12h) BIT LABEL DEFAULT 0 GPIO1_EIN T 0 GPIO CTRL 1 DESCRIPTION GPIO1 interrupt 0 = interrupt not set 1 = interrupt is set Cleared when a ‘1’ is written R19 (13h) 5 GPIO1_PU 0 GPIO 1 GPIO1 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 4 GPIO1_PD 1 GPIO1 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled Rev 4.1 94 WM8993 REGISTER ADDRESS BIT LABEL DEFAULT 3:0 GPIO1_SEL [3:0] 0000 DESCRIPTION GPIO1 function select 0000 = GPIO input 0001 = OPCLK 0010 = Logic 0 0011 = Logic 1 0100 = FLL_LOCK 0101 = TEMPOK 0110 = Reserved 0111 = IRQ 1000 = MICBIAS1 current detect 1001 = MICBIAS1 short circuit detect 1010 = MICBIAS2 current detect 1011 = MICBIAS short circuit detect 11XX = Reserved R20 (14h) 0 GPIO1_DB GPIO1 input de-bounce 0 IRQ_DEBOU NCE R22 (16h) 0 = disabled 1 = enabled 5 GPIOCTRL2 IM_GPIO1_ EINT 0 GPIO1_POL 0 GPIO1 interrupt mask 0 = do not mask interrupt 1 = mask interrupt R23 (17h) 0 GPIO1 interrupt polarity GPIO_POL 0 = active high 1 = active low Table 64 GPIO1 Configuration and Interrupt Control BUTTON DETECT The analogue input pins IN2LN and IN2RN support alternate functions as general purpose digital inputs GPI7 and GPI8 respectively. These digital signals are inputs to the Interrupt function, with selectable de-bounce and polarity control. The associated interrupt bits are latched once set and can be polled at any time or used as inputs to the IRQ output. See “Interrupts” for more details of the Interrupt event handling. Note that button detect functionality can also be implemented on the GPIO1 pin, as described earlier. The interrupt bits are latched once set; they are reset by writing a logic ‘1’ to the _EINT register bits in Register R18 (12h). De-bouncing is provided in order to avoid false event triggers. Note that TOCLK must be enabled when this input de-bouncing is required. REGISTER ADDRESS R18 (12h) BIT 7 LABEL GPI8_EINT DEFAULT 0 GPIO CTRL 1 DESCRIPTION GPI8 interrupt 0 = interrupt not set 1 = interrupt is set Cleared when a ‘1’ is written 6 GPI7_EINT 0 GPI7 interrupt 0 = interrupt not set 1 = interrupt is set Cleared when a ‘1’ is written R20 (14h) 7 GPI8_DB 0 IRQ_DEBOU NCE GPI8 input de-bounce 0 = disabled 1 = enabled 3 GPI7_DB 0 GPI7 input de-bounce 0 = disabled 1 = enabled Rev 4.1 95 WM8993 REGISTER ADDRESS R22 (16h) BIT LABEL DEFAULT 6 IM_GPI8_EI NT 0 GPI8_ENA 0 GPIOCTRL2 DESCRIPTION GPI8 interrupt mask 0 = do not mask interrupt 1 = mask interrupt 4 GPI8 input enable 0 = disabled 1 = enabled 2 IM_GPI7_EI NT 0 GPI7 interrupt mask 0 = do not mask interrupt 1 = mask interrupt 0 GPI7_ENA 0 GPI7 input enable 0 = disabled 1 = enabled R23 (17h) 7 GPI8_POL 0 GPIO_POL GPI8 interrupt polarity 0 = active high 1 = active low 6 GPI7_POL 0 GPI7 interrupt polarity 0 = active high 1 = active low Table 65 Button Detect Interrupt Control ACCESSORY DETECTION Current detection is provided on each of the microphone bias sources MICBIAS1 and MICBIAS2. These can be configured to detect when an external accessory (such as a microphone) has been connected. The output voltage of each of the microphone bias sources is selectable. Two current detection threshold levels can be set; these thresholds are applicable to both microphone bias sources. The logic signals from the current detect circuits may be output directly on the GPIO1 pin, and may also be used to generate Interrupt events. See “GPIO1 Control” for details of outputting the accessory detection flags on the GPIO1 pin. The accessory detection circuits are inputs to the Interrupt function, with selectable de-bounce and polarity control. The associated interrupt bits are latched once set and can be polled at any time or used as inputs to the IRQ output. See “Interrupts” for more details of the Interrupt event handling. The interrupt bits are latched once set; they are reset by writing a logic ‘1’ to the _EINT register bits in Register R18 (12h). De-bouncing is provided in order to avoid false event triggers. Note that TOCLK must be enabled when this input de-bouncing is required. REGISTER ADDRESS R1 (1h) Power Management (1) BIT LABEL DEFAULT 5 MICB2_ENA 0 DESCRIPTION Microphone Bias 2 Enable 0 = OFF (high impedance output) 1 = ON 4 MICB1_ENA 0 Microphone Bias 2 Enable 0 = OFF (high impedance output) 1 = ON R58 (3Ah) MICBIAS 7:6 JD_SCTHR [1:0] 00 Jack Detect (MICBIAS) Short Circuit threshold 00 = 300uA 01 = 600uA 10 = 1200uA 11 = 2400uA These values are for AVDD1=3.0V and scale proportionally with AVDD1. Rev 4.1 96 WM8993 REGISTER ADDRESS BIT 5:4 LABEL JD_THR [1:0] DEFAULT 00 DESCRIPTION Jack Detect (MICBIAS) Current Detect threshold 00 = 150uA 01 = 300uA 10 = 600uA 11 = 1200uA These values are for AVDD1=3.0V and scale proportionally with AVDD1. 2 JD_ENA 0 Jack Detect (MICBIAS) function enable 0 = disabled 1 = enabled 1 MICB2_LVL 0 Microphone Bias 2 Voltage Control 0 = 0.9 * AVDD1 1 = 0.65 * AVDD1 0 MICB1_LVL 0 Microphone Bias 1 Voltage Control 0 = 0.9 * AVDD1 1 = 0.65 * AVDD1 R18 (12h) 15 GPIO CTRL 1 JD2_SC_EI NT 0 MICBIAS2 Short Circuit interrupt 0 = interrupt not set 1 = interrupt is set Cleared when a ‘1’ is written 14 JD2_EINT 0 MICBIAS2 Current Detect interrupt 0 = interrupt not set 1 = interrupt is set Cleared when a ‘1’ is written 10 JD1_SC_EI NT 0 MICBIAS1 Short Circuit interrupt 0 = interrupt not set 1 = interrupt is set Cleared when a ‘1’ is written 9 JD1_EINT 0 MICBIAS1 Current Detect interrupt 0 = interrupt not set 1 = interrupt is set Cleared when a ‘1’ is written R20 (14h) 15 JD2_SC_DB 0 IRQ_DEBOU NCE MICBIAS2 Short Circuit de-bounce 0 = disabled 1 = enabled 14 JD2_DB 0 MICBIAS2 Current Detect de-bounce 0 = disabled 1 = enabled 10 JD1_SC_DB 0 MICBIAS1 Short Circuit de-bounce 0 = disabled 1 = enabled 9 JD1_DB 0 MICBIAS1 Current Detect de-bounce 0 = disabled 1 = enabled R22 (16h) 13 GPIOCTRL2 IM_JD2_EIN T 0 IM_JD2_SC _EINT 0 MICBIAS2 Current Detect interrupt mask 0 = do not mask interrupt 1 = mask interrupt 12 MICBIAS2 Short Circuit interrupt mask 0 = do not mask interrupt 1 = mask interrupt Rev 4.1 97 WM8993 REGISTER ADDRESS BIT LABEL DEFAULT 10 IM_JD1_SC _EINT 0 IM_JD1_EIN T 0 JD2_SC_PO L 0 DESCRIPTION MICBIAS1 Short Circuit interrupt mask 0 = do not mask interrupt 1 = mask interrupt 9 MICBIAS1 Current Detect interrupt mask 0 = do not mask interrupt 1 = mask interrupt R23 (17h) 15 GPIO_POL MICBIAS2 Short Circuit interrupt polarity 0 = active high 1 = active low 14 JD2_POL 0 MICBIAS2 Current Detect interrupt polarity 0 = active high 1 = active low 10 JD1_SC_PO L 0 JD1_POL 0 MICBIAS1 Short Circuit interrupt polarity 0 = active high 1 = active low 9 MICBIAS1 Current Detect interrupt polarity 0 = active high 1 = active low Table 66 MICBIAS Enable and Interrupt Control The MICBIAS current detect function is enabled by setting the JD_ENA register bit. When this function is enabled, two current thresholds can be defined, using the JD_THR and JD_SC_THR registers. When a change in MICBIAS current which crosses either threshold is detected, then an interrupt event can be generated. In a typical application, accessory insertion would be detected when the MICBIAS current exceeds JD_THR, and microphone hookswitch operation would be detected when the MICBIAS current exceeds JD_SCTHR. The current detect threshold functions are both inputs to the Interrupt control circuit and can be used to trigger an Interrupt event when either threshold is crossed. Both events can also be indicated as an output on a GPIO pin - see “GPIO1 Control”. When GPIO1_SEL = 1000, 1001, 1010 or 1011, the selected Jack Detect status indication is output on the GPIO1 pin. A logic 1 indicates that the associated Jack Detect is asserted. Note that the polarity is not programmable for GPIO output; the GPIO1_POL field and the polarity select bits in Table 66 affect the Interrupt behaviour only. In a typical application, microphone insertion would be detected when the MICBIAS current exceeds the Current Detect threshold set by JD_THR. When the JDn_POL interrupt polarity bit is set to 0, then microphone insertion detection will cause the JDn_EINT interrupt status register to be set. (‘n’ = 1 for MICBIAS1, 2 for MICBIAS2.) For detection of microphone removal, the JDn_POL bit should be set to 1. When the JDn_POL interrupt polarity bit is set to 1, then microphone removal detection will cause the JDn_EINT interrupt status register to be set. Microphone hook switch operation is detected when the MICBIAS current exceeds the Short Circuit Detect threshold set by JD_SCTHR. When the JDn_SC_POL interrupt polarity bit is set to 0, then hook switch operation will cause the JDn_SC_EINT interrupt status register to be set. For detection of microphone removal, the JDn_SC_POL bit should be set to 1. When the JDn_SC_POL interrupt polarity bit is set to 1, then hook switch release will cause the JDn_SC_EINT interrupt status register to be set. Rev 4.1 98 WM8993 CLOCK OUTPUT A clock output (OPCLK) derived from CLK_SYS may be output on the GPIO1 pin. This clock is enabled by register bit OPCLK_ENA, and its frequency is controlled by OPCLK_DIV. See “Clocking and Sample Rates” for more details of the System Clock, CLK_SYS. See “GPIO1 Control” for details of GPIO1 output of OPCLK. REGISTER ADDRESS R2 (02h) BIT 11 Power Management (2) R6 (06h) LABEL OPCLK_EN A DEFAULT 0b DESCRIPTION GPIO Clock Output Enable 0 = disabled 1 = enabled 12:9 OPCLK_DIV 0000 Clocking 1 GPIO Output Clock Divider 0000 = CLK_SYS 0001 = CLK_SYS / 2 0010 = CLK_SYS / 3 0011 = CLK_SYS / 4 0100 = CLK_SYS / 5.5 0101 = CLK_SYS / 6 0110 = CLK_SYS / 8 0111 = CLK_SYS / 12 1000 = CLK_SYS / 16 1001 to 1111 = Reserved Table 67 OPCLK Control FLL LOCK STATUS OUTPUT The WM8993 maintains a flag indicating the lock status of the FLL, which may be used to control other events if required. The FLL Lock status may be output directly on the GPIO1 pin, and may also be used to generate Interrupt events. See “GPIO1 Control” for details of outputting the FLL Lock flag on the GPIO1 pin. See “Clocking and Sample Rates” for more details of the FLL. The FLL Lock signal is an input to the Interrupt function, with selectable de-bounce and polarity control. The associated interrupt bit is latched once set and can be polled at any time or used to trigger the IRQ output. See “Interrupts” for more details of the Interrupt event handling. The interrupt bit is latched once set; it is reset by writing a logic ‘1’ to the FLL_LOCK_EINT register bit. De-bouncing is provided in order to avoid false event triggers. Note that TOCLK must be enabled when this input de-bouncing is required. REGISTER ADDRESS R18 (12h) BIT LABEL DEFAULT 8 FLL_LOCK_ EINT 0 GPIO CTRL 1 DESCRIPTION FLL Lock interrupt 0 = interrupt not set 1 = interrupt is set Cleared when a ‘1’ is written R20 (14h) 8 IRQ_DEBOU NCE R22 (16h) FLL_LOCK_ DB 0 IM_FLL_LO CK_EINT 0 FLL_LOCK_ POL 0 FLL Lock de-bounce 0 = disabled 1 = enabled 8 GPIOCTRL2 FLL Lock interrupt mask 0 = do not mask interrupt 1 = mask interrupt R23 (17h) GPIO_POL 8 FLL Lock interrupt polarity 0 = active high (interrupt is triggered when FLL Lock is reached) 1 = active low (interrupt is triggered when FLL is not locked) Table 68 FLL Lock Interrupt Control Rev 4.1 99 WM8993 The FLL Lock signal is asserted when FLL Lock has been reached. When configured to generate an interrupt event, the default value of FLL_LOCK_POL will cause an interrupt event when FLL Lock has been reached. When GPIO1_SEL = 0100, the FLL Lock signal is output on the GPIO1 pin. A logic 1 indicates that FLL Lock has been reached. Note that the polarity is not programmable for GPIO output; the GPIO1_POL and FLL_LOCK_POL fields affect the Interrupt behaviour only. TEMPERATURE SENSOR OUTPUT The WM8993 incorporates a temperature sensor which detects when the device temperature is within normal limits or if the device is approaching a hazardous temperature condition. The temperature status may be output directly on the GPIO1 pin, and may also be used to generate Interrupt events. See “GPIO1 Control” for details of outputting the Temp OK flag on the GPIO1 pin. The temperature sensor signal is an input to the Interrupt function, with selectable de-bounce and polarity control. The associated interrupt bit is latched once set and can be polled at any time or used to trigger the IRQ output. See “Interrupts” for more details of the Interrupt event handling. The interrupt bit is latched once set; it is reset by writing a logic ‘1’ to the TEMPOK_EINT register bit. De-bouncing is provided in order to avoid false event triggers. Note that TOCLK must be enabled when this input de-bouncing is required. Note that the temperature sensor can be configured to automatically disable the audio outputs of the WM8993 (see “Thermal Shutdown”). In some applications, it may be preferable to manage the temperature sensor event through GPIO or Interrupt functions, allowing a host processor to implement a controlled system response to an over-temperature condition. The temperature sensor must be enabled by setting the TSHUT_ENA register bit. When the TSHUT_OPDIS is also set, then a device over-temperature condition will cause the speaker outputs (SPKOUTL and SPKOUTR) of the WM8993 to be disabled. REGISTER ADDRESS R2 (02h) Power Management (2) BIT LABEL DEFAULT 14 TSHUT_EN A 1 TSHUT_OP DIS 1 DESCRIPTION Thermal sensor enable 0 = disabled 1 = enabled 13 Thermal shutdown control (Causes audio outputs to be disabled if an overtemperature occurs. The thermal sensor must also be enabled.) 0 = disabled 1 = enabled R18 (12h) 11 GPIO CTRL 1 TEMPOK_EI NT 0 Temp OK interrupt 0 = interrupt not set 1 = interrupt is set Cleared when a ‘1’ is written R20 (14h) 11 IRQ_DEBOU NCE R22 (16h) TEMPOK_D B 0 IM_TEMPO K_EINT 0 TEMPOK_P OL 1 Temp OK de-bounce 0 = disabled 1 = enabled 11 GPIOCTRL2 Temp OK interrupt mask 0 = do not mask interrupt 1 = mask interrupt R23 (17h) GPIO_POL 11 Temp OK interrupt polarity 0 = active high (interrupt is triggered when temperature is normal) 1 = active low (interrupt is triggered when over-temperature) Table 69 Temperature Sensor Enable and Interrupt Control Rev 4.1 100 WM8993 The Temperature Sensor output is asserted when the device is within normal operating limits. When configured to generate an interrupt event, the default value of TEMPOK_POL will cause an interrupt event when an overtemperature condition has been reached. When GPIO1_SEL = 0101, the Temperature Sensor status is output on the GPIO1 pin. A logic 0 indicates that an overtemperature condition has been reached. Note that the polarity is not programmable for GPIO output; the GPIO1_POL and TEMPOK_POL fields affect the Interrupt behaviour only. CONTROL WRITE SEQUENCER STATUS The WM8993 Control Write Sequencer (WSEQ) can be used to execute a sequence of register write operations in response to a simple trigger event. When the Control Write Sequencer is executing a sequence, normal access to the register map via the Control Interface is restricted. The WM8993 generates a signal indicating the status of the Control Write Sequencer. The WSEQ_BUSY register bit indicates if the sequencer is busy, or if it has completed the commanded sequence. The WEQ_BUSY bit can be polled at any time. The WSEQ_BUSY bit is an input to the GPIO/Interrupt function, with selectable de-bounce and polarity control. The associated interrupt bit is latched once set and can be used to trigger the IRQ output. See “Interrupts” for more details of the Interrupt event handling. The interrupt bit is latched once set; it is reset by writing a logic ‘1’ to the WSEQ_EINT register bit. Debouncing is provided in order to avoid false event triggers. Note that TOCLK must be enabled when this input de-bouncing is required. Note that the read value of WSEQ_EINT is not valid whilst the Write Sequencer is Busy. REGISTER ADDRESS R18 (12h) BIT LABEL DEFAULT 13 WSEQ_EIN T 0 GPIO CTRL 1 DESCRIPTION Write Sequence interrupt 0 = interrupt not set 1 = interrupt is set Cleared when a ‘1’ is written. Note that the read value of WSEQ_EINT is not valid whilst the Write Sequencer is Busy. R20 (14h) 13 WSEQ_DB 0 IRQ_DEBOU NCE R22 (16h) Write Sequencer de-bounce 0 = disabled 1 = enabled 1 GPIOCTRL2 IM_WSEQ_ EINT 0 WSEQ_POL 0 Write Sequencer interrupt mask 0 = do not mask interrupt 1 = mask interrupt R23 (17h) 13 GPIO_POL Write Sequencer interrupt polarity 0 = active high (interrupt is triggered when WSEQ is busy) 1 = active low (interrupt is triggered when WSEQ is idle) R74 (4Ah) Write Sequencer 4 0 WSEQ_BUS Y 0 Sequencer Busy flag (Read Only). 0 = Sequencer idle 1 = Sequencer busy Note: it is not possible to write to control registers via the control interface while the Sequencer is Busy. Table 70 Control Write Sequencer Interrupt Control The Control Write Sequencer status output is asserted when the sequencer is busy. In order to generate an interrupt event indicating that the sequencer has completed its tasks, WSEQ_POL must be set to ‘1’. Rev 4.1 101 WM8993 LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT The GPIO1 pin can be programmed to drive a logic high or logic low signal. See “GPIO1 Control” for details of GPIO1 register control fields. INTERRUPTS The interrupt status flag IRQ is asserted when any un-masked interrupt input is asserted. It represents the OR’d combination of all the un-masked interrupt inputs. If required, this flag may be inverted using the IRQ_POL register bit. The IRQ flag can be polled at any time, or may be output directly on the GPIO1 pin. An interrupt can be generated by any of the following events described earlier:  Button detect input (on GPIO1, GPI7 or GPI8)  Accessory detection (MICBIAS1 or MICBIAS2 current / short circuit detect)  FLL Lock  Temperature Sensor  Control Write Sequencer The interrupt events are indicated by the _EINT register fields described earlier. The interrupt event flags are latched once set; they are reset by writing a logic ‘1’ to the _EINT register bit. Each of these can be masked as an input to the IRQ function by setting the associated IM_ register field. Note that the _EINT register fields are always valid, regardless of the setting of the associated IM_ register fields. The interrupt behaviour is driven by edge detection (not level detection) of the un-masked inputs. Therefore, if an input remains asserted after the interrupt register has been reset, then the interrupt status flag IRQ will not be triggered again. Note that once the IRQ flag is latched then all subsequent trigger events will be ignored until it has been reset – see Figure 34. See “GPIO1 Control” for details of outputting IRQ on the GPIO1 pin. REGISTER ADDRESS R18 (12h) BIT 12 LABEL IRQ DEFAULT 0 GPIO CTRL 1 R23 (17h) DESCRIPTION Interrupt status (IRQ) Polarity is determined by IRQ_POL This bit is read only. 12 IRQ_POL GPIO_POL 1 Interrupt status (IRQ) polarity 0 = active high 1 = active low Table 71 Interrupt (IRQ) Control signal IRQ Figure 34 GPIO Latch Rev 4.1 102 WM8993 The de-bounce function on the GPIO functions enable transient behaviour to be filtered as illustrated below: TOCLK signal IRQ Figure 35 GPIO De-bounce GPIO SUMMARY Details of the GPIO implementation are shown below. When the GPIO pad is configured as an output, the corresponding input is disabled, as shown in Figure 36 below. This avoids an unstable loop condition. Enable GPIO1 Out In Figure 36 GPIO Pad The GPIO register, i.e. latch structure, is shown in Figure 37 below. The illustration describes the GPIO1 functionality; the equivalent logic applies to the other GPIO functions also (eg. FLL_LOCK, TEMPOK, Jack Detect). In the example illustrated, the de-bounce control field GPIO1_DB determines whether the signal is debounced or not. (Note that TOCLK needs to be present in order for the de-bounce circuit to work.) The polarity bit GPIO1_POL controls whether an interrupt is triggered by a logic 1 level (for GPIO1_POL = 0) or a logic 0 level (for GPIO1_POL = 1). The latch will cause the interrupt to be stored until it is reset by writing to the Interrupt Register. The latched signal is passed to the IRQ circuit, shown in Figure 38. The interrupt status bits can be read at any time from Register R18 (12h). The interrupt status bits are reset by writing a logic 1 to the respective bit in Register R18 (12h). GPIO1_POL GPIO1_DB rd 1 latch d TOCLK Debounce signal to IRQ en wr Figure 37 GPIO Function Rev 4.1 103 Rev 4.1 MICBIAS2 MICBIAS1 MCLK + - + - + - + - BCLK LRCLK MICB2_ENA MICB2_LVL Short Circuit detect MIC Current detect MICB1_ENA MICB1_LVL Short Circuit detect MIC Current detect JD_THR [2:0] 000 = 150uA 001 = 300uA 010 = 600uA 011 = 1200uA JD_SCTHR [1:0] 00 = 300uA 01 = 600uA 10 = 1200uA 11 = 2400uA MIC Detect Threshold GPIO1 Input MICBIAS Current Detect MICBIAS Current Detect JD_ENA JD_THR [2:0] Short Circuit Threshold JD_SCTHR [1:0] IN2RN/GPI8 IN2LN/GPI7 GPIO1 Input MCLK_SRC GPI8_ENA = 1 GPI7_ENA = 1 GPIO1_SEL[3:0] = 0000 WSEQ Busy fREF WSEQ_ENA FLL Lock FLL FLL_ENA Control Write Sequencer FLL_CLK_SRC MCLK_INV TSHUT_ENA Temperature Sensor DeBounce TOCLK SYSCLK_SRC fOUT XXXX_DB f/N OPCLK Control Logic 0 Logic 1 XXXX_POL CLK_SYS OPCLK_ENA OPCLKDIV [2:0] IRQ_POL GPIO1_SEL [3:0] IM_XXXX_EINT Latches GPIO1 Output IRQ GPIO1_EINT GPI7_EINT GPI8_EINT JD1_EINT JD1_SC_EINT JD2_EINT JD2_SC_EINT TEMPOK_EINT WSEQ_EINT FLL_LOCK_EINT WM8993 The overall GPIO and Interrupt function is illustrated in Figure 38. Figure 38 GPIO Summary 104 WM8993 DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting DAC data to the WM8993 and outputting ADC data from it. The digital audio interface uses four pins:  ADCDAT: ADC data output  DACDAT: DAC data input  LRCLK: Left/Right data alignment clock  BCLK: Bit clock, for synchronisation The clock signals BCLK and LRCLK can be outputs when the WM8993 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Four different audio data formats are supported:  Left justified  Right justified  I2S  DSP mode All four of these modes are MSB first. They are described in the following sections. Refer to the “Signal Timing Requirements” section for timing information. Time Division Multiplexing (TDM) is available in all four data format modes. The WM8993 can be programmed to send and receive data in one of two time slots. Two variants of DSP mode are supported - ‘Mode A’ and ‘Mode B’. PCM operation is supported using the DSP mode. MASTER AND SLAVE MODE OPERATION The WM8993 digital audio interface can operate as a master or slave as shown in Figure 39 and Figure 40. BCLK BCLK LRCLK WM8993 ADCDAT DACDAT Figure 39 Master Mode LRCLK Processor WM8993 ADCDAT Processor DACDAT Figure 40 Slave Mode The Audio Interface output control is illustrated above. The master mode control register AIF_MSTR1 determines whether the WM8993 generates the clock signals. The AIF_MSTR1 register field is defined in Table 72. BCLK and LRCLK can be enabled as outputs in Slave mode, allowing mixed Master/Slave operation see “Digital Audio Interface Control”. Rev 4.1 105 WM8993 REGISTER ADDRESS R8 (08h) BIT 15 LABEL DEFAULT DESCRIPTION 0 Audio Interface 1 Master Mode Select AIF_MSTR1 Audio Interface (3) 0 = Slave mode 1 = Master mode Table 72 Audio Interface Master/Slave Control OPERATION WITH TDM Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same bus. The WM8993 ADCs and DACs support TDM in master and slave modes for all data formats and word lengths. TDM is enabled and configured using register bits defined in the “Digital Audio Interface Control” section. BCLK BCLK ADCLRC WM8993 WM8993 or Similar CODEC ADCLRC Processor WM8993 Processor ADCDAT ADCDAT DACDAT DACDAT BCLK BCLK ADCLRC WM8993 or Similar CODEC ADCDAT DACDAT ADCLRC ADCDAT DACDAT Figure 41 TDM with WM8993 as Master Figure 42 TDM with Other CODEC as Master BCLK ADCLRC WM8993 Processor ADCDAT DACDAT BCLK WM8993 or Similar CODEC ADCLRC ADCDAT DACDAT Figure 43 TDM with Processor as Master Rev 4.1 106 WM8993 Note: The WM8993 is a 24-bit device. If the user operates the WM8993 in 32-bit mode then the 8 LSBs will be ignored on the receiving side and not driven on the transmitting side. It is therefore recommended to add a pull-down resistor if necessary to the DACDAT line and the ADCDAT line in TDM mode. BCLK FREQUENCY The BCLK frequency is controlled relative to CLK_SYS by the BCLK_DIV divider. Internal clock divide and phase control mechanisms ensure that the BCLK and LRCLK edges will occur in a predictable and repeatable position relative to each other and relative to the data for a given combination of DAC/ADC sample rate and BCLK_DIV settings. BCLK_DIV is defined in the “Digital Audio Interface Control” section. See also “Clocking and Sample Rates” section for more information. AUDIO DATA FORMATS (NORMAL MODE) The audio data modes supported by the WM8993 are described below. Note that the polarity of the BCLK and LRCLK signals can be inverted if required; the following descriptions all assume the default, non-inverted polarity of these signals. In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DACDAT/ ADCDAT 1 2 MSB 3 n-2 Input Word Length (WL) n-1 n 1 2 3 n-2 n-1 n LSB Figure 44 Right Justified Audio Interface (assuming n-bit word length) In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DACDAT/ ADCDAT 1 MSB 2 3 n-2 Input Word Length (WL) n-1 n 1 2 3 n-2 n-1 n LSB Figure 45 Left Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK Rev 4.1 107 WM8993 frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK 1 BCLK DACDAT/ ADCDAT 1 2 1 BCLK 3 MSB n-2 n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 46 I2S Justified Audio Interface (assuming n-bit word length) In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the frame pulse shown in Figure 47 and Figure 48. In device slave mode, Figure 49 and Figure 50, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. 1/fs 1/2fs LRCLK 1 BCLK BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 2 MSB 3 n-2 RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 47 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master) 1/fs 1/2fs LRCLK BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 MSB 2 3 n-2 Input Word Length (WL) RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Figure 48 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master) Rev 4.1 108 WM8993 1/fs LRCLK Falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 2 MSB 3 n-2 RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 49 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave) 1/fs LRCLK Falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 MSB 2 3 n-2 Input Word Length (WL) RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Figure 50 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave) PCM operation is supported in DSP interface mode. WM8993 ADC data that is output on the Left Channel will be read as mono PCM data by the receiving equipment. Mono PCM data received by the WM8993 will be treated as Left Channel data. This data may be routed to the Left/Right DACs as described in the “Digital Mixing” section. AUDIO DATA FORMATS (TDM MODE) TDM is supported in master and slave mode and is enabled by register bits AIF_ADC_TDM and AIF_DAC_TDM. All audio interface data formats support time division multiplexing (TDM) for ADC and DAC data. Two time slots are available (Slot 0 and Slot 1), selected by register bits AIFADC_TDM_CHAN and AIFDAC_TDM_CHAN which control time slots for the ADC data and the DAC data. When TDM is enabled, the ADCDAT pin will be tri-stated immediately before and immediately after data transmission, to allow another ADC device to drive this signal line for the remainder of the sample period. Note that it is important that two ADC devices do not attempt to drive the data pin simultaneously. A short circuit may occur if the transmission time of the two ADC devices overlap with each other. See “Audio Data Formats (TDM Mode)” for details of the ADCDAT output relative to BCLK signal. Note that it is possible to ensure a gap exists between transmissions by setting the transmitted word length to a value higher than the actual length of the data. For example, if 32-bit word length is selected where only 24-bit data is available, then the WM8993 interface will tri-state after transmission of the 24-bit data, ensuring a gap after the WM8993’s TDM slot. When TDM is enabled, BCLK frequency must be high enough to allow data from both time slots to be transferred. The relative timing of Slot 0 and Slot 1 depends upon the selected data format as shown in Figure 51 to Figure 55. Rev 4.1 109 WM8993 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DACDAT/ ADCDAT SLOT 0 SLOT 1 SLOT 0 SLOT 1 Figure 51 TDM in Right-Justified Mode 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DACDAT/ ADCDAT SLOT 0 SLOT 1 SLOT 0 SLOT 1 Figure 52 TDM in Left-Justified Mode 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK 1 BCLK DACDAT/ ADCDAT SLOT 0 1 BCLK SLOT 1 SLOT 0 SLOT 1 Figure 53 TDM in I2S Mode 1/fs LRCLK Falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK DACDAT/ ADCDAT SLOT 0 LEFT SLOT 0 RIGHT SLOT 1 LEFT SLOT 1 RIGHT Figure 54 TDM in DSP Mode A Rev 4.1 110 WM8993 1/fs LRCLK Falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK DACDAT/ ADCDAT SLOT 0 LEFT SLOT 0 RIGHT SLOT 1 LEFT SLOT 1 RIGHT Figure 55 TDM in DSP Mode B DIGITAL AUDIO INTERFACE CONTROL The register bits controlling audio data format, word length, left/right channel data source and TDM are summarised in Table 73. REGISTER ADDRESS BIT R4 (04h) 15 Audio Interface (1) LABEL AIFADCL_SRC DEFAULT 0 DESCRIPTION Left Digital Audio interface source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 14 AIFADCR_SRC 1 Right Digital Audio interface source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel 13 AIFADC_TDM 0 ADC TDM Enable 0 = Normal ADCDAT operation 1 = TDM enabled on ADCDAT 12 AIFADC_TDM_ CHAN 0 AIF_BCLK_INV 0 ADCDAT TDM Channel Select 0 = ADCDAT outputs data on slot 0 1 = ADCDAT output data on slot 1 8 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted Note that AIF_BCLK_INV selects the BCLK polarity in Master mode and in Slave mode. 7 AIF_LRCLK_IN V 0 Right, left and I2S modes – LRCLK polarity 0 = normal LRCLK polarity 1 = invert LRCLK polarity Note that AIF_LRCLK_INV selects the LRCLK polarity in Master mode and in Slave mode. DSP Mode – mode A/B select 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 6:5 AIF_WL [1:0] 10 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Note - see “Companding” for the selection of 8-bit mode. Rev 4.1 111 WM8993 REGISTER ADDRESS BIT 4:3 LABEL AIF_FMT [1:0] DEFAULT 10 DESCRIPTION Digital Audio Interface Format 00 = Right justified 01 = Left justified 10 = I2S Format 11 = DSP Mode R5 (05h) Audio Interface (2) AIFDACL_SRC 15 0 Left DAC Data Source Select 0 = Left DAC outputs left interface data 1 = Left DAC outputs right interface data AIFDACR_SRC 14 1 Right DAC Data Source Select 0 = Right DAC outputs left interface data 1 = Right DAC outputs right interface data AIFDAC_TDM 13 0 DAC TDM Enable 0 = Normal DACDAT operation 1 = TDM enabled on DACDAT AIFDAC_TDM_ CHAN 12 0 DACDAT TDM Channel Select 0 = DACDAT data input on slot 0 1 = DACDAT data input on slot 1 Table 73 Digital Audio Interface Data Control AUDIO INTERFACE OUTPUT TRI-STATE Register bit AIF_TRIS can be used to tri-state the audio interface pins as described in Table 74. All digital audio interface pins will be tri-stated by this function, regardless of the state of other registers which control these pin configurations. REGISTER ADDRESS R9 (09h) BIT 13 LABEL AIF_TRIS DEFAULT 0 Audio Interface (4) DESCRIPTION Audio Interface Tristate 0 = Audio interface pins operate normally 1 = Tristate all audio interface pins Table 74 Digital Audio Interface Tri-State Control BCLK AND LRCLK CONTROL The audio interface can be programmed to operate in master mode or slave mode using the AIF_MSTR1 register bit. In master mode, the BCLK and LRCLK signals are generated by the WM8993 when any of the ADCs or DACs is enabled. In slave mode, the BCLK and LRCLK clock outputs are disabled by default to allow another digital audio interface to drive these pins. It is also possible to force the BCLK or LRCLK signals to be output using BCLK_DIR and LRCLK_DIR, allowing mixed master and slave modes. The clock generators for the audio interface are enabled according to the control signals shown in Figure 56. The BCLK_DIR and LRCLK_DIR fields are defined in Table 75. The BCLK output can be inverted using the AIF_BCLK_INV register bit. The LRCLK output can be inverted using the AIF_LRCLK_INV register control. Note that in Slave mode, when BCLK is an input, the AIF_BCLK_INV register selects the polarity of the received BCLK signal. Under default conditions, DACDAT input is captured on the rising edge of BCLK, as illustrated in Figure 4. When AIF_BCLK_INV = 1, DACDAT input is captured on the falling edge of BCLK. Rev 4.1 112 WM8993 CLOCK OUTPUT CONTROL AIF_MSTR1 LRCLK_DIR ADCL_ENA ADCR_ENA DACL_ENA DACR_ENA enable BCLK /LRCLK_RATE LRCLK AIF_MSTR1 BCLK_DIR ADCL_ENA ADCR_ENA DACL_ENA DACR_ENA enable SYSCLK /BCLKDIV BCLK Figure 56 Digital Audio Interface Clock Control REGISTER ADDRESS R4 (04h) BIT 9 LABEL BCLK_DIR DEFAULT 0 Audio Interface (1) DESCRIPTION BCLK Direction (Forces BCLK clock to be output in slave mode) 0 = BCLK normal operation 1 = BCLK clock output enabled R6 (06h) 4:1 BCLK_DIV 0100 Clocking (1) BCLK Rate 0000 = CLK_SYS 0001 = CLK_SYS / 1.5 0010 = CLK_SYS / 2 0011 = CLK_SYS / 3 0100 = CLK_SYS / 4 0101 = CLK_SYS / 5.5 0110 = CLK_SYS / 6 0111 = CLK_SYS / 8 1000 = CLK_SYS / 11 1001 = CLK_SYS / 12 1010 = CLK_SYS / 16 1011 = CLK_SYS / 22 1100 = CLK_SYS / 24 1101 = CLK_SYS / 32 1110 = CLK_SYS / 44 1111 = CLK_SYS / 48 R8 (08h) Audio Interface (3) Rev 4.1 15 AIF_MSTR1 0 Audio Interface 1 Master Mode Select 0 = Slave mode 1 = Master mode 113 WM8993 REGISTER ADDRESS BIT R9 (09h) LABEL DEFAULT LRCLK_DIR 11 0 Audio Interface (4) DESCRIPTION LRCLK Direction (Forces LRCLK clock to be output in slave mode) 0 = LRCLK normal operation 1 = LRCLK clock output enabled 10:0 LRCLK_RATE [10:0] 040h LRCLK Rate LRCLK clock output = BCLK / LRCLK_RATE Integer (LSB = 1) Valid from 8..2047 Table 75 Digital Audio Interface Clock Control COMPANDING The WM8993 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides as shown in Table 76. REGISTER ADDRESS R5 (05h) BIT 4 LABEL DEFAULT DAC_COMP 0 Audio Interface (2) DESCRIPTION DAC Companding Enable 0 = disabled 1 = enabled 3 DAC_COMPMODE 0 DAC Companding Type 0 = µ-law 1 = A-law 2 ADC_COMP 0 ADC Companding Enable 0 = disabled 1 = enabled 1 ADC_COMPMODE 0 ADC Companding Type 0 = µ-law 1 = A-law Table 76 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) -1 ≤ x ≤ 1 A-law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA)  for x ≤ 1/A F(x) = ( 1 + lnA|x|) / (1 + lnA)  for 1/A ≤ x ≤ 1 The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs of data. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This provides greater precision for low amplitude signals than for high amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits). Rev 4.1 114 WM8993 8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows samples to be passed using as few as 8 BCLK cycles per LRCLK frame. When using DSP mode B, 8bit data words may be transferred consecutively every 8 BCLK cycles. 8-bit mode (without Companding) may be enabled by setting ADC_COMPMODE=1, when DAC_COMP=0 and ADC_COMP=0. DAC_COMPMODE=1 BIT7 BIT[6:4] BIT[3:0] SIGN EXPONENT MANTISSA or Table 77 8-bit Companded Word Composition u-law Companding 1 120 0.9 Companded Output 0.7 80 0.6 0.5 60 0.4 40 0.3 Normalised Output 0.8 100 0.2 20 0.1 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input Figure 57 µ-Law Companding A-law Companding 1 120 0.9 Companded Output 0.7 80 0.6 0.5 60 0.4 40 0.3 Normalised Output 0.8 100 0.2 20 0.1 0 0 0 0.2 0.4 0.6 0.8 1 Normalised Input Figure 58 A-Law Companding Rev 4.1 115 WM8993 LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit is set, the ADC digital data output is routed to the DAC digital data input path. The digital audio interface input (DACDAT) is not used when LOOPBACK is enabled. REGISTER ADDRESS R5 (05h) BIT 0 LABEL LOOPBACK DEFAULT 0 Audio Interface (2) DESCRIPTION Digital Loopback Function 0 = No loopback 1 = Loopback enabled (ADC data output is directly input to DAC data input). Table 78 Loopback Control Note: When the digital sidetone is enabled, ADC data will also be added to DAC digital data input path within the Digital Mixing circuit. This applies regardless of whether LOOPBACK is enabled. DIGITAL PULL-UP AND PULL-DOWN The WM8993 provides integrated pull-up and pull-down resistors on each of the MCLK, DACDAT, LRCLK and BCLK pins. This provides a flexible capability for interfacing with other devices. Each of the pull-up and pull-down resistors can be configured independently using the register bits described in Table 79. REGISTER ADDRESS R122 (7Ah) BIT 7 LABEL MCLK_PU DEFAULT 0 Digital Pulls DESCRIPTION MCLK pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 6 MCLK_PD 0 MCLK pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled 5 DACDAT_PU 0 DACDAT pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 4 DACDAT_PD 0 DACDAT pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled 3 LRCLK_PU 0 LRCLK pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 2 LRCLK_PD 0 LRCLK pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled 1 BCLK_PU 0 BCLK pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 0 BCLK_PD 0 BCLK pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled Table 79 Digital Audio Interface Pull-Up and Pull-Down Control Rev 4.1 116 WM8993 CLOCKING AND SAMPLE RATES The internal clocks for the WM8993 are all derived from a common internal clock source, CLK_SYS. This clock is the reference for the ADCs, DACs, DSP core functions, digital audio interface, Class D switching amplifier, DC servo control and other internal functions. CLK_SYS can either be derived directly from MCLK, or may be generated from a Frequency Locked Loop (FLL) using MCLK, BCLK or LRCLK as a reference. Many commonly-used audio sample rates can be derived directly from typical MCLK frequencies; the FLL provides additional flexibility for a wide range of MCLK frequencies. To avoid audible glitches, all clock configurations must be set up before enabling playback. The FLL can be used to generate a free-running clock in the absence of an external reference source; see “Frequency Locked Loop (FLL)” for further details. The WM8993 supports Manual or Automatic clocking configuration modes. In Automatic mode, the programmable dividers associated with the ADCs, DACs, DSP core functions, Class D switching and DC servo are configured automatically, with values determined from the CLK_SYS_RATE and SAMPLE_RATE fields. In Automatic mode, the user must also configure the OPCLK (if required), the TOCLK (if required) and the digital audio interface. In Manual mode, the entire clocking configuration can be programmed according to the application requirements. The ADC and DAC sample rates are independently selectable, relative to CLK_SYS, using ADC_DIV and DAC_DIV. These fields must be set according to the required sampling frequency. Oversample rates of 64fs or 128fs are supported (based on a 48kHz sample rate). A 256kHz clock, supporting a number of internal functions, is derived from CLK_SYS, via a programmable divider CLK_256K_DIV. The DC servo control is clocked from CLK_SYS, via a programmable divider CLK_DCS_DIV. The Class D switching amplifier is clocked from CLK_SYS, via a programmable divider DCLK_DIV. A GPIO Clock, OPCLK, can be derived from CLK_SYS and output on the GPIO1 pin to provide clocking to other devices. This clock is enabled by OPCLK_ENA and controlled by OPCLK_DIV. A slow clock, TOCLK, is used to de-bounce the button/accessory detect inputs, and to set the timeout period for volume updates when zero-cross detect is used. This clock is enabled by TOCLK_ENA and controlled by TOCLK_RATE, TOCLK_RATE_X4 and TOCLK_RATE_DIV16. In master mode, BCLK is derived from CLK_SYS via a programmable divider set by BCLK_DIV. In master mode, the LRCLK is derived from BCLK via a programmable divider LRCLK_RATE. The LRCLK can be derived from an internal or external BCLK source, allowing mixed master/slave operation. The control registers associated with Clocking and Sample Rates are shown in Table 80 to Table 85. The overall clocking scheme for the WM8993 is illustrated in Figure 59. Rev 4.1 117 WM8993 MCLK_INV MCLK_SRC GPIO1 CLK_SYS_ENA MCLK fREF BCLK LRCLK FLL fOUT SR_MODE SAMPLE_RATE [2:0] CLK_SYS_RATE [3:0] Automatic DSP Clocking Control DAC_OSR128 f/N In Automatic DSP Clocking Mode, the DAC, ADC, 256kHz, DC Servo and Class D clocks are configured automatically according to SAMPLE_RATE and CLK_SYS_RATE. 256kHz Clock The 256k clock for internal functions is set by CLK_256K_DIV. R0Eh[9] ADC_OSR128 0 = f / 4 (64fs) 1 = f / 2 (128fs) 64fs or 128fs f/N 256fs ADC_DIV [2:0] Class D switching clock R06h[8:6] DCLKDIV[2:0] 000 = CLK_SYS 001 = CLK_SYS / 2 010 = CLK_SYS / 3 011 = CLK_SYS / 4 100 = CLK_SYS / 6 101 = CLK_SYS / 8 110 = CLK_SYS / 12 111 = CLK_SYS / 16 256kHz clock to Charge Pump and other circuits f/N DC Servo Clock DC Servo clock is set by CLK_DCS_DIV. This should be set to around 1.5MHz. R06h[12:9] OPCLK_DIV[3:0] 0000 = CLK_SYS 0001 = CLK_SYS / 2 0010 = CLK_SYS / 3 0011 = CLK_SYS / 4 0100 = CLK_SYS / 5.5 0101 = CLK_SYS / 6 0110 = CLK_SYS / 8 0111 = CLK_SYS / 12 1000 = CLK_SYS /16 1001 – 1111 = Reserved Class D Switching Class D switching rate is set by DCLK_DIV. This should be set to around 768kHz. Note that there is an additional divide by two in the output stage producing a 384kHz switching frequency. OPCLK Output GPIO output clock frequency is set by OPCLK_DIV. R06h[4:1] BCLK_DIV[3:0] 0000 = CLK_SYS 0001 = CLK_SYS / 1.5 0010 = CLK_SYS / 2 0011 = CLK_SYS / 3 0100 = CLK_SYS / 4 0101 = CLK_SYS / 5.5 0110 = CLK_SYS / 6 0111 = CLK_SYS / 8 1000 = CLK_SYS / 11 1001 = CLK_SYS / 12 1010 = CLK_SYS / 16 1011 = CLK_SYS / 22 1100 = CLK_SYS / 24 1101 = CLK_SYS / 32 1110 = CLK_SYS / 44 1111 = CLK_SYS / 48 TOCLK Control The slow clock for volume update timeout and GPIO / accessory detect de-bounce is enabled by TOCLK_ENA. The frequency is set by TOCLK_RATE. BCLK Rate BCLK rate is set by BCLK_DIV in master mode. BCLK rate must be high enough to support the higher of the ADC and DAC sample rates. LRCLK Rate LRCLK rate is set by LRCLK_DIV in master mode. The BCLK input to this divider may be internal or external. Automatic DSP Clocking Mode In automatic mode (SR_MODE), most of the clock dividers are configured automatically by setting the SAMPLE_RATE and CLK_SYS_RATE. · · · · ADC DSP CLK_DCS_DIV DCLKDIV R42h[6:1] CLK_256K_DIV[5:0] 000000 = CLK_SYS 000001 = CLK_SYS / 2 000010 = CLK_SYS / 3 …. 111111 = CLK_SYS / 64 ADC DC Servo clock f/N DAC Clocks DAC DSP clock is set by DAC_DIV. This should be set to 256 x Sample Rate in both master or slave modes. Alternate settings are available using DAC_OSR128 in Automatic Clocking Control mode only. DAC DAC DSP R42h[9] DAC_DIV4 0=f/1 1=f/4 f/N CLK_DSP DSP clocks are derived from CLK_SYS. These are enabled by CLK_DSP_ENA. ADC Clocks ADC DSP clock is set by ADC_DIV. This should be set to 256 x Sample Rate in both master or slave modes. Alternate settings are available using ADC_OSR128. N.64.fs f/N CLK_SYS CLK_SYS Internal clocks are derived from CLK_SYS. These are enabled by CLK_SYS_ENA. CLK_SYS can be derived from MCLK or from the FLL output. The CLK_SYS source is selected by SYSCLK_SRC and has a divide by 2 option (MCLKDIV). f/N DAC_DIV [2:0] R07h[7:5] ADC_DIV[2:0] 000 = CLK_DSP 001 = CLK_DSP / 1.5 010 = CLK_DSP / 2 011 = CLK_DSP / 3 100 = CLK_DSP / 4 101 = CLK_DSP / 5.5 110 = CLK_DSP / 6 111 = Reserved R41h[13:10] CLK_DCS_DIV[3:0] 0000 = CLK_SYS 0001 = CLK_SYS / 1.5 0010 = CLK_SYS / 2 0011 = CLK_SYS / 2.5 0100 = CLK_SYS / 3 0101 = CLK_SYS / 4 0110 = CLK_SYS / 5.5 0111 = CLK_SYS / 6 1000 = CLK_SYS / 8 FLL FLL_CLK_SRC selects the input reference for FLL oscillator. f/N R07h[4:2] DAC_DIV2:0] 000 = CLK_DSP 001 = CLK_DSP / 1.5 010 = CLK_DSP / 2 011 = CLK_DSP / 3 100 = CLK_DSP / 4 101 = CLK_DSP / 5.5 110 = CLK_DSP / 6 111 = Reserved R07h[12] MCLK_DIV 0 = MCLK 1 = MCLK / 2 MCLK MCLK_SRC selects master clock source (MCLK pin or GPIO1 pin). N CLK_DSP SYSCLK_SRC FLL_CLK_SRC N = 1 in Manual mode N >= 1 in DAC_OSR128 (Auto) mode CLK_DSP_ENA CLK_256K_DIV TOCLK_ENA f/1024 f/N R41h[8] TOCLK_RATE_DIV16 0=f/1 1 = f / 16 OPCLK_ENA f.N R41h[7] TOCLK_RATE_X4 0=fx1 1=fx4 Button/accessory detect de-bounce, Volume update timeout f/N R06h[15] TOCLK_RATE 0=f/2 1=f/1 GPIO Clock Output f/N OPCLK_DIV f/N f/N BCLK_DIV [3:0] MASTER MODE CLOCK OUTPUTS LRCLK BCLK LRCLK_RATE [10:0] For digital functionality, CLK_SYS minimum is 64fs (DAC mono), 128fs (DAC stereo) or 256fs (ADC). For specified noise performance, CLK_SYS minimum is 3MHz (normal mode) or 6MHz (DAC_OSR128 mode). DAC_OSR128 mode can be selected in Auto mode, by setting DAC_OSR128. The clock divider control fields are ignored and invalid in Auto Mode. Figure 59 Clocking Scheme Rev 4.1 118 WM8993 CLK_SYS CONTROL The MCLK_SRC bit is used to select the MCLK source. The source may be either MCLK or GPIO1. The selected source may also be inverted by setting the register bit MCLK_INV. Note that it is not recommended to change the control bit MCLK_INV while the WM8993 is processing data as this may lead to clocking glitches and signal pop and clicks. The SYSCLK_SRC bit is used to select the source for CLK_SYS. The source may be either the selected MCLK source or the FLL output. The selected source may also be adjusted by the MCLK_DIV divider to generate CLK_SYS. These register fields are described in Table 80. See “Frequency Locked Loop (FLL)” for more details of the Frequency Locked Loop clock generator. Note that, in AIF Slave modes (see “Digital Audio Interface”), it is important to ensure that CLK_SYS is synchronised with the LRCLK input. This can be achieved by selecting an MCLK input that is derived from the same reference as the LRCLK, or can be achieved by selecting the external BCLK or LRCLK signals as a reference input to one of the FLLs, as a source for CLK_SYS. If CLK_SYS is not synchronised with LRCLK, then clicks arising from dropped or repeated audio samples will occur, due to the inherent tolerances of multiple, asynchronous, system clocks. The CLK_SYS signal is enabled by register bit CLK_SYS_ENA. This bit should be set to 0 when reconfiguring clock sources. It is not recommended to change MCLK_SRC or SYSCLK_SRC while the CLK_SYS_ENA bit is set. The following operating frequency limits must be observed when configuring CLK_SYS. Failure to observe these limits will result in degraded noise performance and/or incorrect ADC/DAC functionality.  CLK_SYS ≤ 12.288MHz  CLK_SYS  3MHz  If DAC_OSR128 = 1 (Automatic Mode only), then CLK_SYS  6MHz  If DAC_MONO = 1, then CLK_SYS  64 x fs  If DAC_MONO = 0, then CLK_SYS  128 x fs  If ADCL_ENA = 1 or ADCR_ENA = 1 then CLK_SYS  256 x fs Note that DAC Mono mode (DAC_MONO = 1) is only valid when one or other DAC is disabled. If both DACs are enabled, then the minimum CLK_SYS for clocking the DACs is 128 x fs. The CLK_SYS control register fields are defined in Table 80. REGISTER ADDRESS R7 (07h) BIT 15 LABEL MCLK_SRC DEFAULT 0 Clocking 2 DESCRIPTION MCLK Source Select 0 = MCLK pin 1 = GPIO1 pin 14 SYSCLK_SRC 0 CLK_SYS Source Select 0 = MCLK 1 = FLL output 12 MCLK_DIV 0 MCLK Divider 0 = MCLK 1 = MCLK / 2 10 MCLK_INV 0b MCLK Invert 0 = MCLK not inverted 1 = MCLK inverted R69 (45h) 1 CLK_SYS_ENA Bus Control 1 1 CLK_SYS enable 0 = disabled 1 = enabled Table 80 MCLK and CLK_SYS Control Rev 4.1 119 WM8993 AUTOMATIC CLOCKING CONFIGURATION The WM8993 supports a wide range of standard audio sample rates from 8kHz to 48kHz. The Automatic Clocking Configuration mode simplifies the configuration of the clock dividers in the WM8993 by deriving most of the necessary parameters from a minimum number of user registers. Automatic Clocking Configuration mode is selected by the SR_MODE bit. When Automatic mode is selected (SR_MODE = 0), some of the Manual clocking configuration registers are invalid and ignored. The affected registers are indicated in Table 82 and Table 83. In Automatic mode, the SAMPLE_RATE field selects the sample rate, fs, of the ADC and DAC. Note that, in Automatic mode, the same sample rate always applies to the ADC and DAC. In Automatic mode, the CLK_SYS_RATE field must be set according to the ratio of CLK_SYS to fs. In Automatic mode, a high performance mode of DAC operation can be selected by setting the DAC_OSR128 bit; in 48kHz sample mode, the DAC_OSR128 feature results in 128x oversampling. Audio performance is improved, but power consumption is also increased. In both Manual and Automatic modes, the CLK_SYS_RATE register must be set; this determines the operating behaviour of the headphone amplifier Charge Pump circuit. REGISTER ADDRESS R10 (0Ah) BIT 13 LABEL DAC_OSR128 DEFAULT 0 DAC CTRL DESCRIPTION DAC Oversample Rate Select 0 = disabled 1 = enabled For 48kHz sample rate, the DAC oversample rate is 128fs when DAC_OSR128 is selected. This is valid in Automatic mode only. The default is 64fs. R65 (41h) 9:7 Clocking 3 SAMPLE_RATE [2:0] 101 Selects the Sample Rate (fs) 000 = 8kHz 001 = 11.025kHz, 12kHz 010 = 16kHz 011 = 22.05kHz, 24kHz 100 = 32kHz 101 = 44.1kHz, 48kHz 4:1 CLK_SYS_RAT E [3:0] 0011 Selects the CLK_SYS / fs ratio 0000 = 64 0001 = 128 0010 = 192 0011 = 256 0100 = 384 0101 = 512 0110 = 768 0111 = 1024 1000 = 1408 1001 = 1536 R66 (42h) 0 SR_MODE 1 Clocking 4 Selects Clocking Configuration mode 0 = Automatic 1 = Manual Table 81 Automatic Clocking Configuration Control Rev 4.1 120 WM8993 ADC / DAC CLOCK CONTROL The clocking of the ADC and DAC circuits is derived from CLK_DSP. This signal is generated from CLK_SYS and is separately enabled, using the register bit CLK_SYS_ENA. The ADC and DAC sample rates are independently selectable, relative to CLK_DSP. The programmable dividers allow selection of the commonly used sample rates from typical audio system clocking frequencies (eg. 12.288MHz). In Manual Clocking Configuration mode, these are controlled using the register bits described in Table 82. In Automatic Clocking Configuration mode, the ADC and DAC clocking dividers are configured automatically by the WM8993. The ADC_DIV register controls the ADC clocking rate. The ADC_DIV register should be set to derive 256 x fs from CLK_DSP, where fs is the ADC sampling rate (eg. 48kHz). Two modes of ADC operation can be selected using the ADC_OSR128 bit; in 48kHz sample mode, setting the ADC_OSR128 bit results in 128x oversampling. This bit is enabled by default, giving best audio performance. Deselecting this bit gives 64x oversampling in 48kHz mode, resulting in decreased power consumption. The DAC_DIV and the DAC_DIV4 registers control the DAC clocking rate. For normal operation, DAC_DIV4 is set, and the DAC_DIV register should be set to derive 256 x fs from CLK_DSP, where fs is the DAC sampling rate. Higher performance DAC operation can be achieved by increasing the DAC oversample rate. This is available in Automatic Clocking Configuration mode only - see Table 81. The ADC / DAC Clock Control registers are defined in Table 82. In Manual Clocking Configuration mode, all of these registers may be controlled. In Automatic Clocking Configuration mode, the CLK_SYS_ENA field must be set by the user. The ADC_OSR128 bit may be selected if required. The remaining ADC / DAC Clock Control registers are ignored and invalid in Automatic mode. REGISTER ADDRESS R7 (07h) BIT 7:5 LABEL ADC_DIV [2:0] DEFAULT 000 Clocking 2 DESCRIPTION ADC Sample Rate Divider 000 = CLK_SYS / 1 001 = CLK_SYS / 1.5 010 = CLK_SYS / 2 011 = CLK_SYS / 3 100 = CLK_SYS / 4 101 = CLK_SYS / 5.5 110 = CLK_SYS / 6 111= Reserved Note - this field is ignored and invalid in Automatic Clocking Configuration mode. 4:2 DAC_DIV [2:0] 000 DAC Sample Rate Divider 000 = CLK_SYS / 1 001 = CLK_SYS / 1.5 010 = CLK_SYS / 2 011 = CLK_SYS / 3 100 = CLK_SYS / 4 101 = CLK_SYS / 5.5 110 = CLK_SYS / 6 111= Reserved Note - this field is ignored and invalid in Automatic Clocking Configuration mode. Rev 4.1 121 WM8993 REGISTER ADDRESS R14 (0Eh) BIT 9 LABEL ADC_OSR128 DEFAULT 1 ADC CTRL DESCRIPTION ADC Oversample Rate Select 0 = disabled 1 = enabled For 48kHz sample rate, the ADC oversample rate is 128fs when ADC_OSR128 is selected. Setting this bit to 0 selects 64fs mode. Default is 128fs. R65 (41h) 0 CLK_DSP_ENA 0 Clocking 3 CLK_DSP enable 0 = disabled 1 = enabled R66 (42h) 9 DAC_DIV4 1 Clocking 4 DAC Divide-by-4 select 0 = DAC_DIV 1 = DAC_DIV / 4 Note - this field is ignored and invalid in Automatic Clocking Configuration mode. Table 82 ADC / DAC Clock Control 256K, DC SERVO, CLASS D CLOCK CONTROL Clocking is required to support a variety of other functions on the WM8993, including the DC Servo and the Class D amplifier. In Manual Clocking Configuration mode, these are controlled using the register bits described in Table 83. In Automatic Clocking Configuration mode, these are configured automatically by the WM8993. The DCLK_DIV register controls the Class D amplifier switching frequency. The DCLK_DIV register should be set to derive a clock frequency of around 768kHz. Note that there is an additional divide by two in the output stage producing a 384kHz switching frequency. The class D switching clock frequency should not be altered while the speaker output is active as this may generate an audible click. The CLK_DCS_DIV register controls the DC Servo clocking frequency. The CLK_DCS_DIV register should be set to derive a clock frequency of around 1.5MHz. The CLK_256K_DIV register controls the 256kHz clocking for other circuits, including the Control Write Sequencer. The CLK_256K_DIV register should be set to derive a clock frequency of around 256kHz. REGISTER ADDRESS R6 (06h) Clocking 1 BIT 8:6 LABEL DCLK_DIV [2:0] DEFAULT 111 DESCRIPTION Class D Clock Divider 000 = CLK_SYS 001 = CLK_SYS / 2 010 = CLK_SYS / 3 011 = CLK_SYS / 4 100 = CLK_SYS / 6 101 = CLK_SYS / 8 110 = CLK_SYS / 12 111 = CLK_SYS / 16 Note - this field is ignored and invalid in Automatic Clocking Configuration mode. Rev 4.1 122 WM8993 REGISTER ADDRESS R65 (41h) BIT 13:10 Clocking 3 LABEL CLK_DCS_DIV [3:0] DEFAULT 1000 DESCRIPTION DC Servo Clock Divider 0000 = CLK_SYS 0001 = CLK_SYS / 1.5 0010 = CLK_SYS / 2 0011 = CLK_SYS / 2.5 0100 = CLK_SYS / 3 0101 = CLK_SYS / 4 0110 = CLK_SYS / 5.5 0111 = CLK_SYS / 6 1000 = CLK_SYS / 8 Note - this field is ignored and invalid in Automatic Clocking Configuration mode. R66 (42h) 6:1 Clocking 4 CLK_256K_DIV [5:0] 2Fh 256kHz Clock Divider 0d = CLK_SYS 1d = CLK_SYS / 2 2d = CLK_SYS / 3 …. 63d = CLK_SYS / 64 Note - this field is ignored and invalid in Automatic Clocking Configuration mode. Table 83 256k, DC Servo, Class D Clock Control OPCLK CONTROL A clock output (OPCLK) derived from CLK_SYS may be output on the GPIO1 pin. This clock is enabled by register bit OPCLK_ENA, and its frequency is controlled by OPCLK_DIV. This output of this clock is also dependent upon the GPIO register settings described under “General Purpose Input/Output”. REGISTER ADDRESS R2 (02h) BIT 11 LABEL OPCLK_ENA DEFAULT 0b Power Manageme nt (2) R6 (06h) DESCRIPTION GPIO Clock Output Enable 0 = disabled 1 = enabled 12:9 Clocking 1 OPCLK_DIV [3:0] 0000b GPIO Output Clock Divider 0000 = CLK_SYS 0001 = CLK_SYS / 2 0010 = CLK_SYS / 3 0011 = CLK_SYS / 4 0100 = CLK_SYS / 5.5 0101 = CLK_SYS / 6 0110 = CLK_SYS / 8 0111 = CLK_SYS / 12 1000 = CLK_SYS / 16 1001 to 1111 = Reserved Table 84 OPCLK Control Rev 4.1 123 WM8993 TOCLK CONTROL A slow clock (TOCLK) is derived from the internally generated 256kHz clock to enable input debouncing and volume update timeout functions. This clock is enabled by register bit TOCLK_ENA, and its frequency is controlled by TOCLK_RATE, TOCLK_RATE_X4, and TOCLK_RATE_DIV16, as described in Table 85. A fixed division of 256kHz / 1024 is applied to generate TOCLK. The final TOCLK frequency may be a multiple or fraction of this frequency, according to the TOCLK_RATE, TOCLK_RATE_X4, and TOCLK_RATE_DIV16 register bits. REGISTER ADDRESS R6 (06h) BIT 15 LABEL DEFAULT TOCLK_RATE 0 DESCRIPTION TOCLK Rate Divider (/2) Clocking 1 0=f/2 1=f/1 14 TOCLK_ENA 0 TOCLK Enable 0 = disabled 1 = enabled R66 (42h) 8 Clocking 4 TOCLK_RATE_ DIV16 0 TOCLK_RATE_ X4 0 TOCLK Rate Divider (/16) 0=f/1 1 = f / 16 7 TOCLK Rate Multiplier 0=fx1 1=fx4 Table 85 TOCLK Control A list of possible TOCLK rates is provided in Table 86. TOCLK_RATE TOCLK_RATE_X4 TOCLK_RATE_DIV16 1 1 0 TOCLK FREQ (HZ) PERIOD (MS) 0 1000 1 1 0 500 2 1 0 0 250 4 0 0 0 125 8 1 1 1 62.5 16 0 1 1 31.25 32 1 0 1 15.625 64 0 0 1 7.8125 128 Table 86 TOCLK Rates BCLK AND LRCLK CONTROL In master mode, BCLK is derived from CLK_SYS via a programmable division set by BCLK_DIV. In master mode, LRCLK is derived from BCLK via a programmable division set by LRCLK_RATE. The BCLK input to this divider may be internal or external, allowing mixed master and slave modes. The direction of these signals and the clock frequencies are controlled as described in the “Digital Audio Interface Control” section. Rev 4.1 124 WM8993 FREQUENCY LOCKED LOOP (FLL) The integrated FLL can be used to generate CLK_SYS from a wide variety of different reference sources and frequencies. The FLL can use either MCLK, BCLK or LRCLK as its reference, which may be a high frequency (eg. 12.288MHz) or low frequency (eg. 32,768kHz) reference. The FLL is tolerant of jitter and may be used to generate a stable CLK_SYS from a less stable input signal. The FLL characteristics are summarised in “Electrical Characteristics”. Note that the FLL can be used to generate a free-running clock in the absence of an external reference source. This is described in the “Free-Running FLL Clock” section below. The FLL control registers are illustrated in Figure 60. FLL Source Divide by FLL_CLK_REF_DIV FREF Multiply by N.K Multiply by FLL_FRATIO N.K = Real number FLL_FRATIO = 1, 2, 4, 8, 16 Divide by FLL_OUTDIV FOUT 90MHz < Fvco < 100MHz FREF 0.7 fs dB 0.7 fs -60 0.7 fs Stopband 3 Stopband 3 Attenuation +/- 0.03 0.546 fs Stopband 2 Stopband 2 Attenuation 0.5 fs 0.25 fs dB 1.4 fs -85 dB 1.4 fs f > 1.4 fs -55 Group delay dB 2 ms TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region Rev 4.1 205 WM8993 ADC FILTER RESPONSES Figure 71 ADC Digital Filter Frequency Response Figure 72 ADC Digital Filter Ripple ADC HIGH PASS FILTER RESPONSES -2.3338m -8.3373 -16.672 -25.007 -33.342 -41.677 -50.012 -58.347 -66.682 -75.017 -83.352 2 5.0248 hpf_response.res MAGNITUDE(dB) 12.624 31.716 79.683 200.19 502.96 1.2636k 3.1747k 7.9761k 20.039k hpf_response2.res MAGNITUDE(dB) hpf_response2.res#1 MAGNITUDE(dB) Figure 73 ADC Digital High Pass Filter Frequency Figure 74 ADC Digital High Pass Filter Ripple (48kHz, Response (48kHz, Hi-Fi Mode, ADC_HPF_CUT[1:0]=00) Voice Mode, ADC_HPF_CUT=01, 10 and 11) Rev 4.1 206 WM8993 DAC FILTER RESPONSES MAGNITUDE(dB) 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 -0.005 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (fs) Figure 75 DAC Digital Filter Frequency Response; (Normal Figure 76 DAC Digital Filter Ripple (Normal Mode) Mode); Sample Rate > 24kHz MAGNITUDE(dB) 0.05 0 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 -0.5 Frequency (fs) Figure 77 DAC Digital Filter Frequency Response; (Sloping Figure 78 DAC Digital Filter Ripple (Sloping Stopband Stopband Mode); Sample Rate

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