CDKWM8351-S-1

w WM8351 Wolfson AudioPlus™ Stereo CODEC with Power Management DESCRIPTION FEATURES The WM8351 is an integrated audio and power management subsystem which provides a cost effective, single-chip solution for portable audio and multimedia systems. Stereo Hi-Fi CODEC • DAC SNR 95dB (‘A’ weighted @ 48kHz), THD –81dB • ADC SNR 95dB (‘A’ weighted @ 48kHz), THD –83dB The integrated audio CODEC provides all the necessary functions for high-quality stereo recording and playback. Programmable on-chip amplifiers allow for the direct connection of headphones and microphones with a minimum of external components. A programmable low-noise bias voltage is available to feed one or more electret microphones. Additional audio features include programmable high-pass filter in the ADC input path. • • • The WM8351 includes four programmable DC-DC converters, four low-dropout (LDO) regulators and a current limit switch to generate suitable supply voltages for each part of the system, including the integrated audio CODEC as well as off-chip components such as a digital core and I/O supplies, and LED lighting. An additional on-chip regulator maintains the backup power for always-on functions. The WM8351 can be powered by a lithium battery, by a wall adaptor or USB. An on-chip battery charger supports both trickle charging and fast (constant current, constant voltage) charging of single-cell lithium batteries. The charge current, termination voltage, and charger time-out are programmable to suit different types of batteries. Internal power management circuitry controls the start-up and shutdown sequencing of clocks and supply voltages. It also detects and handles conditions such as under-voltage, extreme temperatures, and deeply discharged or defective batteries, with a minimum of software involvement. A programmable constant-current sink is available for driving LED strings, e.g. for display backlights or photo-flash applications, in a highly power-efficient way. Additional RGB LEDs can be driven through GPIO pins. The WM8351 includes a 32.768kHz crystal oscillator, an internal RC oscillator, a real-time clock (RTC) and an alarm function capable of waking up the system. Internal circuitry can generate all clock signals required to start up the device. The master clock for the audio CODEC can be input directly, or may be generated internally using an integrated, low power Frequency Locked Loop (FLL). To extend battery life, fine-grained power management enables each function in the WM8351 to be independently powered down through the control interface. The WM8351 forms part of the Wolfson AudioPlusTM series of audio and power management solutions. • 40mW on-chip headphone driver with ‘capless’ option 16Ω headphone load: THD -72dB, Po = 20mW 2 differential microphone inputs with low-noise bias voltage and programmable preamps Programmable high-pass filter for ADC • • • Microphone and Headphone detection Auxiliary inputs for analogue signals Sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1 or 48kHz System Control • Support for 2-wire or 3-/4-wire Control Interface • Handles power sequencing, reset signals and fault conditions • Autonomous power source selection (battery, wall adaptor or USB bus) • Total current drawn from USB bus is limited to comply with USB 2.0 standard and USB OTG supplement Supply Generation • 1 x DC-DC Buck Converter (0.85V - 3.4V, Up to 1A) • 2 x DC-DC Buck Converters (0.85V - 3.4V, Up to 500mA) • 1 x DC-DC Boost Converter (5V - 20V, 40 to 200mA) • 4 x LDO voltage regulators (0.9V - 3.3V, 150mA) LED Drivers • Programmable constant-current sink, suitable for screen backlight or white LED photo flash • 3 open-drain outputs for RGB LEDs Battery Charger • Single-cell Li-Ion / Li-Pol battery charger • Thermal protection for charge control; temperature monitoring available for thermal regulation • LED outputs to indicate charge status and fault conditions Additional Features • • • “Always on” RTC with wake-up alarm Watchdog timer Up to 13 configurable GPIO pins • • • On-chip crystal oscillator and internal RC oscillator Low power FLL supporting wide range of input clocks 7x7mm, 129 BGA package, 0.5mm ball pitch APPLICATIONS • • • WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Portable Audio and Media players Portable Navigation Devices Portable systems powered by single-cell lithium batteries Production Data, February 2011, Rev 4.4 Copyright ©2011 Wolfson Microelectronics plc WM8351 Production Data TYPICAL APPLICATIONS The WM8351 is a complete audio and power management solution for portable media devices. The device incorporates three programmable step-down switching regulators, a step-up switching regulator, a full-featured battery charger, four Low Drop-Out (LDO) voltage regulators which can also serve as hot-swap outputs, a backup supply regulator, a programmable white LED driver, a RealTime Clock (RTC) alongside a 32.768kHz (32kHz) oscillator capable of operating from a backup battery, a 12-bit auxiliary ADC for precise measurements, a ROM-programmable power management state machine and numerous protection features all in a single 7x7mm BGA package. When only battery power is available, a battery switch provides power to all switching regulators (and some other internal modules). When external power is applied (eg. from USB or Wall adapter), the WM8351 seamlessly transitions from battery power (a single-cell Lithium battery) to the applicable external supply. The battery charger is then activated, all internal power for the device is drawn from the appropriate external power source and the battery is disconnected from the load. Maximum battery charge current and charge time are programmable. The USB power manager provides accurate current limiting for the USB pin under all conditions. The hot-swap outputs (LDOs in currentlimited ‘Switch Mode’ operation) are ideal for powering memory cards and other devices that can be inserted while the system is fully powered. The integrated Hi-Fi stereo CODEC incorporates preamps and a low-noise bias voltage for differential microphones, and flexible pseudo-differential drivers for headphone and differential/singleended line outputs. External component requirements are reduced as no separate microphone or headphone amplifiers are required. Digital filter options are available in the ADC and DAC paths, to cater for application filtering. The WM8351 is capable of operating without any external clock, as it can derive all required clocks from its internal crystal oscillator, RC clock, and Frequency Locked Loop. An external low jitter clock may be required in some applications for high performance audio. w PD, February 2011, Rev 4.4 2 w LINEDCDC PGND PVDD DGND GND[0:10] DBVDD DCVDD SDATA SCLK IRQ *MASK/HEARTBEAT MCLK X2 X1 *32KHz ROM REGISTERS CONTROL INTERFACE Interrupt Logic Watchdog Timer *GPIO Capability or other Alternate Function restart FLL OSC 32kHz Differential MICs References AUX ADC AUX3 AUX4 days hours mins secs msecs sync RECORD VOLUME RECORD SELECT INPUT PGAs Control interface d_ready ADC Control Logic WALLFB Real Time Clock USB[0:2] Power Supply Controller ADC R ADC L Volume Hi-Fi DAC DIGITAL FILTERS I2S INTERFACE Programmable Filters Volume Hi-Fi ADC DIGITAL FILTERS DAC R DAC L WM8351 OUTPUT MIXERS DC-DC2 5V-20V 40mA mclk Interrupt Logic GPIO DC-DC4 0.85V-3.4V 500mA DC-DC3 0.85V-3.4V 500mA VP2 FB2 NGATE2 L2 PG2 VRTC HIVDD DC-DC1 0.85V-3.4V 1A Memory Supply PV3 L3 FB3 PG3 Wake-Up Timer LINE[0:2] Power Switches BATT[0:2] Power Management Battery Charge Controller PG1[0:1] FB1 L1[0:1] PV1[0:1] 2MHZ RC OSC Sub System Core Supply PV4 L4 FB4 PG4 USB OTG Supply OUT2R_VOL OUT2L_VOL OUT1R_VOL OUT1L_VOL LDO 3 150mA LDO 4 150mA LDO 1 150mA LDO 2 150mA Limit Switch LED Drivers LINEINT SWVRTC *LINE_SW *FLASH/ MR *LDO_ENA *PWR_ON /RST ON Digital Core Supply HPCOM OUT2R OUT2L OUT1R OUT1L OUT4 OUT3 LDOVDD VOUT4 VINB VOUT3 VOUT2 VINA VOUT1 IP OP *ISINKE *ISINKD/ WAKEUP *ISINKC/CH_IND ISINKA Production Data WM8351 BLOCK DIAGRAM AUX1 AUX2 HPGND HPVDD *PWR_OFF/P_CLK *L_PWR1 *L_PWR2 *L_PWR3 ADCDATA DACDATA LRCLK BCLK VMID AVDD REFGND CONF0 CONF1 IN3R IN3L IN1RN IN2R IN1RP IN1LN IN2L IN1LP MICBIAS CREF RREF PD, February 2011, Rev 4.4 3 WM8351 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 TYPICAL APPLICATIONS ..................................................................................... 2 BLOCK DIAGRAM ................................................................................................. 3 TABLE OF CONTENTS ......................................................................................... 4 1 PIN CONFIGURATION .................................................................................. 9 2 ORDERING INFORMATION .......................................................................... 9 3 PIN DESCRIPTION ...................................................................................... 10 4 THERMAL CHARACTERISTICS ................................................................. 13 5 ABSOLUTE MAXIMUM RATINGS .............................................................. 14 6 RECOMMENDED OPERATING CONDITIONS ........................................... 15 7 ELECTRICAL CHARACTERISTICS ............................................................ 16 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 HI-FI AUDIO CODEC ......................................................................................... 16 DC-DC STEP UP CONVERTER ELECTRICAL CHARACTERISTICS ............... 18 DC-DC STEP DOWN CONVERTER ELECTRICAL CHARACTERISTICS ........ 19 LDO REGULATOR ELECTRICAL CHARACTERISTICS ................................... 21 BATTERY CHARGER........................................................................................ 22 CURRENT LIMIT SWITCH ................................................................................ 22 LED DRIVERS ................................................................................................... 23 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) ......................................... 23 DIGITAL INTERFACES ..................................................................................... 24 AUXILIARY ADC ............................................................................................ 24 TYPICAL POWER CONSUMPTION ............................................................ 25 TYPICAL PERFORMANCE DATA............................................................... 27 9.1 9.2 AUDIO CODEC.................................................................................................. 27 DC-DC CONVERTERS...................................................................................... 28 9.2.1 9.2.2 9.2.3 9.3 10 LDO REGULATORS .......................................................................................... 31 SIGNAL TIMING REQUIREMENTS............................................................. 32 10.1 10.2 10.3 10.4 10.5 11 POWER EFFICIENCY ............................................................................................................. 28 OUTPUT VOLTAGE REGULATION ........................................................................................ 29 DYNAMIC OUTPUT VOLTAGE ............................................................................................... 30 SYSTEM CLOCK TIMING .............................................................................. 32 AUDIO INTERFACE TIMING - MASTER MODE ............................................ 32 AUDIO INTERFACE TIMING - SLAVE MODE................................................ 33 AUDIO INTERFACE TIMING - TDM MODE ................................................... 34 CONTROL INTERFACE TIMING.................................................................... 35 CONTROL INTERFACE .............................................................................. 38 11.1 11.2 11.3 11.4 11.5 11.6 11.7 GENERAL DESCRIPTION ............................................................................. 38 CONTROL INTERFACE MODES ................................................................... 38 2-WIRE SERIAL CONTROL MODE ............................................................... 39 3-WIRE SERIAL CONTROL MODE ............................................................... 42 4-WIRE SERIAL CONTROL MODE ............................................................... 43 REGISTER LOCKING .................................................................................... 44 SPECIAL REGISTERS ................................................................................... 44 11.7.1 11.7.2 12 CHIP ID ................................................................................................................................ 44 DEVICE INFORMATION ...................................................................................................... 44 CLOCKING, TIMING AND SAMPLE RATES .............................................. 45 w PD, February 2011, Rev 4.4 4 WM8351 Production Data 12.1 GENERAL DESCRIPTION ............................................................................. 45 12.1.1 12.1.2 12.1.3 12.2 12.3 CRYSTAL OSCILLATOR................................................................................ 46 CLOCKING AND SAMPLE RATES ................................................................ 47 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.4 SYSCLK CONTROL............................................................................................................. 49 ADC / DAC SAMPLE RATES............................................................................................... 50 BCLK CONTROL ................................................................................................................. 52 ADCLRCLK / DACLRCLK CONTROL ................................................................................. 54 OPCLK CONTROL .............................................................................................................. 55 SLOWCLK CONTROL ......................................................................................................... 55 FLL ................................................................................................................. 55 12.4.1 12.4.2 13 CLOCKING THE AUDIO CODEC ........................................................................................ 46 CLOCKING THE DC-DC CONVERTERS ............................................................................ 46 INTERNAL RC OSCILLATOR .............................................................................................. 46 EXAMPLE FLL CALCULATION ........................................................................................... 58 EXAMPLE FLL SETTINGS .................................................................................................. 59 AUDIO CODEC SUBSYSTEM ..................................................................... 60 13.1 13.2 13.3 13.4 GENERAL DESCRIPTION ............................................................................. 60 AUDIO PATHS ............................................................................................... 61 ENABLING THE AUDIO CODEC ................................................................... 62 INPUT SIGNAL PATH .................................................................................... 64 13.4.1 13.4.2 13.4.3 13.4.4 13.4.5 13.4.6 13.4.7 13.5 ANALOGUE TO DIGITAL CONVERTER (ADC) ............................................. 71 13.5.1 13.5.2 13.6 OUT1L AND OUT1R ............................................................................................................ 82 OUT2L AND OUT2R ............................................................................................................ 84 HEADPHONE OUTPUTS EXTERNAL CONNECTIONS ..................................................... 86 OUT3 AND OUT4 ................................................................................................................ 88 DIGITAL AUDIO INTERFACE ........................................................................ 90 13.10.1 13.10.2 13.10.3 13.10.4 13.11 13.12 ENABLING THE ANALOGUE OUTPUTS ............................................................................ 78 OUTPUT MIXERS ................................................................................................................ 79 ANALOGUE OUTPUTS .................................................................................. 82 13.9.1 13.9.2 13.9.3 13.9.4 13.10 DAC PLAYBACK VOLUME CONTROL ............................................................................... 75 DAC SOFT MUTE AND SOFT UN-MUTE............................................................................ 75 DAC DE-EMPHASIS ............................................................................................................ 76 DAC OUTPUT PHASE AND MONO MIXING ....................................................................... 77 DAC STOPBAND ATTENUATION ....................................................................................... 77 OUTPUT SIGNAL PATH ................................................................................ 78 13.8.1 13.8.2 13.9 DIGITAL SIDETONE ............................................................................................................ 73 DIGITAL TO ANALOGUE CONVERTER (DAC) ............................................. 74 13.7.1 13.7.2 13.7.3 13.7.4 13.7.5 13.8 ADC VOLUME CONTROL ................................................................................................... 72 ADC HIGH-PASS FILTER.................................................................................................... 72 DIGITAL MIXING ............................................................................................ 73 13.6.1 13.7 MICROPHONE INPUTS ...................................................................................................... 64 ENABLING THE PRE-AMPLIFIERS .................................................................................... 65 SELECTING INPUT SIGNALS ............................................................................................. 65 CONTROLLING THE PRE-AMPLIFIER GAINS ................................................................... 66 MICROPHONE BIASING ..................................................................................................... 67 AUXILIARY INPUTS (IN3L AND IN3R) ................................................................................ 68 INPUT MIXERS .................................................................................................................... 69 AUDIO DATA FORMATS ..................................................................................................... 90 AUDIO INTERFACE TDM MODE ........................................................................................ 93 TDM DATA FORMATS......................................................................................................... 93 LOOPBACK ......................................................................................................................... 96 COMPANDING ............................................................................................... 96 ADDITIONAL CODEC FUNCTIONS ............................................................... 98 13.12.1 HEADPHONE JACK DETECT ............................................................................................. 98 w PD, February 2011, Rev 4.4 5 WM8351 Production Data 13.12.2 13.12.3 13.12.4 13.12.5 13.12.6 13.12.7 14 POWER MANAGEMENT SUBSYSTEM .................................................... 105 14.1 14.2 GENERAL DESCRIPTION ........................................................................... 105 POWER MANAGEMENT OPERATING STATES ......................................... 105 14.2.1 14.3 14.4 OVERVIEW........................................................................................................................ 139 DC-DC STEP DOWN CONVERTERS ............................................................................... 140 DC-DC STEP UP CONVERTER ........................................................................................ 141 LDO REGULATOR OPERATION ................................................................. 142 CURRENT LIMIT SWITCH ........................................................................ 143 15.1 15.2 GENERAL DESCRIPTION ........................................................................... 143 CONFIGURING THE CURRENT LIMIT SWITCH......................................... 143 15.2.1 15.2.2 15.2.3 16 LDO REGULATOR ENABLE ............................................................................................. 134 LDO REGULATOR CONTROL .......................................................................................... 135 INTERRUPTS AND FAULT PROTECTION ....................................................................... 137 ADDITIONAL CONTROL FOR LDO1 ................................................................................ 138 DC-DC CONVERTER OPERATION ............................................................. 139 14.8.1 14.8.2 14.8.3 14.9 DC-DC CONVERTER ENABLE ......................................................................................... 126 CLOCKING ........................................................................................................................ 126 DC-DC BUCK (STEP-DOWN) CONVERTER CONTROL.................................................. 127 DC-DC BOOST (STEP-UP) CONVERTER CONTROL...................................................... 130 INTERRUPTS AND FAULT PROTECTION ....................................................................... 132 CONFIGURING THE LDO REGULATORS .................................................. 134 14.7.1 14.7.2 14.7.3 14.7.4 14.8 CONFIGURATION MODE 01 ............................................................................................ 117 CONFIGURATION MODE 10 ............................................................................................ 120 CONFIGURATION MODE 11 ............................................................................................ 123 CONFIGURING THE DC-DC CONVERTERS .............................................. 126 14.6.1 14.6.2 14.6.3 14.6.4 14.6.5 14.7 CONTROL INTERFACE REDIRECTION ........................................................................... 111 STARTING UP IN DEVELOPMENT MODE ....................................................................... 112 CONFIGURING THE WM8351 IN DEVELOPMENT MODE .............................................. 113 CUSTOM MODES ........................................................................................ 116 14.5.1 14.5.2 14.5.3 14.6 STARTUP .......................................................................................................................... 107 POWER-UP SEQUENCING .............................................................................................. 108 SHUTDOWN ...................................................................................................................... 108 POWER CYCLING ............................................................................................................ 109 REGISTER RESET ............................................................................................................ 109 RESET SIGNALS............................................................................................................... 110 DEVELOPMENT MODE ............................................................................... 111 14.4.1 14.4.2 14.4.3 14.5 HIBERNATE STATE SELECTION ..................................................................................... 106 POWER SEQUENCING AND CONTROL .................................................... 107 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 15 MICROPHONE DETECTION ............................................................................................... 99 MID-RAIL REFERENCE (VMID) ........................................................................................ 100 ANTI-POP CONTROL ........................................................................................................ 101 UNUSED ANALOGUE INPUTS/OUTPUTS ....................................................................... 102 ZERO CROSS TIMEOUT .................................................................................................. 104 INTERRUPTS AND FAULT PROTECTION ....................................................................... 104 CURRENT LIMIT SWITCH ENABLE ................................................................................. 143 CURRENT LIMIT SWITCH BULK DETECTION CONTROL .............................................. 144 INTERRUPTS AND FAULT PROTECTION ....................................................................... 144 CURRENT SINKS (LED DRIVERS) .......................................................... 146 16.1 16.2 GENERAL DESCRIPTION ........................................................................... 146 CONSTANT-CURRENT SINK ...................................................................... 146 16.2.1 16.2.2 16.2.3 16.2.4 16.2.5 ENABLING THE SINK CURRENT ..................................................................................... 146 PROGRAMMING THE SINK CURRENT............................................................................ 146 FLASH MODE .................................................................................................................... 147 ON/OFF RAMP TIMING ..................................................................................................... 149 INTERRUPTS AND FAULT PROTECTION ....................................................................... 149 w PD, February 2011, Rev 4.4 6 WM8351 Production Data 16.3 16.4 17 OPEN-DRAIN LED OUTPUTS ..................................................................... 150 LED DRIVER CONNECTIONS ..................................................................... 150 POWER SUPPLY CONTROL .................................................................... 151 17.1 17.2 17.3 17.4 17.5 17.6 17.7 GENERAL DESCRIPTION ........................................................................... 151 BATTERY POWERED OPERATION ............................................................ 152 WALL ADAPTOR (LINE) POWERED OPERATION ..................................... 152 USB POWERED OPERATION ..................................................................... 153 EXTERNAL INTERRUPTS ........................................................................... 155 BACKUP POWER ........................................................................................ 155 BATTERY CHARGER .................................................................................. 156 17.7.1 17.7.2 17.7.3 17.7.4 17.7.5 17.7.6 17.7.7 17.7.8 18 19 SYSTEM MONITORING AND UNDERVOLTAGE LOCKOUT (UVLO) ..... 167 AUXILIARY ADC ........................................................................................ 169 19.1 19.2 19.3 19.4 19.5 19.6 19.7 20 GENERAL DESCRIPTION ........................................................................... 169 INITIATING AUXADC MEASUREMENTS .................................................... 170 VOLTAGE SCALING AND REFERENCES................................................... 172 AUXADC READBACK .................................................................................. 173 CALIBRATION .............................................................................................. 175 DIGITAL COMPARATORS ........................................................................... 176 AUXADC INTERRUPTS ............................................................................... 177 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) ................................. 178 20.1 GENERAL DESCRIPTION ........................................................................... 178 20.1.1 20.1.2 20.1.3 20.2 MAIN REFERENCE (VREF) ......................................................................... 188 LOW-POWER REFERENCE........................................................................ 188 REAL-TIME CLOCK (RTC)........................................................................ 189 22.1 22.2 GENERAL DESCRIPTION ........................................................................... 189 RTC CONTROL ............................................................................................ 189 22.2.1 22.2.2 22.2.3 22.2.4 22.2.5 22.3 22.4 22.5 23 24 LIST OF ALTERNATE FUNCTIONS .................................................................................. 181 SELECTING GPIO ALTERNATE FUNCTIONS ................................................................. 184 VOLTAGE REFERENCES ......................................................................... 188 21.1 21.2 22 CONFIGURING GPIO PINS .............................................................................................. 179 INPUT DE-BOUNCE .......................................................................................................... 180 GPIO INTERRUPTS .......................................................................................................... 180 GPIO ALTERNATE FUNCTIONS ................................................................. 181 20.2.1 20.2.2 21 GENERAL DESCRIPTION................................................................................................. 156 BATTERY CHARGER ENABLE ......................................................................................... 158 TRICKLE CHARGING ........................................................................................................ 158 FAST CHARGING .............................................................................................................. 160 BATTERY CHARGER TIMEOUT AND TERMINATION ..................................................... 162 BATTERY CHARGER STATUS ......................................................................................... 163 BATTERY FAULT CONDITIONS ....................................................................................... 164 INTERRUPTS AND FAULT PROTECTION ....................................................................... 166 MODES OF OPERATION .................................................................................................. 189 RTC TIME REGISTERS ..................................................................................................... 189 SETTING THE TIME .......................................................................................................... 190 RTC ALARM REGISTERS ................................................................................................. 190 SETTING THE ALARM ...................................................................................................... 192 TRIMMING THE RTC ................................................................................... 192 RTC GPIO OUTPUT..................................................................................... 193 RTC INTERRUPTS ...................................................................................... 195 WATCHDOG TIMER .................................................................................. 196 INTERRUPT CONTROLLER ..................................................................... 198 24.1 CONFIGURING THE IRQ PIN ...................................................................... 199 w PD, February 2011, Rev 4.4 7 WM8351 24.2 24.3 Production Data FIRST LEVEL INTERRUPTS ....................................................................... 199 SECOND-LEVEL INTERRUPTS .................................................................. 200 24.3.1 24.3.2 24.3.3 24.3.4 24.3.5 24.3.6 24.3.7 24.3.8 24.3.9 24.3.10 24.3.11 24.3.12 25 TEMPERATURE SENSING ....................................................................... 208 25.1 26 OVERVIEW .................................................................................................. 209 REGISTER BITS BY ADDRESS................................................................ 218 DIGITAL FILTER CHARACTERISTICS ..................................................... 316 28.1 28.2 29 CHIP TEMPERATURE MONITORING ......................................................... 208 REGISTER MAP ........................................................................................ 209 26.1 27 28 DAC FILTER RESPONSES .......................................................................... 316 ADC FILTER RESPONSES .......................................................................... 317 APPLICATIONS INFORMATION ............................................................... 318 29.1 29.2 29.3 29.4 TYPICAL CONNECTIONS ........................................................................... 318 VOLTAGE REFERENCE (VREF) COMPONENTS ....................................... 319 DC-DC (STEP-DOWN) CONVERTER EXTERNAL COMPONENTS ............ 319 DC-DC (STEP-UP) CONVERTER EXTERNAL COMPONENTS .................. 321 29.4.1 29.4.2 29.4.3 29.4.4 29.5 29.6 30 31 32 OVERCURRENT INTERRUPTS ........................................................................................ 200 UNDERVOLTAGE INTERRUPTS ...................................................................................... 200 CURRENT SINK (LED DRIVER) INTERRUPTS ................................................................ 201 EXTERNAL INTERRUPTS ................................................................................................ 201 CODEC INTERRUPTS ...................................................................................................... 201 GPIO INTERRUPTS .......................................................................................................... 203 AUXADC AND DIGITAL COMPARATOR INTERRUPTS................................................... 204 RTC INTERRUPTS ............................................................................................................ 204 SYSTEM INTERRUPTS ..................................................................................................... 205 CHARGER INTERRUPTS ................................................................................................. 205 USB INTERRUPTS ............................................................................................................ 206 WAKE-UP INTERRUPTS .................................................................................................. 207 DC-DC (STEP-UP) CONVERTER - CONSTANT VOLTAGE MODE ................................. 321 DC-DC (STEP-UP) CONVERTER - CONSTANT CURRENT MODE ................................. 323 DC-DC (STEP-UP) CONVERTER - USB MODE ............................................................... 324 DC-DC (STEP-UP) CONVERTER RECOMMENDED COMPONENTS ............................. 324 LDO REGULATOR EXTERNAL COMPONENTS ......................................... 325 PCB LAYOUT ............................................................................................... 326 PACKAGE DIAGRAM ................................................................................ 327 IMPORTANT NOTICE ................................................................................ 328 REVISION HISTORY ................................................................................. 329 w PD, February 2011, Rev 4.4 8 WM8351 Production Data 1 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 A DNC DNC OP PV1 L1 PG1 DNC DNC DNC D NC GPIO12 FB2 PG2 B DNC DNC IP PV1 L1 PG1 DNC DNC DNC PVDD GPIO10 NGATE2 VP2 C L4 PG4 FB4 DNC LINEDCD C FB1 GND GND AUX4 GPIO11 PGND PG3 L2 D PV4 BATT HIVDD N/A N/A N/A N/A N/A N/A N/A FB3 PV3 L3 E BATT BATT WALLFB N/A N/A N/A N/A N/A N/A N/A ISINKA DNC SINKGND F LINE LINE LIN E N/A N/A GND GND GND N/A N/A VOUT4 LDO VDD VINB G USB USB U SB N/A N/A GND GND GND N/A N/A VOUT2 VOUT3 VINA H VRTC LINEINT CREF N/A N/A GND GND GND N/A N/A AUX1 VOUT1 AUX3 J CONF0 X1 RREF N/A N/A N/A N/A N/A N/A N/A OUT1R HPCOM AUX2 K CONF1 ON X2 N/A N/A N/A N/A N/A N/A N/A OUT1L OUT4 HPVDD L G PIO0 /RST SW VRTC IR Q GPIO5 GPIO 8 GPIO9 BCLK LRCLK IN3L IN 1LN OUT3 HPGND M G PIO2 GPIO1 SDA GPIO6 DGND MCLK ADCDATA AVD D IN3R INL2 MICBIAS OUT2R OUT2L N G PIO3 SCL GPIO4 GPIO7 DCVDD DBVDD VMID IN1LP INR2 IN1RP IN1RN DACDATA REFG ND 7mm x 7mm BGA1Z Notes: Pin names beginning with a lower-case "n" indicate that the pin is active low. Colour coding indicates function of pins in typical usage: DC-DC converters LDO voltage regulators Power m anagem ent functions Analogue pins for audio codec Digital pins for audio codec Quiet ground Others 2 ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8351GEB/V -25°C to +85°C 129-ball BGA (7 x 7 mm) (Pb-free) MSL3 260oC WM8351GEB/RV -25°C to +85°C 129-ball BGA (7 x 7 mm) (Pb-free, tape and reel) MSL3 260oC Note: Reel quantity = 2,200 w PD, February 2011, Rev 4.4 9 WM8351 3 Production Data PIN DESCRIPTION Notes: Pins are listed in alphabetical order by name. NAME LOCATION(S) TYPE ADCDATA M7 Digital Output AUX1 H11 POWER DOMAIN DESCRIPTION DBVDD Digital audio output (typically from on-chip audio ADC to external IC) Analogue Input LINE Auxiliary ADC input AUX1 (Special function for connection to temperature-sensing NTC resistor in battery pack) AUX2 J13 Analogue Input LINE Auxiliary ADC input AUX2 AUX3 H13 Analogue Input LINE Auxiliary ADC input AUX3 LINE Auxiliary ADC input AUX4 AUX4 C9 Analogue Input AVDD M8 Supply BATT E1, E2, D2 Analogue I/O Analogue supply for audio CODEC Main battery power connection (can draw power or charge battery) BCLK L8 Digital I/O DBVDD Bit clock signal for digital audio interface CREF H3 Analogue Output VRTC Decoupling for VREF reference voltage (connect capacitor here) CONF0 J1 Digital Input VRTC Start-up configuration pin 0 CONF1 K1 Digital Input VRTC Start-up configuration pin 1 DACDATA N7 Digital Input DBVDD Digital audio input (typically from external IC to on-chip audio DAC) DCVDD N5 Supply Digital core supply; powers digital core of audio CODEC DBVDD N6 Supply Digital I/O buffer supply; powers digital audio interface, control interface and pins GPIO4 to GPIO9 DGND M5 Supply Digital ground; return path for DCVDD and DBVDD supplies FB1 C6 Analogue Input PV1 DC-DC1 feedback pin FB2 A12 Analogue Input VP2 DC-DC2 feedback pin FB3 D11 Analogue Input PV3 DC-DC3 feedback pin FB4 C3 Analogue Input PV4 DC-DC4 feedback pin GND F6, F7, F8, G6, G7, G8, H6, H7 H8, C7, C8 Supply Quiet ground connection for audio CODEC. Note that DC-DC Converters use a separate ground connection. GPIO0 L1 Digital I/O VRTC GPIO1 M2 Digital I/O VRTC General Purpose Input/Output pin 0 General Purpose Input/Output pin 1 GPIO2 M1 Digital I/O VRTC General Purpose Input/Output pin 2 GPIO3 N1 Digital I/O VRTC General Purpose Input/Output pin 3 GPIO4 N3 Digital I/O DBVDD General Purpose Input/Output pin 4 GPIO5 L5 Digital I/O DBVDD General Purpose Input/Output pin 5 GPIO6 M4 Digital I/O DBVDD General Purpose Input/Output pin 6 GPIO7 N4 Digital I/O DBVDD General Purpose Input/Output pin 7 GPIO8 L6 Digital I/O DBVDD General Purpose Input/Output pin 8 GPIO9 L7 Digital I/O DBVDD General Purpose Input/Output pin 9 GPIO10 B11 Digital I/O LINE General Purpose Input/Output pin 10 GPIO11 C10 Digital I/O LINE General Purpose Input/Output pin 11 GPIO12 A11 Digital I/O LINE HIVDD D3 Analogue Output HPCOM J12 Analogue Input HPGND L13 Supply HPVDD K13 Supply IN1LN L11 Analogue Input w General Purpose Input/ Output pin 12 Analogue output from power management unit which determines highest supply from Line, Battery or USB. HPVDD Headphone output amplifier noise compensation input HPVDD Headphone ground; return path for HPVDD supply Headphone supply – powers the analogue outputs OUT1L, OUT1R, OUT2L, OUT2R, OUT3 and OUT4 AVDD Inverting input for left microphone channel PD, February 2011, Rev 4.4 10 WM8351 Production Data NAME LOCATION(S) TYPE POWER DOMAIN DESCRIPTION IN1LP N10 Analogue Input AVDD IN1RN N13 Analogue Input AVDD Non-inverting input 1 for left microphone channel Inverting input for right microphone channel IN1RP N12 Analogue Input AVDD Non-inverting input 1 for right microphone channel Non-inverting input 2 for left microphone channel IN2L M10 Analogue Input AVDD IN2R N11 Analogue Input AVDD Non-inverting input 2 for right microphone channel IN3L L10 Analogue Input AVDD Auxiliary input for analogue audio signals (left channel) IN3R M9 Analogue Input AVDD Auxiliary input for analogue audio signals (right channel) IP B3 Analogue Input ISINKA E11 Analogue Output LDOVDD Constant-current LED driver A L1 A5, B5 Analogue I/O PV1 DC-DC1 inductor connection L2 C13 Analogue I/O VP2 DC-DC2 inductor connection L3 D13 Analogue I/O PV3 DC-DC3 inductor connection L4 C1 Analogue I/O PV4 DC-DC4 inductor connection LDOVDD F12 Supply LDO amplifier supply voltage LINEDCDC C5 Supply Supply connection for DC-DC 1 and 4 control circuits LINEINT H2 Supply Supply connection for Internal Reference circuits LINE F1, F2, F3 Supply LINE supply connection LRCLK L9 Digital I/O DBVDD Word clock (left/right clock) signal for digital audio interface Power input to current limit switch MCLK M6 Digital I/O DBVDD Master Clock (may be generated internally or externally) MICBIAS M11 Analogue Output AVDD Low-noise bias voltage for condenser microphones (connect decoupling capacitor here) NGATE2 B12 Analogue Output VP2 DC-DC2 connection to gate of external power FET IRQ L4 Digital Output open-drain DBVDD Interrupt signal from WM8351 to host processor ON K2 Digital Input /RST L2 Digital Output open-drain OP A3 Analogue Output OUT1L K11 Analogue Output VRTC Connection for power-on switch DBVDD System Reset Signal (active low) AVDD Left channel analogue audio output 1 Power output from current limit switch OUT2L M13 Analogue Output AVDD Left channel analogue audio output 2 OUT1R J11 Analogue Output AVDD Right channel analogue audio output 1 OUT2R M12 Analogue Output AVDD Right channel analogue audio output 2 OUT3 L12 Analogue Output AVDD Analogue audio output 3 (or pseudo-ground output for capacitor-less headphone outputs) OUT4 K12 Analogue Output AVDD Analogue audio output 4 PG1 A6, B6 Supply DC-DC1 power ground PG2 A13 Supply DC-DC2 power ground PG3 C12 Supply DC-DC3 power ground PG4 C2 Supply DC-DC4 power ground PGND C11 Supply Ground connection PV1 A4, B4, Supply DC-DC1 line or battery power input PV3 D12 Supply DC-DC3 line or battery power input PV4 D1 Supply DC-DC4 line or battery power input PVDD B10 Supply Supply connection for DC-DC 2 and 3 control circuits REFGND N8 Supply Reference ground for audio ADC and DAC RREF J3 Analogue Output SCLK N2 Digital Input DBVDD Clock signal for 2-wire serial control interface (5V Tolerant) DBVDD Data line for 2-wire serial control interface (5V Tolerant) VRTC Switchable VRTC output. Typically used for battery temperature monitoring SDATA M3 Digital I/O SINKGND E13 Supply SWVRTC L3 Analogue Output w Connection for external 100kΩ current reference resistor Ground connection for ISINKA PD, February 2011, Rev 4.4 11 WM8351 Production Data NAME LOCATION(S) TYPE POWER DOMAIN DESCRIPTION USB G1, G2, G3 Supply Connection to USB power rail VINA G13 Supply Input to voltage regulators LDO1 and LDO2 VINB F13 Supply VMID N9 Analogue I/O AVDD Reference voltage (normally AVDD/2) for audio CODEC (connect capacitor here) VOUT1 H12 Analogue Output VINA Output of voltage regulator LDO1 VOUT2 G11 Analogue Output VINA Output of voltage regulator LDO2 VOUT3 G12 Analogue Output VINB Output of voltage regulator LDO3 VOUT4 F11 Analogue Output VINB Output of voltage regulator LDO4 Input to voltage regulators LDO3 and LDO4 VP2 B13 Supply DC-DC2 power input VRTC H1 Supply Backup power connection (WM8351 can draw power from this pin or re-charge the backup power source) WALLFB E3 Analogue Input LINE Connection to Wall feedback X1 J2 Analogue Input VRTC Connection for 32.768kHz crystal (input to oscillator from crystal) or 32.768kHz external clock input (when not using crystal) X2 K3 Analogue Output VRTC Connection for 32.768kHz crystal (output from oscillator to crystal) DNC A1, A2, A7, A8, A9, A10, B1, B2, B7, B8, B9, C4, E12 w Do Not Connect PD, February 2011, Rev 4.4 12 WM8351 Production Data 4 THERMAL CHARACTERISTICS Thermal analysis must be performed in the intended application to prevent the WM8351 from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the PCB in relation to surrounding components and the number of PCB layers. Connecting the nine central GND balls through thermal vias and into a large ground plane will aid heat extraction. Three main heat transfer paths exist to surrounding air: - Package top to air (radiation). - Package bottom to PCB (radiation). - Package leads to PCB (conduction). The temperature rise TR is given by TR = PD * ӨJA - PD is the power dissipated by the device. - ӨJA is the thermal resistance from the junction of the die to the ambient temperature and is therefore a measure of heat transfer from the die to surrounding air. - For WM8351, ӨJA = 32°C/W The junction temperature TJ is given by TJ = TA + TR 1. TA, is the ambient temperature. The worst case conditions are when the WM8351 is operating in a high ambient temperature, with low supply voltage, high duty cycle and high output current. Under such conditions, it is possible that the heat dissipated could exceed the maximum junction temperature of the device. Care must be taken to avoid this situation. An example calculation of the junction temperature is given below. - PD = 1W (example figure) - ӨJA = 32°C/W - TR = PD * ӨJA = 32°C - TA = 85°C (example figure) - TJ = TA +TR = 117°C The minimum and maximum operating junction temperatures for the WM8351 are quoted in Section 5. The maximum junction temperature is 125°C. Therefore, the junction temperature in the above example is within the operating limits of the WM8351. w PD, February 2011, Rev 4.4 13 WM8351 5 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at +6dB Right Output Mixer 27k DACR_TO_MIXOUTL MIXOUTL_ENA INR_MIXOUTL_VOL[2:0] VMID_vgnd INR_TO_MIXOUTL 27k IN3L_TO_MIXOUTL INL_MIXOUTL_VOL[2:0] IN3L_MIXOUTL_VOL[2:0] - Left Output Mixer -15 -> +6dB OUT2L_VOL[5:0] VMID_vgnd + - -57 -> +6dB OUT1R_VOL[5:0] VMID_vgnd + - OUT1L_VOL[5:0] -57 -> +6dB OUT1R_ZC OUT1_VU OUT1R_ENA OUT1L_ZC OUT1_VU OUT1L_ENA 20k 50k VMID_op VMID_vgnd - 50k 20k 20k 20k OUT2L_MUTE 50k 20k OUT1R_MUTE 20k OUT1L_MUTE OUT2R_INV + - + - + - + - OUT2R_MUTE OUT2R_INV_MUTE 10k OUT1_FB OUT2R_ENA 20k 50k OUT2_FB HPGND HPVDD 20k HPGND VMID_vgnd + 10k HPVDD IN3R_TO_OUT2R OUT2R_INV_MUTE Beep mix -15 -> +6dB IN3R_OUT2R_VOL[2:0] OUT2R_ZC OUT2_VU OUT2R_ENA VMID_vgnd + - OUT2R_VOL[5:0] -57 -> +6dB + - OUT3_ENA VMID_vgnd + - VMID_vgnd VMID_vgnd VMID_op OUT2L_ZC OUT2_VU OUT2L_ENA DACL_TO_OUT3 20k MIXOUTL_TO_OUT3 20k MIXINL_TO_OUT3 20k OUT4_TO_OUT3 20k OUT3_TO_OUT4 20k DACR_TO_OUT4 20k DACL_TO_OUT4 20k MIXOUTL_TO_OUT4 20k VMID_vgnd + - -57 -> +6dB 20k MIXINR_TO_OUT4 MIXOUTR_TO_OUT4 20k OUT4_ATTN OUT4_ENA HPVDD HPGND HPVDD 20k 20k HPGND HPVDD HPGND HPVDD HPGND OUT2R_ENA 20k 20k HP_COM Vmid o/p tie-off OUT1R (HPR) Vmid o/p tie-off OUT1L (HPL) Vmid o/p tie-off OUT2R Vmid o/p tie-off OUT2L Vmid o/p tie-off OUT3 (LINEL/ VMID/ COM2) Vmid o/p tie-off OUT4 (LINER/ MONO/ VMID) Production Data WM8351 13.2 AUDIO PATHS Figure 36 WM8351 Audio Path Diagram PD, February 2011, Rev 4.4 61 DIGITAL WM8351 Production Data 13.3 ENABLING THE AUDIO CODEC Before the audio CODEC can be used, it must be enabled by writing to the CODEC_ENA, SYSCLK_ENA and BIAS_ENA register bits. ADDRESS BIT DEFAULT DESCRIPTION R12 (0Ch) Power Mgmt 5 12 CODEC_EN A LABEL 0 Master codec enable bit. Until this bit is set, all codec registers are held in reset. 0 = All codec registers held in reset 1 = Codec registers operate normally. R11 (0Bh) Power Mgmt 4 14 SYSCLK_ENA 0 CODEC SYSCLK enable 0 = disabled 1 = enabled R8 (08h) Power Mgmt 1 5 BIAS_ENA 0 Enables bias to analogue audio CODEC circuitry 0 = disabled 1 = enabled Table 19 Enabling the Audio CODEC Each individual part of the audio CODEC (e.g. left/right ADC, left/right DAC, each analogue output pin, mic bias etc.) also has its own enable bit, which must be set before that part of the CODEC can be used. These enable bits are described in the sections that follow. In order to minimize output pop and click noise, it is recommended that the WM8351 device is powered up and down under control using the following sequences: Power Up: w 1. Ensure the CODEC power supplies are available before the CODEC is enabled R12[CODEC_ENA]=1 . The order in which this is done should be DCVDD, DBVDD then HPAVVD And/Or AVDD 2. Mute all outputs 3. Enable the anti-pop circuits by setting ANTI_POP. There are three Anti-pop setting options. Recommended value is ANTI_POP = 01. 4. Ensure external capacitors are full discharged on all outputs that are used by delaying 250ms 5. Set the mixers and DAC volume to required settings 6. Enable VMID by setting VMID_ENA = 1. VMID should raise in a controlled fashion and charge the output capacitors 7. Wait approx 500ms to allow VMID to charge. 8. Disable the anti-pop circuits by setting ANTI_POP = 00. 9. Un-mute all outputs PD, February 2011, Rev 4.4 62 WM8351 Production Data Power Down: w 1. Mute all outputs 2. Enable anti-pop circuits by setting ANTI_POP to the appropriate value. 3. Disable circuits down-stream on outputs 4. Disable VMID by setting VMID_ENA = 0 5. Wait for VMID to discharge (typically 500ms) 6. Disable the anti-pop circuits by setting ANTI_POP = 00 7. Disable all outputs PD, February 2011, Rev 4.4 63 WM8351 Production Data 13.4 INPUT SIGNAL PATH The WM8351 has multiple analogue inputs. There are two input channels, Left and Right, each of which consists of an input PGA stage followed by a boost/mix stage switch into the hi-fi ADC. Each input PGA path has three input pins which can be configured in a variety of ways to accommodate single-ended, differential or dual differential microphones. There are two auxiliary input pins which can be fed into to the input boost/mix stage as well as driving into the output path. A bypass path exists from the output of the boost/mix stage into the output left/right mixers. 13.4.1 MICROPHONE INPUTS The microphone inputs of the WM8351 are designed to accommodate electret condenser microphones or analogue line-in signals. They comprise the following pins: • IN1LP: first non-inverting input, left channel • IN2L: second non-inverting input, left channel • IN1LN: inverting input, left channel • IN1RP: first non-inverting input, right channel • IN2R: second non-inverting input, right channel • IN1RN: inverting input, right channel The non-inverting inputs have constant input impedance to VMID, whereas the inverting input’s impedance varies with the pre-amplifier’s gain. (Note: the terms “inverting” and “non-inverting” refer to the microphone pre-amplifiers only. For overall behaviour, the inverting record mixer and the ADC, whose output can optionally be inverted in the digital domain, must also be taken into account.) Each channel has a programmable pre-amplifier, which supports single-ended or pseudo-differentially connected microphones. The amplified signal for each channel can be digitised in the audio ADC and/or mixed into the output signal path. Figure 37 Microphone Inputs and Pre-amplifiers w PD, February 2011, Rev 4.4 64 WM8351 Production Data 13.4.2 ENABLING THE PRE-AMPLIFIERS ADDRESS BIT R9 (09h) Power Mgmt 2 LABEL DEFAULT DESCRIPTION 8 INL_ENA 0 Left input PGA enable 0 = disabled 1 = enabled 9 INR_ENA 0 Right input PGA enable 0 = disabled 1 = enabled R80 (50h) Left Input Volume 15 INL_ENA 0 Left input PGA enable 0 = disabled 1 = enabled R81 (51h) Right Input Volume 15 INR_ENA 0 Right input PGA enable 0 = disabled 1 = enabled Note: These bits can be accessed through R9 or through R80/R81. Reading from or writing to either register location has the same effect. Table 20 Enabling the Microphone Pre-amplifiers 13.4.3 SELECTING INPUT SIGNALS ADDRESS R72 (48h) Mic Input Control BIT LABEL DEFAULT 0 IN1LP_ENA 1 Connect IN1LP pin to left channel input PGA amplifier positive terminal. 0 = IN1LP not connected to input PGA 1 = input PGA amplifier positive terminal connected to IN1LP (constant input impedance) DESCRIPTION 1 IN1LN_ENA 1 Connect IN1LN pin to left channel input PGA negative terminal. 0 = IN1LN not connected to input PGA 1 = IN1LN connected to input PGA amplifier negative terminal. 2 IN2L_ENA 0 Connect IN2L pin to left channel input PGA amplifier 0 = IN2L not connected to input PGA amplifier 1 = IN2L connected to input PGA amplifier 8 IN1RP_ENA 1 Connect IN1RP pin to right channel input PGA amplifier positive terminal. 0 = IN1RP not connected to input PGA 1 = right channel input PGA amplifier positive terminal connected to IN1RP (constant input impedance) 9 IN1RN_ENA 1 Connect IN1RN pin to right channel input PGA negative terminal. 0 = IN1RN not connected to input PGA 1 = IN1RN connected to right channel input PGA amplifier negative terminal. 10 IN2R_ENA 0 Connect IN2R pin to right channel input PGA 0 = IN2R not connected to input PGA amplifier 1 = IN2R connected to input PGA amplifier Table 21 Selecting Input Pins for the Microphone Pre-amplifiers w PD, February 2011, Rev 4.4 65 WM8351 Production Data 13.4.4 CONTROLLING THE PRE-AMPLIFIER GAINS The gain of each microphone pre-amplifier is controlled by writing to the appropriate control registers. The gain of each pre-amplifier applies to all three inputs associated with that pre-amplifier, whether inverting or non-inverting. Although the gain settings for each pre-amplifier are in two separate registers, both gains can be changed simultaneously using the IN_VU bit (see Table 22). Additionally, it is also possible to control the gain updates to occur when the respective signal crosses through zero. This feature reduces clicking noise caused by gain changes. ADDRESS R80 (50h) Left Input Volume R81 (51h) Right Input Volume BIT LABEL DEFAULT 14 INL_MUTE 0 Mute control for left channel input PGA: 0 = Input PGA not muted, normal operation 1 = Input PGA muted (and disconnected from the following input record mixer). DESCRIPTION 13 INL_ZC 0 Left channel input PGA zero cross enable: 0 = Update gain when gain register changes 1 = Update gain on 1st zero cross after gain register write. 8 IN_VU 0 Input left PGA and input right PGA volume do not update until a 1 is written either IN_VU register bit. 7:2 INL_VOL [5:0] 14 INR_MUTE 0 Mute control for right channel input PGA: 0 = Input PGA not muted, normal operation 1 = Input PGA muted (and disconnected from the following input record mixer). 13 INR_ZC 0 Right channel input PGA zero cross enable: 0 = Update gain when gain register changes 1 = Update gain on 1st zero cross after gain register write. 8 IN_VU 0 Input left PGA and input right PGA volume do not update until a 1 is written either IN_VU register bit. 7:2 INR_VOL [5:0] 01_0000 01_0000 Left channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB Right channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB Table 22 Controlling the Microphone Pre-amplifier Gain w PD, February 2011, Rev 4.4 66 WM8351 Production Data 13.4.5 MICROPHONE BIASING The WM8351 provides a programmable, low-noise bias voltage for condenser electret microphones on the MICBIAS pin. ADDRESS BIT R8 (08h) Power Mgmt 1 4 MICB_ENA LABEL R74 (4Ah) Mic Bias Control 15 MICB_ENA 14 MICB_SEL DEFAULT DESCRIPTION 0 Microphone bias enable 0 = OFF (high impedance output) 1 = ON This bit can be accessed through R8 or through R74. Reading from or writing to either register location has the same effect. 0 Microphone bias voltage control: 0 = 0.9 * AVDD 1 = 0.75 * AVDD Note: MICB_ENA can be accessed through R8 or through R74. Reading from or writing to either register location has the same effect. Table 23 Controlling the Microphone Bias Voltage w PD, February 2011, Rev 4.4 67 WM8351 Production Data 13.4.6 AUXILIARY INPUTS (IN3L AND IN3R) The WM8351 provides two additional analogue input pins, IN3L and IN3R, for line-level audio or “beep” signals. Each pin has a simple input buffer whose output signal can be digitised in the audio ADC and/or mixed into the output signal path. The Right input IN3R may also be connected to the Output Beep Mixer, for output on OUT2R (see Table 43). The input buffers have a nominal default gain of -1 (0dB). IN3L_SHORT, R73[6] 20k IN3L To: Left Input Mixer, Left Output Mixer + 20k Vmid IN3R_SHORT, R73[14] 20k IN3R To: Right Input Mixer, Right Output Mixer, Output Beep Mixer + 20k Vmid Figure 38 Auxiliary Input Buffers REGISTER ADDRESS BIT R9 (09h) Power Mgmt 2 10 IN3L_ENA 0 IN3L Amplifier enable 0 = disabled 1 = enabled 11 IN3R_ENA 0 IN3R Amplifier enable 0 = disabled 1 = enabled 7 IN3L_ENA 0 IN3L Amplifier enable 0 = disabled 1 = enabled 15 IN3R_ENA 0 IN3R Amplifier enable 0 = disabled 1 = enabled 6 IN3L_SHORT 0 Short circuit internal input resistor for IN3L amplifier. 0 = Internal resistor in circuit 1 = Internal resistor shorted 14 IN3R_SHORT 0 Short circuit internal input resistor for IN3R amplifier. 0 = Internal resistor in circuit 1 = Internal resistor shorted R73 (49h) IN3 Input Control LABEL DEFAULT DESCRIPTION Note: IN3L_ENA and IN3R_ENA can be accessed through R9 or through R73. Reading from or writing to either register location has the same effect. Table 24 Controlling the Auxiliary Input Buffers w PD, February 2011, Rev 4.4 68 WM8351 Production Data 13.4.7 INPUT MIXERS The WM8351 has mixers in the input signal paths. This allows each ADC to record either a single input signal or a mix of several signals, as desired. The gain for the different input signals can also be adjusted. Each record mixer has four inputs: • the output of the respective (left/right) microphone pre-amplifier • the IN2L and IN2R pins (used as a line input, bypassing the microphone pre-amplifiers) • the output of the respective (left/right) auxiliary input buffer (ie. inputs IN3L or IN3R) • the output of the OUT4 amplifier (only one input mixer at a time can take this signal) Figure 39 Input Mixers w PD, February 2011, Rev 4.4 69 WM8351 Production Data ADDRESS R9 (09h) Power Mgmt 2 R98 (62h) Input mixer volume for left channel R99 (63h) Input mixer volume for right channel R100 (64h) OUT4 Mixer Control BIT LABEL DEFAULT DESCRIPTION 7 MIXINR_ENA 0 Right input mixer enable 0 = disabled 1 = enabled 6 MIXINL_ENA 0 Left input mixer enable 0 = disabled 1 = enabled 0 INL_MIXINL_V OL 0 Boost enable for left channel input PGA: 0 = PGA output has +0dB gain through input record mixer. 1 = PGA output has +20dB gain through input record mixer. 3:1 IN2L_MIXINL_ VOL [2:0] 000 IN2L amplifier volume control to right input mixer. 000 = Path disabled (disconnected) 001 = -12dB gain through mixer 010 = -9dB gain through mixer … 111 = +6dB gain through mixer 11:9 IN3L_MIXINL_ VOL 000 IN3L amplifier volume control to right input mixer. 000 = Path disabled (disconnected) 001 = -12dB gain through mixer 010 = -9dB gain through mixer … 111 = +6dB gain through mixer 0 INR_MIXINR_ VOL 1 Boost enable for right channel input PGA: 0 = PGA output has +0dB gain through input record mixer. 1 = PGA output has +20dB gain through input record mixer. 7:5 IN2R_MIXINR_ VOL [2:0] 000 IN2R amplifier volume control to right input mixer. 000 = Path disabled (disconnected) 001 = -12dB gain through mixer 010 = -9dB gain through mixer … 111 = +6dB gain through mixer 15:13 IN3R_MIXINR_ VOL [2:0] 000 IN3R amplifier volume control to right input mixer. 000 = Path disabled (disconnected) 001 = -12dB gain through mixer 010 = -9dB gain through mixer … 111 = +6dB gain through mixer 15 OUT4_MIXIN_ DST 0 3:1 OUT4_MIXIN_ VOL [2:0] 000 Select routing of OUT4 to input mixers. 0 = OUT4 to left input mixer. 1 = OUT4 to right input mixer. Controls the gain of OUT4 to left and right input mixers: 000 = Path disabled (left and right mute) 001 = -12dB gain through boost stages 010 = -9dB gain through boost stages …. 111 = +6dB gain through boost stages Table 25 Input Mixer Control w PD, February 2011, Rev 4.4 70 WM8351 Production Data 13.5 ANALOGUE TO DIGITAL CONVERTER (ADC) The high-performance stereo ADC within the WM8351 converts analogue input signals to the digital domain. It uses a multi-bit, over-sampled sigma-delta architecture. The ADC’s over-sampling rate is selectable to control the trade-off between best audio performance and lowest power consumption. A variety of digital filtering stages process the ADC’s digital output signal before it is sent to the WM8351 audio interface. These include: • digital decimation and filtering needed for the ADC • digital volume control • A programmable high-pass filter The audio ADC supports all commonly used audio sampling rates between 8kHz and 48kHz (see Figure 40). Figure 40 ADC Digital Filter Path ADDRESS BIT R11 (0Bh) Power Mgmt 4 2 DEFAULT DESCRIPTION ADCL_ENA R66 (42h) ADC Digital Volume L 15 R11 (0Bh) Power Mgmt 4 3 R67 (43h) ADC Digital Volume R 15 R64 (40h) ADC Control LABEL 0 Left ADC enable 0 = disabled 1 = enabled When ADCR and ADCL are used together as a stereo pair, then both ADCs must be enabled together using a single register write to Register R11 (0Bh). ADCR_ENA 0 Right ADC enable 0 = disabled 1 = enabled When ADCR and ADCL are used together as a stereo pair, then both ADCs must be enabled together using a single register write to Register R11 (0Bh). 1 ADCL_DATINV 0 ADC Left channel polarity: 0 = Normal 1 = Inverted 0 ADCR_DATINV 0 ADC Right Channel Polarity 0 = Normal 1 = Inverted Note: ADCL_ENA and ADCR_ENA can be accessed through R11 or through R66/R67. Reading from or writing to either register location has the same effect. Table 26 Enabling the ADC Left and Right Channels When ADCR and ADCL are used together as a stereo pair, then it is important that ADCR_ENA and ADCL_ENA are enabled at the same time using a single register write. This must be implemented by writing to the bits in Register R11 (0Bh). This ensures that the system starts up both channels in a synchronous manner. w PD, February 2011, Rev 4.4 71 WM8351 Production Data 13.5.1 ADC VOLUME CONTROL Programmable digital volume control is provided to attenuate the ADC’s output signal. ADDRESS BIT R66 (42h) ADC Digital Volume L 8 7:0 R67 (43h) ADC Digital Volume R 8 7:0 LABEL ADC_VU ADCL_VO L [7:0] DESCRIPTION 0 ADC left and ADC right volume do not update until a 1 is written to either ADC_VU register bit. 1100_0000 ADC_VU ADCR_VO L [7:0] DEFAULT 0 1100_0000 Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -71.625dB 0000 0010 = -71.25dB ... 0.375dB steps up to 1110 1111 = +17.625dB ADC left and ADC right volume do not update until a 1 is written to either ADC_VU register bit. Right ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -71.625dB 0000 0010 = -71.25dB ... 0.375dB steps up to 1110 1111 = +17.625dB Table 27 ADC Volume Control 13.5.2 ADC HIGH-PASS FILTER A digital high-pass filter is provided to remove DC offsets from the ADC signal. ADDRESS BIT LABEL DEFAULT DESCRIPTION R11 (0Bh) Power Mgmt 4 13 ADC_HPF_EN A 0 R64 (40h) ADC Control 15 High Pass Filter enable 0 = disabled 1 = enabled This bit can be accessed through R11 or through R64. Reading from or writing to either register location has the same effect. ADC_HPF_CU T [1:0] 00 Select cut-off frequency for high-pass filter 00 = 2^-11 (first order) = 3.7Hz @ fs=44.1kHz 01 = 2^-5 (2nd order) = ~250Hz @ fs=8kHz 10 = 2^-4 (2nd order) = ~250Hz @ fs=16kHz 11 = 2^-3 (2nd order) = ~250Hz @ fs=32kHz 9:8 Note: ADC_HPF_ENA can be accessed through R11 or through R64. Reading from or writing to either register location has the same effect. Table 28 Controlling the ADC High-pass Filter w PD, February 2011, Rev 4.4 72 WM8351 Production Data 13.6 DIGITAL MIXING 13.6.1 DIGITAL SIDETONE A digital sidetone is available when ADCs and DACs are operating at the same sample rate. Digital data from either left or right ADC can be mixed with the audio interface data on the left and right DAC channels. Sidetone data is taken from the ADC high pass filter output, to reduce low frequency noise in the sidetone (e.g. wind noise or mechanical vibration). The digital sidetone will not function when ADCs and DACs are operating at different sample rates. When using the digital sidetone, it is recommended that the ADCs are enabled before un-muting the DACs to prevent pop noise. The DAC volumes and sidetone volumes should be set to an appropriate level to avoid clipping at the DAC input. The digital sidetone is controlled as shown Table 29. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R68 (44h) ADC Divider 11:8 ADCL_DAC_SVOL [3:0] 0000 Left Digital Side tone Volume in dB (See Table 30 for volume range) 7:4 ADCR_DAC_SVOL [3:0] 0000 Right Digital Side tone Volume in dB (See Table 30 for volume range) R60 (3Ch) Digital Side Tone Control 13:12 ADC_TO_DACL [1:0] 00 DAC Left Side-tone Control 11 = Unused 10 = Mix ADCR into DACL 01 = Mix ADCL into DACL 00 = No Side-tone mix into DACL 11:10 ADC_TO_DACR [1:0] 00 DAC Right Side-tone Control 11 = Unused 10 = Mix ADCR into DACR 01 = Mix ADCL into DACR 00 = No Side-tone mix into DACR Table 29 Digital Side Tone Control The coding of ADCL_DAC_SVOL and ADCR_DAC_SVOL is described in Table 30. ADCL_DAC_SVOL or ADCR_DAC_SVOL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SIDETONE VOLUME -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 0 0 0 Table 30 Digital Side Tone Control w PD, February 2011, Rev 4.4 73 WM8351 Production Data 13.7 DIGITAL TO ANALOGUE CONVERTER (DAC) The WM8351 contains a high-performance stereo DAC to convert digital audio signals to the analogue domain. Audio data is passed to the WM8351 via the audio interface, and passes through a variety of digital filtering stages before reaching the DAC. These include: • Digital volume control • Digital filtering, interpolation and sigma-delta modulation functions needed for the DAC The audio DAC supports all commonly used audio sampling rates between 8kHz and 48kHz. Figure 41 DAC Overview BIT LABEL DEFAULT R11 (0Bh) Power Mgmt 4 ADDRESS 4 DACL_EN A 0 Left DAC enable 0 = disabled 1 = enabled DESCRIPTION R50 (32h) DAC Digital Volume Left 15 R11 (0Bh) Power Mgmt 4 5 DACR_EN A 0 Right DAC enable 0 = disabled 1 = enabled R51 (33h) DAC Digital Volume Right 15 Note: These bits can be accessed through R11 or through R50/R51. Reading from or writing to either register location has the same effect. Table 31 DAC Enable w PD, February 2011, Rev 4.4 74 WM8351 Production Data 13.7.1 DAC PLAYBACK VOLUME CONTROL REGISTER ADDRESS R50 (32h) DAC Digital Volume Left BIT 8 7:0 R51 (33h) DAC Digital Volume Right 8 7:0 LABEL DAC_VU DACL_VOL [7:0] DAC_VU DACR_VOL [7:0] DEFAULT 0 1100_0000 0 1100_0000 DESCRIPTION DAC left and DAC right volume do not update until a 1 is written to either DAC_VU register bit. Left DAC digital volume control: 0000_0000 = Digital mute 0000_0001 = -71.625dB 0000_0010 = -71.25dB … (0.375dB steps) 1100_000 = 0dB DAC left and DAC right volume do not update until a 1 is written to either DAC_VU register bit. Right DAC digital volume control: 0000_0000 = Digital mute 0000_0001 = -71.625dB 0000_0010 = -71.25dB … (0.375dB steps) 1100_000 = 0dB Table 32 DAC Volume Control 13.7.2 DAC SOFT MUTE AND SOFT UN-MUTE The WM8351 has a soft mute function which, when enabled, gradually attenuates the volume of the DAC output. When soft mute is disabled, the gain will either gradually ramp back up to the digital gain setting, or return instantly to the digital gain setting, depending on the DAC_MUTEMODE register bit. The DAC is soft-muted by default (DAC_MUTE = 1). To play back an audio signal, this function must first be disabled by setting DAC_MUTE to 0. Soft Mute Mode would typically be enabled (DAC_MUTEMODE = 1) when using DAC_MUTE during playback of audio data so that when DAC_MUTE is subsequently disabled, the sudden volume increase will not create pop noise by jumping immediately to the previous volume level (e.g. resuming playback after pausing during a track). Soft Mute Mode would typically be disabled (DAC_MUTEMODE = 0) when un-muting at the start of a music file, in order that the first part of the track is not attenuated (e.g. when starting playback of a new track, or resuming playback after pausing between tracks). DAC muting and un-muting using volume control bits DACL_VOL and DACR_VOL. DAC muting and un-muting using soft mute bit DAC_MUTE. Soft un-mute not enabled (DAC_MUTEMODE = 0). DAC muting and un-muting using soft mute bit DAC_MUTE. Soft un-mute enabled (DAC_MUTEMODE = 1). Figure 42 DAC Mute Control w PD, February 2011, Rev 4.4 75 WM8351 Production Data The volume ramp rate during soft mute and un-mute is controlled by the DAC_MUTERATE bit. Ramp rates of fs/32 and fs/2 are selectable as shown REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R58 (3Ah) DAC Mute 14 DAC_MUTE 1 DAC Mute 0 = disabled 1 = enabled R59 (3Bh) DAC Mute Volume 14 DAC_MUTEM ODE 0 DAC Soft Mute Mode 0 = Disabling soft-mute (DAC_MUTE=0) will cause the volume to change immediately to the DACL_VOL / DACR_VOL settings 1 = Disabling soft-mute (DAC_MUTE=0) will cause the volume to ramp up gradually to the DACL_VOL / DACR_VOL settings 13 DAC_MUTER ATE 0 DAC Soft Mute Ramp Rate 0 = Fast ramp (24kHz at fs=48k, providing maximum delay of 10.7ms) 1 = Slow ramp (1.5kHz at fs=48k, providing maximum delay of 171ms) Table 33 DAC Soft-Mute Control 13.7.3 DAC DE-EMPHASIS Digital de-emphasis can be applied to the DAC playback data (e.g. when the data comes from a CD with pre-emphasis used in the recording). De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. REGISTER ADDRESS BIT R48 (30h) DAC Control 5:4 LABEL DEEMP [1:0] DEFAULT 00 DESCRIPTION De-Emphasis Control 11 = 48kHz sample rate 10 = 44.1kHz sample rate 01 = 32kHz sample rate 00 = No de-emphasis Table 34 DAC De-Emphasis Control w PD, February 2011, Rev 4.4 76 WM8351 Production Data 13.7.4 DAC OUTPUT PHASE AND MONO MIXING The digital audio data is converted to oversampled bit streams in the on-chip 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion. In normal operation, the left and right channel digital audio data is converted to analogue in two separate DACs. It is also possible for the DACs to output a mono mix of left and right channels, using DAC_MONO. Both DACs must be enabled for this mono mix to function. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R48 (30h) DAC Control 13 DAC_MONO 0 Adds left and right channel and halves the resulting output to create a mono output 1 DACL_DATINV 0 DAC data left channel polarity 0 = Normal 1 = Inverted 0 DACR_DATINV 0 DAC data right channel polarity 0 = Normal 1 = Inverted Table 35 DAC Mono Mix and Phase Invert Select 13.7.5 DAC STOPBAND ATTENUATION The DAC digital filter type is selected by the DAC_SB_FILT register bit as shown in Table 36. REGISTER ADDRESS R59 (3Bh) DAC Digital Control BIT 12 LABEL DAC_SB_FILT DEFAULT 0 DESCRIPTION Selects DAC filter characteristics 0 = Normal mode 1 = Sloping stopband mode Table 36 DAC Filter Selection w PD, February 2011, Rev 4.4 77 WM8351 Production Data 13.8 OUTPUT SIGNAL PATH The analogue output pins produce audio signals to drive headphones, line-out connections and/or external loudspeaker amplifiers. These pins include: • OUT1L and OUT1R • OUT2L and OUT2R • OUT3 and OUT4 OUT1L, OUT1R, OUT2L and OUT2R have individual analogue volume PGAs with -57dB to +6dB ranges. AC-coupled and Capless headphone drive modes are available. Common mode noise rejection is possible using the HPCOM connection. OUT3 and OUT4 can be configured as a stereo line out (OUT3 is left output and OUT4 is right output). OUT3 and OUT4 can also be used as a Vmid buffer to provide a “ground” reference for headphone outputs, eliminating the need for DC blocking capacitors. Alternatively, OUT4 can be used to provide a mono mix of left and right channels. All analogue output pins are powered through the HPVDD and HPGND pins. Each output can drive a headphone load down to 16Ω. There are four output mixers in the output signal path: the left and right channel mixers which control the signals to headphone (and optionally the line outputs) and also dedicated OUT3 and OUT4 mixers. 13.8.1 ENABLING THE ANALOGUE OUTPUTS Each output can be individually enabled or disabled via dedicated control bits. ADDRESS BIT R10 (0Ah) 0 R104 (68h) 15 R10 (0Ah) 1 R105 (69h) 15 R10 (0Ah) 2 R106 (70h) 15 R10 (0Ah) 3 R107 (71h) 15 R9 (09h) 4 R92 (5Ch) 15 R9 (09h) 5 R93 (5Dh) 15 LABEL DEFAULT DESCRIPTION OUT1L_ENA 0 OUT1L enable 0 = disabled 1 = enabled OUT1R_ENA 0 OUT1R enable 0 = disabled 1 = enabled OUT2L_ENA 0 OUT2L enable 0 = disabled 1 = enabled OUT2R_ENA 0 OUT2R enable 0 = disabled 1 = enabled OUT3_ENA 0 OUT3 enable 0 = disabled 1 = enabled OUT4_ENA 0 OUT4 enable 0 = disabled 1 = enabled Note: Each bit can be accessed through two separate control registers. Reading from or writing to either register location has the same effect. Table 37 Enabling the Analogue Outputs w PD, February 2011, Rev 4.4 78 WM8351 Production Data 13.8.2 OUTPUT MIXERS The left and right output channel mixers are shown in Figure 43. These mixers allow the AUX inputs, the ADC bypass and the DAC left and right channels to be combined as desired. This allows a mono mix of the DAC channels to be done as well as mixing in external line-in from the IN3. The IN3L/IN3R and PGA inputs have individual volume control from -15dB to +6dB. The DAC channel volumes can be adjusted in the digital domain if required. The outputs of these mixers are routed to OUT1L/OUT1R or OUT2L/OUT2R. They can also optionally be routed to the OUT3 and OUT4 mixers. Figure 43 Output Mixers w PD, February 2011, Rev 4.4 79 WM8351 Production Data Each output mixer can be enabled or disabled by writing either to the power management control register or to the respective mixer’s own control register. Each analogue signal going into the output mixers can be independently enabled or muted for each mixer. ADDRESS R88 (58h) Left Mixer Control BIT LABEL DEFAULT 0 INL_TO_MIXOU TL 0 Left input PGA output to left output mixer 0 = not selected 1 = selected DESCRIPTION 1 INR_TO_MIXOU TL 0 Right input PGA output to left output mixer 0 = not selected 1 = selected 2 IN3L_TO_MIXO UTL 0 IN3L amplifier output to left channel output mixer: 0 = not selected 1 = selected 11 DACL_TO_MIX OUTL 0 Left DAC output to left output mixer 0 = not selected 1 = selected 12 DACR_TO_MIX OUTL 0 Right DAC output to left output mixer 0 = not selected 1 = selected 15 MIXOUTL_ENA 0 Left output channel mixer enable 0 = disabled 1 = enabled R9 (09h) Power Mgmt 2 0 R89 (59h) Right Mixer Control 0 INL_TO_MIXOU TR 0 Left input PGA output to right output mixer 0 = not selected 1 = selected 1 INR_TO_MIXOU TR 0 Right input PGA output to right output mixer 0 = not selected 1 = selected 3 IN3L_TO_MIXO UTR 0 IN3L amplifier output to left channel output mixer: 0 = not selected 1 = selected 11 DACL_TO_MIX OUTR 0 Left DAC output to right output mixer 0 = not selected 1 = selected 12 DACR_TO_MIX OUTR 0 Right DAC output to right output mixer 0 = not selected 1 = selected 15 MIXOUTR_ENA 0 Right Output Mixer Enable 0 = disabled 1 = enabled R9 (09h) Power Mgmt 2 1 Note: MIXOUTL_ENA and MIXOUTR_ENA can be accessed through two separate control registers. Reading from or writing to either register location has the same effect. Table 38 Selecting Signals into the Output Mixers w PD, February 2011, Rev 4.4 80 WM8351 Production Data The gain for microphone pre-amp and auxiliary input (IN3L/IN3R) signals can be independently adjusted for each output mixer. This does not affect the volume of the same signals going into the separate record mixer. The level of the DAC output signals can be adjusted using the DAC’s digital volume control function (see Table 32). ADDRESS R96 (60h) Output Left Mixer Volume R97 (61h) Output Right Mixer Volume BIT LABEL DEFAULT 3:1 INL_MIXOUTL_VOL [2:0] 000 Left input PGA volume control to left output mixer. 000 = Path disabled (disconnected) 001 = -12dB gain through mixer 010 = -9dB gain through mixer … 111 = +6dB gain through mixer DESCRIPTION 7:5 INR_MIXOUTL_VO L [2:0] 000 Right input PGA volume control to left output mixer. 000 = Path disabled (disconnected) 001 = -12dB gain through mixer 010 = -9dB gain through mixer … 111 = +6dB gain through mixer 11:9 IN3L_MIXOUTL_VO L [2:0] 000 IN3L amplifier volume control to left output mixer 000 = Path disabled (disconnected) 001 = -12dB gain through mixer 010 = -9dB gain through mixer … 111 = +6dB gain through mixer 3:1 INL_MIXOUTR_VO L [2:0] 000 Left input PGA volume control to right output mixer. 000 = Path disabled (disconnected) 001 = -12dB gain through mixer 010 = -9dB gain through mixer … 111 = +6dB gain through mixer 7:5 INR_MIXOUTR_VO L [2:0] 000 Right input PGA volume control to right output mixer. 000 = Path disabled (disconnected) 001 = -12dB gain through mixer 010 = -9dB gain through mixer … 111 = +6dB gain through mixer 15:13 IN3R_MIXOUTR_V OL [2:0] 000 IN3R amplifier volume control to right output mixer. 000 = Path disabled (disconnected) 001 = -12dB gain through mixer 010 = -9dB gain through mixer … 111 = +6dB gain through mixer Table 39 Controlling the Gain of Signals Going into the Output Mixers w PD, February 2011, Rev 4.4 81 WM8351 Production Data 13.9 ANALOGUE OUTPUTS 13.9.1 OUT1L AND OUT1R The headphone outputs, OUT1L and OUT1R can drive a 16Ω or 32Ω headphone load, either through DC blocking capacitors, or DC coupled without any capacitor. Each output has an analogue volume control PGA with a gain range of -57dB to +6dB as shown in Figure 44. Common mode noise rejection is also possible on the OUT1L and OUT1R outputs, using HPCOM as the return path. The HPCOM feature must be enabled via the OUT1_FB register field and the HPCOM connection must be AC coupled to the headphone output. A 4.7uF coupling capacitor is required between the noisy ground connection the HPCOM pin. The control register fields for the OUT1L and OUT1R outputs are described in Table 40. The available output configurations are shown in Section 13.9.3. OUT1L_MUTE R104 [14] From left output mixer -1 OUT1L OUT1L_VOL R104 [7:2] OUT1R_MUTE R105 [14] From right output mixer -1 OUT1R OUT1R_VOL R105 [7:2] HPCOM Vmid OUT1_FB R76 [0] Figure 44 Headphone Outputs OUT1L and OUT1R w PD, February 2011, Rev 4.4 82 WM8351 Production Data ADDRESS R104 (68h) OUT1L Volume R105 (69h) OUT1R Volume BIT DEFAULT DESCRIPTION OUT1L_MUTE 0 OUT1L mute: 0 = normal operation 1 = mute 13 OUT1L_ZC 0 OUT1L volume zero cross enable 0 = Change gain immediately 1 = Change gain on zero cross only 8 OUT1_VU 0 OUT1L and OUT1R volumes do not update until a 1 is written to either OUT1_VU. 7:2 OUT1L_VOL [5:0] 14 OUT1R_MUTE 0 OUT1R mute: 0 = normal operation 1 = mute 13 OUT1R_ZC 0 OUT1R volume zero cross enable 0 = Change gain immediately 1 = Change gain on zero cross only 8 OUT1_VU 0 OUT1L and OUT1R volumes do not update until a 1 is written to either OUT1_VU. 7:2 R76 (4Ch) Output Control LABEL 14 0 OUT1R_VOL [5:0] OUT1_FB 11_1001 11_1001 0 OUT1L volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB OUT1R volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Enable Headphone common mode ground feedback for OUT1 0 = disabled (HPCOM unused) 1 = enabled (common mode feedback through HPCOM) Table 40 Controlling OUT1L and OUT1R w PD, February 2011, Rev 4.4 83 WM8351 Production Data 13.9.2 OUT2L AND OUT2R OUT2L and OUT2R are designed as a stereo pair and can drive a headphone, a line load or a loudspeaker amplifier. Each output has an analogue volume control PGA with a gain range of -57dB to +6dB as shown in Figure 45. Common mode noise rejection is also possible on the OUT2L and OUT2R outputs, using HPCOM as the return path. The HPCOM feature must be enabled via the OUT2_FB register field and the HPCOM connection must be AC coupled to the headphone output. A 4.7uF coupling capacitor is required between the noisy ground connection the HPCOM pin. The signal path from the right output mixer to OUT2R can be inverted, using the OUT2R_INV and OUT2R_INV_MUTE register bits. Table 41 describes the required settings of these register bits for inverted and non-inverted configurations. Note that the OUT2R_MUTE mutes the OUT2R signal path in both cases. OUT2R_INV OUT2R_INV_MUTE 0 1 Non-inverting path from MIXOUTR to OUT2R DESCRIPTION 1 0 Inverting path from MIXOUTR to OUT2R Table 41 OUT2R Signal Path Polarity The control register fields for the OUT2L and OUT2R outputs are described in Table 42. The available output configurations are shown in Section 13.9.3. OUT2L_MUTE R106 [14] From left output mixer -1 OUT2L OUT2L_VOL R106 [7:2] OUT2R_MUTE R107 [14] From right output mixer -1 OUT2R OUT2R_VOL R107 [7:2] HPCOM Vmid OUT2_FB R76 [2] Figure 45 Headphone Outputs OUT2L and OUT2R w PD, February 2011, Rev 4.4 84 WM8351 Production Data ADDRESS BIT LABEL DEFAULT R106 (6Ah) for OUT2L Volume 14 OUT2L_MU TE 0 OUT2L mute: 0 = normal operation 1 = mute 13 OUT2L_ZC 0 OUT2L volume zero cross enable 0 = Change gain immediately 1 = Change gain on zero cross only 8 OUT2_VU 0 OUT2L and OUT2R volumes do not update until a 1 is written to either OUT2_VU register bits. R107 (6Bh) for OUT2R R76 (4Ch) Output Control DESCRIPTION 7:2 OUT2L_VO L [5:0] 11_1001 14 OUT2R_M UTE 0 OUT2R mute: 0 = normal operation 1 = mute 13 OUT2R_ZC 0 OUT2R volume zero cross enable 0 = Change gain immediately 1 = Change gain on zero cross only 10 OUT2R_IN V 0 Enable OUT2R inverting amplifier 0 = disabled 1 = enabled This register must be set to 0 when using the non-inverting MIXOUT2R to OUT2R path. This register must be set to 1 when using the inverting MIXOUT2R to OUT2R path. 9 OUT2R_IN V_MUTE 1 Mute output of PGA to inverting amplifier. 0 = PGA output goes to inverting amplifier 1 = PGA output goes to output driver This register must be set to 0 when using the inverting MIXOUT2R to OUT2R path. This register must be set to 1 when using the non-inverting MIXOUT2R to OUT2R path. 8 OUT2_VU 0 OUT2L and OUT2R volumes do not update until a 1 is written to either OUT2_VU register bits. 7:2 OUT2R_VO L [5:0] 11_1001 2 OUT2_FB 0 OUT2L volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB OUT2R volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Enable Headphone common mode ground feedback for OUT2 0 = disabled (HPCOM unused) 1 = enabled (common mode feedback through HPCOM) Table 42 Controlling OUT2L and OUT2R w PD, February 2011, Rev 4.4 85 WM8351 Production Data A beep signal on the IN3R pin (see Table 43) can be mixed into OUT2R independently of the right output mixer (i.e. without mixing the same beep signal into OUT1R). Note that this feature is only possible when the inverting path configuration (MIXOUTR to OUT2R) is selected. See Table 41 for the required register settings. ADDRESS R111 (6Fh) Beep Volume BIT LABEL DEFAULT 15 IN3R_TO_O UT2R 0 Beep mixer enable 0 = disabled 1 = enabled DESCRIPTION 7:5 IN3R_OUT2R _VOL [2:0] 000 Beep mixer volume: 000 = -15dB … in +3dB steps 111 = +6dB Table 43 Controlling the “Beep” Path (IN3R to OUT2R) 13.9.3 HEADPHONE OUTPUTS EXTERNAL CONNECTIONS Some example headphone output configurations are shown below. Figure 46 AC-Coupled Headphone Drive Figure 47 DC-Coupled (Capless) Mode Headphone Drive Figure 48 AC-Coupled Headphone Drive with Common Mode Noise Rejection w PD, February 2011, Rev 4.4 86 WM8351 Production Data Notes: 1. The above figures illustrate the headphone connections to outputs OUT1L and OUT1R. The equivalent configurations apply equally to OUT2L and OUT2R. 2. The DC-coupled configuration illustrated in Figure 47 shows OUT4 (muted) being used as the Ground Return connection. The same capability may alternatively be provided using OUT3. 3. Twin headphone output (OUT1L, OUT1R, OUT2L and OUT2R) is possible, using a shared Ground Return connection via any of OUT3, OUT4, HPCOM or AGND. 4. Capless operation is not possible when using the HPCOM feature. When DC blocking capacitors are used their capacitance and the load resistance together determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. For a 16Ω load and a capacitance of 220μF, the following derivation of cut-off frequency applies: fc = 1 / 2π RLC1 = 1 / (2π x 16Ω x 220μF) = 45 Hz In the DC coupled configuration, the headphone “ground” is connected to VMID. The OUT3 or OUT4 pins can be configured as DC output drivers by de-selecting all inputs to the OUT3 or OUT4 mixers. The DC voltage on VMID in this configuration is equal to the DC offset on the OUT1L and OUT2L pins therefore no DC blocking capacitors are required. This saves space and material cost in portable applications. It is recommended to only use the DC coupled configuration to drive headphones, and not to use this configuration to drive the line input of another device. w PD, February 2011, Rev 4.4 87 WM8351 Production Data 13.9.4 OUT3 AND OUT4 The additional analogue outputs OUT3 and OUT4 have independent mixers and can be used in a number of different ways: • OUT3 and OUT4 as a stereo pair (OUT3 = left, OUT4 = right) to drive a headphone or line load • OUT3 or OUT4 as pseudo-ground outputs for headphones connected directly (without DC blocking capacitors) to OUT1L/OUT1R or OUT2L/OUT2R • OUT4 as a mono mix of left and right signals The OUT3 and OUT4 output stages are powered from HPVDD and HPGND. If OUT4 is providing a mono mix, it is recommended to reduce the level of OUT4 by 6dB to avoid clipping in the event of 2 full-scale signals being combined. This is implemented via the OUT4_ATT register field. When OUT4_ATT is asserted, then OUT4 = (L+R) / 2. Figure 49 OUT 3 and OUT4 Mixers w PD, February 2011, Rev 4.4 88 WM8351 Production Data OUT3 can provide a buffered midrail headphone pseudo-ground, or a left line output. It can also be a common mode input for OUT2L/OUT2R. OUT4 can provide a buffered midrail headphone pseudoground, a right line output, or a mono mix output. It can also be mixed into the input boost mixer for recording. ADDRESS R92 (5Ch) OUT3 Mixer BIT LABEL DEFAULT DESCRIPTION 11 DACL_TO_OUT3 0 Left DAC output to OUT3 0 = disabled 1 = enabled 8 MIXINL_TO_OUT3 0 Left input mixer to OUT3 0 = disabled 1 = enabled 3 OUT4_TO_OUT3 0 OUT4 mixer to OUT3 0 = disabled 1 = enabled 0 MIXOUTL_TO_OUT 3 0 Left output mixer to OUT3 0 = disabled 1 = enabled R92 (5Ch) OUT3 Mixer 15 OUT3_ENA 0 R9 (09h) Power Mgmt 2 4 OUT3 enable 0 = disabled 1 = enabled Note: OUT3_ENA can be accessed through R92 or R9. Reading from or writing to either register location has the same effect. Table 44 Controlling the OUT3 Mixer ADDRESS R93 (5Dh) OUT4 Mixer BIT LABEL DEFAULT DESCRIPTION 12 DACR_TO_OUT4 0 Right DAC output to OUT4 0 = disabled 1 = enabled 11 DACL_TO_OUT4 0 Left DAC output to OUT4 0 = Disabled 1 = Enabled 10 OUT4_ATT 0 Reduce OUT4 output by 6dB 0 = Output at normal level 1 = Output reduced by 6dB 9 MIXINR_TO_OUT4 0 Right input mixer to OUT4 0 = disabled 1 = enabled 2 OUT3_TO_OUT4 0 OUT3 mixer to OUT4 This function is not supported 1 MIXOUTR_TO OUT4 0 Right output mixer to OUT4 0 = Disabled 1 = Enabled 0 MIXOUTL_TO_OUT4 0 Left output mixer to OUT4 0 = disabled 1 = enabled R93 (5Dh) OUT4 Mixer 15 OUT4_ENA 0 R9 (09h) Power Mgmt 2 5 OUT4 enable 0 = disabled 1 = enabled Note: OUT4_ENA can be accessed through R93 or R9. Reading from or writing to either register location has the same effect. Table 45 Controlling the OUT4 Mixer w PD, February 2011, Rev 4.4 89 WM8351 Production Data 13.10 DIGITAL AUDIO INTERFACE The audio interface enables the WM8351 to exchange audio data with other system components. It is separate from the control interface and has four dedicated pins: • ADCDAT: Output pin for data coming from the audio ADC • DACDAT: Input pin for audio data going to the audio DAC • LRCLK: Data Left/Right alignment clock (also known as “word clock”) • BCLK: Bit clock, for synchronisation The LRCLK and BCLK pins are outputs when the WM8351 operates as a master device and are inputs when it is a slave device. In order to allow the ADC and DAC to run at different sampling rates, separate ADCLRCLK and ADCBCLK signals are both available through GPIO pins: GPIO5 (ADCLRCLK) and GPIO6 or GPIO8 (ADCBCLK). This feature also allows mixed Master/Slave operation between the ADC and DAC. 13.10.1 AUDIO DATA FORMATS The audio interface supports six different audio data formats: • Left justified • Right justified • I 2S • DSP mode A • DSP mode B • TDM Mode In all of these formats, the MSB (most significant bit) of each data sample is transferred first and the LSB (least significant bit) last. ADDRESS BIT LABEL DEFAULT R112 (70h) Audio Interface 15 AIF_BCLK_INV 0 BCLK polarity 0 = normal 1 = inverted DESCRIPTION 13 AIF_TRI 0 Sets Output enables for LRCLK and BCLK and ADCDAT to inactive state 0 = normal 1 = forces pins to Hi-Z 12 AIF_LRCLK_IN V 0 LRCLK clock polarity 0 = normal 1 = inverted DSP Mode – mode A/B select 0 = MSB is available on 2nd BCLK rising edge after LRCLK rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRCLK rising edge (mode B) w 11:10 AIF_WL [1:0] 10 (24 bits) 8:9 AIF_FMT [1:0] 10 Data word length 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits Note: When using the Right-Justified data format (AIF_FMT=00), the maximum word length is 24 bits. Data format PD, February 2011, Rev 4.4 90 WM8351 Production Data ADDRESS BIT LABEL DEFAULT DESCRIPTION (I2S) R114 (72h) Audio Interface ADC Control R115 (73h) Audio Interface DAC Control 00 = Right Justified 01 = Left Justified 10 = I2S 11 = DSP / PCM mode Note - see Section 13.11 for the selection of 8-bit mode. 7 AIFADC_PD 0 Enables a pull down on ADC data pin 0 = disabled 1 = enabled 6 AIFADCL_SRC 0 Selects Left channel ADC output. 0 = ADC Left channel 1 = ADC Right channel 5 AIFADCR_SRC 1 Selects Right channel ADC output. 0 = ADC Left channel 1 = ADC Right channel 4 AIFADC_TDM_ CHAN 0 ADCDAT TDM Channel Select 0 = ADCDAT outputs data on slot 0 1 = ADCDAT output data on slot 1 3 AIFADC_TDM 0 ADC TDM Enable 0 = Normal ADCDAT operation 1 = TDM enabled on ADCDAT 7 AIFDAC_PD 0 Enables a pull down on DAC data pin 0 = disabled 1 = enabled 6 DACL_SRC 0 Selects Left channel DAC input. 0 = DAC Left channel 1 = DAC Right channel 5 DACR_SRC 1 Selects Right channel DAC input. 0 = DAC Left channel 1 = DAC Right channel 4 AIFDAC_TDM_ CHAN 0 DACDAT TDM Channel Select 0 = DACDAT outputs data on slot 0 1 = DACDAT output data on slot 1 3 AIFDAC_TDM 0 DAC TDM Enable 0 = Normal DACDAT operation 1 = TDM enabled on DACDAT Table 46 Selecting the Audio Data Format In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DACDAT/ ADCDAT 1 MSB 2 3 n-2 Input Word Length (WL) n-1 n 1 2 3 n-2 n-1 n LSB Figure 50 Left Justified Audio Interface (assuming n-bit word length) w PD, February 2011, Rev 4.4 91 WM8351 Production Data In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition. Figure 51 Right Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. Figure 52 I2S Audio Interface (assuming n-bit word length) In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. Figure 53 DSP/PCM Mode Audio Interface (mode A, AIF_LRCLK_INV=0) w PD, February 2011, Rev 4.4 92 WM8351 Production Data Figure 54 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLK_INV=1) 13.10.2 AUDIO INTERFACE TDM MODE The digital audio interface on WM8351 has the facility of tri-stating the ADCDAT pin to allow multiple data sources to operate on the same bus. Time division multiplexing (TDM) is also supported, allowing audio output data to be transferred simultaneously from two different sources. TDM mode is enabled for the ADC and DAC by register bits AIFADC_TDM and AIFDAC_TDM respectively. TDM slot selection for the WM8351 is set for the ADC and DAC by register bits AIFADC_TDM_CHAN and AIFDAC_TDM_CHAN respectively, as defined in Table 46. When not actively transmitting data, the ADCDAT pin will be tristated in TDM mode, to allow other devices to transmit data. 13.10.3 TDM DATA FORMATS All selectable data formats support TDM. The allocation of time slots is controlled by register bits AIFADC_TDM_CHAN and AIFDAC_TDM_CHAN. Two possible slots (SLOT0 and SLOT1) are available for the ADC and for the DAC. Timing signals for the various interface formats in TDM mode are shown below for the ADC. Similar slot allocation will exist for the DAC. Left Justified Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 to the start of SLOT1 is determined by the selected word length of the interface of the WM8351. Figure 55 Left Justified Mode with TDM w PD, February 2011, Rev 4.4 93 WM8351 Production Data Right Justified Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the end of SLOT1 to the end of SLOT0 is determined by the selected word length of the interface of the WM8351. Figure 56 Right Justified Mode with TDM I2S Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 to the start of SLOT1 is determined by the selected word length of the interface of the WM8351. Figure 57 I2S Mode with TDM DSP/PCM Mode A, Master Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 (left) to the start of SLOT1 (left) is determined by the selected word length of the interface of the WM8351. Figure 58 DSP/PCM Mode A, Master Mode with TDM w PD, February 2011, Rev 4.4 94 WM8351 Production Data DSP/PCM Mode B, Master Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 (left) to the start of SLOT1 (left) is determined by the selected word length of the interface of the WM8351. Figure 59 DSP/PCM Mode B, Master Mode, with TDM DSP/PCM Mode A, Slave Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 (left) to the start of SLOT1 (left) is determined by the selected word length of the interface of the WM8351. Figure 60 DSP/PCM Mode A, Slave Mode with TDM DSP/PCM Mode B, Slave Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 (left) to the start of SLOT1 (left) is determined by the selected word length of the interface of the WM8351. Figure 61 DSP/PCM Mode B, Slave Mode, with TDM w PD, February 2011, Rev 4.4 95 WM8351 Production Data 13.10.4 LOOPBACK When the loopback feature is enabled, the audio ADC’s digital output data is looped back to the audio DAC and converted back into an analogue signal. This is often useful for test and evaluation purposes. ADDRESS R113 (71h) ADC Control BIT LABEL DEFAULT 0 LOOPBACK 0 DESCRIPTION Digital Loopback Function 0 = No loopback. 1 = Loopback enabled, ADC data output is fed directly into DAC data input. Table 47 Enabling loopback 13.11 COMPANDING The WM8351 supports A-law and μ-law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively. REGISTER ADDRESS R113 (71h) Companding Control BIT LABEL DEFAULT DESCRIPTION 4 ADC_COMPM ODE 0 ADC Companding mode select: 0 = μ-law 1 = A-law (Note: Setting ADC_COMPMODE=1 selects 8-bit mode when DAC_COMP=0 and ADC_COMP=0) 5 ADC_COMP 0 ADC Companding enable 0 = off 1 = on 6 DAC_COMPM ODE 0 DAC Companding mode select: 0 = μ-law 1 = A-law (Note: Setting DAC_COMPMODE=1 selects 8-bit mode when DAC_COMP=0 and ADC_COMP=0) 7 DAC_COMP 0 DAC Companding enable 0 = off 1 = on Table 49 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: μ-law (where μ=255 for the U.S. and Japan): F(x) = ln( 1 + μ|x|) / ln( 1 + μ) -1 ≤ x ≤ 1 law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) } for x ≤ 1/A F(x) = ( 1 + lnA|x|) / (1 + lnA) } for 1/A ≤ x ≤ 1 The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for μ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs of data. Companding converts 13 bits (μ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This provides greater precision for low amplitude signals than for high amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word comprising sign (1 bit), exponent (3 bits) and mantissa (4-bits). w PD, February 2011, Rev 4.4 96 WM8351 Production Data 8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows samples to be passed using as few as 8 BCLK cycles per LRCLK frame. When using DSP mode B, 8-bit data words may be transferred consecutively every 8 BCLK cycles. 8-bit mode (without Companding) may be enabled by setting ADC_COMPMODE=1 when ADC_COMP=0. BIT7 BIT[6:4] BIT[3:0] SIG N EXPONENT MANTISSA Table 50 8-bit Companded Word Composition u-law Companding 1 120 0.9 Companded Output 0.7 80 0.6 0.5 60 0.4 40 0.3 Normalised Output 0.8 100 0.2 20 0.1 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input Figure 39 μ-Law Companding A-law Companding 1 120 0.9 Companded Output 0.7 80 0.6 0.5 60 0.4 40 0.3 Normalised Output 0.8 100 0.2 20 0.1 0 0 0 0.2 0.4 0.6 0.8 1 Normalised Input Figure 40 A-Law Companding w PD, February 2011, Rev 4.4 97 WM8351 Production Data 13.12 ADDITIONAL CODEC FUNCTIONS 13.12.1 HEADPHONE JACK DETECT The IN2L and IN2R pins can be selected as headphone jack detect inputs, to enable automatic control of the analogue outputs when a headphone is plugged into a jack socket. Jack Detection on the IN2L or IN2R pins is enabled by register bits JDL_ENA or JDR_ENA respectively. When Jack Detection is enabled, the associated second level interrupts CODEC_JCK_DET_L_EINT and CODEC_JCK_DET_R_EINT indicate the status of the jack socket. See Section 13.12.7 for further details. The Headphone Jack Detect function requires the internal slow clock to be enabled - see Section 12.3.6. REGISTER ADDRESS R77 (4Dh) Jack Detect BIT LABEL DEFAULT DESCRIPTION 15 JDL_ENA 0 Jack Detect Enable for inputs connected to IN2L 0 = disabled 1 = enabled 14 JDR_ENA 0 Jack Detect Enable for input connected to IN2R 0 = disabled 1 = enabled Table 48 Headphone Jack Detect w PD, February 2011, Rev 4.4 98 WM8351 Production Data 13.12.2 MICROPHONE DETECTION The WM8351 can detect when a microphone has been plugged in, and/or when the microphone is short-circuited. It detects these events by comparing the current drawn from the MICBIAS pin against two thresholds. The thresholds for plug-in detection and short-circuit detection are programmable. A MICBIAS current above the MCDTHR threshold level is used to indicate that a microphone is plugged in, and is associated with the CODEC_MICD_EINT interrupt. If the bias current exceeds the MCDSCTHR limit, this indicates a microphone short-circuit condition, and the WM8351 raises a CODEC_MICSCD_EINT interrupt. See Section 13.12.7 for further details. Note that the MICBIAS current thresholds are subject to a wide tolerance - up to +/-50% of the specified value. Microphone detection requires the internal slow clock to be enabled - see Section 12.3.6. ADDRESS R8 (08h) Power Mgmt 1 R74 (4Ah) Mic Bias Control BIT LABEL DEFAULT 8 MIC_DET_ENA 0 DESCRIPTION Enable MIC detect: 0 = disabled 1 = enabled 7 MIC_DET_ENA 0 4:2 MCDTHR [2:0] 000 Threshold for bias current detection 000 = 160μA 001 = 330μA 010 = 500μA 011 = 680μA 100 = 850μA 101 = 1000μA 110 = 1200μA 111 = 1400μA These threshold currents scale proportionally with AVDD. The values given are for AVDD=3.3V. 1:0 MCDSCTHR [1:0] 00 Threshold for microphone short-circuit detection 00 = 400μA 01 = 900μA 10 = 1350μA 11 = 1800μA These threshold currents scale proportionally with AVDD. The values given are for AVDD=3.3V. Note: MIC_DET_ENA can be accessed through R8 or through R74. Reading from or writing to either register location has the same effect. Table 49 Controlling Microphone Bias Current Detection w PD, February 2011, Rev 4.4 99 WM8351 Production Data 13.12.3 MID-RAIL REFERENCE (VMID) VMID provides a potential mid-way between AVDD and GND, used in many parts of the audio CODEC. It is generated from AVDD using on-chip potential dividers. Different resistor values can be selected for this purpose. A medium resistance should be used when the CODEC is active. A high resistance option provides a more power-efficient way to maintain the VMID voltage when the CODEC is in “Standby” (i.e. inactive but ready to start immediately, without needing to wait for the VMID capacitor to be charged). For startup and shutdown the VMID generator provides soft VMID ramping to reduce pops and clicks. The speed of this ramp is selectable using the anti-pop controls and can be tuned to the application. Figure 62 Generating the Mid-rail Reference ADDRESS BIT R8 (08h) Power Management 1 2 VMID_EN A LABEL DEFAULT 0 1:0 VMID [1:0] 00 (off) DESCRIPTION Enables VMID resistor string 0 = disabled, 1 = enabled Resistor selection for VMID potential divider 00 = off 01 = VMID comes from 300kΩ R-string 10 = VMID comes from 50kΩ R-string 11 = VMID comes from 5kΩ R-string Table 50 Controlling the Mid-rail Reference w PD, February 2011, Rev 4.4 100 WM8351 Production Data 13.12.4 ANTI-POP CONTROL ADDRESS R78 (4Eh) Anti pop control DEFAULT DESCRIPTION 9:8 BIT ANTI_POP [1:0] LABEL 00 Reduces pop when VMID is enabled by setting the speed of the S-ramp for VMID. 00 = no S-ramp (will pop) 01 = fastest S-curve 10 = medium S-curve 11 = slowest S-curve 7:6 DIS_OP_LN4 [1:0] 00 Sets the Discharge rate for OUT4 00 = discharge path OFF 01 = fastest discharge 10 = medium discharge 11 = slowest discharge 5:4 DIS_OP_LN3 [1:0] 00 Sets the Discharge rate for OUT3 00 = discharge path OFF 01 = fastest discharge 10 = medium discharge 11 = slowest discharge 3:2 DIS_OP_OUT2 [1:0] 00 Sets the discharge rate for OUT2L and OUT2R 00 = discharge path OFF 01 = fastest discharge 10 = medium discharge 11 = slowest discharge 1:0 DIS_OP_OUT1 [1:0] 00 Sets the discharge rate for OUT1L and OUT1R 00 = discharge path OFF 01 = fastest discharge 10 = medium discharge 11 = slowest discharge Table 51 Control Registers for Anti-pop w PD, February 2011, Rev 4.4 101 WM8351 Production Data 13.12.5 UNUSED ANALOGUE INPUTS/OUTPUTS Whenever an analogue input/output is disabled, it remains connected to AVDD/2 through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between the voltage buffer and the output pins can be controlled using the VROI control bits. The default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. If high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 30kΩ. There are individual VROI bits for each output or output pair. This allows matching of the rise times of the outputs if they are driving different capacitors. Using the small resistance with a capacitor for headphone outputs (typically 220uF) and the larger resistance with a line load capacitance (10uF for example); will allow both sets of outputs to power up in around the same time, around 200ms. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R8 (08h) Power Mgmt 1 13 VBUF_ENA 0 Forces ON the tie-off amplifiers 0 = Disabled 1 = Enabled R76 (4Ch) Output Control 8 OUT1_VROI 0 VREF (AVDD/2) to OUT1L/OUT1R resistance 0 = approx 500Ω 1 = approx 30 kΩ 9 OUT2_VROI 0 VREF (AVDD/2) to OUT2L/OUT2R resistance 0 = approx 500Ω 1 = approx 30 kΩ 10 OUT3_VROI 0 VREF (AVDD/2) to OUT3 resistance 0 = approx 500Ω 1 = approx 30 kΩ 11 OUT4_VROI 0 VREF (AVDD/2) to OUT4 resistance 0 = approx 500Ω 1 = approx 30 kΩ Table 52 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown below. This buffer can be enabled using the VBUF_ENA register bit. w PD, February 2011, Rev 4.4 102 WM8351 Production Data AVDD/2 + AVDD/2 500 VBUF_ENA R8[13] Used to tie off all unused inputs. OUT1L 30k OUT1L_ENA OUT1_VROI R76[8] R10[0] 500 OUT1R 30k AVDD/2 + AVDD/2 OUT1R_ENA R10[1] 500 OUT4 VBUF_ENA R8[13] Used to tie off all unused outputs. 30k OUT4_ENA R9[5] OUT4_VROI R76[11] 500 OUT3 30k OUT3_VROI R76[10] OUT3_ENA R9[4] 500 OUT2L 30k OUT2L_ENA OUT2_VROI R76[9] R10[2] 500 OUT2R 30k OUT2R_ENA R10[3] Figure 63 Unused Input/Output Pin Tie-off Buffers OUT1R/L_ENA/ OUT2R/L_ENA OUT3/4_ENA VROI OUTPUT CONFIGURATION 0 0 500Ω tie-off to AVDD/2 0 1 30kΩ tie-off to AVDD/2 1 X Output enabled (DC level = AVDD/2) 1 X Output enabled (DC level = 1.5 x AVDD/2) Table 53 Unused Output Pin Tie-off Options w PD, February 2011, Rev 4.4 103 WM8351 Production Data 13.12.6 ZERO CROSS TIMEOUT A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. The zero-cross timeout function requires the internal slow clock to be enabled - see Section 12.3.6. 13.12.7 INTERRUPTS AND FAULT PROTECTION The CODEC has its own first-level interrupt, CODEC_INT (see Section 24). This comprises four second-level interrupts which indicate Jack detect and Microphone current conditions. These interrupts can be individually masked by setting the applicable mask bit(s) as described in Table 54. ADDRESS R31 (1Fh) Comparator Interrupt Status R39 (27h) Comparator Interrupt Status Mask BIT LABEL DESCRIPTION 11 CODEC_JCK_DET_L_EINT Left channel Jack detection interrupt. (Rising and Falling Edge triggered) Note: This bit is cleared once read. 10 CODEC_JCK_DET_R_EINT Right channel Jack detection interrupt. (Rising and Falling Edge triggered) Note: This bit is cleared once read. 9 CODEC_MICSCD_EINT Mic short-circuit detect interrupt. (Rising and Falling Edge triggered) Note: This bit is cleared once read. 8 CODEC_MICD_EINT Mic detect interrupt. (Rising and Falling Edge triggered) Note: This bit is cleared once read. “IM_” + name of respective bit in R31 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Each bit in R39 enables or masks the corresponding bit in R31. The default value for these bits is 0 (unmasked). 11:8 Table 54 CODEC Interrupts w PD, February 2011, Rev 4.4 104 WM8351 Production Data 14 POWER MANAGEMENT SUBSYSTEM 14.1 GENERAL DESCRIPTION The WM8351 provides five DC-DC Converters and four LDO Regulators which each deliver high efficiency across a wide range of line and load conditions. These power management components are designed to support application processors and associated peripherals. They are also suitable for providing power to the analogue and digital functions of the on-board CODEC and GPIO features. The output voltage of each of the converters and regulators is programmable in software through control registers. The WM8351 has a number of operating states which are either selected by software control or are selected autonomously according to the available power supply conditions. A low power active ‘Hibernate’ state is provided, with programmable characteristics. The ‘Backup’ and ‘Zero’ states are selected autonomously when the available supply voltages do not permit full operation of the WM8351. Four configuration modes are provided, selected by hardware control. Development Mode gives complete control over the configuration and start-up behaviour of the WM8351. Three different Custom Modes each have a defined set of configuration parameters, which determine the start-up timing and output voltage of each of the DC-DC Converters and LDO Regulators. The configuration of each of the GPIO pins is also contained with the configuration modes definitions. 14.2 POWER MANAGEMENT OPERATING STATES The WM8351 autonomously controls the power-up and power-down sequencing for itself and for other connected devices. It also selects the most appropriate power source available at any given time (see Section 17). The stable states of the WM8351 are: ACTIVE - All WM8351 functions can be used. The WM8351 enters the ACTIVE state after a valid start-up event (see Section 14.3.1), provided that no fault condition occurred during start-up. HIBERNATE - This is an alternative active state with programmable characteristics, allowing an optional low power system condition. The internally generated supply voltages can be individually enabled or disabled as desired. The WM8351 enters the HIBERNATE state from ACTIVE by setting the HIBERNATE register bit or when commanded via a GPIO pin configured as a HIBERNATE alternate function. OFF - All DC-DC converters and regulators LDO2, LDO3 and LDO4 are disabled. LDO1 may remain active (See Section 14.7.4). The VRTC regulator remains active and powers the always-on functions (such as crystal oscillator and RTC.) Register settings are restored to default settings. Trickle charging for the main battery is enabled by default. The WM8351 enters the OFF state from ACTIVE if a shutdown event occurs (see Section 14.3.3), or if the power source falls below the shutdown threshold (see Section 18). The WM8351 enters the OFF state from BACKUP if a power source greater than the UVLO threshold becomes available. BACKUP - The crystal oscillator and RTC are enabled, powered from the backup power (VRTC) supply. All other functions are disabled. The WM8351 enters the BACKUP state from OFF if the power source falls below the UVLO threshold (see Section 18), and provided that backup power (VRTC) is available (i.e. LINE falls below the UVLO level but VRTC remains above the Power-On Reset threshold). ZERO - All functions are disabled and all data in registers is lost. The WM8351 goes into this state when no power source is available and VRTC falls below the Power-On Reset threshold. The Active state can only be entered via the PRE-ACTIVE state. In Development Mode, the PreActive state is the state in which the WM8351 start-up parameters may be defined, prior to the startup sequence being triggered. The ACTIVE state is only entered on completion of the start-up sequence. The WM8351 operating states and valid transitions are illustrated in Figure 64. w PD, February 2011, Rev 4.4 105 WM8351 Production Data Figure 64 WM8351 Operating State Diagram 14.2.1 HIBERNATE STATE SELECTION The WM8351 moves from the ACTIVE to the HIBERNATE state when the HIBERNATE register bit is set. It can also move to hibernate using the Hibernate Edge or the Hibernate Level function from the GPIOs. It returns to the ACTIVE state when the Hibernate Level GPIO function is reset and the HIBERNATE bit is set to 0. It can also return to ACTIVE via the Hibernate Edge function or when a wake-up event (see Section 14.3.1) occurs. If a fault condition occurs in the HIBERNATE state, the WM8351 moves to the OFF state. ADDRESS BIT LABEL DEFAULT R5 (05h) System Hibernate 15 HIBERNATE 0 DESCRIPTION Determines what state the chip should operate in. 0 = Active state 1 = Hibernate state The register bit defaults to 0 when a reset happens Table 55 Invoking HIBERNATE State The behaviour of the WM8351 in the HIBERNATE state is programmable in terms of supply voltage generation, interrupts and resets. Fast battery charging is disabled in the HIBERNATE state, but trickle charging is possible. w PD, February 2011, Rev 4.4 106 WM8351 Production Data 14.3 POWER SEQUENCING AND CONTROL 14.3.1 STARTUP The WM8351 moves from OFF or HIBERNATE states to the ACTIVE state when a startup event occurs. Startup events include: • A trigger signal on the ON pin lasting more than 40ms. The active polarity of this input is set by the register field ON_POL. • A trigger signal on a GPIO pin configured as /WAKEUP lasting more than 40ms. The active polarity of this input is set by GPn_CFG for the applicable GPIO pin (see Section 20). • A trigger signal on a GPIO pin configured as PWR_ON input lasting more than 40ms. The active polarity of this input is set by GPn_CFG for the applicable GPIO pin (see Section 20). • Programmed ALARM from RTC module, if enabled (see Section 22). • Wall adaptor plug-in (WALL_FB rises above 4.0V). • USB plug-in (USB pin rises above 4.0V). The start-up events are only valid provided also that the available supply voltage, sensed on the LINE pin, is greater than the start-up threshold set by PCCMP_ON_THR, as defined in Section 18. Start-Up by Wall adaptor plug-in occurs when the Wall Adapter feedback pin detects a voltage greater than 4.0V. See Section 17.1 for a description of the WALL_FB pin function. Start-Up by USB plug-in occurs when the USB voltage rises above the LINE voltage. If USB Suspend mode is invoked, then USB plug-in starts the WM8351 on battery power, if available. When USB Suspend Mode is not invoked, this start-up event will lead to starting the WM8351 on USB power, and USB 100mA trickle charging of the battery is enabled. Note that applying a battery voltage is not a start-up event, i.e. connecting a battery pack does not start the WM8351. The WM8351 starts up on battery power if a startup event occurs and battery power is the only power source available, provided the battery voltage is above the startup threshold. (The start-up threshold is set by PCCMP_ON_THR, as defined in Section 18.) In the ACTIVE state, the host processor can read the Interrupt status fields in Register R31 in order to determine what action initiated the start-up. These fields indicate, for example, if the start-up was due to a reset caused by an error condition, or if the start-up was caused by a PWR_ON input, or if the start-up was caused by an RTC alarm. The first-level interrupt WKUP_INT is triggered whenever any of the second-level interrupt events described in Table 56 is set. See Section 24 for further details of Interrupt. ADDRESS R31 (1Fh) Comparator Interrupt Status w BIT LABEL DESCRIPTION 6 WKUP_OFF_STATE_EINT Indicates that the chip started from the OFF state. (Rising Edge triggered) Note: This bit is cleared once read. 5 WKUP_HIB_STATE_EINT Indicated the chip started up from the hibernate state. (Rising Edge triggered) Note: This bit is cleared once read. 4 WKUP_CONV_FAULT_EINT Indicates the wakeup was caused by a converter fault leading to the chip being reset. (Rising Edge triggered) Note: This bit is cleared once read. 3 WKUP_WDOG_RST_EINT Indicates the wakeup was caused by a watchdog heartbeat being missed, and hence the chip being reset. (Rising Edge triggered) Note: This bit is cleared once read. PD, February 2011, Rev 4.4 107 WM8351 Production Data ADDRESS R39 (27h) Comparator Interrupt Status Mask BIT LABEL 2 WKUP_GP_PWR_ON_EINT PWR_ON (Alternate GPIO function) pin has been pressed for longer than specified time. (Rising Edge triggered) Note: This bit is cleared once read. 1 WKUP_ONKEY_EINT ON key has been pressed for longer than specified time. (Rising Edge triggered) Note: This bit is cleared once read. 0 WKUP_GP_WAKEUP_EINT WAKEUP (Alternate GPIO function) pin has been pressed for longer than specified time. (Rising Edge triggered) Note: This bit is cleared once read. “IM_” + name of respective bit in R31 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Each bit in R39 enables or masks the corresponding bit in R31. The default value for these bits is 0 (unmasked). 6:0 DESCRIPTION Table 56 Wake-Up Interrupts 14.3.2 POWER-UP SEQUENCING The WM8351 power supply blocks can be commanded to start up according to a defined sequence when the WM8351 is commanded into the ACTIVE state. This sequence comprises fourteen timeslots, where the enabling of each DC-DC converter, LDO voltage regulator and the current limit switch is associated with one timeslot. In order to minimise supply in-rush current at power-up time, the start-up of these power supply blocks should be staggered in time by the use of this feature. The WM8351 proceeds from one time slot to the next after a delay of approximately 1.28ms, provided that all power supply blocks started up in the current time slot (if any) have reached 90% of their programmed output voltage. See Section 14.3.4 for details of the WM8351 behaviour if any power supply block fails to achieve 90% of its programmed output voltage. 14.3.3 SHUTDOWN The WM8351 goes from ACTIVE or HIBERNATE to the OFF state when a shutdown event occurs. Shutdown events include: • Software shutdown (setting CHIP_ON = 0) • A trigger signal on a GPIO pin configured as PWR_OFF lasting more than 5ms. The active polarity of this input is set by GPn_CFG for the applicable GPIO pin (see Section 20). • A trigger signal on the ON pin lasting more than 10 seconds. The active polarity of this input is set by the register field ON_POL. If required, the de-bounce time can be set to 5 seconds using the ON_DEB_T register bit. • Watchdog time-out (see Section 23) after 7 previous faults. • Fault conditions programmed to trigger a shutdown (see Section 18). • Thermal shutdown (see Section 25) As part of the start-up sequence, the CHIP_ON bit is set to 1. The software shutdown is commanded by writing 0 to the CHIP_ON register field as described in Table 57. w PD, February 2011, Rev 4.4 108 WM8351 Production Data ADDRESS BIT R3 (03h) System Control 1 15 CHIP_ON LABEL DEFAULT 0 Indicates whether the system is on or off. Writing 0 to this bit powers down the whole chip. Registers which are affected by state machine reset will get reset. Once the system is turned OFF it can be restarted by any of the valid ON event. DESCRIPTION 3 ON_DEB_T 0 ON pin off function debounce time 0 = 10s 1 = 5s 1 ON_POL 1 ON pin polarity: 0 = Active high (ON) 1 = Active low (/ON) Table 57 Software Shutdown As part of the shutdown sequence, the WM8351 asserts the /RST and /MEMRST reset signals, resets its internal control registers, disables most of its functions, resets the CHIP_ON bit to 0 and moves to the OFF state. (Note that /MEMRST is an optional output available on GPIO pins only.) 14.3.4 POWER CYCLING If an undervoltage fault or a limit switch overcurrent fault is detected (eg. during start-up, or when exiting the HIBERNATE state), the WM8351 will respond according to various configurable options. The Limit Switch and each of the DC Converters and LDO Regulators may be programmed to shutdown the system in the event of a fault condition. In these events (where a system shutdown is selected), the WM8351 will either shut down or will attempt to re-start, depending on the state of the POWERCYCLE register bit. If POWERCYCLE = 0, then a fault condition will result in the shutdown of the WM8351, reverting to the OFF state. If POWERCYCLE = 1, then the WM8351 will make a maximum of 8 attempts to restart. Each attempt will be scheduled at 200ms intervals. After 8 consecutive failed attempts, the WM8351 reverts to the OFF state and resets the power cycling counter. Any subsequent start-up event again has a maximum of 8 attempts to start up (provided that POWERCYCLE = 1). ADDRESS BIT LABEL DEFAULT DESCRIPTION R3 (03h) System Control 13 POWERCYCL E 0 Action to take on a fault (if fault response is set to shutdown system): 0 = Shut down 1 = Shutdown everything then go through startup sequence. ie. Reboot the system. Table 58 Controlling Power Cycling 14.3.5 REGISTER RESET The control registers of the WM8351 are reset when it goes into the OFF state. Under default conditions, the control registers are also reset when exiting the HIBERNATE state; this behaviour is selectable using the REG_RESET_HIB_MODE control bit. In Development mode, the register reset in OFF can be disabled using the RECONFIG_AT_ON register field. See Section 14.4 for a definition of this field. ADDRESS R5 (05h) System Hibernate BIT LABEL DEFAULT 5 REG_RESE T_HIB_MOD E 0 DESCRIPTION Action of the internal register reset signal when going from Hibernate to Active. 0 = Do a register reset when leaving the hibernate state. 1 = Do not do a register reset when leaving the hibernate state Table 59 Register Reset Control w PD, February 2011, Rev 4.4 109 WM8351 Production Data 14.3.6 RESET SIGNALS The WM8351 provides an active-low reset output signal to the host processor on the open-drain /RST pin. The /RST pin is asserted low in the OFF state. The status of the /RST pin in HIBERNATE state is configurable using the RST_HIB_MODE bit. In start-up, after all enabled power supplies reach 90% of their programmed output voltage, the /RST output is held low for a programmable duration set by RSTB_TO. The /RST pin is then set high. The /RST output is set low during the shutdown sequence. In Configuration Mode 11 only, the “crystal detect” mode is enabled; this controls the /RST output behaviour. In this mode, the WM8351 monitors the 32kHz crystal oscillator during start-up to verify that the output frequency is valid. The /RST output is held low until this has been achieved. An additional GPIO output, /RST can be generated, with the same functionality as the /RST pin. A GPIO pin must be configured as /RST in order to output this signal (see Section 20). The WM8351 can also generate a separate /MEMRST signal for other subsystems such as external memory. This allows resetting some subsystems in the HIBERNATE state, while not resetting others. The /MEMRST feature is provided via a GPIO pin (see Section 20). Note that /MEMRST is not a valid control signal during the start-up as the GPIO pins are not configured at this time. The MEM_VALID field provides an indication of whether the contents of the external memory (under control of /MEMRST) are valid. The /RST and /MEMRST signals can also be asserted under control of a manual reset input. A GPIO pin (see Section 20) must be configured as /MR to enable this feature. Note that the /MR input has no effect on the WM8351 circuits other than asserting /RST and /MEMRST. ADDRESS R3 (03h) System Control 1 R5 (05h) System Hibernate BIT LABEL DEFAULT DESCRIPTION 11:10 RSTB_TO [1:0] 11 Time that the /RST pin and /MEMRST output is held low after the chip reaches the active state. 00 = 15ms 01 = 30ms 10 = 60ms 11 = 120ms 5 MEM_VALID 0 Indicates that the contents of external memory are still valid. This bit is cleared on startup and whenever /MEMRST is asserted from the main state machine. The system software should set this bit once the external memory has been set up. Controlled in hibernate mode by MEMRST_HIB_MODE 0 = External memory is not valid and needs restoring. 1 = External memory is valid. 4 RST_HIB_M ODE 0 /RST pin state in hibernate mode: 0 = Asserted (low) 1 = Not asserted (high) 2 MEMRST_H IB_MODE 0 /MEMRST (Alternative GPIO function) pin state in hibernate mode 0 = Asserted (low) 1 = Not asserted (high) Table 60 Controlling Reset Signals The WM8351 can be commanded to assert the /RST and /MEMRST signals by writing a logic ‘1’ to the SYS_RST register bit. In this case, the /RST and /MEMRST outputs are asserted low for the duration specified by RSTB_TO. w PD, February 2011, Rev 4.4 110 WM8351 Production Data Care must be taken if writing to this bit in 2-wire (I2C) Control Interface mode. The WM8351 will act upon the register write operation as soon as it has received the address and data fields; this may happen before the I2C Acknowledge has been clocked by the host processor. If the /RST signal causes the processor to reset before it has clocked the I2C Acknowledge, then the WM8351 will continue to assert the Acknowledge signal (ie. pull the SDA pin low) after the processor has completed its reset. On some processors, it may be necessary to toggle the SCLK pin in order to clear the Acknowledge signal and resume I2C communications. ADDRESS BIT R3 (03h) System Control 1 14 LABEL SYS_RST DEFAULT DESCRIPTION 0 Allows the processors to reboot itself 0 = Do nothing 1 = Perform a processor reset by asserting the /RST and /MEMRST (GPIO) pins for the programmed duration Protected by security key. Table 61 Software Reset Command 14.4 DEVELOPMENT MODE The WM8351 can start in different modes depending on the state of the CONF1 and CONF0 pins. Development mode is selected by tying CONF1 and CONF0 to logic 0. Development mode gives complete control over the configuration and startup behaviour of the WM8351 and allows overriding the default values of selected registers (listed in Table 64). It enables configuration of the WM8351 before startup. This is especially useful for evaluation and debugging. In low-volume production, an external ‘genie’ (low-cost, small-size microcontroller) may be used to configure the WM8351 in Development mode. The ‘genie’ is used to write the required register values to generate the desired supplies and to configure the GPIO pins as required. These register write operations can be achieved via a secondary control interface, which is provided by redirecting the control interface to two GPIO pins as described below. The configuration mode pins CONF1 and CONF0 should be tied to fixed logic levels. The start-up sequence that they control is initiated on every transition from the OFF to the ACTIVE state. 14.4.1 CONTROL INTERFACE REDIRECTION In Development mode, the 2-wire control interface is initially redirected from the primary control interface (dedicated SDATA and SCLK pins, which require a DBVDD supply) to the secondary control interface (the GPIO10 and GPIO11 pins, which can run on an externally generated supply provided through the LINE pin). When using GPIO pins for the Control Interface, GPIO11 provides the SDATA functionality, and GPIO10 provides the SCLK functionality. Use of the secondary interface makes it possible to configure the WM8351 before the DBVDD supply voltage becomes available (e.g. in the OFF and PRE-ACTIVE states). The control interface can be switched back to the primary interface at any time by writing to the USE_DEV_PINS bit. In a typical application, the primary control interface would be selected after the WM8351 is fully configured. The device address for the secondary control interface is 0x34h, and cannot be changed. In development mode only, the primary interface address can be selected by writing to the DEV_ADDR bits through the secondary interface. Note that this functionality is only available in Development mode. w PD, February 2011, Rev 4.4 111 WM8351 Production Data ADDRESS R6 (06h) Interface Control BIT LABEL DEFAULT DESCRIPTION 15 USE_DEV_ PINS 1 Selects which pins to use for the 2-wire control: 0 = Use 2-wire I/F pins as 2-wire interface 1 = Use GPIO 10 and 11 as 2-wire interface, e.g. to download settings from PIC. Only applies when CONFIG pins[1:0] = 00. 14:13 DEV_ADDR [1:0] 00 Selects device address (only valid when CONF_STS = 00) 00 = 0x34 01 = 0x36 10 = 0x3C 11 = 0x3E Note: In custom modes (CONF[1:0]≠00), the secondary control interface is never used and the control bits described here have no effect. Table 62 Control Interface Switching in Development Mode 14.4.2 STARTING UP IN DEVELOPMENT MODE In Development mode, the GPIO1 pin is configured as a DO_CONF output (see Section 20), which is asserted high to indicate that the WM8351 is about to start up. This may be used to trigger the ‘genie’ to configure the WM8351 via the secondary control interface. Figure 65 Configuration Timing in Development Mode On completion of the register configuration, the power-up sequence is initiated by writing a logic 1 to the CONFIG_DONE bit. If the CONFIG_DONE bit is not set before the maximum set-up time has elapsed (see Figure 65), then the WM8351 will revert to the OFF state. An alternative implementation is to start up the WM8351 by setting CONFIG_DONE to ‘1’ without first programming the converter/LDO settings. By this method, the rising edge of the /RST signal may be used to trigger the WM8351 configuration process after the device has entered the ACTIVE state. In this case, the DC-DC converters and LDOs turn on immediately when they are enabled (time slots are no longer relevant because the WM8351 is already in the ACTIVE state). To reduce in-rush current, any configuration sequence triggered by /RST should therefore include supply staggering in software (i.e. time delays between powering up individual supply domains). Note that, whether using DO_CONF or /RST to trigger configuration, the on-chip watchdog imposes a time-out for configuration; if the WM8351 watchdog is not serviced, it restarts the system. This can be prevented, if necessary, by disabling the watchdog. w PD, February 2011, Rev 4.4 112 WM8351 Production Data By default, the DO_CONF output will be set low when the WM8351 enters the OFF state and set high on every transition from OFF to ACTIVE, re-triggering the external ‘genie’. Also, by default, the internal control registers will be reset when the WM8351 enters the OFF state. This behaviour can be changed using the RECONFIG_AT_ON register bit. If RECONFIG_AT_ON is set to 0, then the control registers will not be reset when going into the OFF state, and the DO_CONF output will remain set high after the first powering up of the chip, regardless of subsequent state transitions. De-selection of RECONFIG_AT_ON should be used with caution, as this can potentially lead to system failures in some applications. If RECONFIG_AT_ON is set to 0, and an OFF event occurs, then it is possible that control registers will not be set to the intended start-up values when the WM8351 subsequently returns to the ON state. The impact of this will depend upon the hardware and software of the particular target application, and is not necessarily a risk in every instance. Please contact Wolfson Applications support if further guidance is required on this topic. Note that RECONFIG_AT_ON should never be set to 0 in Custom Modes 01, 10 or 11. Setting this bit to 0 may result in erroneous behaviour and deviation from the custom configuration settings. Under default settings, the control registers are always reset in the OFF state. The register fields DO_CONF and RECONFIG_AT_ON are defined in Table 63. ADDRESS R6 (06h) Interface Control BIT LABEL DEFAULT 12 CONFIG_D ONE 0 Tells the system that the PIC micro has completed its programming. 0 = Programming still to be done 1 = Programming complete Only applies when CONFIG pins[1:0] = 00. DESCRIPTION 11 RECONFIG _AT_ON 1 Selects whether to reset the registers in the OFF state and whether to reload the device configuration from the PIC when an ON event occurs. 0 = Do not reset registers in the OFF state. Do not load configuration data when an ON event occurs. 1 = Reset registers in the OFF state. Load configuration from the PIC when an ON event occurs. Note that, in development mode, the device configuration from the PIC is always loaded when first powering up the chip. This bit must always be set to default (1) in Custom Modes 01, 10 and 11. Table 63 Start-Up Control in Development Mode Note: if the WM8351 enters the BACKUP state as a result of an undervoltage condition (see Section 18), then the control registers will be reset, but DO_CONF will remain high. When the supply voltage rises and device comes out of BACKUP, the DO_CONF output will still be high. If the DO_CONF signal is used to trigger an external ‘genie’ device, then this may not work, as the DO_CONF has remained high through the BACKUP state transition, and the WM8351 device will become locked in the PRE-ACTIVE state when an ON event occurs. This problem may be avoided by ensuring that the ‘genie’ monitors the LINE voltage in order to recognise the undervoltage condition, and that it verifies the I2C Acknowledge signal on the secondary interface (GPIO10 and GPIO11) to determine whether it can execute its programming function. 14.4.3 CONFIGURING THE WM8351 IN DEVELOPMENT MODE The WM8351 can be configured in Development mode by writing to control bits that determine its startup behaviour. The locations of these register bits are shown in Table 64 below. A typical configuration sequence would include writes to some or all of the registers listed. If none of the highlighted bits in any given register needs to be changed from its default, then no write to that register is recommended. w PD, February 2011, Rev 4.4 113 WM8351 Production Data The configuration bits include: • Duration control bits for the /RST reset signal (RSTB_TO) • GPIO pull-up / pull-down settings and debounce times (GPn_PD, GPn_PU, GPn_DB and GP_DBTIME) • Alternate function and input/output selection for GPIO pins (GPn_FN, GPn_DIR and GPn_CFG) • Voltage settings for DC-DC converters and LDO regulators (DCn_VSEL and LDOn_VSEL) • Time slots for automatic start of all DC-DC converters, all LDO regulators and the Current Limit Switch during startup (DCn_ENSLOT, LDOn_ENSLOT and LS_ENSLOT). Note that supplies can be programmed to not start up automatically by setting the respective _ENSLOT bits to 0000. Typically, the final step in the sequence is a write to register R6, in order to: w • Select the WM8351 device address on the primary control interface, using the DEV_ADDR bits. • Allow the WM8351 to proceed to startup. This is achieved by setting the CONFIG_DONE bit (R6 bit 12) to 1. • Switch the control interface back to the primary interface (if desired), so that a host processor can communicate with the WM8351. This is achieved by setting USE_DEV_PINS (R6 bit 15) to 0. PD, February 2011, Rev 4.4 114 WM8351 Production Data REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Select /RST duration R3 (03h) RSTB_TO Unlock protected registers R219 (DBh) 0013h Alternate function and input/output selection for GPIO pins R140 (8Ch) GP3_FN GP2_FN GP1_FN GP0_FN R141 (8Dh) GP7_FN GP6_FN GP5_FN GP4_FN R142 (8Eh) GP11_FN GP10_FN GP9_FN GP8_FN R143 (8Fh) GP12_FN R128 (80h) GPn_DB (n = 0 to 12) R129 (81h) GPn_PU (n = 0 to 12) R130 (82h) GPn_PD (n = 0 to 12) R134 (86h) GPn_DIR (n = 0 to 12) R135 (87h) GPn_CFG (n = 0 to 12) Disable battery charger (only if battery type is not compatible with WM8351 charger) R168 (A8h) 0 Re-lock protected registers R219 (DBh) FFFFh Configure supply generation R180 (B4h) DC1_VSEL[6:0] R181(B5h) DC1_ENSLOT[3:0] R183 (B7h) DC2_ENSLOT[3:0] R186 (BAh) DC3_VSEL[6:0] R187 (BBh) DC3_ENSLOT 3:0] R189 (BDh) DC4_VSEL[6:0] R190 (BEh) DC4_ENSLOT[3:0] R199 (C7h) LS_ENSLOT[3:0] R200 (C8h) LDO1_VSEL[4:0] R201 (C9h) LDO1_ENSLOT[3:0] R203 (CAh) LDO2_VSEL[4:0] R204 (CBh) LDO2_ENSLOT[3:0] R206 (CEh) LDO3_VSEL[4:0] R207 (CFh) LDO3_ENSLOT[3:0] R209 (D1h) LDO4_VSEL[4:0] R210 (D2h) LDO4_ENSLOT[3:0] Proceed to startup and hand over to host processor R6 (06h) 0 DEV_ADDR 1 Table 64 Suggested Sequence of Register Writes for WM8351 Configuration in Development Mode Note that configuration only includes registers that are required for starting up correctly. All other register settings should be loaded after the WM8351 has started up. Most of these control fields are described here within Section 14. See Section 11.6 for details of Register Locking. See Section 20 for details of the GPIO configuration fields. See Section 17.7 for details of the Battery Charger configuration. When using the /RST signal to trigger configuration, writing to the _ENSLOT and RSTB_TO fields can be omitted (the reset and power-up sequence has already taken place, so the write would have no effect). However, additional writes to R13 or R176 should be added to enable the DC-DC converters and LDO regulators one by one. w PD, February 2011, Rev 4.4 115 WM8351 Production Data 14.5 CUSTOM MODES The WM8351 provides three custom start-up modes. These are selected by setting the CONF1 and CONF0 pins = 01, 10 or 11. The custom mode start-up sequences define the following parameters: • Polarity of the ON pin (Active low or high) • Configuration of the USB power source • Configuration of the Watchdog timer mode • Configuration of the Control Interface mode • Configuration of the 32kHz oscillator (enabled or disabled) • Configuration of the real-time-clock (enabled or disabled) • Configuration of LDO1 • Selection of crystal oscillator detect mode (see Section 14.3.6) • Configuration of the voltage settings and start-up timeslots for DC-DC and LDO supplies • Configuration of GPIO pins In Development Mode, the RECONFIG_AT_ON register bit (see Section 14.4.2) may be used to control the device configuration behaviour. In Custom Modes 01, 10 or 11, the default setting (RECONFIG_AT_ON = 1) must always be used. Setting this bit to 0 may result in erroneous behaviour and deviation from the custom configuration settings. The custom modes do not allow configuring the WM8351 in the OFF state. As a result, evaluation and debugging in custom modes is limited. w PD, February 2011, Rev 4.4 116 WM8351 Production Data 14.5.1 CONFIGURATION MODE 01 In Configuration Mode 01, the following general default settings apply: PARAMETER REGISTER SETTING DESCRIPTION ON polarity ON_POL = 1 ON pin is Active Low USB power source USB_SLV_500MA = 1 Selects 500mA limit in USB slave Watchdog timer WDOG_MODE [1:0] = 00 Watchdog is disabled Control Interface SPI_3WIRE = 0 SPI_4WIRE = 0 SPI_CFG = 0 Control Interface is 2-wire mode 32kHz oscillator OSC32K_ENA = 1 32kHz Oscillator is enabled Real Time Clock RTC_TICK_ENA = 1 RTC_CLKSRC = 0 Real Time Clock is enabled LDO1 LDO1_PIN_MODE = 1 LDO1_PIN_EN = 0 LDO1 enabled at all times Crystal detect mode Crystal detect mode is not enabled. The default voltages and the power-up sequence for all DC-DCs and LDOs in Configuration Mode 01 are shown below in Table 65 and Figure 66. The time delay between each time slot is approximately 1.28ms. Note that the Limit Switch is not enabled automatically in Configuration Mode 01; as a result, the Limit Switch remains open when the WM8351 enters the ACTIVE state. w PD, February 2011, Rev 4.4 117 WM8351 Production Data SUPPLY REGISTER SETTING DESCRIPTION DCDC1 DC1_ENSLOT [3:0] = 0011 DC1_VSEL [6:0] = 000_1110 Third timeslot 1.2V DCDC2 DC2_ENSLOT [3:0] = 0000 Disabled DCDC3 DC3_ENSLOT [3:0] = 0001 DC3_VSEL [6:0] = 010_0110 First timeslot 1.8V DCDC4 DC4_ENSLOT [3:0] = 0010 DC4_VSEL [6:0] = 110_0010 Second timeslot 3.3V LDO1 LDO1_ENSLOT [3:0] = 0000 LDO1_VSEL [4:0] = 0_0110 (See note below) 1.2V LDO2 LDO2_ENSLOT [3:0] = 0011 LDO2_VSEL [4:0] = 1_0000 Third timeslot 1.8V LDO3 LDO3_ENSLOT [3:0] = 0010 LDO3_VSEL [4:0] =1_1111 Second timeslot 3.3V LDO4 LDO4_ENSLOT [3:0] = 0010 LDO4_VSEL [4:0] = 0_1010 Second timeslot 1.4V Table 65 Default Supply Voltages / Power-up Sequence for Configuration Mode 01 Note: In this Configuration Mode, LDO1 is enabled at all times. Therefore, the setting of LDO1_ENSLOT has no effect. Figure 66 Power-up Sequence - Configuration Mode 01 w PD, February 2011, Rev 4.4 118 WM8351 Production Data The default GPIO settings for configuration mode 01 are shown below in Table 66. GPIO PIN POWER DOMAIN DEFAULT GPIO FUNCTION DEFAULT DIRECTION DEFAULT PULL-UP / PULL-DOWN DEFAULT DE-BOUNCE GPIO0 VRTC GP0_FN [3:0] = 0000 GPIO GP0_DIR = 1 GP0_CFG =1 Input, Active High GP0_PD=0 GP0_PU=0 Normal Mode GP0_DB = 1 Debounce enabled GPIO1 VRTC GP1_FN [3:0] = 0000 GPIO GP1_DIR = 1 GP1_CFG =1 Input, Active High GP1_PD=0 GP1_PU=0 Normal Mode GP1_DB = 1 Debounce enabled GPIO2 VRTC GP2_FN [3:0] = 0011 32KHZ GP2_DIR = 0 GP2_CFG =1 Output, Open Drain GP2_PD=0 GP2_PU=0 Normal Mode GP2_DB = 1 Debounce enabled GPIO3 VRTC GP3_FN [3:0] = 0000 GPIO GP3_DIR = 1 GP3_CFG =1 Input, Active High GP3_PD=0 GP3_PU=0 Normal Mode GP3_DB = 1 Debounce enabled GPIO4 DBVDD GP4_FN [3:0] = 0000 GPIO GP4_DIR = 1 GP4_CFG =1 Input, Active High GP4_PD=0 GP4_PU=0 Normal Mode GP4_DB = 1 Debounce enabled GPIO5 DBVDD GP5_FN [3:0] = 0001 L_PWR1 GP5_DIR = 1 GP5_CFG =0 Input, Active Low GP5_PD=0 GP5_PU=0 Normal Mode GP5_DB = 1 Debounce enabled GPIO6 DBVDD GP6_FN [3:0] = 0001 L_PWR2 GP6_DIR = 1 GP6_CFG =0 Input, Active Low GP6_PD=0 GP6_PU=0 Normal Mode GP6_DB = 1 Debounce enabled GPIO7 DBVDD GP7_FN [3:0] = 0001 L_PWR3 GP7_DIR = 1 GP7_CFG =0 Input, Active Low GP7_PD=0 GP7_PU=0 Normal Mode GP7_DB = 1 Debounce enabled GPIO8 DBVDD GP8_FN [3:0] = 0011 /BATT_FAULT GP8_DIR = 0 GP8_CFG =0 Output, CMOS GP8_PD=0 GP8_PU=0 Normal Mode GP8_DB = 1 Debounce enabled GPIO9 DBVDD GP9_FN [3:0] = 0001 /VCC_FAULT GP9_DIR = 0 GP9_CFG =0 Output, CMOS GP9_PD=0 GP9_PU=0 Normal Mode GP9_DB = 1 Debounce enabled GPIO10 LINE GP10_FN [3:0] = 0000 GPIO GP10_DIR = 1 GP10_CFG =1 Input, Active High GP10_PD=0 GP10_PU=0 Normal Mode GP10_DB = 1 Debounce enabled GPIO11 LINE GP11_FN [3:0] = 0000 GPIO GP11_DIR = 1 GP11_CFG =1 Input, Active High GP11_PD=0 GP11_PU=0 Normal Mode GP11_DB = 1 Debounce enabled GPIO12 LINE GP12_FN [3:0] = 0011 LINE_SW GP12_DIR = 0 GP12_CFG =0 Output, CMOS GP12_PD=0 GP12_PU=0 Normal Mode GP12_DB = 1 Debounce enabled Table 66 Default GPIO Settings for Configuration Mode 01 w PD, February 2011, Rev 4.4 119 WM8351 Production Data 14.5.2 CONFIGURATION MODE 10 In Configuration Mode 10, the following general default settings apply: PARAMETER REGISTER SETTING DESCRIPTION ON polarity ON_POL = 1 ON pin is Active Low USB power source USB_SLV_500MA = 1 Selects 500mA limit in USB slave Watchdog timer WDOG_MODE [1:0] = 01 Watchdog set to Interrupt on Timeout Control Interface SPI_3WIRE = 0 SPI_4WIRE = 0 SPI_CFG = 0 Control Interface is 2-wire mode 32kHz oscillator OSC32K_ENA = 1 32kHz Oscillator is enabled Real Time Clock RTC_TICK_ENA = 1 RTC_CLKSRC = 0 Real Time Clock is enabled, driven by the internal 32kHz oscillator LDO1 LDO1_PIN_MODE = 0 LDO1_PIN_EN = 0 LDO1 controlled as normal via register bits Crystal detect mode Crystal detect mode is not enabled. The default voltages and the power-up sequence for all DC-DCs and LDOs in Configuration Mode 10 are shown below in Table 67 and Figure 67. The time delay between each time slot is approximately 1.28ms. Note that the Limit Switch is not enabled automatically in Configuration Mode 10; as a result, the Limit Switch remains open when the WM8351 enters the ACTIVE state. w PD, February 2011, Rev 4.4 120 WM8351 Production Data SUPPLY REGISTER SETTING DESCRIPTION DCDC1 DC1_ENSLOT [3:0] = 0010 DC1_VSEL [6:0] = 001_1010 Second timeslot 1.5V DCDC2 DC2_ENSLOT [3:0] = 0000 Disabled DCDC3 DC3_ENSLOT [3:0] = 0001 DC3_VSEL [6:0] = 101_0110 First timeslot 3.0V DCDC4 DC4_ENSLOT [3:0] = 0011 DC4_VSEL [6:0] = 010_0110 Third timeslot 1.8V LDO1 LDO1_ENSLOT [3:0] = 0001 LDO1_VSEL [4:0] = 1_1100 First timeslot 3.0V LDO2 LDO2_ENSLOT [3:0] = 0011 LDO2_VSEL [4:0] = 1_0000 Third timeslot 1.8V LDO3 LDO3_ENSLOT [3:0] = 0000 LDO3_VSEL [4:0] = 1_0101 Disabled 2.3V LDO4 LDO4_ENSLOT [3:0] = 0000 LDO4_VSEL [4:0] = 1_1010 Disabled 2.8V Table 67 Default Supply Voltages / Power-up Sequence for Configuration Mode 10 Figure 67 Power-up Sequence - Configuration Mode 10 w PD, February 2011, Rev 4.4 121 WM8351 Production Data The default GPIO settings for configuration mode 10 are shown below in Table 68. GPIO PIN POWER DOMAIN DEFAULT GPIO FUNCTION DEFAULT DIRECTION DEFAULT PULL-UP / PULL-DOWN DEFAULT DE-BOUNCE GPIO0 VRTC GP0_FN [3:0] = 0000 GPIO GP0_DIR = 0 GP0_CFG =0 Output, CMOS GP0_PD=0 GP0_PU=0 Normal Mode GP0_DB = 1 Debounce enabled GPIO1 VRTC GP1_FN [3:0] = 0001 PWR_ON GP1_DIR = 1 GP1_CFG =1 Input, Active High GP1_PD=0 GP1_PU=0 Normal Mode GP1_DB = 1 Debounce enabled GPIO2 VRTC GP2_FN [3:0] = 0011 32kHz GP2_DIR = 0 GP2_CFG =1 Output, Open Drain GP2_PD=0 GP2_PU=0 Normal Mode GP2_DB = 1 Debounce enabled GPIO3 VRTC GP3_FN [3:0] = 0001 PWR_ON GP3_DIR = 1 GP3_CFG =0 Input, Active Low GP3_PD=0 GP3_PU=0 Normal Mode GP3_DB = 1 Debounce enabled GPIO4 DBVDD GP4_FN [3:0] = 0011 HIBERNATE Level GP4_DIR = 1 GP4_CFG =1 Input, Active High GP4_PD=1 GP4_PU=0 Pull-down GP4_DB = 1 Debounce enabled GPIO5 DBVDD GP5_FN [3:0] = 0000 GPIO GP5_DIR = 1 GP5_CFG =1 Input, Active High GP5_PD=0 GP5_PU=0 Normal Mode GP5_DB = 1 Debounce enabled GPIO6 DBVDD GP6_FN [3:0] = 0000 GPIO GP6_DIR = 1 GP6_CFG =1 Input, Active High GP6_PD=0 GP6_PU=0 Normal Mode GP6_DB = 1 Debounce enabled GPIO7 DBVDD GP7_FN [3:0] = 0000 GPIO GP7_DIR = 1 GP7_CFG =1 Input, Active High GP7_PD=0 GP7_PU=0 Normal Mode GP7_DB = 1 Debounce enabled GPIO8 DBVDD GP8_FN [3:0] = 0000 GPIO GP8_DIR = 1 GP8_CFG =1 Input, Active High GP8_PD=1 GP8_PU=0 Pull-down GP8_DB = 1 Debounce enabled GPIO9 DBVDD GP9_FN [3:0] = 0000 GPIO GP9_DIR = 0 GP9_CFG =0 Output, CMOS GP9_PD=0 GP9_PU=0 Normal Mode GP9_DB = 1 Debounce enabled GPIO10 LINE GP10_FN [3:0] = 0000 GPIO GP10_DIR = 0 GP10_CFG =1 Output, Open Drain GP10_PD=0 GP10_PU=0 Normal Mode GP10_DB = 1 Debounce enabled GPIO11 LINE GP11_FN [3:0] = 0010 /WAKEUP GP11_DIR = 1 GP11_CFG =1 (see note) GP11_PD=0 GP11_PU=0 Normal Mode GP11_DB = 1 Debounce enabled GPIO12 LINE GP12_FN [3:0] = 0000 GPIO GP12_DIR = 0 GP12_CFG =0 Output, CMOS GP12_PD=0 GP12_PU=0 Normal Mode GP12_DB = 1 Debounce enabled Note: The alternate GPIO functions PWR_ON and /WAKEUP are system wakeup events. The debounce time of these functions are determined by GP_DBTIME[1:0] + 40ms Table 68 Default GPIO Settings for Configuration Mode 10 Note that setting GP11_CFG = 1 results in Active Low function for /WAKEUP. In most cases, setting GPn_CFG = 1 results in Active High function, but /MR, /WAKEUP and /LDO_ENA are exceptions to this. See Section 20. w PD, February 2011, Rev 4.4 122 WM8351 Production Data 14.5.3 CONFIGURATION MODE 11 In Configuration Mode 11, the following general default settings apply: PARAMETER REGISTER SETTING DESCRIPTION ON polarity ON_POL = 1 ON pin is Active Low USB power source USB_SLV_500MA = 1 Selects 500mA limit in USB slave Watchdog timer WDOG_MODE [1:0] = 00 Watchdog is disabled Control Interface SPI_3WIRE = 0 SPI_4WIRE = 0 SPI_CFG = 0 Control Interface is 2-wire mode 32kHz oscillator OSC32K_ENA = 1 32kHz Oscillator is enabled Real Time Clock RTC_TICK_ENA = 1 RTC_CLKSRC = 0 Real Time Clock is enabled, driven by the internal 32kHz oscillator LDO1 LDO1_PIN_MODE = 0 LDO1_PIN_EN = 0 LDO1 controlled as normal via register bits Crystal detect mode Crystal detect mode is enabled. (/RST output is held low until 32kHz oscillator is valid.) The default voltages and the power-up sequence for all DC-DCs and LDOs in configuration mode 11 are shown below in Table 69 and Figure 68. The time delay between each time slot is approximately 1.28ms. Note that the Limit Switch is not enabled automatically in Configuration Mode 11; as a result, the Limit Switch remains open when the WM8351 enters the ACTIVE state. w PD, February 2011, Rev 4.4 123 WM8351 Production Data SUPPLY REGISTER SETTING DESCRIPTION DCDC1 DC1_ENSLOT [3:0] = 0001 DC1_VSEL [6:0] = 000_1110 First timeslot 1.2V DCDC2 DC2_ENSLOT [3:0] = 0000 Disabled DCDC3 DC3_ENSLOT [3:0] = 0010 DC3_VSEL [6:0] = 010_0110 Second timeslot 1.8V DCDC4 DC4_ENSLOT [3:0] = 0101 DC4_VSEL [6:0] = 110_0010 Fifth timeslot 3.3V LDO1 LDO1_ENSLOT [3:0] = 0011 LDO1_VSEL [4:0] = 0_0110 Third timeslot 1.2V LDO2 LDO2_ENSLOT [3:0] = 0000 LDO2_VSEL [4:0] = 1_0110 Disabled 2.4V LDO3 LDO3_ENSLOT [3:0] = 0000 LDO3_VSEL [4:0] = 1_1001 Disabled 2.7V LDO4 LDO4_ENSLOT [3:0] = 0100 LDO4_VSEL [4:0] = 1_1010 Fourth timeslot 2.8V Table 69 Default Supply Voltages / Power-up Sequence for Configuration Mode 11 Figure 68 Power-up Sequence - Configuration Mode 11 w PD, February 2011, Rev 4.4 124 WM8351 Production Data The default GPIO settings for configuration mode 11 are shown below in Table 70. GPIO PIN POWER DOMAIN DEFAULT GPIO FUNCTION DEFAULT DIRECTION DEFAULT PULL-UP / PULL-DOWN DEFAULT DE-BOUNCE GPIO0 VRTC GP0_FN [3:0] = 0000 GPIO GP0_DIR = 1 GP0_CFG =1 Input, Active High GP0_PD=0 GP0_PU=0 Normal Mode GP0_DB = 0 Debounce enabled GPIO1 VRTC GP1_FN [3:0] = 0001 PWR_ON GP1_DIR = 1 GP1_CFG =0 Input, Active Low GP1_PD=0 GP1_PU=0 Normal Mode GP1_DB = 1 Debounce enabled GPIO2 VRTC GP2_FN [3:0] = 0011 32kHz GP2_DIR = 0 GP2_CFG =1 Output, Open Drain GP2_PD=0 GP2_PU=0 Normal Mode GP2_DB = 1 Debounce enabled GPIO3 VRTC GP3_FN [3:0] = 0000 GPIO GP3_DIR = 1 GP3_CFG =1 Input, Active High GP3_PD=0 GP3_PU=0 Normal Mode GP3_DB = 1 Debounce enabled GPIO4 DBVDD GP4_FN [3:0] = 0001 /MR GP4_DIR = 1 GP4_CFG =1 (see note) GP4_PD=0 GP4_PU=1 Pull-up GP4_DB = 1 Debounce enabled GPIO5 DBVDD GP5_FN [3:0] = 0000 GPIO GP5_DIR = 1 GP5_CFG =1 Input, Active High GP5_PD=0 GP5_PU=0 Normal Mode GP5_DB = 1 Debounce enabled GPIO6 DBVDD GP6_FN [3:0] = 0000 GPIO GP6_DIR = 1 GP6_CFG =1 Input, Active High GP6_PD=0 GP6_PU=0 Normal Mode GP6_DB = 1 Debounce enabled GPIO7 DBVDD GP7_FN [3:0] = 0000 GPIO GP7_DIR = 1 GP7_CFG =1 Input, Active High GP7_PD=0 GP7_PU=0 Normal Mode GP7_DB = 1 Debounce enabled GPIO8 DBVDD GP8_FN [3:0] = 0000 GPIO GP8_DIR = 1 GP8_CFG =1 Input, Active High GP8_PD=0 GP8_PU=0 Normal Mode GP8_DB = 1 Debounce enabled GPIO9 DBVDD GP9_FN [3:0] = 0000 GPIO GP9_DIR = 1 GP9_CFG =1 Input, Active High GP9_PD=0 GP9_PU=0 Normal Mode GP9_DB = 1 Debounce enabled GPIO10 LINE GP10_FN [3:0] = 0011 CH_IND GP10_DIR = 0 GP10_CFG =1 Output, Open Drain GP10_PD=0 GP10_PU=0 Normal Mode GP10_DB = 1 Debounce enabled GPIO11 LINE GP11_FN [3:0] = 0010 /WAKEUP GP11_DIR = 1 GP11_CFG =1 (see note) GP11_PD=0 GP11_PU=0 Normal Mode GP11_DB = 1 Debounce enabled GPIO12 LINE GP12_FN [3:0] = 0011 LINE_SW GP12_DIR = 0 GP12_CFG =0 Output, CMOS GP12_PD=0 GP12_PU=0 Normal Mode GP12_DB = 1 Debounce enabled Note: The alternate GPIO functions PWR_ON and /WAKEUP are system wakeup events. The debounce time of these functions are determined by GP_DBTIME[1:0] + 40ms Table 70 Default GPIO Settings for Configuration Mode 11 Note that setting GP4_CFG = 1 results in Active Low function for /MR. Also, setting GP11_CFG = 1 results in Active Low function for /WAKEUP. In most cases, setting GPn_CFG = 1 results in Active High function, but /MR, /WAKEUP and /LDO_ENA are exceptions to this. See Section 20. w PD, February 2011, Rev 4.4 125 WM8351 Production Data 14.6 CONFIGURING THE DC-DC CONVERTERS The configuration of the DC-DC converters is described in the following sections. Some of the control fields form part of the Custom Mode configuration settings and therefore will not require to be set in software in some applications. 14.6.1 DC-DC CONVERTER ENABLE The DC-DC Converters can be enabled in software using the register fields defined in Table 71. All DC-DC converters include a soft-start feature that helps to reduce the inductor current at start up. In order to further reduce supply in-rush current, individual converters should be programmed to start in different time slots within the start-up sequence. In the WM8351 ACTIVE state, the DC-DC Converters can be enabled in software using the DCn_ENA bits. Setting these bits whilst in the Pre-Active state (see Figure 65) will not immediately enable the corresponding DC-DC converter; these bits will only become effective once the WM8351 has reached the ACTIVE state. Each Converter may be programmed to switch on in a selected timeslot within the start-up sequence. The WM8351 will set the DCn_ENA field for any DC-DC converter that is enabled during the start-up sequence. Note that setting the DCn_ENSLOT fields in software is only relevant to the Development Mode, as these fields are assigned preset values in each of the Custom Modes. Each Converter may be programmed to switch off in a selected timeslot within the shutdown sequence. If a Converter is not allocated to one of the 14 shutdown timeslots, it will be disabled when the WM8351 enters the OFF state. ADDRESS BIT LABEL DEFAULT DESCRIPTION Note: n is a number between 1 and 6 that identifies the individual DC-DC converter R13 (0Dh) or 0,1,2,3 DCn_ENA R176 (B0h) Dependant on CONFIG[1:0] settings DCDCn converter enable 0 = disabled 1 = enabled Note: internal conditions may prevent the converter from actually switching on - see DCDC/LDO Status register for actual converter status. Note: These bits can be accessed through R13 or through R176. Reading from or writing to either register location has the same effect. R181 (B5h) for DC-DC1 13:10 DCn_ENSLO Dependant on T [3:0] CONFIG[1:0] settings Time slot for DC-DCn start-up 0000 = Disabled (do not start up) 0001 = Start-up in time slot 1 … (total 14 slots available) 1110 = Start-up in time slot 14 1111 = Start up on entering ACTIVE DCn_SDSLO T [3:0] Time slot for DC-DCn shutdown. 0000 = Shut down on entering OFF 0001 = Shutdown in time slot 1 …. (total 14 slots available) 1110 = Shutdown in time slot 14 1111 = Shut down on entering OFF R184 (B8h) for DC-DC2 R187 (BBh) for DC-DC3 9:6 0000 R190 (BEh) for DC-DC4 Note: n is number between 1 and 4 that identifies the individual DC-DC converter Table 71 Enabling and Disabling the DC-DC Converters 14.6.2 CLOCKING The DC-DC converters are controlled by an internally generated clock signal from the RC Oscillator with a constant frequency of around 2.0MHz for DC-DC 1, 3 and 4, and a constant frequency of around 1.0MHz for DC-DC 2. w PD, February 2011, Rev 4.4 126 WM8351 Production Data 14.6.3 DC-DC BUCK (STEP-DOWN) CONVERTER CONTROL DC-DC Converters 1, 3 and 4 are buck converters which can be configured to operate in different operating modes using the register bits described in Table 72. In Active mode, the DC-DC Converters operate to their highest level of performance. The DC-DC Converters will automatically select PWM or Pulse-Skipping operation according to the load condition. This enables the power efficiency to be maximised across a wide range of load conditions. It is possible to force the Converters to use the higher performance PWM mode; in this mode, pulseskipping is disabled and the output voltage is regulated by switching at a constant frequency which improves the transient response at light loads. In Standby/Hysteretic Mode, the DC-DC Converters disable some of the internal control circuitry in order to reduce power consumption. The load regulation may be degraded in this mode of operation. The efficiency data in Section 9.2.1 shows the conditions under which Standby Mode can offer better efficiency than Active Mode. In LDO Mode, the DC-DC Converters are reconfigured as low power LDOs. When DCn_SLEEP = 0, the corresponding DCn_ACTIVE register bit selects between Active and Standby/Hysteretic modes for the associated DC-DC converter. The DCn_SLEEP register bits control the selection of LDO Mode. Setting DCn_SLEEP = 1 selects LDO Mode. This bit takes precedence over the corresponding DCn_ACTIVE bit. ADDRESS R177 (B1h) DC-DC Active Options R178 (B2h) DC-DC Sleep Options BIT LABEL DEFAULT 0 DC1_ACTIVE 1 2 DC3_ACTIVE 1 3 DC4_ACTIVE 1 0 DC1_SLEEP 0 2 DC3_SLEEP 0 3 DC4_SLEEP 0 DESCRIPTION DC-DCn Active mode 0 = Select Standby mode 1 = Select Active mode DC-DCn Sleep Mode 0 = Normal DC-DC operation 1 = Select LDO mode Note: n is either 1, 3 or 4 and identifies the individual DC-DC converter R248 (F8h) DCDC1 Test Controls 4 DC1_FORCE_ PWM 0 Force DC-DC1 PWM mode 0 = Normal DC-DC operation 1 = Force DC-DC PWM mode R250 (FAh) DCDC3 Test Controls 4 DC3_FORCE_ PWM 0 Force DC-DC3 PWM mode 0 = Normal DC-DC operation 1 = Force DC-DC PWM mode R251 (FBh) DCDC4 Test Controls 4 DC4_FORCE_ PWM 0 Force DC-DC4 PWM mode 0 = Normal DC-DC operation 1 = Force DC-DC PWM mode Table 72 Operating Mode Control for DC-DC Converters 1, 3 and 4 w PD, February 2011, Rev 4.4 127 WM8351 Production Data DC-DC Converters 1, 3 and 4 can also be controlled by the device HIBERNATE bit, or by hardware input signals L_PWR1, L_PWR2 and L_PWR3. Several GPIO pins can be assigned as L_PWR pins. Each converter can be assigned to one of these three signals, or else to the device HIBERNATE bit. The signals are active high and each converter’s response to the selected signal is programmable as defined in Table 73. Note that, when a GPIO pin is configured as a Hibernate input pin, and this input is asserted, then all DC-DC Converters will be placed in Hibernate mode. In order to use GPIO pins as L_PWR pins, they must be configured by setting the respective GPn_FN, and GPn_DIR bits to the appropriate value (see Section 20). ADDRESS BIT LABEL DEFAULT DESCRIPTION R182 (B6h) for DC-DC1 14:12 DCn_HIB_M ODE [2:0] 001 DC-DCn Hibernate behaviour: 000 = Use current settings (no change) 001 = Select voltage image settings 010 = Force standby mode 011 = Force standby mode and voltage image settings 100 = Force LDO mode 101 = Force LDO mode and voltage image settings 110 = Reserved 111 = Disable output 9:8 DCn_HIB_T RIG [1:0] 00 DC-DCn Hibernate signal select 00 = HIBERNATE register bit 01 = L_PWR1 10 = L_PWR2 11 = L_PWR3 Note that Hibernate is also selected when a GPIO Hibernate input is asserted. R188 (BCh) for DC-DC3 R191 (BFh) for DC-DC4 Note: n is either 1, 3 or 4 and identifies the individual DC-DC converter Table 73 Low-Power Mode Control for DC-DC Converters 1, 3 and 4 w PD, February 2011, Rev 4.4 128 WM8351 Production Data The default output voltage for DC-DC Converters 1, 3 and 4 is set by writing to the DCn_VSEL register bits. The ‘image’ voltage settings DCn_VIMG are alternate values that may be invoked when the HIBERNATE software or hardware control is asserted as described above. The DC-DC Converters 1, 3 and 4 are dynamically programmable - the output voltage may be adjusted in software at any time. These Converters are buck (step-down) converters; their output voltage can therefore be lower than the input voltage, but cannot be higher. ADDRESS R180 (B4h) for DC-DC1 BIT 6:0 LABEL DCn_VSEL [6:0] DEFAULT Dependant on CONFIG[1:0] settings R186 (BAh) for DC-DC3 110 0110 = 3.4V 110 0010 = 3.3V 101 0110 = 3.0V 100 1110 = 2.8V …… 010 0110 = 1.8V 000 1110 = 1.2V 000 0110 = 1.0V 000 0000 = 0.85V R189 (BDh) for DC-DC4 R182 (B6h) for DC-DC1 DESCRIPTION DC-DCn Converter output voltage settings in 25mV steps. Maximum output = 3.4V. 6:0 DCn_VIMG [6:0] 000 0110 R188 (BCh) for DC-DC3 DC-DCn Converter output image voltage settings in 25mv steps. Maximum output = 3.4V. 110 0110 = 3.4V 110 0010 = 3.3V 101 0110 = 3.0V 100 1110 = 2.8V …… 010 0110 = 1.8V 000 1110 = 1.2V 000 0110 = 1.0V 000 0000 = 0.85V R191 (BFh) for DC-DC4 Note: n is either 1, 3 or 4 and identifies the individual DC-DC converter Table 74 Output Voltage Control for DC-DC Converters 1, 3 and 4 When the DC-DC Converters 1, 3 and 4 are disabled, the output can be set to float or else the outputs can be actively discharged through internal resistors. This feature is controlled using the register bits described in Table 75. ADDRESS R180 (B4h) for DC-DC1 R186 (BAh) for DC-DC3 BIT LABEL DEFAULT 10 DCn_OPFLT 0 DESCRIPTION Enable discharge of DC-DCn outputs when DC-DCn is disabled 0 = Enabled - Output to be discharged 1 = Disabled - Output is left floating R189 (BDh) for DC-DC4 Note: n is either 1, 3 or 4 and identifies the individual DC-DC converter Table 75 Output Float Control for DC-DC Converters 1, 3 and 4 w PD, February 2011, Rev 4.4 129 WM8351 Production Data A summary of the Mode Control and Voltage Control for DC-DC Converter 1 is provided in Table 76. Note that “Hibernate” in Table 76 refers to a GPIO Hibernate input or to the applicable Hibernate signal selected by the DC1_HIB_TRIG field. The equivalent logic applies for DC-DC 3 and 4. Note that the DC-DC Converters must also be enabled as described in Table 71. HIBERNATE DC1_HIB_MODE DC1_SLEEP DC1_ACTIVE OPERATING MODE OUTPUT VOLTAGE DC1_VSEL 0 X 0 0 Standby/Hysteretic 0 X 0 1 Active DC1_VSEL 0 X 1 X LDO Mode DC1_VSEL 1 000 DC1_VSEL 001 0 0 Standby/Hysteretic 0 1 Active DC1_VSEL 1 X LDO Mode DC1_VSEL DC1_VIMG 0 0 Standby/Hysteretic 0 1 Active DC1_VIMG 1 X LDO Mode DC1_VIMG 010 X X Standby/Hysteretic DC1_VSEL 011 X X Standby/Hysteretic DC1_VIMG 100 X X LDO Mode DC1_VSEL 101 X X LDO Mode DC1_VIMG 110 X X Disabled N/A 111 X X Disabled N/A Table 76 DC1 Converter Operating Mode Selection 14.6.4 DC-DC BOOST (STEP-UP) CONVERTER CONTROL DC-DC Converter 2 is a boost converter which can be configured to operate in different operating modes, using the register bits described in Table 77. In Switch mode, the DC-DC Converter acts as a switch between VP2 and L2. The switch is enabled (closed) by setting DC2_ENA = 1. The switch is disabled (opened) by setting DC2_ENA = 0. Note that the switch voltage source on VP2 must be >1.2V to ensure reliable operation. In Boost mode, the DC-DC Converter operates as a step-up converter, employing current-mode architecture, capable of powering LED lights. The output voltage can be higher than the input voltage, but cannot be lower. Different configurations of voltage feedback are available in boost mode, to control the output voltage in different ways. The voltage feedback mode is selected by the DC2_FBSRC register field. When DC2_FBSRC = 00, the converter’s output voltage is set by two external resistors connected to FB2. See Section 29 for Applications Information covering the selection of suitable components. When DC2_FBSRC = 01, the converter uses the ISINKA pin as feedback and adjusts its output voltage in order to achieve the required ISINKA current. When DC2_FBSRC = 11, the converter’s output voltage is set by two internal resistors, resulting in a fixed 5V output, suitable for USB interfaces. The current-controlled configuration using ISINKA is intended for controlling a string of seriallyconnected LEDs driven by the DC-DC boost converter. See Table 97 for a definition of the CS1_ISEL register field which determines the required ISINKA current. In this mode, external resistors connected on the FB2 pin determine the maximum output voltage. See Section 29 for Applications Information covering the selection of suitable components. In all configurations, the input pin VP2 must be externally wired to one of the supply rails, BATT or LINE. Using LINE has the advantage that the converters can operate when the battery is flat, defective or absent. Note that VP2 should not be connected to the USB supply rail. The DC2_RMPH and DC2_RMPL bits defined in Table 77 should be set according to the desired output voltage in order to optimise the transient response of the converter. Selecting a different value could result in sub-harmonic oscillation of the converter. w PD, February 2011, Rev 4.4 130 WM8351 Production Data The DC2_ILIM bits defined in Table 77 should be set according to the intended output load conditions. ADDRESS BIT R183 (B7h) DC-DC2 Control 14 DC2_MODE LABEL DEFAULT 0 DC-DC2 Converter Mode 0 = boost mode 1 = switch mode DESCRIPTION 6 DC2_ILIM 0 DC-DC2 peak current limit select 0 = Higher peak current 1 = Lower peak current 4:3 DC2_RMPH DC2_RMPL 01 DC-DC2 compensation ramp {DC2_RMPH, DC2_RMPL} 00 = 20V < VOUT ≤ 30V 01 = 10V < VOUT ≤ 20V 10 = 5V < VOUT ≤ 10V 11 = VOUT ≤ 5V (will be chosen automatically if DC2_FBSRC=11) 1:0 DC2_FBSRC [1:0] 00 DC-DCn voltage feedback selection 00 = voltage feedback (using external resistor divider on pin FBn) 01 = current sink ISINKA used as feedback 10 = Reserved 11 = voltage feedback (using internal resistor divider on pin USB) Table 77 Operating Mode Control for DC-DC Converter 2 DC-DC Converter 2 can also be controlled by the device HIBERNATE bit, or by hardware input signals L_PWR1, L_PWR2 and L_PWR3. Several GPIO pins can be assigned as L_PWR pins. The converter can be assigned to one of these three signals, or else to the device HIBERNATE bit. The signals are active high and the converter’s response to the selected signal is programmable as defined in Table 78. Note that, when a GPIO pin is configured as a Hibernate input pin, and this input is asserted, then all DC-DC Converters will be placed in Hibernate mode. In order to use GPIO pins as L_PWR pins, they must be configured by setting the respective GPn_FN, and GPn_DIR bits to the appropriate value (see Section 20). w PD, February 2011, Rev 4.4 131 WM8351 Production Data ADDRESS R183 (B7h) DC-DC2 Control BIT LABEL DEFAULT 12 DC2_HIB_MO DE 0 DC-DC2 Hibernate behaviour: 0 = Continue as in Active state 1 = Disable converter output DESCRIPTION 9:8 DC2_HIB_TRI G [1:0] 00 DC-DC2 Hibernate signal select 00 = HIBERNATE register bit 01 = L_PWR1 10 = L_PWR2 11 = L_PWR3 Note that Hibernate is also selected when a GPIO Hibernate input is asserted. Table 78 Hibernate Mode Control for DC-DC Converter 2 14.6.5 INTERRUPTS AND FAULT PROTECTION Each DC-DC Converter is monitored for voltage accuracy and fault conditions. An undervoltage condition is set if the voltage falls below 95% of the required level. The action taken in response to a fault condition can be set independently for each DC-DC Converter, as described in Table 79. The DCn_ERRACT fields configure the fault response to disable the respective converter or to shut down the entire system if desired. In addition, DC-DC Converter fault conditions also generate a second-level interrupt (see Section 24). To prevent false alarms during short current surges, faults are only signalled if the fault condition persists. When a DC-DC Converter is started up, any initial fault condition is ignored until the Converter has been allowed time to settle. The time for which any fault condition is ignored is set by the PUTO register field, as described in Table 79. ADDRESS R181 (B5h) for DC-DC1 BIT LABEL DEFAULT 15:14 DCn_ERRAC T [1:0] 00 Action to take on DC-DCn fault (as well as generating an interrupt): 00 = ignore 01 = shut down converter 10 = shut down system 11 = reserved (shut down system) 13:12 PUTO [1:0] 00 Power up time out value for all converters 00 = 0.5ms 01 = 2ms 10 = 32ms 11 = 256ms R184 (B8h) for DC-DC2 DESCRIPTION R187 (BBh) for DC-DC3 R190 (BEh) for DC-DC4 R177 (B1h) DCDC Active options Note: n is a number between 1 and 4 that identifies the individual DC-DC converter Table 79 Fault Responses for DC-DC Converters w PD, February 2011, Rev 4.4 132 WM8351 Production Data The DC-DC Converters and the LDO Regulators have a first-level interrupt, UV_INT (see Section 24). This comprises second-level interrupts from each of the DC-DC Converters and the LDO Regulators. Each DC-DC Converter has a dedicated second-level interrupt which indicates an under-voltage condition. These can be masked by setting the applicable mask bit as defined in Table 80. ADDRESS BIT R28 (1Ch) Under Voltage Interrupt Status 3 UV_DC4_EINT DCDC4 Under-voltage interrupt. (Rising Edge triggered) Note: This bit is cleared once read. 2 UV_DC3_EINT DCDC3 Under-voltage interrupt. (Rising Edge triggered) Note: This bit is cleared once read. 1 UV_DC2_EINT DCDC2 Under-voltage interrupt. (Rising Edge triggered) Note: This bit is cleared once read. 0 UV_DC1_EINT DCDC1 Under-voltage interrupt. (Rising Edge triggered) Note: This bit is cleared once read. “IM_” + name of respective bit in R28 Mask bits for DC-DC converter undervoltage interrupts Each of these bits masks the respective bit in R28 when it is set to 1 (e.g. UV_DC1_EINT in R28 does not trigger a UV_INT interrupt when IM_UV_DC1_EINT in R36 is set). R36 (24h) Under Voltage Interrupt Mask as in R28 LABEL DESCRIPTION Note: there is no over-current fault condition for converter 2. Table 80 DC-DC Converter Interrupts The status of the DC-DC Converters can be indicated and monitored externally via a GPIO pin configured as /VCC_FAULT (see Section 20). When a GPIO pin is configured as /VCC_FAULT output, a logic low level on this pin indicates that there is a fault condition on one of the LDO Regulators, DC-DC Converters, or the Current Limit switch. The /VCC_FAULT output is configurable by the control fields in Register R215. The fields described in Table 81 determine which of the DC-DCs contribute to the /VCC_FAULT indication. An undervoltage or overvoltage condition on any unmasked DC-DC Converter will cause the /VCC_FAULT output to be set to logic low. ADDRESS R215 (D7h) VCC_FAULT BIT LABEL DEFAULT DESCRIPTION 3 DC4_FAULT 0 DCDC4 fault mask for the /VCC_FAULT 0 = don't mask converter fault 1 = mask converter fault 2 DC3_FAULT 0 DCDC3 fault mask for the /VCC_FAULT 0 = don't mask converter fault 1 = mask converter fault 1 DC2_FAULT DCDC2 fault mask for the /VCC_FAULT 0 = don't mask converter fault 1 = mask converter fault 0 DC1_FAULT DCDC1 fault mask for the /VCC_FAULT 0 = don't mask converter fault 1 = mask converter fault Table 81 DC Converter /VCCFAULT Mask Bits w PD, February 2011, Rev 4.4 133 WM8351 Production Data 14.7 CONFIGURING THE LDO REGULATORS The configuration of the LDO Regulators is described in the following sections. Some of the control fields form part of the Custom Mode configuration settings and therefore will not require to be set in software in some applications. 14.7.1 LDO REGULATOR ENABLE The LDO Regulators can be enabled in software using the register fields defined in Table 82. To reduce supply in-rush current, individual regulators should be programmed to start in different time slots within the start-up sequence. In the WM8351 ACTIVE state, the LDO Regulators can be enabled in software using the LDOn_ENA bits. Setting these bits whilst in the Pre-Active state (see Figure 65) will not immediately enable the corresponding LDO Regulators; these bits will only become effective once the WM8351 has reached the ACTIVE state. Each Regulator may be programmed to switch on in a selected timeslot within the start-up sequence. The WM8351 will set the LDOn_ENA field for any LDO Regulator that is enabled during the start-up sequence. Note that setting the LDOn_ENSLOT fields in software is only relevant to the Development Mode, as these fields are assigned preset values in each of the Custom Modes. Each Regulator may be programmed to switch off in a selected timeslot within the shutdown sequence. If a Regulator is not allocated to one of the 14 shutdown timeslots, it will be disabled when the WM8351 enters the OFF state. ADDRESS R13 (0Dh) or BIT DEFAULT DESCRIPTION 8 LDO1_ENA LABEL 0 LDO1 enable 0 = disabled 1 = enabled Note: internal conditions may prevent the converter from actually switching on see DCDC/LDO Status register for actual converter status. 9 LDO2_ENA 0 LDO2 enable 0 = disabled 1 = enabled Note: internal conditions may prevent the converter from actually switching on see DCDC/LDO Status register for actual converter status. 10 LDO3_ENA 0 LDO3 enable 0 = disabled 1 = enabled Note: internal conditions may prevent the converter from actually switching on see DCDC/LDO Status register for actual converter status. 11 LDO4_ENA 0 LDO4 enable 0 = disabled 1 = enabled Note: internal conditions may prevent the converter from actually switching on see DCDC/LDO Status register for actual converter status. R176 (B0h) DC-DC / LDO requested Note: These bits can be accessed through R13 or through R176. Reading from or writing to either register location has the same effect. R201 (C9h) for LDO1 R204 (CCh) for LDO2 w 13:10 LDOn_ENSL OT [3:0] 0000 Time slot for LDOn start-up 0000 = Disabled (do not start up) 0001 = Start-up in time slot 1 … (total 14 slots available) 1110 = Start-up in time slot 14 PD, February 2011, Rev 4.4 134 WM8351 Production Data ADDRESS BIT LABEL DEFAULT DESCRIPTION 1111 = Start up on entering ACTIVE R207 (CFh) for LDO3 9:6 LDOn_SDSL OT [3:0] 0000 R210 (D2h) for LDO4 Time slot for LDOn shutdown. 0000 = Shut down on entering OFF 0001 = Shutdown in time slot 1 …. (total 14 slots available) 1110 = Shutdown in time slot 14 1111 = Shut down on entering OFF Note: n is a number between 1 and 4 that identifies the individual LDO regulator Table 82 Enabling and Disabling the LDO Regulators 14.7.2 LDO REGULATOR CONTROL The LDO Regulators can be configured to operate in different modes using the register bits described in Table 83. In Switch mode, the Regulators operate as current-limited switches with no voltage regulation. In LDO Regulator mode, the Regulators generate an output voltage determined by the LDOn_VSEL fields. The LDO Regulators are dynamically programmable - the output voltage may be adjusted in software at any time. The Regulators are critically damped to ensure there is no voltage overshoot or undershoot when adjusting the output voltage. The default output voltage for the LDO Regulators is set by writing to the LDOn_VSEL register bits. The ‘image’ voltage settings LDOn_VIMG are alternate values that may be invoked when the HIBERNATE software or hardware control is asserted. ADDRESS R200 (C8h) for LDO1 R203 (CBh) for LDO2 BIT LABEL 14 LDOn_SWI 4:0 LDOn_VSEL [4:0] R206 (CEh) for LDO3 DEFAULT LDOn Regulator mode 0 = LDO voltage regulator 1 = Current-limited switch (no voltage regulation, LDOn_VSEL has no effect) Dependant on CONFIG[1:0] settings LDOn Regulator output voltage (when LDOn_SWI=0) 1 1111 = 3.3V … (100mV steps) 1 0000 = 1.8V 0 1111 = 1.65V … (50mV steps) 0 0000 = 0.9V R209 (D1h) for LDO4 R202 (CAh) for LDO1 DESCRIPTION 0 4:0 LDOn_VIMG [4:0] 1 1100 R205 (CDh) for LDO2 R208 (D0h) for LDO3 LDOn Regulator output image voltage 1 1111 = 3.3V … (100mV steps) 1 0000 = 1.8V 0 1111 = 1.65V … (50mV steps) 0 0000 = 0.9V R211 (D3h) for LDO4 Note: n is a number between 1 and 4 that identifies the individual LDO regulator Table 83 Controlling Regulator Voltage and Switch Mode w PD, February 2011, Rev 4.4 135 WM8351 Production Data The LDO Regulators can also be controlled by the device HIBERNATE bit, or by hardware input signals L_PWR1, L_PWR2 and L_PWR3. Several GPIO pins can be assigned as L_PWR pins. Each Regulator can be assigned to one of these three signals, or else to the device HIBERNATE bit. The signals are active high and each Regulator’s response to the selected signal is programmable as defined in Table 84. Note that, when a GPIO pin is configured as a Hibernate input pin, and this input is asserted, then all LDO Regulators will be placed in Hibernate mode. In order to use GPIO pins as L_PWR pins, they must be configured by setting the respective GPn_FN, and GPn_DIR bits to the appropriate value (see Section 20). ADDRESS BIT LABEL DEFAULT DESCRIPTION Note: n is a number between 1 and 4 that identifies the individual LDO regulator R202 (CAh) for LDO1 13:12 LDOn_HIB_M ODE [1:0] 00 LDO Hibernate behaviour: 00 = Select voltage image settings 01 = disable output 10 = reserved 11 = reserved 9:8 LDOn_HIB_T RIG [1:0] 00 LDO Hibernate signal select 00 = Hibernate register bit 01 = L_PWR1 10 = L_PWR2 11 = L_PWR3 R205 (CDh) for LDO2 R208 (D0h) for LDO3 R211 (D3h) for LDO4 Table 84 Configuring Hardware Control for LDO Regulators When the LDO Regulators are disabled, the output can be set to float or else the outputs can be actively discharged through internal resistors. This feature is controlled using the register bits described in Table 85. Note that the “float” option is only supported when at least one other LDO Regulator remains enabled. If LDO Regulators 1, 2, 3 and 4 are all disabled, then the LDO Regulator outputs will be discharged, regardless of the LDOn_OPFLT registers. ADDRESS R200 (C8h) for LDO1 BIT 10 LABEL LDOn_OPFLT DEFAULT DESCRIPTION 0 Enable discharge of LDOn outputs when LDOn disabled 0 = Enabled - Output to be discharged 1 = Disabled - Output is left floating Note - if LDO Regulators 1, 2, 3 and 4 are all disabled, then the outputs will all be discharged, regardless of the LDOn_OPFLT bit. R203 (CBh) for LDO2 R206 (CEh) for LDO3 R209 (D1h) for LDO4 Note: n is a number between 1 and 4 that identifies the individual LDO regulator Table 85 Output Float Control for LDO Regulators w PD, February 2011, Rev 4.4 136 WM8351 Production Data 14.7.3 INTERRUPTS AND FAULT PROTECTION Each LDO Regulator is monitored for voltage accuracy and fault conditions. An undervoltage condition is set if the voltage falls below 95% of the required level. The action taken in response to a fault condition can be set independently for each LDO Regulator, as described in Table 86. The LDOn_ERRACT fields configure the fault response to disable the respective regulator or to shut down the entire system if desired. In addition, LDO Regulator fault conditions also generate a second-level interrupt (see Section 24). To prevent false alarms during short current surges, faults are only signalled if the fault condition persists. ADDRESS R201 (C9h) for LDO1 BIT LABEL DEFAULT 15:14 LDOn_ERRACT [1:0] 00 R204 (CCh) for LDO2 DESCRIPTION Action to take on fault (as well as generating an interrupt): 00 = ignore 01 = shut down regulator 10 = shut down system 11 = reserved (shut down system) R207 (CFh) for LDO3 R210 (D2h) for LDO4 Note: n is a number between 1 and 4 that identifies the individual LDO regulator Table 86 Fault Responses for LDO Regulators The DC-DC Converters and the LDO Regulators have a first-level interrupt, UV_INT (see Section 24). This comprises second-level interrupts from each of the DC-DC Converters and the LDO Regulators. Each LDO Regulator has a dedicated second-level interrupt which indicates an under-voltage condition. These can be masked by setting the applicable mask bit as defined in Table 87. ADDRESS BIT R28 (1Ch) Under Voltage Interrupt Status 11 UV_LDO4_EINT LDO4 Under-voltage interrupt. (Rising Edge triggered) Note: This bit is cleared once read. 10 UV_LDO3_EINT LDO3 Under-voltage interrupt. (Rising Edge triggered) Note: This bit is cleared once read. 9 UV_LDO2_EINT LDO2 Under-voltage interrupt. (Rising Edge triggered) Note: This bit is cleared once read. 8 UV_LDO1_EINT LDO1 Under-voltage interrupt. (Rising Edge triggered) Note: This bit is cleared once read. “IM_” + name of respective bit in R28 Mask bits for LDO regulator under-voltage interrupts Each of these bits masks the respective bit in R28 when it is set to 1 (e.g. UV_LDO1_EINT in R28 does not trigger a UV_INT interrupt when IM_UV_LDO1_EINT in R36 is set). R36 (24h) Under Voltage Interrupt Mask as in R28 LABEL DESCRIPTION Table 87 LDO Regulator Interrupts w PD, February 2011, Rev 4.4 137 WM8351 Production Data The status of the LDO Regulators can be indicated and monitored externally via a GPIO pin configured as /VCC_FAULT (see Section 20). When a GPIO pin is configured as /VCC_FAULT output, a logic low level on this pin indicates that there is a fault condition on one of the LDO Regulators, DC-DC Converters, or the Current Limit switch. The /VCC_FAULT output is configurable by the control fields in Register R215. The fields described in Table 88 determine which of the LDOs contribute to the /VCC_FAULT indication. An undervoltage or overvoltage condition on any unmasked LDO will cause the /VCC_FAULT output to be set to logic low. ADDRESS R215 (D7h) VCC_FAULT BIT LABEL DEFAULT DESCRIPTION 11 LDO4_FAULT 0 LDO4 fault mask for the /VCC_FAULT 0 = don't mask converter fault 1 = mask converter fault 10 LDO3_FAULT 0 LDO3 fault mask for the /VCC_FAULT 0 = don't mask converter fault 1 = mask converter fault 9 LDO2_FAULT 0 LDO2 fault mask for the /VCC_FAULT 0 = don't mask converter fault 1 = mask converter fault 8 LDO1_FAULT 0 LDO1 fault mask for the /VCC_FAULT 0 = don't mask converter fault 1 = mask converter fault Table 88 LDO Regulator /VCCFAULT mask bits 14.7.4 ADDITIONAL CONTROL FOR LDO1 By default, all DC Converters and LDOs are disabled in the OFF state. Additional control is provided to enable LDO1 to be configured differently, allowing it to be enabled in the OFF state, or else to be controlled by a GPIO pin configured as /LDO_ENA (see Section 20.2.2). These options are selected by setting the register fields described in Table 89. In practical applications, however, these options are set by the Config Mode settings and are not set by users. Operation of LDO1 in the OFF state is subject to the restriction that VOUT1 must be set to at least 1.8V. CONDITION DESCRIPTION LDO1_PIN_MODE = 0 LDO1 controlled as normal via register bits LDO1_PIN_MODE = 1 LDO1_PIN_EN = 0 LDO1 enabled at all times LDO1_PIN_MODE = 1 LDO1_PIN_EN = 1 LDO1 controlled by /LDO_ENA only Table 89 LDO1 Additional Control Notes: w 1. LDO1 is always disabled in BACKUP and ZERO states. 2. When LDO1_PIN_MODE = 1, then LDO1 only operates as determined by the LDO1_VSEL field. The Hibernate settings are ignored under this configuration. PD, February 2011, Rev 4.4 138 WM8351 Production Data 14.8 DC-DC CONVERTER OPERATION 14.8.1 OVERVIEW The WM8351 provides four DC-DC switching converters. Three of these are Buck (Step-down) converters and one is a Boost (Step-up) converter. The principal characteristics and typical usage for each DC-DC converter are shown below. Typical Application Converter Type DC-DC 1 DC-DC 2 DC-DC 3 / 4 Other system components Constant-current LED drivers or I/O supply Digital supply for WM8351 and other components Step-down Step-up, using external NFET Step-down Input Voltage Range 2.7V to 5.5V Output Voltage Range 0.85V to 3.4V Load Current Rating Up to 1A (may be limited by application) Switching Frequency 2.0MHz 5V to 20V 170mA @ 5V 40mA @ 20V 1.0MHz 0.85V to 3.4V Up to 500mA (may be limited by application) 2.0MHz Table 90 DC-DC Converter Characteristics w PD, February 2011, Rev 4.4 139 WM8351 Production Data 14.8.2 DC-DC STEP DOWN CONVERTERS DC-DC Converters 1, 3 and 4 are versatile step-down, pulse-width-modulated (PWM) DC-DC converters designed to deliver high power efficiency across full load conditions. The converters offer Active and Standby/Hysteretic operating modes in order to maximise efficiency for different loads. A low-power LDO sleep mode is also available to further reduce quiescent current at very lightly loaded conditions. The DC-DC Converters maintain output voltage regulation during the switch-over between operating modes. The step-down regulators are designed with fixed frequency current mode architecture. The current feedback loop is through the PMOS current path and is amplified and summed with an internal slope compensation network. The voltage feedback loop is through an internal feedback divider. The ON time is determined by comparing the summed current feedback and the output of the switcher error amplifier. The period is set by the internal RC oscillator, which provides a 2.0MHz clock. A supply pin (PVDD) provides the core supply for DC-DC Converter 3. Another supply pin (LINEDCDC) provides the core supply for DC-DC Converters 1 and 4. The input voltage connection to DC-DC Converters 1, 3 and 4 is provided on PV1, PV3 and PV4 respectively. These input voltages may be provided from the LINE voltage. The connections to DC-DC Converter 1 are illustrated in Figure 69. The equivalent circuit applies to DC-DC Converters 3 and 4 also. Figure 69 Step-Down DC-DC Converter Connections The external components at the converter output are required by the DC-DC Converter integral loop compensation circuit. Note that the recommended output capacitor Cout varies according to the required transient response on DC-DC1. A single recommended value is provided for Cout on DCDC3 and DC-DC4. See Section 29.3 for details of the recommended external components. w PD, February 2011, Rev 4.4 140 WM8351 Production Data 14.8.3 DC-DC STEP UP CONVERTER DC-DC Converter 2 is a versatile step-up pulse-width-modulated (PWM) DC-DC converter designed to deliver high power efficiency across full load conditions. The converter can also be used as a switch. DC-DC Converter 2 is designed with a fixed frequency current mode architecture. The clock frequency is set by the internal RC oscillator, which provides a 1.0MHz clock. The PVDD supply pin provides the core supply for DC-DC Converter 2. The connections to DC-DC Converter 2 in Constant Voltage Mode are illustrated in Figure 70. See Section 29.4 for details of the connections for the Constant Current and USB operating modes of the DC-DC Step-Up Converter. Figure 70 Step-Up DC-DC Converter Connections The external components at the converter output are required by the DC-DC Converter integral loop compensation circuit. Note that the recommended output capacitor Cout varies according to the required output voltage. See Section 29.4 for details of the recommended external components. w PD, February 2011, Rev 4.4 141 WM8351 Production Data 14.9 LDO REGULATOR OPERATION The WM8351 provides four identical LDO voltage regulators to generate accurate, low-noise supply voltages for various system components. The LDOs can also operate as current-limited switches, with no voltage regulation; this is useful for ‘Hot Swap’ outputs, i.e. supply rails for external devices that are plugged in when the system is already powered up - the current-limiting function prevents the in-rush current into the external device from disturbing other system power supplies. The LDO regulators are dynamically programmable. Each regulator output is current-limited; the output voltage is automatically throttled back if the load current exceeds the limit. A single supply pin (LDOVDD) provides the core supply for all four LDOs. The input voltage connection to LDO1 and LDO2 is provided on the VINA pin. The input voltage connection to LDO3 and LDO4 is provided on the VINB pin. These input voltages can be provided from one of the DC-DC Converters or from the LINE voltage. Note that separate voltage regulators are provided to generate the backup supply VRTC and the microphone bias voltage MICBIAS. The connections to LDO Regulator 1 are illustrated in Figure 71. The equivalent circuit applies to LDO2, LDO3 and LDO4. Figure 71 LDO Regulator Connections An input and output capacitor are recommended for each LDO Regulator, as illustrated above. See Section 29.5 for details of the recommended external components. w PD, February 2011, Rev 4.4 142 WM8351 Production Data 15 CURRENT LIMIT SWITCH 15.1 GENERAL DESCRIPTION The WM8351 includes an on-chip Current Limit Switch to control external devices and to support hotplugging of accessories and power supplies. When the switch is enabled, it normally has a low resistance, allowing current to pass through (from the IP pin to the OP pin). If the current limit threshold is reached, the WM8351 can raise an interrupt, disable the switch and/or shut down the whole device. 15.2 CONFIGURING THE CURRENT LIMIT SWITCH 15.2.1 CURRENT LIMIT SWITCH ENABLE The Current Limit Switch can be enabled in software using the register fields defined in Table 91. In Active mode, the Current Limit Switch can be enabled in software using the LS_ENA bit. Setting this bit whilst in the Pre-Active state (see Figure 65) will not immediately enable the Current Limit Switch; this bit will only become effective once the WM8351 has reached the Active state. The Current Limit Switch may be programmed to become enabled in a selected timeslot within the start-up sequence. When this happens, the WM8351 will set the LS_ENA bit. Note that setting the LS_ENSLOT field in software is only relevant to the Development Mode, as this field is assigned a preset value in each of the Custom Modes. The Current Limit Switch may be programmed to switch off in a selected timeslot within the shutdown sequence. If the Limit Switch is not allocated to one of the 14 shutdown timeslots, it will be disabled when the WM8351 enters the OFF state. The Current Limit Switch behaviour in Hibernate mode is controlled by the LS_HIB_MODE bit. ADDRESS BIT R13 (0Dh) 15 R176 (B0h) DC-DC / LDO requested 15 LABEL LS_ENA DEFAULT DESCRIPTION 0 Limit switch enable 0 = disabled 1 = enabled Note: internal conditions may prevent the converter from actually switching on - see DCDC/LDO Status register for actual converter status. Note: LS_ENA can be accessed through R13 or through R176. Reading from or writing to either register location has the same effect. R199 (C7h) Limit switch control 13:10 LS_ENSLOT [3:0] 0000 Time slot for Limit Switch start-up 0000 = Disabled (do not start up) 0001 = Start-up in time slot 1 … (total 14 slots available) 1110 = Start-up in time slot 14 1111 = Start-up on entering ACTIVE 9:6 LS_SDSLOT [3:0] 0000 Time slot for Limit Switch shutdown. 0000 = Shut down on entering OFF 0001 = Shutdown in time slot 1 …. (total 14 slots available) 1110 = Shutdown in time slot 14 1111 = Shut down on entering OFF 4 LS_HIB_MO DE 0 Limit switch hibernate mode setting 0 = disabled 1 = leave setting as in Active mode Table 91 Enabling and Disabling the Current Limit Switch w PD, February 2011, Rev 4.4 143 WM8351 Production Data 15.2.2 CURRENT LIMIT SWITCH BULK DETECTION CONTROL The Current Limit Switch can be connected to voltages which may be higher than the device LINE voltage. To support this capability, the switch is powered from the highest available voltage; this requires a bulk detection circuit in order to select the highest available voltage. The bulk detection circuit is always enabled whenever the Current Limit Switch is enabled. It is possible to control whether the bulk detection circuit is enabled or not when the Current Limit Switch is disabled. This is controlled in Active mode by the LS_PROT bit, and in Hibernate mode by the LS_HIB_PROT bit. Disabling the Bulk Detection circuit will reduce power consumption. It is important to note, however, that the Bulk Detection circuit should always be enabled if voltages greater than LINE could be present on IP or OP. This applies regardless of whether the Current Switch is open or closed. ADDRESS R199 (C7h) Limit switch control BIT LABEL DEFAULT 1 LS_HIB_PRO T 1 Controls the bulk detection circuit when Limit Switch is disabled in Hibernate mode. 0 = bulk detection disabled 1 = bulk detection enabled DESCRIPTION 0 LS_PROT 1 Controls the bulk detection circuit when Limit Switch is disabled in Active mode. 0 = bulk detection disabled 1 = bulk detection enabled Table 92 Current Limit Switch Bulk Detection Control 15.2.3 INTERRUPTS AND FAULT PROTECTION The response to an over-current condition is selectable. To prevent false alarms during short current surges, faults are only signalled if the fault condition persists. ADDRESS R199 (C7h) Limit switch control BIT 15:14 LABEL LS_ERRACT [1:0] DEFAULT 00 DESCRIPTION Current limit detection behaviour 00 = ignore 01 = disable switch 10 = shut down system 11 = shut down system Table 93 Fault Response for the Current Limit Switch The limit switch has its own first-level interrupt, OC_INT (see Section 24). This contains a single second-level interrupt, OC_LS_EINT, indicating an over-current condition. OC_LS_EINT can be masked by setting the IM_OC_LS_EINT bit. ADDRESS BIT R29 (1Dh) Over Current Interrupt Status 15 OC_LS_EINT LABEL Limit Switch Over-current interrupt. (Rising Edge triggered) Note: This bit is cleared once read. DESCRIPTION R37 (25h) Over Current Interrupt Mask 15 IM_OC_LS_EINT Mask bit for Limit switch over-current interrupt When set to 1, IM_OC_LS_EINT masks OC_LS_EINT in R29 and does not trigger an OC_INT interrupt when OC_LS_EINT is set). Table 94 Current Limit Switch Interrupts The status of the Current Limit Switch can be indicated and monitored externally via a GPIO pin configured as /VCC_FAULT (see Section 20). When a GPIO pin is configured as /VCC_FAULT output, a logic low level on this pin indicates that there is a fault condition on one of the LDO Regulators, DC-DC Converters, or the Current Limit switch. w PD, February 2011, Rev 4.4 144 WM8351 Production Data The /VCC_FAULT output is configurable by the control fields in Register R215. The LS_FAULT bit described in Table 95 selects whether the Limit Switch contributes to the /VCC_FAULT indication. When LS_FAULT = 0, then an overcurrent condition on the Limit Switch will cause the /VCC_FAULT output to be set to logic low. ADDRESS R215 (D7h) VCC_FAULT BIT 15 LABEL LS_FAULT DEFAULT 0 DESCRIPTION Limit Switch fault mask for the /VCC_FAULT 0 = don't mask converter fault 1 = mask converter fault Table 95 Limit Switch /VCCFAULT Mask w PD, February 2011, Rev 4.4 145 WM8351 Production Data 16 CURRENT SINKS (LED DRIVERS) 16.1 GENERAL DESCRIPTION The WM8351 includes four pins for driving different types of LEDs. The ISINKA pin provides a programmable constant-current sink designed to drive a string of serially connected LEDs, including white LEDs used in display backlights or in camera flash applications. Using ISINKA in conjunction with DC-DC Converter 2 provides a particularly power-efficient way to drive such LED strings. The ground connection associated with this Current Sink is the SINKGND pin. ISINKC, ISINKD and ISINKE are regular open-drain outputs. They are alternate functions of the GPIO10, GPIO11 and GPIO12 pins respectively. These GPIOs are provided on the LINE power domain; the associated ground connection is the GND pin. 16.2 CONSTANT-CURRENT SINK ISINKA is a dedicated LED driver pin equipped with a programmable constant current sink. It is designed to drive a string of serially connected white LEDs such as those used in display backlights or photo-flash applications. Powering LEDs in this way is particularly power efficient because no series resistor is required. DC-DC converter 2, operating as a current-controlled voltage source, is an ideal power source for LED strings. This converter can generate voltages higher than BATT or LINE, which can overcome the combined forward voltages of long LED strings (e.g. a string of 7 white LEDs with a forward voltage of 4V requires at least 28V). 16.2.1 ENABLING THE SINK CURRENT In Active mode, ISINKA can be enabled in software using the CS1_ENA register field defined in Table 96. If required, the Current Sink function may also be controlled by the Hibernate bit. Note that these control bits do not exist for ISINKC, ISINKD or ISINKE. ADDRESS BIT R14 (0Eh) Power mgmt (7) 0 R172 (ACh) Current Sink Driver A 15 12 LABEL DEFAULT DESCRIPTION CS1_ENA 0 Current Sink 1 enable (ISINKA pin) 0 = disabled 1 = enabled CS1_HIB_MO DE 0 Current Sink 1 behaviour in Hibernate mode 0 = disable current sink in Hibernate 1 = leave current sink as in Active Note: CS1_ENA can be accessed through R14 or through R172. Reading from or writing to either register location has the same effect. Table 96 Enabling ISINKA When ISINKA is used in conjunction with DC-DC Converter 2, the ISINK should always be switched on before the DC-DC Converter is switched on. Conversely, the DC-DC Converter should always be switched off before the ISINK is switched off. If high voltages are used, additional external components may also be needed to protect the WM8351. 16.2.2 PROGRAMMING THE SINK CURRENT The sink current for ISINKA can be programmed by writing to the CS1_ISEL register bit. The current steps are logarithmic to match the logarithmic light sensitivity characteristic of the human eye. The step size is 1.5dB (i.e. the current doubles every four steps). w PD, February 2011, Rev 4.4 146 WM8351 Production Data ADDRESS R172 (ACh) Current Sink Driver A BIT 5:0 LABEL CS1_ISEL DEFAULT DESCRIPTION 00 0000 ISINKA current = 4.05μA × 2CS1_ISEL/4 where CS1_ISEL is an unsigned binary number Minimum: 00 0000 = 4.05μA, Maximum: 11 1111 = 220mA (from circuit simulation) or CS1_ISEL = 13.3 × log (desired current / 4.05μA) Table 97 Controlling the Sink Current for ISINKA Note that currents above 40mA are not supported continuously; these settings are intended for flash mode only. 16.2.3 FLASH MODE The current sink can either sink current continuously (LED mode) or in short bursts (flash mode). The operating mode is selected by the CS1_FLASH_MODE bit, as described in Table 98. In LED mode, the current sink is controlled by setting CS1_DRIVE. For as long as this bit is asserted, the LED is enabled continuously. In Flash mode, the current sink may be set to automatically flash every 4 seconds by setting CS1_FLASH_RATE = 1, or may be triggered normally by setting CS1_FLASH_RATE = 0. When normal triggering is selected in Flash mode, the trigger control can be either a GPIO Flash input (see Section 20) or a register control. Setting CS1_TRIGSRC = 1 selects GPIO as the trigger. The flash will be edge triggered by the selected GPIO input. Setting CS1_TRIGSRC = 0 selects the register field CS1_DRIVE as the trigger. In this case, writing a 1 to CS1_DRIVE will trigger a flash; this bit will be reset at the end of the flash. In all flash modes, the duration of each flash is set by CS1_FLASH_DUR. The status of each current sink may be read from the CS1_DRIVE bit. In all modes, the current sink must also be enabled via the applicable CS1_ENA bit (see Table 96). Note that some photo-flash applications may require a reservoir capacitor to store sufficient charge for the flash. w PD, February 2011, Rev 4.4 147 WM8351 Production Data ADDRESS R173 (ADh) CSA Flash Control BIT LABEL DEFAULT 15 CS1_FLASH_M ODE 0 Determines the function of the current sink 0 = LED mode 1 = Flash mode DESCRIPTION 14 CS1_TRIGSRC 0 Selects the trigger in Flash mode. 0 = Flash triggered by CS1_DRIVE bit 1 = Flash triggered from GPIO pin configured as FLASH This bit has no effect when CS1_FLASH_MODE=0 13 CS1_DRIVE 0 Enables the current sink ISINKA LED mode0 = disable LED 1 = enabled LED FLASH modeRegister bit used to trigger the flash, if CS1_TRIGSRC is set to 0. Flash is started when the bit goes high, it is then reset at the end of the flash duration. Duration is determined by CS1_FLASH_DUR. This bit has no effect if CS1_TRIGSRC is set to 1. 12 CS1_FLASH_R ATE 0 Determines the Flash rate 0 = Normal Operation. Once per trigger (Either register bit or GPIO) 1 = Flash will be internally triggered every 4 second 9:8 CS1_FLASH_D UR [1:0] 00 Sets duration of flash 00 = 32ms 01 = 64ms 10 = 96ms 11 = 1024ms Table 98 Configuring Flash Mode for ISINKA w PD, February 2011, Rev 4.4 148 WM8351 Production Data 16.2.4 ON/OFF RAMP TIMING The sink current for ISINKA can be programmed to switch on and off gradually in LED and in Flash modes. The current ramp duration is as described in Table 99. ADDRESS R173 (ADh) CSA Flash Contro BIT LABEL DEFAULT 5:4 CS1_OFF_RA MP [1:0] 00 1:0 CS1_ON_RAM P [1:0] 00 DESCRIPTION Switch-off ramp duration LED Mode Flash Mode 00 = instant (no ramp) 01 = 0.25s 10 = 0.5s 11 = 1s 00 = instant (no ramp) 01 = 1.95ms 10 = 3.91ms 11 = 7.8ms Switch-on ramp duration Similar to CS1_OFF_RAMP Table 99 Configuring On/Off Ramp Timing for ISINKA 16.2.5 INTERRUPTS AND FAULT PROTECTION The Current Sink has its own first-level interrupt, CS_INT (see Section 24). This contains a single second-level interrupt, CS1_EINT, indicating that the Current Sink is unable to sink the amount of current that has been programmed and may be out of spec. CS1_EINT can be masked by setting the IM_CS1_EINT bit. ADDRESS BIT R26 (1Ah) Interrupt Status 2 13 CS1_EINT LABEL Flag to indicate drain voltage can no longer be regulated and output current may be out of spec. (Rising Edge triggered) Note: This bit is cleared once read. DESCRIPTION R34 (22h) Interrupt Status 2 Mask 13 IM_CS1_EINT Mask bit for Current Sink over-current interrupt When set to 1, IM_CS1_EINT masks CS1_EINT in R26 and does not trigger a CS_INT interrupt when CS1_EINT is set. Table 100 Current Sink Interrupts w PD, February 2011, Rev 4.4 149 WM8351 Production Data 16.3 OPEN-DRAIN LED OUTPUTS The three open-drain outputs ISINKC, ISINKD and ISINKE are alternate functions of the GPIO10, GPIO11 and GPIO12 pins, respectively (see Section 20). They can drive LEDs connected to LINE, with a series resistor. Note that the GPIO pins have other alternate functions, which will not be available that pin is configured as ISINKC, ISINKD or ISINKE. 16.4 LED DRIVER CONNECTIONS The recommended connection for LEDs on ISINKA is illustrated in Figure 72. Figure 72 LED Connection to ISINKA The recommended connections for LEDs on ISINKC, ISINKD and ISINKE are illustrated in Figure 73. Figure 73 LED Connections to ISINKC, ISINKD and ISINKE w PD, February 2011, Rev 4.4 150 WM8351 Production Data 17 POWER SUPPLY CONTROL 17.1 GENERAL DESCRIPTION The WM8351 can take its power supply from a Wall adaptor, a USB interface or from a single-cell lithium battery. The WM8351 autonomously chooses the most appropriate power source available, and supports hot-swapping between sources (ie. the system can remain in operation while different sources are connected and disconnected). Comparators within the WM8351 identify which power supplies are available and select the power source in the following order of preference: • Wall adaptor (LINE pins) • USB power rail (USB pins) • Battery (BATT pins) Note that the Wall supply is always the first choice of supply, (providing that it is within required limits), even if the Wall supply voltage is lower than the USB voltage. When Wall or USB is selected as the power source, this may be used to charge the Battery, using the integrated battery charger circuit. For battery charging to occur, the USB or LINE supply voltage must be no less than 4.0V. Figure 74 illustrates the WM8351 connections associated with the WALL, USB and Battery supplies. Figure 74 WM8351 Power Supply Connections The Wall Adaptor supply connects to LINE via a FET switch as illustrated in Figure 74. The FET switch is necessary in order to provide isolation between the Wall supply and the Battery/USB supplies; this is vital in the event of the USB voltage being greater than the Wall supply voltage. The Wall Adapter voltage is sensed directly on the WALL_FB pin; this allows the WM8351 to determine the preferred supply, including when the FET is switched off. The gate connection to the external FET is controlled by LINE_SW, which is an alternate function that can be enabled on GPIO12 (see Section 20). Note that, if the USB connection is not used, then the FET may not be required and the Wall supply may be connected directly to LINE. LINE is primarily an output from the WM8351; this output is the preferred supply, where the WM8351 has arbitrated between the Wall, Battery and USB connections. This output is suitable for supplying power to the other blocks of the WM8351, including the DC-DC Converters and LDO Regulators. LINE is also an input under some conditions, such as battery charging from Wall or providing power at the USB connection. w PD, February 2011, Rev 4.4 151 WM8351 Production Data HIVDD is an external connection which exists for the purposes of decoupling only. It represents the highest available power supply connected to the WM8351. It should be noted that the preferred supply (on the LINE pin) is not necessarily the same voltage as HIVDD - the Wall supply will always be the preferred voltage when it is within the intended limits, even if it is not also the highest available source. The main battery connects directly to the BATT pin. When the battery is the preferred supply source, this pin is an input. When battery charging is in operation, this pin is an output. (Note that the backup VRTC battery is connected separately - see Section 17.5.) The USB interface connects directly to the USB pin. In USB Master Mode (USB is less than LINE), the WM8351 can supply power to external devices on this pin. In USB Slave Mode (USB is greater than LINE), the WM8351 can use this pin as an input to power the device and/or to charge a battery connected to the BATT pin. Note that, when USB is the preferred power supply, the Battery may also be used if necessary to supplement the current drawn from the USB pin (ie. to source current into LINE when required). All loads connected to the WM8351 should normally be connected to the LINE pin. The inputs to the DC-DC Converters and LDOs should be connected to the LINE pin. It is not recommended to connect any load directly to the battery (BATT). Note that the inputs to the LDOs may be connected to the outputs of the DC-DCs if desired. 17.2 BATTERY POWERED OPERATION The WM8351 selects battery power when the Battery voltage is higher than the Wall (LINE) and USB supplies. In practical usage, this means the Battery is used when Wall (LINE) and USB are both disconnected. The battery can also be used to supplement the USB supply when required (ie. to source current into LINE). If the Wall (LINE) or USB supply becomes available during battery operation, then the selected power source is adjusted accordingly. Battery pack temperature sensing is enabled by default. The battery’s NTC resistor is monitored via the AUX1 pin on the WM8351, as described in Section 17.7. Note that the absence of this NTC connection will lead to a temperature failure condition being detected and battery charging will not be possible. Safe operation of the battery charger outside the designed operating temperatures is not guaranteed when a battery NTC resistor is not used. The designed operating temperatures are noted in Section 17.7.7. 17.3 WALL ADAPTOR (LINE) POWERED OPERATION The WM8351 selects Wall Adaptor power via the LINE pins whenever the Wall Adaptor supply is within the normal operating limits of 4.0V to 5.5V. The Wall Adaptor is also selected as the power source below 4.0V in the case where it is the highest available power source. The minimum LINE voltage is a programmable threshold in the range 2.9V to 3.6V (see Section 18). The maximum recommended operating voltage for LINE is 5.5V. Note that USB power is not used when a suitable LINE supply is available, even if the USB supply is higher than the Wall (LINE) supply. If the Wall (LINE) supply becomes unsuitable and a USB is available, then the USB supply will be selected as the preferred power source. Note that, when hot-swapping from Wall (LINE) to USB supply, a usable Battery must be present on the BATT pin. When the Wall (LINE) supply is selected and a Battery is connected, then trickle charging is enabled by default, including when the WM8351 is in the OFF or HIBERNATE states. When the WM8351 is in the ACTIVE state, then fast charging may be selected under software control. w PD, February 2011, Rev 4.4 152 WM8351 Production Data 17.4 USB POWERED OPERATION The WM8351 selects USB Slave mode by default. In USB Slave Mode, the USB pin can be used as one of the sources of power for the WM8351. In USB Master Mode (selected using the USB_MSTR register bit) the WM8351 can provide power to an external USB device. In USB Slave mode, the WM8351 selects USB power if the Wall (LINE) supply is outside its normal operating limits and the USB supply is the highest supply source available. For a transition from OFF to ACTIVE state to occur under USB power, the USB supply must be no less than 4.0V. The maximum current drawn from the USB supply can be set to 100mA (USB low power mode) or 500mA (USB high power mode). The default is set according to the selected Config Mode (see Section 14). When the WM8351 is in the ACTIVE state, USB high power mode can be selected using the register bits USB_MSTR_500MA (in USB Master Mode) or USB_SLV_500MA (in USB Slave Mode) as defined in Table 101. If a USB current higher than the applicable threshold is demanded, then internal protection circuits will limit the USB current, and the USB_LIMIT_EINT interrupt will be asserted. Short term currents higher than 500mA can also be supported. This may be necessary for supporting transient demands (eg. for a hard drive starting up). When the USB_NOLIM register field is set, the internal protection circuits are disabled, and the current limit interrupt threshold is raised to double the normal value. In 500mA mode, the current limit interrupt threshold is raised to approximately 1A. This feature must be used with caution, as the internal protection circuits are disabled when USB_NOLIM is set. The maximum steady-state current supported is 500mA; higher currents can only be supported for short term transients. USB power may be supplemented by battery power if available and if necessary to maintain the USB current within the applicable limit. If a suitable Wall (LINE) supply becomes available during USB operation, then this will be selected as the preferred power source. Note that, when hot-swapping from USB to Wall supply, a usable Battery must be present on the BATT pin. In USB low power mode, trickle charging is enabled by default. Trickle charging is suspended if necessary to keep within the 100mA USB limit. In USB high power mode, fast charging is possible (subject to other conditions - see Section 17.7.4). The fast charge current is controlled dynamically as necessary to keep the overall USB current within the 500mA limit. Note that Battery Charging from the USB source is only possible in USB Slave Mode. USB power may be suspended by writing to the USB_SUSPEND register bit. Setting this bit to ‘1’ disconnects the WM8351 from the USB supply, resulting in the selection of Battery as the power source. USB Suspend mode is invoked under software control, by writing to the USB_SUSPEND bit. Suspend mode should be invoked whenever the USB connection is not used. To comply with the USB 2.0 specification, the host processor should initially invoke USB Suspend mode after the WM8351 has successfully started up, and whenever the USB connection is not in use. If the USB connection is active and USB enumeration has been completed, the host processor may (but is not required to) switch the WM8351 into USB low-power mode or USB high-power mode. However, if wall adaptor power is available, it is recommended to remain in USB Suspend mode. w PD, February 2011, Rev 4.4 153 WM8351 Production Data ADDRESS BIT R4 (04h) System Control 2 14 USB_SUSPEND LABEL DEFAULT 0 Opens the USB switch 0 = USB enabled 1 = USB suspended The register bit defaults to 0, when a reset happens or LINE < UVLO or the system fail on boot due to the upper limit of the Hysteresis Comp not been met. DESCRIPTION 13 USB_MSTR 0 Set the chip to be a USB master 0 = Slave 1 = Master The register bit defaults to 0, when a reset happens or the USB state machine moves from MASTER mode to SLAVE mode. 11 USB_MSTR_500MA 0 Set 500mA or 100mA mode when the USB switch is in master mode 0 = 100mA 1 = 500mA 9 USB_SLV_500MA Dependant on CONFIG settings Set 500mA or 100mA mode when the USB switch is in slave mode 0 = 100mA 1 = 500mA The register bit defaults to 0, when a reset happens or LINE