CM-2

CS1810xx, CS4961xx, & CM-2 Digital Audio Networking Processor CobraNet Silicon Series Version 2.3 ™ CS18100x, CS18101x, CS18102x, and CM-2 CS49610x, CS49611x, a nd C S49612x Hardware U ser’s M anual Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. ©Copyright 2005 Cirrus Logic, Inc. JUN ’05 DS651UM23 CobraNet Hardware User’s Manual Table of Contents Table of Contents List of Figures......................................................................................................................................... 4 1.0 .Introduction ..................................................................................................................................... 5 2.0 Features ........................................................................................................................................... 6 2.1 CobraNet............................................................................................................................. 6 2.2 CobraNet Interface.............................................................................................................. 6 2.3 Host Interface...................................................................................................................... 7 2.4 Asynchronous Serial Interface ............................................................................................ 7 2.5 Synchronous Serial Audio Interface.................................................................................... 7 2.6 Audio Clock Interface .......................................................................................................... 7 2.7 Audio Routing and Processing............................................................................................ 7 3.0 Hardware.......................................................................................................................................... 8 4.0 Pinout and Signal Descriptions ........................................................................................................ 9 4.1 CS1810xx & CS4961xx Package Pinouts......................................................................... 10 4.1.1 CS1810xx/CS4961xx Pinout............................................................................. 10 4.1.2 CM-2 Connector Pinout..................................................................................... 11 4.2 Signal Descriptions ...........................................................................................................12 4.2.1 Host Port Signals ..............................................................................................12 4.2.2 Asynchronous Serial Port (UART Bridge) Signals ............................................ 12 4.2.3 Synchronous Serial (Audio) Signals.................................................................. 13 4.2.4 Audio Clock Signals .......................................................................................... 13 4.2.5 Miscellaneous Signals....................................................................................... 14 4.2.6 Power and Ground Signals ............................................................................... 14 4.2.7 System Signals ................................................................................................. 15 4.3 Characteristics and Specifications .................................................................................... 16 4.3.1 Absolute Maximum Ratings .............................................................................. 16 4.3.2 Recommended Operating Conditions ............................................................... 16 4.3.3 Digital DC Characteristics ................................................................................. 16 4.3.4 Power Supply Characteristics ........................................................................... 16 5.0 Synchronization.............................................................................................................................. 17 5.1 Synchronization Modes..................................................................................................... 17 5.1.1 Internal Mode .................................................................................................... 18 5.1.2 External Word Clock Mode ............................................................................... 18 5.1.3 External Master Clock Mode ............................................................................. 18 6.0 Digital Audio Interface .................................................................................................................... 19 6.1 Digital Audio Interface Timing ........................................................................................... 20 6.1.1 Normal Mode Data Timing ................................................................................ 21 6.1.2 I2S Mode Data Timing....................................................................................... 21 6.1.3 Standard Mode Data Timing ............................................................................. 22 7.0 Host Management Interface (HMI)................................................................................................. 23 7.1 Hardware........................................................................................................................... 23 7.4 Protocol and Messages..................................................................................................... 28 7.4.1 Messages.......................................................................................................... 28 7.4.1.1. Translate Address ................................................................................. 29 7.4.1.2. Interrupt Acknowledge........................................................................... 29 7.4.1.3. Goto Packet........................................................................................... 29 7.4.1.4. Goto Translation .................................................................................... 29 7.4.1.5. Packet Received ................................................................................... 30 7.4.1.6. Packet Transmit .................................................................................... 30 7.4.1.7. Goto Counters ....................................................................................... 30 7.4.2 Status ................................................................................................................ 31 2 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User’s Manual Table of Contents 7.4.3 Data................................................................................................................... 32 7.4.3.1. Region length ........................................................................................ 32 7.4.3.2. Writable Region ..................................................................................... 32 7.4.3.3. Translation Complete ............................................................................ 32 7.4.3.4. Packet Transmission Complete............................................................. 32 7.4.3.5. Received Packet Available .................................................................... 32 7.4.3.6. Message Togglebit ................................................................................ 32 8.0 HMI Reference Code ..................................................................................................................... 33 8.1 HMI Definitions.................................................................................................................. 33 8.2 HMI Access Code ............................................................................................................. 34 8.3 CM-1, CM-2 Auto-detection ..............................................................................................36 9.0 Mechanical Drawings and Schematics .......................................................................................... 37 9.1 CM-2 Mechanical Drawings ..............................................................................................38 9.2 CM-2 Schematics.............................................................................................................. 44 9.3 CS1810xx/CS4961xx Package ......................................................................................... 51 9.4 Temperature Specifications ..............................................................................................52 10.0 Ordering Information .................................................................................................................... 53 10.1 Device Part Numbers ...................................................................................................... 53 10.2 Device Part Numbering Scheme..................................................................................... 53 DS651UM23 Version 2.3 ©Copyright 2005 Cirrus Logic, Inc. 3 CobraNet Hardware User’s Manual List of Figures List of Figures Figure 1. CobraNet Data Services ......................................................................................................... 5 Figure 2. CobraNet Interface Hardware Block Diagram......................................................................... 8 Figure 3. Audio Clock Sub-system....................................................................................................... 17 Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) CS18100x/CS49610x & CS18101x/CS49611x ............................................................ 19 Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) CS18102x/CS49612x ................................................................................................... 19 Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1..................................... 20 Figure 7. Serial Port Data Timing Overview......................................................................................... 20 Figure 8. Audio Data Timing Detail - Normal Mode, 64FS CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 21 Figure 9. Audio Data Timing Detail - Normal Mode, 128FS CS18102x/CS49612x ................................................................................................... 21 Figure 10. Audio Data Timing Detail - I2S Mode, 64FS CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 21 Figure 11. Audio Data Timing Detail - I2S Mode, 128FS CS18102x & CS49612x................................................................................................ 21 Figure 12. Audio Data Timing Detail - Standard Mode, 64FS CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 22 Figure 13. Audio Data Timing Detail - Standard Mode, 128FS CS18102x/CS49612x ................................................................................................... 22 Figure 14. Host Port Read Cycle Timing - Motorola Mode .................................................................. 25 Figure 15. Host Port Write Cycle Timing - Motorola Mode................................................................... 25 Figure 16. Parallal Control Port - Intel Mode Read Cycle .................................................................... 27 Figure 17. Parallel Control Port - Intel Mode Write Cycle .................................................................... 27 Figure 18. CM-2 Module Assembly Drawing, Top ............................................................................... 38 Figure 19. CM-2 Module Assembly Drawing, Bottom .......................................................................... 39 Figure 20. General PCB Dimensions ................................................................................................... 40 Figure 21. Example Configuration, Side View...................................................................................... 41 Figure 22. Faceplate Dimensions ........................................................................................................ 42 Figure 23. Connector Detail ................................................................................................................. 43 Figure 24. CM-2 RevF Schematic Page 1 of 7 .................................................................................... 44 Figure 25. CM-2 RevF Schematic Page 2 of 7 .................................................................................... 45 Figure 26. CM-2 RevF Schematic Page 3 of 7 .................................................................................... 46 Figure 27. CM-2 RevF Schematic Page 4 of 7 .................................................................................... 47 Figure 28. CM-2 RevF Schematic Page 5 of 7 .................................................................................... 48 Figure 29. CM-2 RevF Schematic Page 6 of 7 .................................................................................... 49 Figure 30. CM-2 RevF Schematic Page 7 of 7 .................................................................................... 50 Figure 31. 144-Pin LQFP Package Drawing ........................................................................................ 51 Figure 32. Device Part Numbering Explanation ................................................................................... 53 4 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User’s Manual Introduction 1.0 Introduction This document is intended to help hardware designers integrate the CobraNetTM interface into an audio system design. It covers the CS18100x, CS18101x, CS18102x, CS49610x, CS49611x, and CS49612x members of the CobraNetTM Silicon Series of devices, where “x” is the ROM version (ROM ID). This document also describes the CM-2 module with schematics, mechanical drawings, etc. CobraNet is a combination of hardware (the CobraNet interface), network protocol, and firmware. CobraNet operates on a switched Ethernet network and provides the following additional communications services. • Isochronous (Audio) Data Transport • Sample Clock Distribution • Control and Monitoring Data Transport The CobraNet interface performs synchronous-to-isochronous and isochronous-tosynchronous conversions as well as the data formatting required for transporting real-time digital audio over the network. The CobraNet interface has provisions for carrying and utilizing control and monitoring data such as Simple Network Management Protocol (SNMP) through the same network connection as the audio. Standard data transport capabilities of Ethernet are shown here as unregulated traffic. Since CobraNet is Ethernet based, in most cases, data communications and CobraNet applications can coexist on the same physical network. Figure 1 illustrates the different data services available through the CobraNet system. Isochronous Data Isochronous Data (Audio) (Audio) Ethernet Ethernet Unregulated Unregulated Traffic Traffic Control Data Control Data Clock Clock Figure 1. CobraNet Data Services DS651UM23 Version 2.3 ©Copyright 2005 Cirrus Logic, Inc. 5 CobraNet Hardware User’s Manual Features 2.0 Features 2.1 CobraNet • Real-time Digital Audio Distribution via Ethernet • No Overall Limit on Network Channel Capacity • Fully IEEE 802.3 Ethernet Standards Compliant • Fiber optic and gigabit Ethernet variants are fully supported. • Ethernet infrastructure can be used simultaneously for audio and data communications. • Free CobraCAD™ Audio Network Design Tool • High-quality Audio Sample Clock Delivery Over Ethernet • Bit-transparent 16-, 20-, and 24-bit Audio Transport • Professional 48-kHz and 96-kHz sample rate • Select Latency as Low as 1.33ms • Flexible Many-to-many Network Audio Routing Capabilities • Reduced-cost, Improved-performance, Convergent Audio Distribution Infrastructure 2.2 CobraNet Interface • 120 MIPS Customer-configurable Audio DSP • Auto-negotiating 100Mbit Full-duplex Ethernet Connections • Up to 32-channel Audio I/O Capability • Implements CobraNet Protocol for real-time transport of audio over Ethernet. • Local Management via 8-bit Parallel Host Port • UDP/IP Network Stack with Dynamic IP Address Assignment via BOOTP or RARP • Remote Management via Simple Network Management Protocol (SNMP) • Economical Three-chip Solution • Available Module form factor allows for flexible integration into audio products. • Non-volatile Storage of Configuration Parameters • Safely Upgrade Firmware Over Ethernet Connection • LED Indicators for Ethernet Link, Activity, Port Selection, and Conductor Status • Watchdog Timer Output for System Integrity Assurance • Comprehensive Power-on Self-test (POST) • Error and Fault Reporting and Logging Mechanisms 6 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User’s Manual Features 2.3 Host Interface • 8-bit Data, 4-bit Address • Virtual 24-bit Addressing with 32-bit Data • Polled, Interrupt, and DMA Modes of Operation • Configure and Monitor CobraNet Interface • Transmit or Receive Ethernet Packets at Near-100-Mbit Wire Speed 2.4 Asynchronous Serial Interface • Full-duplex Capable • 8-bit Data Format • Supports all Standard Baud Rates 2.5 Synchronous Serial Audio Interface • Up to Four Bi-directional Interfaces Supporting up to 32 Channels of Audio I/O • 64FS (3.072 MHz) Bit Rate for CS18100x/CS49610x and CS18101x/ CS49611x • 128FS (6.144 MHz) Bit Rate for CS18102x/CS49612x • Accommodates Many Synchronous Serial Formats Including I2S • 32-bit Data Resolution on All Audio I/O 2.6 Audio Clock Interface • 5 Host Audio-clocking Modes for Maximum Flexibility in Digital Audio Interface Design • Low-jitter Master Audio Clock Oscillator (24.576 MHz) • Synchronize to Supplied Master and/or Sample Clock • Sophisticated jitter attenuation assures network perturbations do not affect audio performance. 2.7 Audio Routing and Processing • Single-channel Granularity in Routing From Synchronous Serial Audio Interface to CobraNet Network • Two levels of inward audio routing affords flexibility in audio I/O interface design in the host system. • Local Audio Loopback and Output Duplication Capability • Peak-read Audio Metering with Ballistics DS651UM23 Version 2.3 ©Copyright 2005 Cirrus Logic, Inc. 7 CobraNet Hardware User’s Manual Hardware 3.0 Hardware Figure 2 shows a high-level view of the CobraNet CM-2 interface hardware architecture. Clock VCXO Control Clock Flash Memory CobraNet CM-2 Module Audio Serial Host CS1810xx/ CS4961xx Ethernet Controller Ethernet Magnetics Figure 2. CobraNet Interface Hardware Block Diagram Flash memory holds the CobraNet firmware and management interface variable settings. The CS1810xx or CS4961xx network processor is the heart of the CobraNet interface. It implements the network protocol stacks and performs the synchronous-to-isochronous and isochronous-to-synchronous conversions. The network processor has a role in sample clock regeneration and performs all interactions with the host system. The sample clock is generated by a voltage-controlled crystal oscillator (VCXO) controlled by the network processor. The VCXO frequency is carefully adjusted to achieve lock with the network clock. The Ethernet controller is a standard interface chip that implements the 100-Mbit Fast Ethernet standard. As per Ethernet requirements the interface is transformer isolated. 8 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.0 Pinout and Signal Descriptions This section details the chip pinout and signal interfaces for each module and is divided as follows: • "CS1810xx & CS4961xx Package Pinouts" on page 10 • "Host Port Signals" on page 12 • "Asynchronous Serial Port (UART Bridge) Signals" on page 12 • "Synchronous Serial (Audio) Signals" on page 13 • "Audio Clock Signals" on page 13 • "Miscellaneous Signals" on page 14 • "Power and Ground Signals" on page 14 • "System Signals" on page 15 DS651UM23 Version 2.3 ©Copyright 2005 Cirrus Logic, Inc. 9 CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.1 CS1810xx & CS4961xx Package Pinouts 4.1.1 CS1810xx/CS4961xx Pinout Table 1 lists the pinout for the 144-pin LQFP CS1810xx/CS4961xx device. The interfaces for these signals are expanded in the following sections. Table 1. CS1810xx/CS4961xx Pin Assignments Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name VCXO_CTRL MCLK_SEL DBDA DBCK NC NC NC DAO_MCLK TEST VDDD HS3 NC GND DAO2_LRCLK DAO1_DATA3 DAO1_DATA2/HS2 DAO1_DATA1/HS1 VDDIO DAO1_DATA0/HS0 DAO1_SCLK GND DAO1_LRCLK UART_TX_OE VDDD UART_TXD UART_RXD GND NC DATA7 DATA6 DATA5 DATA4 VDDIO DATA3 DATA2 GND Pin # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 WE Pin Name DATA1 Pin # 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin Name VDDIO ADDR10 ADDR14 GND ADDR13 NC NC NC NC ADDR15 VDDD ADDR16 ADDR17 GND ADDR18 ADDR19 OE CS1 VDDIO MUTE HRESET GND WATCHDOG IOWAIT REFCLK_IN VDDD GPIO0 GPIO1 GND HACK HDS HEN HADDR3 HADDR2 HR/W GPIO2 Pin # 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin Name HADDR1 HADDR0 HDATA7 HDATA6 VDDIO HDATA5 HDATA4 GND HDATA3 HDATA2 VDDD HDATA1 HDATA0 GND XTAL_OUT XTO XTI GND_a FILT2 FILT1 VDDA VDDD DAI1_DATA3 DAI1_DATA2 GND DAI1_DATA1 DAI1_DATA0 VDDIO DAI1_SCLK DAI1_LRCLK GND HREQ NC NC IRQ1 IRQ2 DATA0 DATA15 DATA14 DATA13 DATA12 VDDIO DATA11 DATA10 GND DATA9 DATA8 NC NC NC NC VDDD ADDR12 ADDR11 GND ADDR9 ADDR8 VDDIO ADDR7 ADDR6 GND ADDR5 CS2 VDDD ADDR4 ADDR3 GND ADDR2 ADDR1 ADDR0 10 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.1.2 CM-2 Connector Pinout Table 1 lists the pinout for the four pinout connectors on the CM-2 board (J1-J4). The interfaces for these signals are expanded following the table. Table 2. CM-2 Pin Assignments Conn. J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 Pin Name UART_RXD UART_TX_OE HACK HR/W HDS HREQ HEN HADDR0 HADDR1 HADDR2 HDATA0 HDATA1 HDATA2 HDATA3 HDATA4 HDATA5 HDATA6 HRESET HDATA7 HADDR3 UART_TXD GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V Conn. J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 Pin # B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND Pin Name VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V RSVD1 GND VCC_+3.3V RSVD2 MUTE FS1 MCLK_OUT MCLK_IN REFCLK_IN DAO1_SCLK/DAI1_SCLK DAO1_DATA0 DAO1_DATA1 DAO1_DATA2 DAO1_DATA3 DAI1_DATA0 DAI1_DATA1 DAI1_DATA2 Conn. J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 Pin # A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 Pin Name DAI1_DATA3 RSVD3 WATCHDOG RSVD4 AUX_POWER2 AUX_POWER0 GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND GND VCC_+5V VCC_+5V AUX_POWER3 AUX_POWER1 DS651UM23 Version 2.3 ©Copyright 2005 Cirrus Logic, Inc. 11 CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.2 Signal Descriptions 4.2.1 Host Port Signals The host port is used to manage and monitor the CobraNet interface. Electrical operation and protocol is detailed in the "Host Management Interface (HMI)" on page 23 of this Manual. The host port can operate in two modes in order to accomodate Motorola® or Intel® style interfaces. The default mode is Motorola. Intel mode is set via a firmware modification. Table 2-1: Host Port Signals Signal Description Direction CM-2 Pin # J1:A19, A[17:11] J1:A20, A[10:8] J1:A4 J1:A4 J1:A6 J1:A3 J1:A5 J1:A5 J1:A7 J1:A7 CS1810xx/ CS4961xx Pin # 111, 112, 114, 115, 117, 118, 102, 121 105, 106, 109,110 107 107 140 102 103 103 104 104 Host port data. Notes HDATA[7:0] Host Data In/Out HADDR[3:0] HRW HRD HREQ HACK HDS HWR HEN HCS Host Address Host Direction Host Read Host Request Host Alert Host Strobe Host Write Host Enable Select In In In Out Out In In In In Host port address. Host port transfer direction (Motorola mode). Host Read (Intel mode). Host port data request. Host port interrupt request. Host port strobe (Motorola mode). Host Write (Intel mode). Host Port Enable. Select (Intel mode). 4.2.2 Asynchronous Serial Port (UART Bridge) Signals Level-shifting drive circuits are typically required between these signals and any external connections. Signal UART_RXD UART_TXD UART_TX_OE Description Asynchronous Serial Receive Data Asynchronous Serial Transmit Data Transmit Drive Enable Direction In Out Out CM-2 Pin # J1:A1 J1:B1 J1:A2 CS1810xx/ CS4961xx Pin # 26 25 23 Notes Pull-up to VCC if unused. Enable transmit (active high) drive for two wire multi-drop interface. 12 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.2.3 Synchronous Serial (Audio) Signals The synchronous serial interfaces are used to bring digital audio into and out of the system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing and format is described in "Digital Audio Interface" on page 19. CM-2 Pin # CS1810xx/ CS4961xx Pin # Signal Description Direction Notes Synchronous serial bit clock. 64 FS for CS18100x & CS49610x (2x1 channel) 64 FS for CS18101x & CS49611x (2x4 channels) 128 FS for CS18102x & CS49612x (4x4 channels) Typically tied to DAI1_SCLK. Output synchronous serial audio data DAO1_DATA[3:1] not used for CS18100x & CS49610x. DAO1_SCLK Audio Bit Clock Out J3:A7 20 DAO1_DATA[3:0] Audio Output Data Out J3:A18, B18 15-17, 19 DAI1_DATA[3:0] Audio Input Data In Input synchronous serial audio data J3: 131, 132, 134, 135 DAI1_DATA[3:1] not used for CS18100x & A[15:12] CS49610x. J4:A7 137 Should be tied to DAO1_SCLK. Synchronous serial bit clock. DAI1_SCLK Audio Bit Clock In 4.2.4 Audio Clock Signals See "Synchronization" on page 17 for an overview of synchronization modes and issues. CM-2 Pin # CS1810xx/ CS4961xx Pin # 138 J3:A3 J3:A3 22 14 Signal DAI1_LRCLK DAO1_LRCLK (FS1) DAO2_LRCLK (FS1) Description Sample clock input Sample clock output Sample clock output Direction In Out Out Notes Should be tied to DAO1_LRCLK for all devices. FS1 (word clock) for CS18100x/CS49610x and CS18101x/CS49611x. FS1 (word clock) for CS18102x & CS49612x. Clock input for synchronizing network to an external clock source, for redundancy control and synchronization of FS divider chain to external source. See "Synchronization" on page 17 for more detail. For systems featuring multiple CobraNet interfaces operating off a common master clock. See "Synchronization" on page 17 for more detail. Low jitter 24.576 MHz master audio clock. REFCLK_IN Reference clock In J3:A6 97 MCLK_IN Master audio clock input Master audio clock output In J3:A5 8* MCLK_OUT Out J3:A4 8* *An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out implementation. DS651UM23 Version 2.3 ©Copyright 2005 Cirrus Logic, Inc. 13 CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.2.5 Miscellaneous Signals Signal HRESET Description Reset Direction In CM-2 Pin # J1:A18 CS1810xx/ CS4961xx Pin # 93 Notes System reset (active low). 10 ns max rise time. 1 ms min assertion time. Toggles at 750 Hz nominal rate to indicate proper operation. Period duration in excess of 200 ms indicates hardware or software failure has occurred and the interface should be reset. Note that improper operation can also be indicated by short pulses (> 16; MSG_B = ( address & 0xff00 ) >> 8; MSG_C = address & 0xff; MSG_D = CVR_TRANSLATE_ADDRESS; while( !( ( msgack ^ MSG_D ) & ( 1