CRD42528

CRD42528 Reference Design for the CS49300 and CS42528 Features Supports 4 digital S/PDIF (IEC60958/IEC61937) inputs 8 Discrete analog inputs using the CS42528 + 3 external CS5351 ADCs for 8 analog channels of input at 48 kHz and 96 kHz 2 Channel upsampling supported 8 Discrete analog outputs from the CS42528 2 Digital S/PDIF (IEC60958/IEC61937) outputs using the CS42528 Mux and XMT958 transmitter on the CS49300 On board SRAM for AAC 5.1 discrete channel decoding In system programmable Flash, capable of holding 16 DSP programs Description The CRD42528 is a reference design for the CS49300 DSP family and the CS42528 CODEC. It supports up to 8 channels of analog input at 48 and 96 kHz, or 2 channels of analog input at 192 kHz. One of four digital S/PDIF inputs may be selected. Additionally, up to 2 channels of digital S/PDIF output and 8 channels of analog output at up to 192 kHz are supported. The on board SRAM is included to allow for AAC 5.1 discrete channel decoding, and on-board flash memory is included to allow in-system programming of up to 16 DSP images. The DSP supports the following algorithms, including (but not limited to) AAC, Dolby Digital (AC-3), Dolby Digital EX, DTS, DTS-ES, DTS Neo:6, Cirrus Original Surround (including COS 6.1), SRS CircleSurround, SRS TruSurround, Pro Logic II, MPEG Multichannel (including EX), and HDCD. The control interface to the CRD42528 is the UDSP System Platform. All control and data I/O is connected to headers, which allows the CRD42528 to be used easily in a end system or as a reference design. A larger block diagram is shown on the next page. ORDERING INFORMATION CRD42528 Reference Design RXP0 RXP1 CS42528 AOUT1 AOUT2 L R 4x SPDIF L R CS5351 RXP2 RXP3 AIN SAI CDI CS493XX-IBA (or CS492XX) AUDATA0 AUDATA1 CX_SDIN1 AOUT3 AOUT4 Ls Rs Ls Rs 8x ANALOG C Sub SBL SBR AIN SDOUT CX_SDIN2 CX_SDIN3 Ext ADC In CS5351 SDOUT AIN DAI CS5351 SDOUT AIN External SRAM/Flash EMAD AOUT5 AOUT6 C Sub SBL / Lt SBR / Rt AUDATA2 AOUT7 AUDATA3 CX_SDIN4 AOUT8 IEC60958 Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Logic, Inc. 2003 (All Rights Reserved) MAY’ 03 DS586RD2 1 RXP0 RXP1 CS42528 AOUT1 AOUT2 L R 4x SPDIF L R CS5351 RXP2 RXP3 AIN SAI CDI CS493XX-IBA (or CS492XX) AUDATA0 AUDATA1 CX_SDIN1 AOUT3 AOUT4 Ls Rs Ls Rs 8x ANALOG C Sub SBL SBR AIN SDOUT CX_SDIN2 CX_SDIN3 Ext ADC In CS5351 SDOUT AIN DAI CS5351 SDOUT AIN External SRAM/Flash EMAD AOUT5 AOUT6 C Sub SBL / Lt SBR / Rt AUDATA2 AOUT7 AUDATA3 CX_SDIN4 AOUT8 IEC60958 Figure 1. Block Diagram of the CRD42528 2 TABLE OF CONTENTS 1. QUICK START................................................................................................. 5 2. DESIGN DESCRIPTION................................................................................. 7 2.1 Clock and Data Connections .............................................................................................. 7 2.1.1 Analog Input Mode................................................................................................. 7 2.1.2 Digital Input Mode .................................................................................................. 7 2.2 Control ................................................................................................................................ 7 2.3 Assembly Options for Ease of Manufacture ....................................................................... 8 2.3.1 Analog Input Options ............................................................................................. 8 2.3.2 Analog Output Options........................................................................................... 8 2.3.3 Memory Options..................................................................................................... 9 2.4 Revision A Errata................................................................................................................ 9 APPENDIX A: APPENDIX B: APPENDIX C: APPENDIX D: APPENDIX E: APPENDIX F: APPENDIX G: APPENDIX H: Installation of Board Control Software...................................................12 CRD42528.INI ........................................................................................13 Board Control Software ..........................................................................14 Schematics ..............................................................................................16 Layout Plots (Ground Plane Vias are Flooded).......................................29 Bill of Materials - CRD42528 .................................................................32 UDSP Schematics ...................................................................................37 Bill of Materials - UDSP.........................................................................46 LIST OF FIGURES Figure 1. Block Diagram of the CRD42528 ..................................................................................... 2 Figure 2. Mute Control Rev A.......................................................................................................... 9 Figure 3. Mute Control - Corrected ................................................................................................. 9 Figure 4. Data and Clock Connections for 8 Channel Analog Input and Output ........................... 10 Contacting Cirrus Logic Support F o r a ll pro du ct qu estio ns a nd in qu iries con tact a C irrus L og ic S ales R e pre se ntative . To find one nearest you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this doc ument is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or i mplied). 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CERTAIN APPLICATIONS USING SEM ICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONM ENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTO MER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTIO N WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product namesin this docum ent may be trademarks or service marks of their respective owners. I2 C is a registered trademark of Philips Semiconductor. Purchase of I2 C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I 2 C Patent Rights to use those components in a standard I 2 C system. 3 Figure 5. Clock and Data Connections for S/PDIF (IEC61937 / IEC60958) Input ........................ 11 Figure 6. Control and Data I/O ...................................................................................................... 16 Figure 7. DSP................................................................................................................................ 17 Figure 8. External Memory ............................................................................................................ 18 Figure 9. CoDec ............................................................................................................................ 19 Figure 10. External A/D Converters .............................................................................................. 20 Figure 11. L/R Input Filters............................................................................................................ 21 Figure 12. Ls/Rs Input Filters ........................................................................................................ 22 Figure 13. C/Sub Input Filters ....................................................................................................... 23 Figure 14. SBL/SBR Input Filters .................................................................................................. 24 Figure 15. L/R Output Filters ......................................................................................................... 25 Figure 16. Ls/Rs Output Filters ..................................................................................................... 26 Figure 17. C/Sub Output Filters..................................................................................................... 27 Figure 18. SBL/SBR Output Filters ............................................................................................... 28 Figure 19. Top Layer ..................................................................................................................... 29 Figure 20. Bottom Layer................................................................................................................ 30 Figure 21. Assembly Drawing ....................................................................................................... 31 Figure 22. UDSP - Top .................................................................................................................. 37 Figure 23. UDSP - Digital Audio Port ............................................................................................ 38 Figure 24. UDSP - Headphone Amplifier ...................................................................................... 39 Figure 25. UDSP - Microcontroller ................................................................................................ 40 Figure 26. UDSP - Power.............................................................................................................. 41 Figure 27. UDSP - Parellel Port Interface ..................................................................................... 42 Figure 28. UDSP - RS232 Interface .............................................................................................. 43 Figure 29. UDSP - RS422 Interface .............................................................................................. 44 Figure 30. UDSP - S/PDIF I/O....................................................................................................... 45 LIST OF TABLES Table 1. Communication Mode Options .......................................................................................... 8 Table 2. Analog Input Assembly Options ........................................................................................ 8 Table 3. Analog Output Assembly Options ..................................................................................... 8 4 1. QUICK START A PC with an ECP parallel port, a stereo analog audio source, and powered speakers are required to use the CRD42528 in the mode specified in this Quick Start. 1) Install the drivers supplied with the board on the PC. Refer to “UDSP Schematics” on page 37 for details on installing the drivers. 2) Connect the supplied parallel port cable to J46 on the UDSP MainBoard (marked P PORT) and to the computer’s ECP parallel port. 3) Connect the analog output from an audio source to AIO7-8 (Left and Right Inputs) The input channels are mapped as follows: AIO8 - Left AIO7 - Right AIO6 - Left Surround AIO5 - Right Surround AIO4 - Center AIO3 - Subwoofer / Low Frequency Effects (LFE) AIO2 - Surround Back Left AIO1 - Surround Back Right 5) Connect the supplied power supply to the power connector on the board and to an appropriate power outlet. 6) Verify that LEDs D1, D7, D9, and D11 on the UDSP board are lit. LED D2 will flash to indicate that the PLD on the UDSP is functional. 7) Open a DOS window and navigate to the C:\CS49300\CRD42528\Configs directory. 8) Type in “setpld -r 99” on the DOS prompt. (This reads the PLD version register and verifies that the PC can communicate with the board). If the driver generates the error message “!!! Board does not appear to be connected !!!”, then your parallel port address may not be 0x378 or your port is not ECP capable. If your parallel port address is not 0x378, depress the reset switch S3 and type in “setpld -r 99 -p3bc” or “setpld -r 99 -p278” to communicate using a different parallel port address. 9) Verify that LED D1 (marked ERR) has turned OFF, indicating that the driver has successfully communicated with the board. 10) If the above steps give an error, refer to “UDSP Schematics” on page 37 and verify that the drivers and PC have been set up as described (and that the parallel port address is correct / set to ECP mode). 11) If the above steps give the expected results, t y p e in “an alo g _ in_ 9 6 kH z”, “an alo g _in_ 9 6k H z p 3b c”, or “analog_in_96kHz -p278” (depending on your parallel port address) at the DOS prompt. This batch file will configure the PLD, boot the DSP, and configure the CS42528 for 8 channel analog processing at 96 kHz. 12) The audio data on the Left and Right Input connectors (AIO7-8) should now be heard on the output. 13) The batch files use various files to configure the software, board, and the DSP code. Each batch 5 4) Connect powered speakers to AIO15-16. The output channels are mapped as follows (more speakers can be connected to the line level outputs as required by each application): AIO16 - Left AIO15 - Right AIO14 - Left Surround AIO13 - Right Surround AIO12 - Center AIO11 - Subwoofer or Low Frequency Effects (LFE) AIO10 - Surround Back Left or Lt AIO9 - Surround Back Right or Rt file has been commented. Various batch files for the commonly used applications have been supplied with the software. These batch files can be run from the DOS prompt like the “analog_in_96kHz.bat” file. Please note that while only license-free code is supplied with the CRD42528, a complete list of algorithms supported by the CRD42528 (including Dolby Digital EX and DTS-ES) is available from your local Cirrus Logic, Inc. Field Applications Engineer. Caution:Use caution while editing and making changes to these files (editing a copy will always insure an easily accessible backup). It is strongly recommended that jumpers and switches on the UDSP MainBoard be left in their default positions. 6 2. DESIGN DESCRIPTION 2.1 Clock and Data Connections There are 2 main modes of operation of the CRD42528, Analog Input Mode and Digital Input Mode. In Analog Input Mode, up to 8 channels of analog input can be processed by the DSP. In Digital Input Mode, S/PDIF (IEC61937/IEC60958) data is sent to the DSP for decoding or processing. In both cases, the output from the DSP is sent back to the CS42528 to generate analog output. cations use a single mono surround channel, referred to as Surround Back (SB). The digital output from the CS5351 is sent directly to the DSP’s DAI port. Once the DSP has processed the incoming digital inputs, data is returned to the CS42528 to be converted back to analog. The data, coming from the DSP’s DAO port, is clocked by the CS42528’s CX port clocks. 2.1.2 Digital Input Mode A detailed diagram of the clock and data connections for analog input mode can be found in Figure 5, “Clock and Data Connections for S/PDIF (IEC61937 / IEC60958) Input,” on page 11. To process incoming S/PDIF (IEC61937/IEC60958) data streams, digital input is wired directly from the UDSP’s optical receivers to the CS42528. The CS42528 will then lock to the incoming stream and convert it to an I2S data stream, which is then sent to the DSP from the CS42528’s SAI port. This data is input on the DSP’s CDI port. The DSP will process this stream (i.e., decode the compressed stream or process the PCM data), and then send up to 8 channels of I2S data to the CS42528 on it’s DAO port. This PCM data is input on the CS42528’s CX port. The CS42528 then converts the audio data back to analog. 2.1.1 Analog Input Mode A detailed diagram of the clock and data connections for analog input mode can be found in Figure 4, “Data and Clock Connections for 8 Channel Analog Input and Output,” on page 10. When Analog Input Mode is used, the CRD42528 will process up to 8 channels of analog input. The analog source is the analog I/O connectors on the UDSP MainBoard, which are routed directly to the CRD42528. The Left (L) and Right (R) analog inputs are connected, via input filters, to the CS42528’s analog input pins. When 6 channel (referred to as 5.1 channel) input is desired, two external CS5351 Analog to Digital Converters are used. These external ADCs receive the RMCK output from the CS42528. In this mode, RMCK will pass through the 12.288 MHz oscillator connected to OMCK. The external ADC serial ports are driven from the CS42528’s CX port clocks. The Left Surround (Ls), Right Surround (Rs), Center (C), and Subwoofer (Sub) inputs to the CRD42528 are connected to the external CS5351’s analog inputs, and the digital outputs from the two external CS5351s is then connected to the CS42528’s ADCIN1/2 pins. The CS42528 will incorporate all of the data from the external ADCs and it’s own analog input data onto a single line and send it to the DSP via the CS42528’s SAI port. In this way, the DSP gets the L, R, Ls, Rs, C, and Sub channels into it’s CDI port. For 7 or 8 channel (6.1 or 7.1 channel) operation, another external CS5351 is used to convert the Surround Back Left (SBL) and Surround Back Right (SBR) analog inputs. Please note that many appli- 2.2 Control Control of the CRD42528 is done via the UDSP headers (J2 and J3) in either SPI or I2C mode. Different resistors must be populated or not populated according to the desired communication mode. These options can be found in Table 1. For I2C mode, please note that the DSP defaults to address checking disabled. This can only be changed after a firmware image has been loaded onto the DSP (either via host boot or autoboot). Please see the CS49300 datasheet for more details on I2C address checking. 7 Mode SPI Populate R98, R99, R10, R12, R16, R143 R13, R14, R18, R100, R144,R168, R166 Do Not Populate R13, R14, R18, R100, R144,R168, R166 R98, R99, R10, R12, R16, R143 Number of Analog Input Channels 2 (L, R) Populate R148, R149, R150 Do Not Populate U18, U33, U2, Ls, Rs, C, Sub, SBL and SBR Input Filters I2C 6 (L, R, Ls, Rs, C, Sub) R150, U18, U33, R148, R149, U2, Ls, Rs, C, Sub, SBL and SBR SBL and SBR Input Filters Input Filters U18, U33, U2, Ls, Rs, C, Sub, SBL and SBR Input Filters R148, R149, R150 Table 1. Communication Mode Options 2.3 Assembly Options for Ease of Manufacture There are variety of options available on a build of the CRD42528 that allow for different input and output options, as well as performance differentiation. This allows the same board to be used in both low-end and high-end applications. Please note that systems with lower performance may require external analog Bass Management circuitry to comply with Dolby specifications. 8 (L, R, Ls, Rs, C, Sub, SBL/Lz, SBR/Rz) Table 2. Analog Input Assembly Options 2.3.2 Analog Output Options The CRD42528 supports 2, 6, or 8 channels of analog output. A list of components that needs to be populated for each configuration is shown in Table 3. Number of Analog Output Channels 2 (L/Lt, R/Rt) 2.3.1 Analog Input Options The CRD42528 supports 2, 6, or 8 channels of analog input. A list of components that needs to be populated for each configuration is shown in Table 2. Populate Do Not Populate U27 = CS42516 Ls/Rs, C/Sub, SBL/SBR Output or CS42526, L/R Output Filters Filters U27 = CS42516 SBL/SBR Output or CS42526, Filters L/R, Ls/Rs, C/Sub Output Filters U27 = CS42518 or CS42528, L/R, Ls/Rs, C/Sub, SBL/SBR Output Filters 6 (L, R, Ls, Rs, C, Sub) 8 (L, R, Ls, Rs, C, Sub, SBL/Lz, SBR/Rz) Table 3. Analog Output Assembly Options 8 2.3.3 Memory Options There are many available applications that can run on the CS49300 family DSP. DSP applications require a 32k-byte page in an external ROM, Flash, or other non-volatile storage. Some applications, called Internal Boot Assisted (IBA) codes, consist of a few hundred bytes of download firmware. When using IBA codes ONLY, the external Flash or ROM may be omitted from the design IF AND ONLY IF the IBA codes are stored in the host microcontroller’s available non-volatile memory. In these applications, U24 and C132 may be omitted. For a full AAC 5.1 discrete channels of output, external SRAM must be used. For all other applications, the SRAM U16 and support component C133 may be omitted. Other options exist for AAC multichannel, including a stereo downmixed AAC output following by Dolby ProLogic II processor, which generates 5.1 channels of output. For a full list of codes (including IBA codes) and their requirements, please contact your local Cirrus Field Applications Engineer. as shown in Figure 2 should be modified as shown in Figure 3. Figure 2. Mute Control Rev A 2.4 Revision A Errata The revision A CRD42528 requires the following modification to the mute circuitry. The mute signal Figure 3. Mute Control - Corrected 9 ADC Data SBL / SBR Analog In CS5351 CX Clocks (at 64 Fs SCLK, LRCLK=Fs) and data Ls / Rs / C / Sub Analog In ADC Data CS5351 CX Clocks (at 64 Fs SCLK, LRCLK=Fs) and data CS49300 4 Channels CS42528 2 Channels DAI ADCIN SAI Clocks(CS42528) / CDI Clocks(CS49300) at 128 Fs SCLK, LRCLK=Fs SAI Port 6 Channels SAI Data(CS42528) / CDI Data(CS49300) CDI L / R Analog In AIN CX Clocks(CS42528) / DAI Clocks(CS49300) at 64 Fs SCLK, LRCLK=Fs CX Port 8 Channels CX Data DAO AOUT L / R / Ls / Rs / C / Sub / SBL / SBR Analog Out Analog Input / Output Digital Data Digital Serial Clocks (SCLK and LRCLK) Figure 4. Data and Clock Connections for 8 Channel Analog Input and Output 10 CS49300 CS42528 SAI Clocks(CS42528) / CDI Clocks(CS49300) at 128 Fs SCLK, LRCLK=Fs SAI Port 2 Channels or Compressed SAI Data(CS42528) / CDI Data(CS49300) CDI S/PDIF (IEC61937 / IEC60958) RXP CX Clocks(CS42528) / DAI Clocks(CS49300) at 64 Fs SCLK, LRCLK=Fs CX Port 8 Channels CX Data DAO AOUT L / R / Ls / Rs / C / Sub / SBL / SBR Analog Out Analog Input / Output Digital Data Digital Serial Clocks (SCLK and LRCLK) Figure 5. Clock and Data Connections for S/PDIF (IEC61937 / IEC60958) Input 11 APPENDIX A: INSTALLATION OF BOARD CONTROL SOFTWARE The UDSP PC driver utility set comes in two versions. The Direct Hardware version will communicate directly with the PC’s parallel port to control the UDSP board. The DLPortIO version uses the DLPortIO driver to access the parallel port on hardware protected operating systems. In general, direct hardware capable operating systems (such as Microsoft® Windows 95®, Windows 98®, and Windows ME®) allow any program to directly control any of the PC’s peripherals. With the UDSP board, this allows for faster interface speeds (up to 4 times faster). For protected operating systems (such as Microsoft® Windows NT®, Windows 2000®, and Windows XP®), the UDSP driver set requires the use of the DLPortIO driver. This utility allows the UDSP drivers to access the parallel port safely. The UDSP driver set requires bidirectional communication with the UDSP board, and hence a bidirectional capable parallel port is needed. An ECP-type port is required. Please note that an SPPtype port will not work with the UDSP board. The type and location (I/O address) of the parallel port installed can be found in the Windows Control Panel (please see Windows Help for more information on these settings). The UDSP drivers assume by default that the parallel port address is 0x378. Other ports may be used with the -pXXX option, where XXX is 3bc or 278. Installation on Microsoft® Windows 95®, 98®, ME® and other direct hardware capable Windows® versions 1. Run “Setup.exe” from the CRD42528 CD that was shipped with the kit. The UDSP drivers have now been successfully installed. The CRD42528 kit is now ready for use. Several demonstration batch files (*.bat) are available in the CRD42528\Configs directory. Please see the “Quick Start” on page 5 for information on the use of these batch files. Installation on Microsoft® Windows NT®, Windows 2000®, and Windows XP® and other protected Windows® versions 1.Run “Setup.exe” from the CRD42528 CD that was shipped with the kit. 2.Run “Port95nt.exe” from c:\udsp directory to install the DLPortIO driver to access the parallel port. The UDSP drivers have now been successfully installed. The CRD42528 kit is now ready for use. Several demonstration batch files (*.bat) are available in the CRD42528\Configs directory. Please see “Quick Start” on page5 for information on the use of these batch files. 12 APPENDIX B: CRD42528.INI # Horizontal Fields: # [part] [I2Caddr] [SPIaddr] [SPI CSn] # [reset(bit to drop in PLD addr 0x01)] # [INTREQ_NUM] [Print Format] #[Parallel word length] [Parallel CSn] #[Read_Type] # # Vertical Fields: #board - first non-comment, non-blank line #parts - other lines # note: reset can only take on values 01,02 # # Default is CS4930 interface # # INTREQ_NUM is the bit position within the INT register in the PLD # # Read_Type can be DSP or normal # # Word Length is in bytes # CRD42528 DSP 02 00 00 01 02 03 01 00 DSP 42528 9e 9e 02 02 ff 01 00 00 normal default 02 00 00 01 02 03 01 00 DSP 13 APPENDIX C: BOARD CONTROL SOFTWARE There is a suite of programs used to control the UDSP from a PC DOS command line. These software tools are designed to so that they can be scripted using the MS-DOS batch language. They will work with any of the 3 standard parallel port addresses (0x378, 0x3bc, 0x278). The default address for all of the programs is 0x378 (typically LPT1). The port address can be changed by using the '-p' option. Each time a program is executed, the address that was used can be shown on the screen using the ‘-v’ option. If a program seems to fail, verificatio n o f th e p arallel po rt ad dress sh ou ld alw ay s be the first step in trou blesho otin g. All of these programs are designed to access the daughter card connected to the UDSP board using SPI or I2C® serial communication. The communication mode can be chosen from the command line with the '-m' option. The mode chosen must correspond to the communication mode used by the devices on the daughter card. If the device on the board is set up for one communication mode, and the drivers are used with another, results will be unpredictable. All devices on the daughter card are configured for SPI serial communication mode by default, and that is also the default mode for the software. The usage of each program will vary, depending on the type of UDSP daughter card that is installed. The URST, URD, and UCMD programs get a valid list of devices for the installed daughter card from the file specified by the “uINI_path” DOS environment variable. This file will list all of the devices available to the UDSP parallel port drivers, along with each device’s I 2C address, SPI address, chip select number, and reset number (for reset capable devices). It also specifies how messages from the device should be read. For DSP-style reads, the driver will read until the INTREQ line goes high. For non-DSP devices, the read operation will read out 1 byte. Please note that most non-DSP devices require an aborted write operation to properly set the MAP pointer before reading. The device list file, called CRD42528.INI, must follow a very specific format. An example of this can be found “CRD42528.INI” on page 13. This file should not be changed. A list of available drivers and their usage is found below: UCMD.exe - Send commands or configuration files to a target device. Usage: ucmd [-dZZZZ..] [-mY] [-pWWW] [-v] -d = device ZZZZ.. = device designator, eg dspab, dspc, 8415a, etc. -m = communication mode Y = mode designator (i=I2C, s=SPI*, m=MOT, n=INT) ABCDEF.. = hex data (1-100 bytes) -f = send configuration file X = .cfg file containing configuration parameters -p = parallel port address WWW = address in hex (278, 378* or 3bc) -v = enable verbose mode * = default value Example: ucmd 000001 -d4341 -p3bc Notes: A configuration file is a list of commands, contained in an ASCII text file. This file can be any length, and should list the commands in hex, with an even number of characters per line. Comments can be made in the file by putting a # at the beginning of the line. The entire line will be interpreted as a comment. Please see the accompanying *.cfg files for examples of a configuration file. 14 URD.exe - Program used to read back responses from a target device. If a DSP-type device is selected and the INTREQ pin is not low when URD.exe is executed, the program will wait until INTREQ drops. Press the ‘Enter’ key to exit the read wait loop. Usage: urd [-dZZZZ..] [-mY] [-pXXX] [-v] [-h] -d = device ZZZZ = device designator, eg dspab, dspc, 8415a, etc. -m = communication mode Y = mode designator (i=I2C, s=SPI*, m=MOT, n=INT) -p = parallel port address XXX = address in hex (278, 378* or 3bc) -v = enable verbose mode -h = this message * = default value EXAMPLE: urd -d4940c -p378 Notes: If the associated INTREQ pin is not low when URD is executed, the program will wait until INTREQ drops for DSP devices ONLY. Press the ‘Enter’ key to exit the program in this case. URST.exe - Program used to perform hard reset or soft reset on the target device. Usage: urst [-dZZZZ..] [-mY] [-s] [-pXXX] [-v] [-h] -d = device ZZZZ = device designator, eg dspab, dspc, 8415a -m = communication mode Y = mode designator (i = I2C, s = SPI*, n = INTEL, m = MOTOROLA) -s = Soft Reset -p = parallel port address XXX = address in hex (278, 378* or 3bc) -v = enable verbose mode -h = this message * = default value SetPLD.exe - Program used to read and write PLD registers. Usage: setpld -r/-w RR [DD] Where -r is to read from register RR, -w is to write data DD into register RR. RR and DD are in hex. 15 16 APPENDIX D: SCHEMATICS Figure 6. Control and Data I/O Figure 7. DSP 17 18 Figure 8. External Memory Figure 9. CoDec 19 20 Figure 10. External A/D Converters Figure 11. L/R Input Filters 21 22 Figure 12. Ls/Rs Input Filters Figure 13. C/Sub Input Filters 23 24 Figure 14. SBL/SBR Input Filters Figure 15. L/R Output Filters 25 26 Figure 16. Ls/Rs Output Filters Figure 17. C/Sub Output Filters 27 28 Figure 18. SBL/SBR Output Filters APPENDIX E: LAYOUT PLOTS (GROUND PLANE VIAS ARE FLOODED) Figure 19. Top Layer 29 30 Figure 20. Bottom Layer Figure 21. Assembly Drawing 31 32 APPENDIX F: BILL OF MATERIALS - CRD42528 Item 1 Qty 20 Reference 5361A_SDAT 5361B_SDAT CX_LRCK CX_SCLK CX_SDIN1 CX_SDIN2 CX_SDIN3 CX_SDIN4 CX_SDOUT INT OMCK RMCK RST- SAI_LRCK SAI_SCLK SAI_SDOUT TP1 TP2 TP3 TP4 C1 C6 C34 C37 C44 C52 C54 C62 C63 C69 C71 C79 C85 C87 C103 C105 C2 C3 C8 C11 C12 C13 C14 C15 C19 C22 C24 C26 C27 C28 C31 C33 C38 C39 C45 C47 C48 C55 C58 C59 C64 C65 C80 C81 C95 C96 C97 C98 C99 C107 C109 C115 C119 C121 C122 C123 C131 C132 C133 C134 C141 C145 C146 C152 C159 C160 C181 C182 C183 C184 C185 C4 C41 C50 C60 C67 C75 C83 C91 C5 C42 C51 C61 C68 C76 C84 C92 C7 C49 C53 C70 C86 C102 C104 C106 C9 C40 C43 C57 C66 C74 C82 C90 C10 C25 C32 C35 C73 C118 Part Number 5002 Manufacturer KEYSTONE Description TESTPOINT, SINGLE POST Notes 2 16 ECE-V1CA220SR PANASONIC CAP, 22uF, ELEC, VS SERIES, SMT CASE-C, 16V, 20% CAP, 0.1UF, X7R, 0805, 50V, 10% 3 55 C0805C104K5RAC KEMET 4 5 6 7 8 8 8 8 8 6 C0805C182K5GAC C0805C122J5GAC C1206C562J5GAC C0805C391J5GAC ECE-V1CS100SR KEMET KEMET KEMET KEMET PANASONIC CAP, 1800PF, COG, 0805, 50V, 10% CAP, 1200pF, COG, 0805, 50V, 5% CAP, 5600PF, COG, 1206, 50V, 5% CAP, 390PF, COG, 0805, 50V, 5% CAP, 10uF, ELEC, VS SERIES, SMT CASE-A, 16V, 20% Item 9 10 11 12 13 Qty 1 1 1 10 1 C16 C17 C18 Reference Part Number C1206C225K8RAC C0805C221J5RAC C0805C103K5RAC C0805C471J5GAC ECE-VOJA470WR Manufacturer KEMET KEMET KEMET KEMET PANASONIC Description CAP, 2.2uF, X7R, 1206, 10V, 10%. CAP, 220PF, X7R, 0805, 50V, 5% CAP, 0.01UF, X7R, 0805, 50V, 10% CAP, 470PF, COG, 0805, 50V, 5% CAP, 47uF, ELEC, VA SERIES, SMT CASE-B, 6.3V, 20% CAP, 2700PF, COG, 0805, 50V, 5% CAP, 1uF, ELEC, VS SERIES, SMT CASE-A, 50V, 20% CAP, 47uF, ELEC, VA SERIES, SMT CASE-C, 10V, 20% CAP, 4.7uF, ELEC, VS SERIES, SMT CASE-B, 25V, 20% CAP, 8200PF, X7R, 0805, 50V, 5% CAP, 220PF, COG, 0805, 50V, 5% CAP, 100uF, ELEC, VS SERIES, SMT CASE-C, 10V, 20% STAKE HEADER, 16X2, 2MM PITCH Notes C20 C56 C72 C89 C111 C117 C126 C140 C147 C156 C21 14 15 8 6 C23 C88 C110 C116 C127 C139 C148 C155 C29 C30 C93 C94 C186 C187 C36 C46 C77 C100 C112 C114 C129 C135 C151 C153 C180 C78 C101 C149 C179 ECJ-2VC1H272J ECE-V1HS010SR PANASONIC PANASONIC 16 11 ECE-V1AA470WR PANASONIC 17 4 ECE-V1EA4R7SR PANASONIC 18 19 20 1 1 1 C108 C113 C142 C0805C822J5RAC C0805C221J5GAC ECE-V1AA101WR KEMET KEMET PANASONIC 21 33 1 J1 87089-3216 MOLEX Install on secondary side 34 Item 22 23 24 25 26 27 Qty 2 1 2 8 8 16 J2 J3 J4 L1 L2 Reference Part Number 87089-4016 87089-1417 BLM21P300 2SC3326 CRCW08052001F CRCW0805473J Manufacturer MOLEX MOLEX MURATA TOSHIBA DALE DALE Description STAKE HEADER, 20X2, 2MM PITCH STAKE HEADER, 7X2, 2MM PITCH FBEAD,0805,30100MHz,3AMPS TRANSISTOR, NPN, EPITAXIAL TYPE, SC59 RES, 2.00K, 0805, 1/10W, 1%. 100ppm RES, 47K, 0805, 1/10W, 5%, 200ppm RES, 560, 0805, 1/10W, 1%, 100ppm RES, 1.87K, 0805, 1/10W, 1%. 100ppm RES, 887 OHMS, 0805, 1/10W, 1%. 100ppm RES, 4.7K, 0805 1/8W, 5%, 200ppm RES, 634 OHMS, 0805, 1/10W, 1%. 100ppm RES, 3.3K, 0805, 1/10W, 5%, 200ppm RES, 0-OHM, 0805 Notes Install on secondary side Install on secondary side Q2 Q3 Q4 Q5 Q8 Q11 Q12 Q13 R1 R27 R38 R47 R56 R65 R74 R86 R2 R29 R31 R39 R48 R57 R66 R75 R87 R105 R114 R115 R124 R125 R134 R142 R3 R30 R40 R49 R58 R67 R79 R88 R4 R32 R41 R50 R59 R68 R80 R89 R5 R33 R42 R51 R60 R69 R81 R90 R6 R7 R8 R77 R103 R106 R113 R116 R123 R126 R133 R137 R138 R141 R9 R14 R98 R99 R100 R104 R130 R156 R157 R163 R165 R10 R12 R13 R16 R18 R22 R143 R144 R146 R147 R148 R149 R150 R160 R161 R166 R167 R168 28 29 30 31 32 8 8 8 2 12 CRCW08055600F CRCW08051871F CRCW08058870F CRCW0805472J CRCW08056340F DALE DALE DALE DALE DALE 33 34 11 18 CRCW0805332J CRCW0805000FT DALE DALE R14,R100 are not populated R13,R18,R144,R 146,R148,R149, R150,R160,R166 ,R168 are not populated Item 35 36 37 38 39 40 41 42 43 Qty 9 8 6 1 1 8 8 8 7 Reference R11 R145 R151 R152 R153 R158 R159 R162 R164 R15 R34 R43 R52 R61 R70 R82 R91 R17 R19 R20 R76 R129 R154 R21 R23 R24 R35 R44 R53 R62 R71 R83 R92 R25 R36 R45 R54 R63 R72 R84 R93 R26 R37 R46 R55 R64 R73 R85 R94 R28 R96 R97 R109 R110 R119 R120 R78 R102 R107 R112 R117 R122 R127 R132 R139 R140 R95 R108 R111 R118 R121 R128 R131 R136 R101 R135 R155 RN1 Part Number CRCW0805103J CRCW08051651F ERJ-6GEYJ330V CRCW0805162J CRCW08052003F CRCW08056191F CRCW08055491F CRCW08052941F CRCW08051000F Manufacturer VISHAY DALE PANASONIC DALE DALE DALE DALE DALE DALE Description RES, 10K, 0805, 1/10W, 5%. 200ppm RES, 1.65K, 0805, 1/10W, 1%. 100ppm RES, 33 OHMS, 1/10W,0805, 5% RES, 1.6K, 0805, 1/10W, 5%, 200ppm RES, 200K, 0805, 1/10W, 1%. 100ppm RES, 6.19K, 0805, 1/10W, 1%. 100ppm RES, 5.49K, 0805, 1/10W, 1%. 100ppm RES, 2.94K, 0805, 1/10W, 1%. 100ppm RES, 100-OHM, 0805, 1/10W, 1%. 100ppm. 100ppm RES, 91 OHMS, 0805, 1/8W, 5% RES, 100K, 0805, 1/10W, 1%. 100ppm RES, 2.80K, 0805, 1/10W, 1%. 100ppm RES, 390, 0805, 1/10W, 5%, 200ppm RESISTOR NETWORK, 9 BUSSED, SIP10, 10K Notes 44 45 46 47 48 10 8 2 1 1 CRCW0805910J CRCW08051003F CRCW08052801F CRCW0805391J 4610X-101-103 DALE DALE DALE DALE BOURNS 35 36 Item 49 50 Qty 10 3 Reference U1 U4 U5 U6 U7 U8 U9 U10 U22 U23 U2 U18 U33 Part Number NJM-2068E CS5351-KZ Manufacturer NJR CRYSTAL SEMI Description IC, DUAL LOW NOISE OPAMP, SO8-150 IC,CS5351-KZ,192 kHz AUDIO A/D CONVERTER,TSSOP24-173 128 X 8 STATIC RAM, 32 LEAD TSOP, 70NS IC, OCTAL EDGE-TRIGGERED D-TYPE FLIPFLOPS WITH 3-STATE OUTPUTS, TSSOP20-173 IC, OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, TSSOP20-173 IC, ELVIS, QFP64, 10X10mm, 0.5mm PITCH IC, MULTI-STANDARD AUDIO DECODER, PLCC44 IC, FLASH MEMORY, 512KX8, 256 BYTE SECTOR, PLCC32 OSCILLATOR, 12.288MHZ, 3.3V, FULLSIZE CASE Socket, Pin, Pop-in, SM Socket, PLCC-44 Socket, PLCC-32 Notes 51 52 1 2 U16 U19 U20 CY62128VLL-70ZI SN74LVC574APW CYPRESS TEXAS INSTRUMENTS INC 53 1 U21 SN74LVC245APW TEXAS INSTRUMENTS INC CIRRUS LOGIC CIRRUS LOGIC 54 55 1 1 U27 U3 CS4252 CS493302-CL 56 1 U24 AT29LV040A-25JC ATMEL 57 1 Y1 CV11AF-12.288MHZ CAL CRYSTAL 58 59 60 4 1 1 XY1 XU3 XU24 8134-HC-5P2 540-99-044-1740000 540-99-032-1740000 AUGAT MILL-MAX MILL-MAX APPENDIX G: UDSP SCHEMATICS J15 PHONO JACK RA AIO[16..1] AIO11 AIO1 AIO2 AIO3 AIO4 AIO5 AIO6 AIO7 AIO8 AIO9 AIO10 AIO11 AIO12 AIO13 AIO14 AIO15 AIO16 P1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 AIO1 J16 PHONO JACK RA 1 2 MICROCONTROLLER GND J17 PHONO JACK RA 5V_MOSI 5V_MISO 5V_SCK AIO12 2V_MOSI 2V_MISO 2V_SCK IRQn[5..0] RS232 Interface GND J19 PHONO JACK RA RXD TXD AIO13 RS232 CTS RTS RXD TXD CTS RTS EMAD[7..0] DSP_WRn EMOEn EXTMEMn PP_D[7..0] PP_CTRL[2..0] PP_STROBEn PP_ACKn PP_STATUS[3..0] 5V_MOSI 5V_MISO 5V_SCK 2V_MOSI 2V_MISO 2V_SCK IRQn[5..0] RXD TXD CTS RTS EMAD[7..0] DSP_WRn DSP_RDn EXTMEMn PP_D[7..0] PP_CTRL[2..0] PP_STROBEn PP_ACKn PP_STATUS[3..0] ADDR15 ADDR16 ADDR17 ADDR18 BMCTRL0 BMCTRL1 MUTECTRL0 MUTECTRL1 MUTECTRL2 2V_DBDA 2V_DBCK1 2V_DBCK2 2V_MRESETn 5V_MRESETn 2V_DSP1_RESETn 2V_DSP2_RESETn ADC_MCLK ADC_SCLK ADC_LRCLK ADC_SDOUT[4..1] DSP1_CDI_SCLK DSP1_CDI_LRCLK DSP1_CDI_SDIN DSP1_DAI_SCLK DSP1_DAI_LRCLK DSP1_DAI_SDIN DSP1_DAO_MCLK DSP1_DAO_SCLK DSP1_DAO_LRCLK DSP1_DAO_SDOUT[4..1] DSP2_CDI_SCLK DSP2_CDI_LRCLK DSP2_CDI_SDIN DSP2_DAI_SCLK DSP2_DAI_LRCLK DSP2_DAI_SDIN DSP2_DAO_MCLK DSP2_DAO_SCLK DSP2_DAO_LRCLK DSP2_DAO_SDOUT[4..1] ADDR15 ADDR16 ADDR17 ADDR18 BMCTRL0 BMCTRL1 MUTECTRL0 MUTECTRL1 MUTECTRL2 2V_DBDA 2V_DBCK1 2V_DBCK2 2V_MRESETn 5V_MRESETn 2V_DSP1_RESETn 2V_DSP2_RESETn ADC_MCLK ADC_SCLK ADC_LRCLK ADC_SDOUT[4..1] DSP1_CDI_SCLK DSP1_CDI_LRCLK DSP1_CDI_SDIN DSP1_DAI_SCLK DSP1_DAI_LRCLK DSP1_DAI_SDIN DSP1_DAO_MCLK DSP1_DAO_SCLK DSP1_DAO_LRCLK DSP1_DAO_SDOUT[4..1] DSP2_CDI_SCLK DSP2_CDI_LRCLK DSP2_CDI_SDIN DSP2_DAI_SCLK DSP2_DAI_LRCLK DSP2_DAI_SDIN DSP2_DAO_MCLK DSP2_DAO_SCLK DSP2_DAO_LRCLK DSP2_DAO_SDOUT[4..1] +2.5V +3.3V +5VD IRQn[5..0] CSn0 CSn1 CSn2 CSn3 CSn4 CSn5 CSn6 CSn7 CSn0 CSn1 CSn2 CSn3 CSn4 CSn5 CSn6 CSn7 GND J18 PHONO JACK RA 1 2 AIO2 ANALOG I/O SPARE[6..0] SPARE2 SPARE0 MUTECTRL2 MUTECTRL0 BMCTRL0 ADDR15 ADDR17 SPARE4 IRQn5 IRQn3 IRQn1 IRQn0 CSn6 CSn4 CSn2 CSn0 2V_SCK 2V_MOSI 5V_SCK 5V_MOSI P2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SOCKET 16X2-2MM GND SPARE3 SPARE1 MUTECTRL1 BMCTRL1 DSP_WRn GND ADDR16 ADDR18 GND IRQn4 IRQn2 GND CSn7 CSn5 CSn3 CSn1 GND 2V_MISO GND 5V_MISO SPARE[6..0] AIO3 GND J20 PHONO JACK RA 1 2 GND J22 PHONO JACK RA PARALLEL PORT PP_D[7..0] PP_CTRL[2..0] PP_STROBEn PP_ACKn PP_STATUS[3..0] PPORT Digital Audio Port (DAP) IRQn[5..0] CSn[7..0] AIO4 AIO14 GND J21 PHONO JACK RA 1 2 CSn[7..0] GND J24 PHONO JACK RA AIO15 DAP_MCLK DAP_SCLK DAP_LRCLK DAP_SDOUT[8..1] DAP_SDIN[4..1] DAP DAP_MCLK DAP_SCLK DAP_LRCLK DAP_SDOUT[8..1] DAP_SDIN[4..1] SPDIF_RX1 SPDIF_RX2 SPDIF_RX3 SPDIF_TX1 SPDIF_TX2 SPDIF_TX3 SPDIF_TX4 SPDIF_MCLK SPDIF_SCLK SPDIF_LRCLK SPDIF_SDOUT DIP_MODE_SEL[7..0] SPARE[6..0] DAP_MCLK DAP_SCLK DAP_LRCLK DAP_SDOUT[8..1] DAP_SDIN[4..1] SPDIF_RX1 SPDIF_RX2 SPDIF_RX3 SPDIF_TX1 SPDIF_TX2 SPDIF_TX3 SPDIF_TX4 SPDIF_MCLK SPDIF_SCLK SPDIF_LRCLK SPDIF_SDOUT DIP_MODE_SEL[7..0] SPARE[6..0] RS422_DATA1 RS422_CLK1 RS422_CLK2 ADC_DIF[1..0] HACK DC_OSC AIO5 GND J23 PHONO JACK RA 1 2 CONTROL1 P3 2V_DSP1_RESETn 2V_MRESETn 2V_DBDA 2V_DBCK1 2V_DBCK2 EMAD0 EMAD2 EMAD4 EMAD6 EMOEn GND +15VBUS GND -15VBUS GND +2.5V GND +3.3V GND +5VD 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SOCKET 20X2-2MM GND J25 PHONO JACK RA 1 2 GND J26 PHONO JACK RA AIO16 EMAD[7..0] GND RS422_DATA1 RS422_CLK1 RS422_CLK2 J28 TERMINAL BLUE ADC_DIF[1..0] HACK DC_OSC +15V 1 2V_DSP2_RESETn 5V_MRESETn GND GND EMAD[7..0] GND EMAD1 EMAD3 EMAD5 EMAD7 EXTMEMn GND +15VBUS GND -15VBUS GND +2.5V GND +3.3V GND +5VD AIO6 GND AIO7 J27 PHONO JACK RA 1 2 GND J29 PHONO JACK RA 1 2 POWER/CONTROL2 Power +15VBUS J30 TERMINAL BLACK +15VBUS MICRO SPDIF_RXN0 SPDIF_RXP0 SPDIF_RX1 SPDIF_RX3 SPDIF_TX1 SPDIF_TX3 SPDIF_RXN0 SPDIF_RXP0 SPDIF_RX1 SPDIF_RX2 SPDIF_RX3 SPDIF_RX4 SPDIF_RXN0 SPDIF_RXP0 SPDIF_RX1 SPDIF_RX2 SPDIF_RX3 SPDIF_RX4 P4 1 3 5 7 9 11 13 2 4 6 8 10 12 14 GND GND SPDIF_RX2 SPDIF_RX4 SPDIF_TX2 SPDIF_TX4 GND SOCKET 20X2-2MM AIO8 GND J31 PHONO JACK RA 1 2 GND 1 GND GND -15VBUS GND SPDIF I/O -15VBUS SPDIF_TX1 SPDIF_TX2 SPDIF_TX3 SPDIF_TX4 SPDIF_TX1 SPDIF_TX2 SPDIF_TX3 SPDIF_TX4 SPDIF I/O DSP1_CDI_SCLK DSP1_CDI_LRCLK DSP1_DAI_SCLK DSP1_DAI_LRCLK DSP1_DAO_MCLK DSP1_DAO_SCLK DSP1_DAO_LRCLK DSP1_DAO_SDOUT2 DSP1_DAO_SDOUT4 DSP2_CDI_SCLK DSP2_CDI_LRCLK DSP2_DAI_SCLK DSP2_DAI_LRCLK DSP2_DAO_MCLK DSP2_DAO_SCLK DSP2_DAO_LRCLK DSP2_DAO_SDOUT2 DSP2_DAO_SDOUT4 SPARE4 SPARE6 P5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SOCKET 7X2-2MM AIO9 J32 TERMINAL GREEN +5VD Power SPDIF -15V 1 DSP1_DAO_SDOUT[4..1] J34 TERMINAL RED RS422 BUFFER +5VD RS422_DATA1 RS422_CLK1 RS422_CLK2 RS422_DATA1 RS422_CLK1 RS422_CLK2 DSP2_DAO_SDOUT[4..1] RS422 J35 DIN5M HEADPHONE AIO[10..1] AIO[10..1]] SPARE[6..0] +5V 1 GND DSP1_CDI_SDIN GND DSP1_DAI_SDIN GND GND DSP1_DAO_SDOUT1 DSP1_DAO_SDOUT3 GND GND DSP2_CDI_SDIN GND DSP2_DAI_SDIN GND GND DSP2_DAO_SDOUT1 DSP2_DAO_SDOUT3 GND SPARE5 GND DSP1_DAO_SDOUT[4..1] AIO10 J33 PHONO JACK RA 1 2 GND DSP2_DAO_SDOUT[4..1] SPARE[6..0] 6 SOCKET 20X2-2MM FOR PHIHONG PSA-46-304 3 5 +5VD +15VBUS SERIAL AUDIO I/O 1 ADC_MCLK ADC_LRCLK ADC_SDOUT1 ADC_SDOUT3 SPDIF_MCLK SPDIF_SCLK SPDIF_SDOUT DIP_MODE_SEL7 DIP_MODE_SEL6 DIP_MODE_SEL5 DIP_MODE_SEL4 DIP_MODE_SEL3 DIP_MODE_SEL2 DIP_MODE_SEL1 DIP_MODE_SEL0 ADC_DIF0 ADC_DIF1 HACK P6 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND ADC_SCLK ADC_SDOUT2 ADC_SDOUT4 GND SPDIF_LRCLK GND 1 -15VBUS 4 2 HEADPHONE GND GND GND GND DC_OSC GND ADC_DIF[1..0] DC_OSC +2.5V 2V_DBDA 2V_DBCK1 2V_DBCK2 R11 R12 R13 4.7k 4.7k 4.7k SOCKET 20X2-2MM SERIAL AUDIO I/O 2 J36 1 3 5 2 4 6 HEADER 3X2 GND Figure 22. UDSP - Top 37 38 pg(4) DAP_SDOUT[8..1] DAP_SDOUT1 DAP_SDOUT2 DAP_SDOUT3 DAP_SDOUT4 DAP_SDOUT5 DAP_SDOUT6 DAP_SDOUT7 DAP_SDOUT8 U17 2 3 4 5 6 7 8 9 GND 1 19 A1 A2 A3 A4 A5 A6 A7 A8 G1 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 VCC GND 18 17 16 15 14 13 12 11 20 10 1 2 3 4 5 6 7 8 RP8 22 RPACK8 16 15 14 13 12 11 10 9 DAP_SDOUT1_B DAP_SDOUT2_B DAP_SDOUT3_B DAP_SDOUT4_B DAP_SDOUT5_B DAP_SDOUT6_B DAP_SDOUT7_B DAP_SDOUT8_B J47 C39 0.1uf 1 3 5 2 4 6 +5VD +3.3V +2.5V 74ACT541 HEADER 3X2 DAP VL SEL JP4 pg(4) DAP_MCLK pg(4) DAP_LRCLK pg(4) DAP_SCLK 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 pg(4) DAP_SDIN[4..1] U18 DAP_SDIN1 DAP_SDIN2 DAP_SDIN3 DAP_SDIN4 R52 R53 R54 R55 33 33 33 33 3 6 8 11 1Y 2Y 3Y 4Y 1A 2A 3A 4A 1OE 2OE 3OE 4OE VCC 74ACT125 2 5 9 12 1 4 10 13 14 C40 0.1uf DAP_SDOUT1_B DAP_SDOUT2_B DAP_SDOUT3_B DAP_SDOUT4_B DAP_SDOUT5_B DAP_SDOUT6_B DAP_SDOUT7_B DAP_SDOUT8_B DAP_SDIN1_B DAP_SDIN2_B DAP_SDIN3_B DAP_SDIN4_B HEADER 16X2 DIGITAL AUDIO PORT Figure 23. UDSP - Digital Audio Port A pg(1) AIO[10..1] AIO1 AIO2 AIO3 AIO4 AIO5 AIO6 AIO7 AIO8 AIO9 AIO10 J48 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 C79 + 1uf/50 +5VD C81 C82 + U21 2 8 VIN1 VIN2 VOUT1 VOUT2 BYPASS VDD GND 1 9 3 10 5 + GND 100uf/16 VCC C83 + 0.1uf C84 1uf/50 100uf/16 C80 J51 1 2 3 4 5 HEADPHONE JACK + R65 4.7k 1uf/50 4 7 6 CLOCK SHUTDWN UP/DWN LM4811 GND +5VD R82 10k +5VD R83 10k U24 A B N/C GND 1 2 3 4 ENCODER GND HEADER 10X2 Figure 24. UDSP - Headphone Amplifier 39 HEADER 3X1 R85 330 R86 33 0 2 2 2 1 2 3 4 5 6 7 8 9 10 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 1 1 1 1 1 1 1 RED_LED GREEN_LED S1 1 2 3 4 5 6 7 8 GND 1 1 1 1 2 3 GND SW SPDT SWITCH4 pg(1) 2V_DBDA 2 1 2 1 RESET GND GND PP_RESETn 2 1N4148 D5 1 5 NCS CS NWS I/O NRS I/O I/O I/O GND18 I/O I/O I/O I/O I/O I/O I/O VCC19 I/O I/O I/O I/O I/O I/O I/O GND17 I/O I/O DEV_OE INPUT GCLK2 INPUT DEV_CLRN I/O I/O I/O VCC18 I/O I/O I/O I/O I/O I/O I/O GND16 I/O I/O I/O I/O I/O I/O DATA7 VCC17 DATA6 I/O DATA5 DATA4 I/O DATA3 DATA2 DATA1 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 C18 10nf GND R29 R30 330 K 10M C19 33nf GND UC_PWR GND PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 44 43 42 41 40 39 38 37 36 35 34 U8 TP26 TP27 TP28 TP30 TP31 TP32 +5VD R31 10k pg(1) DSP1_DAI_SDIN pg(1) DSP1_DAO_MCLK pg(1) DSP1_DAO_SCLK pg(1) DSP1_DAO_LRCLK TP29 pg(1) DSP1_DAO_SDOUT1 pg(1) DSP1_DAO_SDOUT2 pg(1) DSP1_DAO_SDOUT3 pg(1) DSP1_DAO_SDOUT4 pg(1) DSP2_CDI_SDIN pg(1) DSP2_CDI_SCLK pg(1) DSP2_CDI_LRCLK pg(1) DSP2_DAI_SDIN pg(1) DSP2_DAI_SCLK pg(1) DSP2_DAI_LRCLK pg(1) DSP2_DAO_MCLK TP38 pg(1) DSP2_DAO_SCLK pg(1) DSP2_DAO_LRCLK pg(1) DSP2_DAO_SDOUT1 pg(1) DSP2_DAO_SDOUT2 pg(1) DSP2_DAO_SDOUT3 pg(1) DSP2_DAO_SDOUT4 SPARE4 DSP1_DAI_SDIN DSP1_DAO_MCLK DSP1_DAO_SCLK DSP1_DAO_LRCLK DSP1_DAO_SDOUT1 DSP1_DAO_SDOUT2 DSP1_DAO_SDOUT3 DSP1_DAO_SDOUT4 DSP2_CDI_SDIN DSP2_CDI_SCLK DSP2_CDI_LRCLK DSP2_DAI_SDIN DSP2_DAI_SCLK HS_BUS0 DSP2_DAI_LRCLK DSP2_DAO_MCLK DSP2_DAO_SCLK DSP2_DAO_LRCLK DSP2_DAO_SDOUT1 DSP2_DAO_SDOUT2 DSP2_DAO_SDOUT3 DSP2_DAO_SDOUT4 SPARE5 SPARE6 ADC_SDOUT4 ADC_SDOUT3 ADC_SDOUT2 ADC_SDOUT1 ADDR15 ADDR16 ADDR17 ADDR18 SPARE4 IRQn5 IRQn4 IRQn3 IRQn2 IRQn1 IRQn0 CSn11 CSn10 CSn9 CSn8 5V_CSn 7 5V_CSn 6 5V_CSn 5 5V_CSn 4 5V_CSn 3 5V_CSn 2 5V_CSn 1 5V_CSn 0 5V_DSP2_RESET n 5V_DSP1_RESET n 5V_DBCK2 5V_DBCK1 5V_DBDA EMAD0 EMAD1 EMAD2 EMAD3 EMAD4 EMAD5 EMAD6 EMAD7 EXTMEMn DSP_WRn DSP_RDn RTS ADDR15 pg(1) ADDR16 pg(1) ADDR17 pg(1) ADDR18 pg(1) 10 9 8 7 6 5 4 3 2 1 22pf 4 1 C21 22pf GND 3 2 GND Y1 32.768 KHZ GND GND TP34 TP36 TP39 TP40 TP41 TP42 TP43 TP44 pg(7) RXD pg(7) TXD TP50 5V_MRESET n PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 IRQn_1 OSC1 OSC2 CGMXFC VSSA VDDA PTA7/KBD7 PTA6/KBD6 PTA5/KBD5 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK VSS VDD PTD4/T1CH0 PTD5/T1CH1 PTD6/T2CH0 PTD7/T2CH1 PTB0/AD0 12 13 14 15 16 17 18 19 20 21 22 I/O I/O I/O I/O I/O I/O I/O I/O GND6 I/O I/O I/O I/O I/O I/O I/O VCC7 I/O I/O I/O I/O I/O I/O I/O GND7 I/O I/O I/O VCC8 INPUT GCLK1 INPUT GND8 I/O I/O VCC9 I/O I/O I/O I/O I/O I/O I/O GND9 I/O I/O I/O I/O I/O I/O I/O VCC10 I/O I/O I/O I/O I/O I/O I/O I/O +5VD C25 0.1uf GND 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 U10 5V_DBCK1 5V_DBCK2 5V_DSP1_RESET n 5V_DSP2_RESET n 5V_MRESET n 5V_SCK 5V_MOSI 2 3 4 5 6 7 8 9 1 19 GND A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 20 10 1 2 3 4 5 6 7 8 CSn GND TDI CASCn INIT_CONFn R38 22 RPACK8 16 15 14 13 12 11 10 9 +3.3V C28 0.1uf 2V_DBCK1pg(1) 2V_DBCK2pg(1) 2V_DSP1_RESETpg(1) n 2V_DSP2_RESETpg(1) n 2V_MRESET pg(1) n 2V_SCKpg(1) VL +5VD pg(2) DAP_SCLK pg(2) DAP_LRCLK pg(2) DAP_MCLK 2V_MOSIpg(1) 2 3 Q2 BSS138ZX 3 2 1 5V_MOSI pg(1) SPDIF_LRCLK pg(1,9) SPDIF_TX3 pg(1,9) SPDIF_TX2 pg(1,9) SPDIF_TX1 pg(1,9) SPDIF_RX3 pg(1,9) SPDIF_RX2 pg(1,9) SPDIF_RX1 1 R39 2.2k R40 2.2k OE1 VCC OE2 GND 74LVC541A GND J44 HEADER 3X1 SPI/I2C MODE DAP_SDOUT6 DAP_SDOUT5 DAP_SDOUT4 DAP_SDOUT3 DAP_SDOUT2 DAP_SDOUT1 DAP_SCLK DAP_LRCLK DAP_MCLK DIP_MODE_SEL7 DIP_MODE_SEL6 DIP_MODE_SEL5 DIP_MODE_SEL4 DIP_MODE_SEL3 DIP_MODE_SEL2 DIP_MODE_SEL1 DIP_MODE_SEL0 SPDIF_LRCLK PP_RESETn SPDIF_TX3 SPDIF_TX2 SPDIF_TX1 SPDIF_RX3 SPDIF_RX2 SPDIF_RX1 PTC6 PTC4 5V_MRESET n 61 62 63 64 65 66 67 68 70 71 72 73 74 75 76 78 79 80 81 82 83 84 86 87 88 90 91 92 GND 120 119 118 117 116 115 114 113 111 110 109 108 107 106 105 103 102 101 100 99 98 97 95 94 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTA6 PTA7 RDIP_MODE_SEL3 PTC0 PTC1 PTC2 PTC3 PTC5 IRQOUTn UC_SSn MISO 2V_MISO 5V_MISO 5V_MOSI RDIP_MODE_SEL0 RDIP_MODE_SEL1 RDIP_MODE_SEL2 5V_SCK +2.5V +3.3V TP61 FPGA_DCLK FPGA_STATU Sn R41 10k R42 10k 4 5 6 7 8 TCK DOUT TDO VCC TMS 3 2 1 20 19 9 10 11 12 13 2 1 2 IRQn1 +3.3V 1 pg(1) EMAD[7..0] EMAD[7..0] EMAD0 EMAD1 EMAD2 EMAD3 EMAD4 EMAD5 EMAD6 EMAD7 DSP_RDn 2 3 4 5 6 7 8 9 11 U12 D0 D1 D2 D3 D4 D5 D6 D7 CK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 F_A0 F_A1 F_A2 F_A3 F_A4 F_A5 F_A6 F_A7 +5VD DSP_RDn 20 10 C30 0.1uf GND GND GND GND GND 11 CK DSP_RDn 20 10 C31 0.1uf GND +5VD 11 CK VCC 1 OE GND 74HC574A VCC 1 OE GND 74HC574A VCC 1 OE GND 74HC574A 20 10 C32 0.1uf +5VD F_A0 F_A1 F_A2 F_A3 F_A4 F_A5 F_A6 F_A7 2 3 4 5 6 7 8 9 U13 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 F_A8 F_A9 F_A1 0 F_A1 1 F_A1 2 F_A1 3 F_A1 4 F_A1 5 F_A8 F_A9 F_A1 0 F_A1 1 F_A1 2 F_A1 3 F_A1 4 F_A1 5 2 3 4 5 6 7 8 9 U14 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 F_A1 6 F_A1 7 F_A1 8 F_A0 F_A1 F_A2 F_A3 F_A4 F_A5 F_A6 F_A7 F_A8 F_A9 F_A1 0 F_A1 1 F_A1 2 F_A1 3 F_A1 4 F_A1 5 F_A1 6 F_A1 7 F_A1 8 DSP_RDn CSn9 DSP_WRn 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 1 24 22 31 RP1 10k RPACK9 1A 2A 3A 4A 1OE 2OE 3OE 4OE VCC 1Y 2Y 3Y 4Y GND HEADER 10X2 EXTERNAL CONTROL GND R43 10K PTC0 1 4 10 13 14 C29 0.1uf 2 3 4 5 6 7 8 9 10 U15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 OE CE WE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 13 14 15 17 18 19 20 21 D0 D1 D2 D3 D4 D5 D6 D7 D[7..0] VL 74ACT125 GND R44 R45 R46 +5VD R47 1k 1k 1k 1k TCK TDO TMS TDI JP3 1 3 5 7 9 2 4 6 8 10 +5VD VL HEADER 5X2 GND 32 16 GND GND F_A[18..0] VCC VSS +5VD C33 0.1uf AM29F040-150JC 512K X 8 FLASH EMAD[7..0] EMAD0 EMAD1 EMAD2 EMAD3 EMAD4 EMAD5 EMAD6 EMAD7 R74 R75 R76 R77 R78 R79 R80 R81 U23 47 47 47 47 47 47 47 47 +3.3V C89 0.1uf 18 17 16 15 14 13 12 11 20 10 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 VCC GND A1 A2 A3 A4 A5 A6 A7 A8 1G DIR 2 3 4 5 6 7 8 9 19 1 D0 D1 D2 D3 D4 D5 D6 D7 DSP_RDn DSP_WRn 74VHC245 GND Figure 25. UDSP - Microcontroller 1 40 +3.3V +3.3V 1 2 3 U2 +3.3V R14 10k RPACK9 U3 GREEN LED GREEN LED D15 D14 GREEN LED GREEN LED GREEN LED GREEN LED GREEN LED GREEN LED D19 D16 D17 D20 D18 D21 DIP_PWR 5V_MOSI 5V_MISO 5V_SCK CSn8 5 2 6 1 VCC nHOLD nWP VSS 25LC640-SN SI SO SCK nCS 8 7 3 4 GND GND 16 15 14 13 12 11 10 9 DIP_MODE_SEL7 DIP_MODE_SEL6 DIP_MODE_SEL5 DIP_MODE_SEL4 DIP_MODE_SEL3 DIP_MODE_SEL2 DIP_MODE_SEL1 DIP_MODE_SEL0 DIP_MODE_SEL[7..0] pg(1) TP1 5V_MRESET n CSn11 CSn10 GND IRQn5 5V_MISO 5V_MOSI 5V_SCK GND GND J38 1 2 3 4 5 6 7 8 9 10 +5VD +5VD TP2 TP3 TP4 TP5 J39 1 2 3 4 5 6 7 8 HEADER 8X1 GND DISPLAY/CONTROL HEADERS GND SW SPDT +5VD NOTES: R19 10k +3.3V SW2 1 2 3 GND SW SPDT +5VD R21 10k SW3 1 2 3 GND SW SPDT +5VD R22 10k SW4 R23 2.2k R24 2.2k 3 Q1 BSS138ZX +5VD 5V_DBDA VL +5VD pg(6) PP_D[7..0] PP_CTRL1 PP_CTRL2 PP_D0 MCLK_OSC PP_D1 PP_D2 PP_D3 PP_D4 PP_D5 PP_D6 PP_D7 PP_ACKn PP_STATUS 0 PP_STATUS 1 PP_STATUS 2 PP_STATUS 3 DSP1_ABO OT DSP1_CDI_LRCLK DSP1_CDI_SCLK DSP1_CDI_SDIN DSP1_DAI_SCLK HS_BUS4 DSP1_DAI_LRCLK HS_BUS3 HS_BUS2 HS_BUS1 212 213 214 215 217 218 219 220 221 222 223 225 226 227 228 229 230 231 233 234 235 236 237 238 239 240 +3.3V GND 211 210 209 208 207 206 204 203 202 201 200 199 198 196 195 194 193 192 191 190 188 187 186 185 184 183 182 181 PP_CTRL0 PP_STROBn E HS_BUS5 HS_BUS6 HS_BUS7 RS422_DAT 1 A RS422_CLK 1 RS422_CLK 2 RED_LED GREEN_LED SPARE3 SPARE2 SPARE1 SPARE0 MUTECTRL2 MUTECTRL1 MUTECTRL0 BMCTRL1 BMCTRL0 REMOTE_LOCALn_SEL SWITCH4 SWITCH3 PP_CTRL_SEL_PIN DSP1_ABO OT ADC_DIF0 ADC_DIF1 HACK pg(1) SWITCH3 GND R89 10k R90 10k RDIP_MODE_SEL1 4 GND 5 RDIP_MODE_SEL3 6 S2 2 C1 8 4 C2 1 3 2 1 RDIP_MODE_SEL2 GND RDIP_MODE_SEL0 R87 10k R88 10k +3.3V REMOTE_LOCALn_SEL +3.3V +3.3V JP1 1. SHORTING TRACES ACROSS HEADER PINS MUST BE CUT BEFORE DEBUG HEADER INSTALATION AND USE +5VD +5VD U4 1 2 3 4 A0 A1 A2 GND VCC WC SCL SDA 8 7 6 5 5V_SCK 5V_MOSI GND GND C15 0.1uf 5V_CSn 0 5V_CSn 1 5V_CSn 2 5V_CSn 3 5V_CSn 4 5V_CSn 5 5V_CSn 6 5V_CSn 7 1 2 3 4 5 6 7 8 J40A 1 2 3 4 5 6 7 8 HEADER 8X3 J40B 1 2 3 4 5 6 7 8 HEADER 8X3 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 R17 16 15 14 13 12 11 10 9 22 RPACK8 CSn0 CSn1 CSn2 CSn3 CSn4 CSn5 CSn6 CSn7 pg(1) pg(1) pg(1) pg(1) pg(1) pg(1) pg(1) pg(1) J40C 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 2V_CSn 0 2V_CSn 1 2V_CSn 2 2V_CSn 3 2V_CSn 4 2V_CSn 5 2V_CSn 6 2V_CSn 7 ON +5VD 5V_CSn 7 5V_CSn 6 5V_CSn 5 5V_CSn 4 5V_CSn 3 5V_CSn 2 5V_CSn 1 5V_CSn 0 C13 0.1uf 2 3 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 20 10 2V_CSn 7 2V_CSn 6 2V_CSn 5 2V_CSn 4 2V_CSn 3 2V_CSn 2 2V_CSn 1 2V_CSn 0 +3.3V C14 0.1uf D1 RED LED D2 GREEN LED OE1 VCC OE2 GND 74LVC541A +5VD R18 10k SW1 1 2 3 PP_CTRL_SEL_PIN SW DIP-8 GND GND HEADER 10X1 24LC128-SN HEADER 8X3 ON OFF 1 2 3 HEADER 3X1 OSC PWR C16 0.1uf U5 14 7 +5V GND 12.288MHZ NC CLKOUT 1 R20 8 33 MCLK_OSC TP6 PP_CTRL0 PP_CTRL1 PP_CTRL2 PP_CTRL[2..0] pg(6) SWITCH, ROTARY DIP PP_STROBn pg(6) E RS422_DAT 1 pg(8) A RS422_CLK pg(8)TP13 TP14 TP15 TP16 1 RS422_CLK pg(8) 2 SPARE[6..0] pg(1) pg(6) PP_STATUS[3..0] pg(6) PP_ACKn R25 2.2k +5VD +5VD 5V_MRESET pg(1) n D3 1N4148 D4 2 1N4148 1 1 OUT VSS C17 TP25 0.1uf MN13821T +5VD 2 3 pg(1) DSP1_CDI_LRCLK pg(1) DSP1_CDI_SCLK pg(1) DSP1_CDI_SDIN pg(1) DSP1_DAI_SCLK pg(1) DSP1_DAI_LRCLK MUTECTRL2 pg(1) MUTECTRL1 pg(1) MUTECTRL0 pg(1) BMCTRL1 pg(1) BMCTRL0 pg(1) SPDIF_TX4 pg(1,9) S3 PTS645TL50 1 2 GND 4 3 R26 4.7k U6 VDD ADC_DIF[1..0] pg(1) R27 10k RPACK9 R28 10k TCK FPGA_CONFIG_DONE TDO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 TCK CONF_DONE NCEO TDO VCC1 I/O I/O I/O I/O GND1 CLKUSR I/O I/O I/O I/O VCC2 I/O I/O I/O I/O I/O GND2 RDYNBUSY I/O I/O INIT_DONE VCC3 I/O I/O I/O I/O GND3 I/O I/O I/O I/O VCC4 I/O I/O I/O I/O GND4 I/O I/O I/O I/O VCC5 I/O I/O I/O I/O GND5 I/O I/O I/O I/O VCC6 TMS TRST NSTATUS DATA0 DCLK NCE TDI GND15 I/O I/O I/O I/O I/O VCC16 I/O I/O I/O I/O GND14 I/O I/O I/O I/O VCC15 I/O I/O I/O I/O GND13 I/O I/O I/O I/O VCC14 I/O I/O I/O I/O GND12 I/O I/O I/O I/O VCC13 I/O I/O I/O I/O GND11 I/O I/O I/O I/O VCC12 I/O I/O I/O I/O GND10 MSEL0 MSEL1 VCC11 NCONFIG 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 FPGA_DAT 0 A FPGA_DCLK CONFIG_TDO +2.5V IRQn[5..0]pg(1) C20 1 2 3 4 5 6 7 8 9 10 11 RST PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTE0/TxD PTE1/RxD IRQ PTA1/KBD1 PTA0/KBD0 VSSAD/VREFL VDDAD/VREFH PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 33 32 31 30 29 28 27 26 25 24 23 PTA1 PTA0 GND HS_BUS7 HS_BUS6 HS_BUS5 HS_BUS4 HS_BUS3 HS_BUS2 HS_BUS1 HS_BUS0 TP35 TP37 TP45TP46TP47 pg(1) SPARE[6..0] pg(1) ADC_SDOUT[4..1] DC_OSC pg(1) R32 R33 10k 10k +5VD +5VD +5VD R34 2.2k JP2 R36 10k PTC2 pg(1) 5V_MOSI pg(1) 5V_SCK +5VD FB1 BEAD C22 0.1uf GND GND C23 0.1uf GND UC_PWR R35 10k UC_SSn MISO GND TP51 TP52 TP53 TP54 TP56 TP58 TP59 TP60 EXTMEMn pg( 1) DSP_WRn pg(1) DSP_RDn pg(1) RTS pg(7) MC68HC908GP32CFB DSP_WRn DSP_RDn RUN PROG pg(1) ADC_SCLK pg(1) SPDIF_SDOUT pg(1) ADC_LRCLK pg(1) SPDIF_SCLK pg(2) DAP_SDIN[4..1] pg(1) SPDIF_MCLK pg(1) ADC_MCLK ADC_SCLK SPDIF_SDOUT ADC_LRCLK SPDIF_SCLK SPDIF_MCLK ADC_MCLK DAP_SDIN4 DAP_SDIN3 DAP_SDIN2 DAP_SDIN1 DAP_SDOUT8 DAP_SDOUT7 TMS 1 2 3 HEADER 3X1 TP55 TP57 CTS pg(7) RTS pg(7) uC GND +3.3V R37 10k J41 GND C24 0.1uf FPGA_STATU Sn FPGA_CONFIGn OFF ON 3 2 1 HEADER 3X1 GND JTAG I/F VCC C26 0.1uf GND U7 EPF10K20RC240-4 TMS +3.3V C27 0.1uf GND CONFIG_TDO FPGA_DAT 0 A TCK pg(2) DAP_SDOUT[8..1] DAP_SDOUT8 DAP_SDOUT7 U9 EPC2LC20 DCLK VCCSEL NC1 NC2 OE VPP NC5 NC4 NC3 VPPSEL 18 17 16 15 14 GND +5VD +3.3V R72 33 0 2V_MISOpg(1) 5V_MISOpg(1) FPGA_CONFIGn 5V_SCKpg(1) TDI FPGA_CONFIG_DONE D12 RED LED GND J45 5V_MOSI 5V_MISO 2V_MISO 5V_SCK CSn0 CSn2 IRQOUTn IRQn0 IRQn2 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 R73 33 0 D13 GREEN LED U11 CSn1 CSn3 PTC1 PTC3 PTC4 2 5 9 12 3 6 8 11 TCK TDI TMS +15V R56 1k +15VBUS 2 1 U19 LM39401T-3.3 VIN GND VOUT 3 + R57 121 GND GND 1 1 VR1 500 POT CW R58 0 + C45 10uf/16 C42 0.1uf GND C41 10uf/16 +3.3V TP85 TP86 D6 ZMM5248B C44 0.1uf + C43 100uf/16 D7 GREEN LED 18V 2 D8 ZMM5248B C47 0.1uf + C46 100uf/16 GND D9 GREEN LED 2 18V R59 -15VBUS 1k -15V 1 3 J37 GND GND GND VL 1 3 2 4 +3.3V +2.5V 2 HEADER 2X2 VL SEL TP88 TP89 TP90 TP91 TP92 TP93 TP94 GND TP95 TP96 +5VD TP97 TP98 VCC +5VD 1 U20 LT2937ET-2.5 VIN GND VOUT 3 R60 121 TP99 TP100 +2.5V R61 374 D10 ZMM5248B + C50 100uf/16 C51 0.1uf + C52 100uf/16 C53 0.1uf + 6.3V C54 100uf/16 1 VR2 500 POT CW 2 D11 GREEN LED 2 R62 0 2 + C55 10uf/16 1 GND GND +3.3V + C60 0.1uf C61 0.1uf C62 0.1uf C63 0.1uf C64 0.1uf C65 0.1uf C66 0.1uf C67 0.1uf C68 0.1uf C69 0.1uf C70 0.1uf C71 0.1uf C72 0.1uf C73 0.1uf C74 0.1uf C75 0.1uf C76 0.1uf C77 0.1uf C78 0.1uf C56 10uf/16 + C57 10uf/16 + C58 10uf/16 + C59 10uf/16 GND Figure 26. UDSP - Power 3 41 2 3 4 5 6 2 3 4 5 6 RP5 X_D0 X_D1 X_D2 X_D3 X_D4 X_D5 X_D6 X_D7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 470 RPACK8 TP65 PP_D0 PP_D1 PP_D2 PP_D3 PP_D4 PP_D5 PP_D6 PP_D7 PP_D[7..0] pg(4) X_nSTROBE nAUTOFEED nINIT nSELECTIN R48 R49 R50 R51 2.2k 2.2k 2.2k 2.2k PP_STROBEn pg(4) PP_CTRL0 pg(4) PP_CTRL1 pg(4) PP_CTRL2 pg(4) +5VD 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 J46 DB25M_RA X_nSTROBE nAUTOFEED X_D0 nERROR X_D1 nINIT X_D2 nSELECTIN X_D3 X_D4 X_D5 X_D6 X_D7 X_ACKn nBUSY PE SELECT RP6 1 1k RPACK5 2 3 4 5 6 2 3 4 5 6 42 +5VD RP2 1 1k RPACK5 +5VD RP3 1 1k RPACK5 +5VD RP4 1 1k RPACK5 X_ACKn TP66 TP68 TP70 RP7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 22 RPACK8 PP_ACKn pg(4) TP67 TP69 TP71 nBUSY PE SELECT nERROR PP_STATUS0 PP_STATUS1 PP_STATUS2 PP_STATUS3 PP_STATUS[3..0] pg(4) GND Figure 27. UDSP - Parellel Port Interface TP72 TP73 TP74 TP75 RX_IN RTS_IN pg(4) TXD pg(4) CTS U16 13 8 12 10 1 R1IN R2IN T1IN T2IN C1+ VCC C1V+ C2+ V5 C2MAX232CWE GND C37 1uf/16C GND GND C38 1uf/16C GND 16 2 6 15 C35 1uf/16C R1OUT R2OUT T1OUT T2OUT 11 9 14 7 TX_OUT CTS_OUT RXD pg(4) RTS pg(4) TP76 TP77 TP78 TP79 +5VD TP80 TP81 TP82 TP83 SHORT TX_OUT RTS_IN RX_IN CTS_OUT SHORT (CD_O) (DSR_O) (TX) (RTS_I) (RX) (CTS_O) (DTR_I) (RI_O) DB9F-RA 1 6 2 7 3 8 4 9 5 P7 GND FB2 BEAD C34 1uf/16C 3 4 C36 1uf/16C Figure 28. UDSP - RS232 Interface 43 44 P8 5 9 4 8 3 7 2 6 1 DB9F-RA GND CLK2+ CLK1+ DATA1R66 CLK2+ CLK2DATA1+ DATA1CLK1+ CLK1100 5% DATA1+ CLK2R67 100 5% CLK1R68 100 5% 11 12 DO2+ DO2U22 15 16 13 14 10 09 RI1RI1+ DO1DO1+ RI2RI2+ RO1 DI1 RO2 VCC DEN REN DI2 GND 1 2 8 3 4 5 7 6 RS422_DATA1 pg(4) RS422_CLK2 pg(4) RS422_CLK1 pg(4) +5VD C90 1uf/16C DS8922A GND Figure 29. UDSP - RS422 Interface J1 5 4 3 2 1 6 TORX-173 RX_PWR C1 0.1uf J3 PHONO JACK RA 1 2 SPDIF_TX1 SPDIF_RXP0 R2 75 +5VD SPDIF_RXP0 pg(1) C2 0.1uf R1 8.20k 4 3 2 1 J2 5 6 TOTX-173 SPDIF_RX1 pg(1,4) GND U1A 4 3 2 1 RX_PWR C4 0.1uf J6 1 2 3 HEADER 3X1 GND 5 SPDIF_RXN0 pg(1) pg(1,4) SPDIF_TX1 1 3 2 74ACT08 0.1uf 1% R4 93.1 1% 1 6 T1 67129600 2 J7 SPDIF_TX2 4 3 2 1 RX_PWR C6 0.1uf +5VD C5 0.1uf R5 8.20k 3 2 1 6 TOTX-173 5 4 3 0.1uf 74ACT08 1% R7 93.1 1% 1 5 6 T2 67129600 2 J11 SPDIF_RX4 pg(1) +5VD J49 SPDIF_TX4 +5VD C87 0.1uf R69 8.20k 5 4 3 2 U1C 1 6 TOTX-173 U1D pg(1,4) SPDIF_TX4 12 11 13 74ACT08 0.1uf 1% R71 93.1 1% 1 5 6 T4 67129600 2 C88 R70 374 3 J50 PHONO JACK RA 1 pg(1,4) SPDIF_TX3 9 8 10 74ACT08 2 0.1uf 1% R10 93.1 1% 1 5 6 T3 67129600 2 C11 R9 374 3 TOTX-173 J13 PHONO JACK RA 1 C9 0.1uf R8 8.20k SPDIF_TX3 5 4 3 2 1 6 2 4 4 J9 PHONO JACK RA 1 2 C3 R3 374 3 J5 PHONO JACK RA 1 5 2 J4 4 6 TORX-173 SPDIF_RX2 pg(1,4) J8 5 6 TORX-173 SPDIF_RX3 pg(1,4) pg(1,4) SPDIF_TX2 J10 5 4 3 2 1 6 TORX-173 GND RX_PWR 47uH C8 0.1uf L1 VCC +5VD U1B 4 6 5 C7 R6 374 4 Figure 30. UDSP - S/PDIF I/O 45 46 APPENDIX H: BILL OF MATERIALS - UDSP Item Qty Reference C1 C2 C3 C4 C5 C6 C7 C8 C9 C11 C13 C14 C15 C16 C17 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C39 C40 C42 C44 C47 C51 C53 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C83 C87 C88 C89 C18 C19 C21 C20 C34 C35 C36 C37 C38 C90 C41 C56 C57 C58 C59 C43 C46 C50 C52 C54 C80 C82 C55 C45 C79 C81 C84 D1 D12 D2 D7 D9 D11 D13 D14 D15 D16 D17 D18 D19 D20 D21 D3 D4 D5 D6 D8 D10 FB1 FB2 JP1 JP2 JP5 J6 J41 J44 JP3 JP4 J1 J4 J8 J10 J2 J7 J11 J49 J3 J5 J9 J13 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J29 J31 J33 J50 J28 J30 MFG_PN MFG DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 57 1 1 2 6 5 7 2 3 2 13 3 3 2 6 1 1 4 4 C1206C104K5RAC C1206C103K1RAC C1206C333K1RAC C1206C220J1GAC C1206C105M4RAC ECE-V1CA100SR ECE-V1CA101WP ECE-V1CA100SR ECE-V1HS010SR LN1251C-(TR) LN1351C-(TR) LL4148DI ZMM5248B EXC-ML45A910U TSW-103-07-G-S TSW-105-07-G-D TSW-116-07-T-D TORX-173 TOTX-173 KEMET KEMET KEMET KEMET KEMET PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC VISHAY VISHAY PANASONIC SAMTEC SAMTEC SAMTEC TOSHIBA TOSHIBA CAP CERAMIC 0.1UF 50V 10% X7R 1206 CAP CERAMIC 10NF 100V 10% X7R 1206 CAP CERAMIC 33NF 100V 10% X7R 1206 CAP CERAMIC 22PF 100V 5% COG 1206 CAP CERAMIC 1UF 16V 20% 1206 CAP ELECT AL 10UF 16V 20% SM_B CAP ELECT AL 100UF 16V 20% SM_D CAP ELECT AL 10UF 16V 20% SM_B CAP 1uF ELEC VS SERIES SMT CASE-A 50V 20% LED RED DIFF 10MA SM LED GREEN DIFF 10MA SM DIODE HS SWITCHING MELF SOD-80 DIODE ZENER 18V 500MW SOD-80 FERRITE BEAD 1806 HEADER MALE 0.1 IN HDR3X1 HEADER MALE 0.1 IN HDR5X2 STAKE HEADER 16X2 .1"" CENTER TIN OPTICAL TOSLINK RECIEVER OPTICAL TRANSMITTER 20 21 22 21 1 1 ARJ2018 111-0110-001 111-0103-001 A/D ELECT E.F.JOHNSON E.F.JOHNSON PHONO JACK RA GOLD BINDING POST BLUE BPOST BINDING POST BLACK BPOST Item 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Qty 1 1 4 1 2 1 1 1 1 2 1 1 1 1 4 1 2 2 3 2 2 1 4 4 1 5 4 5 Reference J32 J34 JX28 JX30 JX32 JX34 J35 J36 J47 J37 J38 J39 J40 J45 J48 J46 J51 L1 P1 P2 P3 P5 P6 P4 P8 P7 Q2 Q1 RP1 R14 R27 RP2 RP3 RP4 RP6 RP5 RP7 RP8 R17 R38 R1 R5 R8 R69 R2 R3 R6 R9 R61 R70 R4 R7 R10 R71 R11 R12 R13 R26 R65 MFG_PN 111-0104-001 111-0102-001 "1-1.5 X.25'TIN X.25"" TIN SDS-50J TSW-103-07-G-D TSW-102-07-G-D TSW-110-07-G-S TSW-108-07-G-S TSW-108-07-G-T TSW-110-07-G-D 747238-4 CON-AD3056-50 ELJ-FA470KF ESQT-116-03-G-D-375 ESQT-120-03-G-D-375 ESQT-107-03-G-D-375 745781-4 BSS138ZX 4610X-101-103 4606X-101-102 4606X-101-102 4816P-T01-220 4816P-T01-220 ERJ-8GEYJ822 ERJ-8ENF75R0 ERJ-8ENF3740 ERJ-8ENF93R1 ERJ-8GEYJ472 MFG E.F.JOHNSON E.F.JOHNSON TYPE E" CUI STACK SAMTEC SAMTEC SAMTEC SAMTEC SAMTEC SAMTEC AMP DESCRIPTION BINDING POST GREEN BPOST BINDING POST RED BPOST SQUIRES CONNECTOR CIRCULAR DIN5M HEADER MALE 0.1 IN HDR3X2 HEADER MALE 0.1 IN HDR2X2 HEADER MALE 0.1 IN HDR10X1 HEADER MALE 0.1 IN HDR8X1 HEADER MALE 0.1 IN HDR8X3 HEADER MALE 0.1 IN HDR10X2 CONNECTOR DB25 MALE RA A/D ELECTRONICS CONNECTOR STEREO HEADPHONE JACK PANASONIC SAMTEC SAMTEC SAMTEC AMP ZETEX BOURNS BOURNS BOURNS BOURNS BOURNS PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC INDUCTOR 47UH 1210 HEADER FEMALE 2MM SOK16X2-2MM HEADER FEMALE 2MM SOK20X2-2MM HEADER FEMALE 2MM SOK7X2-2MM CONNECTOR D-SHELL9 RA .318 MOUNT FEMALE MOSFET N CH 1.5VT SOT23 RES R-PACK9 10K 1/8W 2% SIP10 RES R-PACK5 1K 1/8W 2% SIP6 RES R-PACK5 1K 1/8W 2% SIP6 RES R-PACK8 221/8W 2% SO16N RES R-PACK8 22 1/8W 2% SO16N RES THICK FILM 8.20K 1/8W 5% 1206 RES THICK FILM 75 1/8W 5% 1206 RES THICK FILM 374 1/8W 1% 1206 RES THICK FILM 93.1 1/8W 1% 1206 RES THICK FILM 4.7K 1/8W 5% 1206 47 48 Item Qty Reference R18 R19 R21 R22 R28 R31 R32 R33 R35 R36 R37 R41 R42 R43 R82 R83 R87 R88 R89 R90 R20 R52 R53 R54 R55 R23 R24 R25 R34 R39 R40 R48 R49 R50 R51 R29 R30 R44 R45 R46 R47 R56 R59 R60 R57 R62 R58 R66 R67 R68 R72 R73 R85 R86 R74 R75 R76 R77 R78 R79 R80 R81 R84 SW1 SW2 SW3 SW4 S1 S2 S3 TP1 TP2 TP3 TP4 TP5 TP6 TP13 TP14 TP15 TP16 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP34 TP35 TP36 TP37 TP38 TP39 TP40 TP41 TP42 TP43 TP44 TP45 TP46 TP47 TP50 TP51 TP52 TP53 TP54 TP55 TP56 TP57 TP58 TP59 TP60 TP61 TP65 TP66 TP67 TP68 TP69 TP70 TP71 TP72 T T1 T2 T3 T4 U1 U2 U10 U3 U4 MFG_PN MFG DESCRIPTION 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 20 5 10 1 1 6 2 2 3 4 8 1 4 1 1 1 ERJ-8ENF1002 ERJ-8GEYJ330 ERJ-8GEYJ222 ERJ-8GEYJ334 ERJ-8GEYJ106 ERJ-8GEYJ102 ERJ-8ENF1210 ERJ-8GEY0R00V CRCW12061000F ERJ-8GEYJ331 ERJ-8GEYJ470V 4610X-101-331 TS01CBE 76SB08 94HBB16 PTS645TL50 PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC DALE PANASONIC PANASONIC BOURNS C&K GRAYHILL GRAYHILL C&K RES THICK FILM 10K 1/8W 1% 1206 RES THICK FILM 33 1/8W 5% 1206 RES THICK FILM 2.2K 1/8W 5% 1206 RES THICK FILM 330K 1/8W 5% 1206 RES THICK FILM 10MEG 1/8W 5% 1206 RES THICK FILM 1K 1/8W 5% 1206 RES THICK FILM 121 1/8W 1% 1206 RES THICK FILM 0 1/8W 5% 1206 RES 100 OHMS 1206 1/8W 1% 100ppm RES THICK FILM330 1/8W 5% 1206 RES 49.9-OHM 1% 0805 1/10W RES R-PACK9 330 1/8W 2% SIP10 SWITCH SLIDE SPDT SWITCH DIP 8 POS ROCKER DIP16 SWITCH DIP ROTARY HEX SM SWITCH 6MM TACT W/ ESD PIN 130GF DPST 67 68 69 70 71 72 78 4 1 2 1 1 NONE 67129600 74ACT08SC SN74LVC541ADW 25LC640I-SN 24LC128I-SN NONE SCHOTT FAIRCHILD TI MICROCHIP MICROCHIP TEST POINT PAD62H40 TRANSFORMER TH IC QUAD AND GATE SO14N IC OCTAL BUFFER SO20-300 IC EEPROM SERIAL SPI 8KX8 SO8N IC EEPROM I2C SERIAL 16KX8 SO8N 49 Item 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Qty 1 4 1 1 1 1 1 2 3 1 1 1 1 1 1 1 1 1 2 1 8 8 1 Reference U5 UX5 U6 U7 U8 U9 UX9 U11 U18 U12 U13 U14 U15 U16 U17 U19 U20 U21 U22 U23 U24 VR2 VR1 Y1 MFG_PN CX21AF-12.2880MHZ 8134-HC-5P2 MN13821T EPF10K30AQC240-1 MC68HC908GP32CFB EPC2LC20 540-99-020-17-40000 MM74ACT125AD SN74HCT574DW AM29F040B-150JC MAX232CWE MM74ACT541AD LM39401T-3.3 LT2937ET-2.5 LM4811MM DS8922M TC74VHC245FT EVQ-VEMF0224B 3296Y-501 CM200S32.768KDZFT 313-6477-032 H343-ND UDSP-1B.0 MFG CAL CRYSTAL AUGAT PANASONIC ALTERA MOTOROLA ALTERA MILL-MAX FAIRCHILD TI AMD MAXIM FAIRCHILD LINEAR TECH DESCRIPTION IC OSCILLATOR 12.2880MHZ 50PPM OSC14 S0CKET PIN P0P-INSM IC VOLTAGE DETECTOR OD 4.4-4.7V SC59A IC FPGA -4 PQFP240 IC MICROCONTROLLER 32K PQFP44 IC CONFIG EEPROM PLCC20 S0CKET PLCC-20 SMT IC QUAD BUFFER W/ 3-STATE SO14-150 IC D-FLOP TRI-STATE OCTAL SO20-300 IC FLASH 512KX8 150NS 32PLCC IC RS232 TRANSCEIVER SO16W IC BUFFER OCTAL SO20-300 IC VREG POSITIVE 2.5V TO220AB NATIONAL SEMI IC VREG POSITIVE 3.3V TO220AB NATIONAL SEMI IC HEADPHONE AMPLIFIER MSOP-8 IC RS422 DIFFERENTIAL LINE DRIVER NATIONAL SEMI SO16-240 TOSHIBA PANASONIC BOURNS CITIZEN E.F. JOHNSON DIGI-KEY BI-DIR OCTAL BUFFER TRI-STATE TSSOP20 ENCODER ROTARY RES POTENTIOMETER 500 25 TURN TOP ADJ TH CRYSTAL 32.768 KHZ PARALLEL 12.5PF LOAD STAND-0FF .875"" HT 1/4 FLAT 4-40 THREAD SCREW 4-40 5/16 MACHINE PRINTED CIRCUIT BOARD