CRD4412

CS4412 30 W Quad Half-Bridge Digital Amplifier Power Stage Features Configurable Outputs (10% THD+N) – 2 x 15 W into 8 Ω, Full-Bridge – 1 x 30 W into 4 Ω, Parallel Full-Bridge – 4 x 7 W into 4 Ω, Half-Bridge – 2 x 7 W into 4 Ω, Half-Bridge + 1 x 15 W into 8 Ω, Full-Bridge Space-Efficient Thermally-Enhanced QFN – No External Heat Sink Required > 100 dB Dynamic Range - System Level 0.1% THD+N @ 1 W - System Level Built-In Protection with Error Reporting – Over-current – Thermal Warning and Overload – Under-voltage +9 V to +18 V High Voltage Supply PWM Popguard® for Quiet Startup High Efficiency (85%) Low RDS(ON) Low Quiescent Current Low Power Standby Mode 2.5 V to 5 V Common Applications Integrated Digital Televisions Portable Docking Stations Mini/Micro Shelf Systems Powered Desktop Speakers General Description The CS4412 is a high-efficiency power stage for digital Class-D amplifiers designed to input PWM signals from a modulator such as the CS4525. The power stage outputs can be configured as four half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge channels, or one parallel full-bridge channel. The CS4412 integrates on-chip over-current, undervoltage, over-temperature protection and error reporting as well as a thermal warning indicator. The low RDS(ON) outputs can source up to 2.4 A peak current, delivering 85% efficiency. This efficiency provides for a small device package and lower power supplies. The CS4412 is available in a 48-pin QFN package in Commercial grade (-40 to +70° C). The CRD4412 customer reference design is also available. Please refer to “Ordering Information” on page 22 for complete ordering information. 9 V to 18 V VP In 1 In 2 In 3 In 4 Non-Overlap Time Insertion Mode Configuration Non-Overlap Time Insertion Gate Drive Amplifier Out 1 Gate Drive Amplifier Out 2 Reset Hardware Configuration Current & Thermal Data Control Logic Non-Overlap Time Insertion Gate Drive Amplifier Out 3 Protection & Error Reporting Non-Overlap Time Insertion Gate Drive Amplifier Out 4 PGND Advance Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) SEPTEMBER '06 DS749A1 CS4412 TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 2 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4 RECOMMENDED OPERATING CONDITIONS .................................................................................... 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4 PWM POWER OUTPUT CHARACTERISTICS ..................................................................................... 5 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 DIGITAL INTERFACE SPECIFICATIONS ............................................................................................. 6 DIGITAL I/O PIN CHARACTERISTICS ................................................................................................. 7 3. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 8 4. APPLICATIONS ................................................................................................................................... 12 4.1 Overview ........................................................................................................................................ 12 4.2 Reset and Power-Up ...................................................................................................................... 12 4.2.1 PWM Popguard Transient Control ........................................................................................ 12 4.2.2 Recommended Power-Up Sequence .................................................................................... 12 4.2.3 Recommended Power-Down Sequence .............................................................................. 13 4.3 Output Mode Configuration ............................................................................................................ 13 4.4 Output Filters ................................................................................................................................. 14 4.4.1 Half-Bridge Output Filter ........................................................................................................ 14 4.4.2 Full-Bridge Output Filter (Stereo or Parallel) ......................................................................... 15 4.5 Device Protection and Error Reporting .......................................................................................... 16 4.5.1 Over-current Protection ......................................................................................................... 16 4.5.2 Thermal Warning, Thermal Error, and Under-Voltage Error ................................................. 16 5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT ....................................................................... 17 5.1 Power Supply and Grounding ........................................................................................................ 17 5.1.1 Integrated VD Regulator ........................................................................................................ 17 5.2 QFN Thermal Pad .......................................................................................................................... 17 6. PARAMETER DEFINITIONS ................................................................................................................ 18 7. PACKAGE DIMENSIONS .................................................................................................................... 19 8. THERMAL CHARACTERISTICS ......................................................................................................... 20 8.1 Thermal Flag .................................................................................................................................. 20 9. ORDERING INFORMATION ................................................................................................................ 21 10. REVISION HISTORY .......................................................................................................................... 21 LIST OF FIGURES Figure 1.Stereo Full-Bridge Typical Connection Diagram ........................................................................... 8 Figure 2.2.1 Channel Typical Configuration Diagram ................................................................................. 9 Figure 3.4-Channel Half-Bridge Typical Connection Diagram .................................................................. 10 Figure 4.Mono Parallel Full-Bridge Typical Connection Diagram ............................................................. 11 Figure 5.Output Filter - Half-Bridge ........................................................................................................... 14 Figure 6.Output Filter - Full-Bridge ............................................................................................................ 15 LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 7 Table 2. Output Mode Configuration Options ............................................................................................ 13 Table 3. Low-Pass Filter Components - Half-Bridge ................................................................................. 14 Table 4. DC-Blocking Capacitors Values - Half-Bridge ............................................................................. 15 Table 5. Low-Pass Filter Components - Full-Bridge ................................................................................. 15 Table 6. Over-current Error Conditions ..................................................................................................... 16 Table 7. Thermal and Under-Voltage Error Conditions ............................................................................. 16 Table 8. VD Supply Level Indication ......................................................................................................... 17 2 DS749A1 CS4412 1. PIN DESCRIPTION ERROC12 ERRUVTE ERROC34 RST34 RAMP PGND PGND 39 PGND 38 48 47 46 45 44 43 42 41 40 CNFG0 CNFG1 CNFG2 IN1 IN2 IN3 IN4 RST12 LVD GND VD_REG VD PGND 37 TWR GND GND 1 2 3 4 5 6 7 8 9 10 11 12 Top-Down View 48-Pin QFN Package 36 35 34 33 32 31 VP OUT1 PGND PGND OUT2 VP VP OUT3 PGND PGND OUT4 VP CS4412 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 VA_REG OCREF GND GND GND GND GND GND GND PGND PGND Pin Name CNFG0 CNFG1 CNFG2 IN1 IN2 IN3 IN4 RST1/2 RST3/4 LVD VD_REG VD VA_REG Pin # 1 2 3 4 5 6 7 8 46 9 11 12 13 Pin Description Out Configuration Select (Input) - Used to set the PWM output configuration mode. See “Output Mode Configuration” on page 14. PWM Input (Input) - Inputs from a PWM modulator. Reset Input (Input) - Reset inputs for channels 1/2 and 3/4 respectively. Active low. VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying 5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, LVD must be GND. Core Digital Power (Output) - Filter connection for the internally generated power supply for the low voltage digital circuitry. Digital Power (Input) - Low voltage power supply for internal logic. Core Analog Power (Output) - Filter connection for internally generated power supply for the low voltage analog circuitry DS749A1 RAMP_CAP 3 CS4412 Pin Name OCREF RAMP_CAP Pin # 21 24 10,14 15,16 17,18 19,20 47,48 25,30 31,36 22,23 27,28 33,34 37,38 39,40 26 29 32 35 41 42 43 44 45 Pin Description Over-current Reference (Input) - Sets over-current trip level. Connect pin through a resistor to GND. See “Device Protection and Error Reporting” on page 17. This pins should not be left floating. Output Ramp Capacitor (Input) - Sets the output ramp time for half-bridge configured outputs. GND Ground (Input) - Ground for the internal logic and I/O. These pins should be connected to the common system ground. High Voltage Output Power (Input) - High voltage power supply for the individual output power half-bridge devices. Power Ground (Input) - Ground for the individual output power half-bridge devices. These pins should be connected to the common system ground. VP PGND OUT4 OUT3 OUT2 OUT1 TWR ERRUVTE ERROC1/2 ERROC3/4 RAMP PWM Output (Output) - Amplified PWM power half-bridge outputs. Thermal Warning Output (Output) - Thermal warning output. Open drain, active low. See “Device Protection and Error Reporting” on page 17. Thermal and Under-voltage Error Output (Output) - Error flag for thermal shutdown and undervoltage. Open drain, active low. See “Device Protection and Error Reporting” on page 17 Over-current Error Output (Output) - Over-current error flag for the associated outputs. Open drain, active low. See “Device Protection and Error Reporting” on page 17. Ramp-up/down Select (Input) - Set high to enable ramping. When set low, ramping is disabled. See “PWM Popguard Transient Control” on page 13. 4 DS749A1 CS4412 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND=PGND=0 V, all voltages with respect to ground. Parameters DC Power Supply Digital and Analog Core VD VD VD Power Stage Temperature Ambient Temperature Junction Temperature Commercial TA TJ -40 +70 +150 °C °C VP 2.375 3.135 4.75 8.1 2.5 3.3 5.0 2.625 3.465 5.25 19.8 V V V V Symbol Min Nom Max Units ABSOLUTE MAXIMUM RATINGS GND = PGND = 0 V; all voltages with respect to ground. (Note 1) Parameters DC Power Supply Power Stage Power Stage Digital and Analog Core Inputs Input Current Digital Input Voltage Temperature Ambient Operating Temperature - Power Applied Commercial Storage Temperature TA Tstg -40 -65 +85 +150 °C °C Outputs Switching and Under Load No Output Switching (Note 2) (Note 2) (Note 3) (Note 4) (Note 2) Iin VIND -0.3 ±10 VD + 0.4 mA V VP VP VD -0.3 -0.3 -0.3 19.8 23.0 6.0 V V V Symbol Min Max Units Notes: 1. Operation beyond these limits may result in permanent damage to the device. 2. Normal operation is not guaranteed at these extremes. 3. Any pin except supplies. Transient currents of up to ±100 mA on the PWM input pins will not cause SCR latch-up. 4. The maximum over/under voltage is limited by the input current. DS749A1 5 CS4412 PWM POWER OUTPUT CHARACTERISTICS Test Conditions (unless otherwise specified): GND = PGND = 0 V; All voltages with respect to ground; TA = 25° C; VD = 3.3 V; VP = 18 V; RL = 8 Ω for full-bridge, RL = 4 Ω for half-bridge and parallel full-bridge; PWM Switch Rate = 384 kHz; 10 Hz to 20 kHz Measurement Bandwidth; Input source is CS4525 PWM_SIG outputs; Performance measurements taken with a full scale 997 Hz sine wave and AES17 filter. Parameters Power Output per Channel Stereo Full-Bridge Half-Bridge Parallel Full-Bridge Total Harmonic Distortion + Noise Stereo Full-Bridge Half-Bridge THD+N Parallel Full-Bridge Dynamic Range Stereo Full-Bridge Half-Bridge Parallel Full-Bridge MOSFET On Resistance Efficiency Minimum Output Pulse Width Rise Time of OUTx Fall Time of OUTx PWM Output Over-Current Error Trip Point Junction Thermal Warning Trip Point Junction Thermal Error Trip Point VP Under-Voltage Error Trip Point Ramp-Up Time - Half-Bridge Configuration Ramp-Down Time- Half-Bridge Configuration RDS(ON) h PWmin tr tf ICE TTW TTE VUV TRU TRD Capacitor = 1000 µF Capacitor = 1000 µF DYR PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted Id = 0.5 A, TJ = 50°C PO = 2 x 11.3 W, RL = 8 Ω No Load Resistive Load Resistive Load OCREF = 16.2 kΩ 2.4 4.5 102 99 102 99 102 99 518 85 50 20 20 120 140 0.8 50 615 dB dB dB dB dB dB mΩ % ns ns ns A °C °C V s s PO THD+N < 10% THD+N < 1% THD+N < 10% THD+N < 1% THD+N < 10% THD+N < 1% PO = 1 W PO = 0 dBFS = 11.3 W PO = 1 W PO = 0 dBFS = 5.0 W PO = 1 W PO = 0 dBFS = 22.6 W 15 12 7 5.5 30 23.5 0.1 0.3 0.1 0.3 0.1 0.3 W W W W W W % % % % % % Symbol Conditions Min Typ Max Units 6 DS749A1 CS4412 DC ELECTRICAL CHARACTERISTICS GND = PGND = 0 V; All voltages with respect to ground; PWM switch rate = 384 kHz; Unless otherwise specified. Parameters Normal Operation Power Supply Current Power Dissipation 50 % Duty Cycle VP Idle Current (Note 6) Power-Down Mode Power Supply Current Power Supply Current VD_REG Characteristics Nominal Voltage DC current source VA_REG Characteristics Nominal Voltage DC current source 2.25 2.5 2.75 1 V mA 2.25 2.5 2.75 3 V mA (Notes 5, 8) VD = 3.3 V VD = 3.3 V VP = 18 V (Note 7) VD = 3 .3 V VP = 18 V 4.3 100 mA μA 20 66 20 mA mW mA Min Typ Max Units Notes: 5. Normal operation is defined as RSTx/y = HI. 6. All outputs idle. 7. Power-Down Mode is defined as RSTx/y = LOW with all input lines held static. 8. Power supply current increases with increasing PWM switching rates. DIGITAL INTERFACE SPECIFICATIONS GND = PGND = 0 V; All voltages with respect to ground; Unless otherwise specified. Parameters High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Input Leakage Current Input Capacitance Io=2 mA Symbol VIH VIL VOH Iin Min 0.7*VD_REG 0.90*VD - Max VD 0.20*VD_REG ±10 8 Units V V V μA pF DS749A1 7 CS4412 DIGITAL I/O PIN CHARACTERISTICS The logic level for each input is set by its corresponding power supply and should not exceed the maximum ratings. Power Pin Supply Number VD 1 2 3 4 5 6 7 8 9 41 42 43 44 45 46 VP 35 32 29 26 Pin Name CNFG0 CNFG1 CNFG2 IN1 IN2 IN3 IN4 RST12 LVD TWR ERRUVTE ERROC12 ERROC34 RAMP RST34 OUT1 OUT2 OUT3 OUT4 I/O Input Input Input Input Input Input Input Input Input Output Output Output Output Input Input/ Output Output Output Output Driver 2.5 V-5.0 V, Open Drain 2.5 V-5.0 V, Open Drain 2.5 V-5.0 V, Open Drain 2.5 V-5.0 V, Open Drain 9 V-18 V Power MOSFET 9 V-18 V Power MOSFET 9 V-18 V Power MOSFET 9 V-18 V Power MOSFET Table 1. I/O Power Rails Receiver 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V 2.5 V-5.0 V - 8 DS749A1 CS4412 3. TYPICAL CONNECTION DIAGRAMS +3.3 V or +5.0 V 10 µF 0.1 µF 470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF +9 V to +18 V 12 25 30 31 36 VP VP VP RAMP_CAP 24 PWM1+ PWM2+ PWM3+ PWM4+ 4 5 6 7 IN1 IN2 IN3 IN4 OUT1 35 VP VD Output Filter CS4412 1 CNFG0 CNFG1 CNFG2 LVD RAMP OUT2 32 Hardware Control Settings 2 3 9 45 Output Filter VD 22 kΩ 22 kΩ 22 kΩ 22 kΩ OUT3 29 Output Filter 43 44 ERROC12 ERROC34 ERRUVTE TWR RST12 RST34 OUT4 26 System Control Logic 42 41 8 46 Output Filter 11 VD_REG GND 10 GND 14 GND 15 10 µF 0.1 µF 13 VA_REG GND 16 GND 17 GND 18 GND 19 10 µF 0.1 µF 16.2 kΩ 21 OCREF GND 20 GND 47 GND 48 22 Figure 1. Stereo Full-Bridge Typical Connection Diagram DS749A1 N D P G N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D 23 27 28 33 34 37 38 39 40 PG 9 CS4412 +3.3 V or +5.0 V 10 µF 0.1 µF 470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 470 µF 470 µF +9 V to +18 V 12 25 30 31 36 VP VP VP RAMP_CAP 24 PWM1+ PWM2+ PWM3+ PWM4+ 4 5 6 7 IN1 IN2 IN3 IN4 OUT1 35 VP VD Output Filter CS4412 1 CNFG0 CNFG1 CNFG2 LVD RAMP OUT2 32 Hardware Control Settings 2 3 9 45 Output Filter VD 22 kΩ 22 kΩ 22 kΩ 22 kΩ 43 44 ERROC12 ERROC34 ERRUVTE TWR RST12 RST34 OUT3 29 Output Filter System Control Logic 42 41 8 46 OUT4 26 Output Filter 11 VD_REG GND 10 GND 14 GND 15 10 µF 0.1 µF 13 VA_REG GND 16 GND 17 GND 18 GND 19 10 µF 0.1 µF 16.2 kΩ 21 OCREF GND 20 GND 47 GND 48 22 Figure 2. 2.1 Channel Typical Configuration Diagram 10 N D P G N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D 23 27 28 33 34 37 38 39 40 PG DS749A1 CS4412 +3.3 V or +5.0 V 10 µF 0.1 µF 470 µF 470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 470 µF 470 µF +9 V to +18 V 390 pF 12 25 30 31 36 VP VP VP RAMP_CAP 24 PWM1+ PWM2+ PWM3+ PWM4+ 4 5 6 7 IN1 IN2 IN3 IN4 OUT1 35 VP VD Output Filter CS4412 1 CNFG0 CNFG1 CNFG2 LVD RAMP OUT2 32 Hardware Control Settings 2 3 9 45 Output Filter VD 22 kΩ OUT3 29 ERROC12 ERROC34 ERRUVTE TWR RST12 RST34 OUT4 26 Output Filter 22 kΩ 22 kΩ System Control Logic 22 kΩ 43 44 42 41 8 46 Output Filter 11 VD_REG GND 10 GND 14 GND 15 10 µF 0.1 µF 13 VA_REG GND 16 GND 17 GND 18 GND 19 10 µF 0.1 µF 16.2 kΩ 21 OCREF GND 20 GND 47 GND 48 N D N D N D N D PG 39 40 N D N D N D P G N PG N D PG PG PG PG PG 22 23 27 28 33 34 PG 37 38 Figure 3. 4-Channel Half-Bridge Typical Connection Diagram DS749A1 PG N D D 11 CS4412 +3.3 V or +5.0 V 10 µF 0.1 µF 470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF +9 V to +18 V 12 25 30 31 36 VP VP VP RAMP_CAP 24 PWM1+ PWM2+ PWM3+ PWM4+ 4 5 6 7 IN1 IN2 IN3 IN4 CS4412 1 CNFG0 CNFG1 CNFG2 LVD RAMP OUT3 29 OUT1 35 OUT2 32 Hardware Control Settings 2 3 9 45 VP VD Output Filter VD 22 kΩ 22 kΩ 22 kΩ OUT4 26 Output Filter 43 44 ERROC12 ERROC34 ERRUVTE TWR RST12 RST34 System Control Logic 42 41 8 46 11 VD_REG GND 10 GND 14 GND 15 10 µF 0.1 µF 13 VA_REG GND 16 GND 17 GND 18 GND 19 10 µF 0.1 µF 16.2 kΩ 21 OCREF GND 20 GND 47 GND 48 22 Figure 4. Mono Parallel Full-Bridge Typical Connection Diagram 12 N D P G N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D 23 27 28 33 34 37 38 39 40 PG DS749A1 CS4412 4. APPLICATIONS 4.1 Overview The CS4412 is a high-efficiency power stage for digital Class-D amplifiers designed to be configured as four half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge channels, or one parallel full-bridge channel. The CS4412 integrates on-chip over-current, under-voltage, over-temperature protection and error reporting as well as a thermal warning indicator. The low RDS(ON) outputs can source up to 2.4 A peak current, delivering 85% efficiency. This efficiency provides for smaller device package, no external heat sink requirements, and smaller power supplies. 4.2 Reset and Power-Up Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks, and configuration pins are stable. It is also recommended that the RSTx/y pin be activated if the voltage supplies drop below the recommended operating condition to prevent power-glitch- related issues. When RSTx/y is low, the corresponding channels of the CS4412 enter a low-power mode and all of the channels’ internal states are reset and the outputs are set to HI-Z. When RSTx/y is high, the desired mode settings will be loaded and the outputs will begin normal operation. 4.2.1 PWM Popguard Transient Control The CS4412 uses Popguard technology to minimize the effects of output transients during power-up and power-down for half-bridge configurations. This technique reduces the audio transients commonly produced by half-bridge, single-supply amplifiers when implemented with external DC-blocking capacitors connected in series with the audio outputs. When the device is configured for ramping (RAMP set high) and RSTx/y is set high, the OUTx/y outputs will ramp-up to the bias point (VP/2). This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up transient. The OUTx/y outputs will not begin normal operation until the ramp has reached the bias point. The INx/y inputs must begin switching before the ramp cycle begins. When the device is configured for ramping (RAMP set high) and RSTx/y is set low, the OUTx/y outputs will begin to slowly ramp down from the bias point to PGND, allowing the DC-blocking capacitor to discharge. The ramp feature should only be used in quad half-bridge configuration. It is not necessary to complete a ramp-up/down sequence before ramping up/down again. 4.2.2 Recommended Power-Up Sequence 1. Turn on the system power. 2. Hold RSTx/y low until the power supply and system clocks are stable. In this state, all associated outputs are HI-Z. 3. Start the PWM modulator output. 4. Once the PWM modulator output is valid, release RSTx/y high. If the CS4412 is configured for ramping, the outputs will ramp to the bias point and then begin switching normally. If the CS4412 is not configured for ramping, the outputs will immediately begin switching normally. DS749A1 13 CS4412 4.2.3 Recommended Power-Down Sequence 1. Mute the logic-level PWM inputs present on IN1 - IN4 by applying 50 % duty-cycle inputs. 2. Set RSTx/y low. If the CS4412 is configured for ramping, the outputs will ramp down to PGND and then become HI-Z. If the CS4412 is not configured for ramping, the outputs will immediately become HI-Z. 3. Power down the remainder of the system. 4. Turn off the system power. 4.3 Output Mode Configuration The CS4412 can be configured for several modes of operation. Table 2 shows the setting of the CNFG[2:0] inputs and the corresponding mode of operation. These pins should remain static during operation (RSTx/y set high). CNFG2 CNFG1 CNFG0 Output Config. 0 0 0 0 0 1 Stereo Full-Bridge Tied Loads Stereo Half-Bridge and Mono FullBridge Tied Loads Mono Parallel FullBridge Tied Load Quad Half-Bridge Tied Loads Description IN1 must be inverted from IN2 for full-bridge operation. IN3 must be inverted from IN4 for full-bridge operation. IN1 must be provided for half-bridge operation. IN2 must be provided for half-bridge operation. IN3 must be inverted from IN4 for full-bridge operation. IN1 and IN3 must be inverted from IN2 and IN4 for parallel fullbridge operation. IN1 must be provided for half-bridge operation. IN2 must be provided for half-bridge operation. IN3 must be provided for half-bridge operation. IN4 must be provided for half-bridge operation. IN1 must be provided for full-bridge operation. Wire IN2 to IN1. IN2 is internally inverted for full-bridge operation. IN3 must be provided for full-bridge operation. Wire IN4 to IN3. IN4 is internally inverted for full-bridge operation. IN1 must be provided for half-bridge operation. IN2 must be provided for half-bridge operation. IN3 must be provided for full-bridge operation. Wire IN4 to IN3. IN4 is internally inverted for full-bridge operation. IN1 must be provided for parallel full-bridge operation. Wire IN4, IN3, and IN2 to IN1. IN2 and IN4 are internally inverted for parallel full-bridge operation. IN1 must be provided for half-bridge operation. IN2 must be provided for half-bridge operation. IN3 must be provided for half-bridge operation. IN4 must be provided for half-bridge operation. 0 0 1 1 0 1 1 0 0 Stereo Full-Bridge Tied Loads With Inversion Stereo Half-Bridge & Mono Full-Bridge Tied Loads With Inversion Mono Parallel FullBridge Tied Load With Inversion Quad Half-Bridge Tied Loads 1 0 1 1 1 0 1 1 1 Table 2. Output Mode Configuration Options 14 DS749A1 CS4412 4.4 Output Filters The filter placed after the PWM outputs can greatly affect the output performance. The filter not only reduces radiated EMI (snubber filter), but also filters high frequency content from the switching output before going to the speaker (low-pass LC filter). 4.4.1 Half-Bridge Output Filter Figure 5 shows the output filter for a half-bridge configuration. The transient-voltage suppression circuit (snubber circuit) is comprised of a resistor (20 Ω, ¼ W) and capacitors (220 pF) and should be placed as close as possible to the corresponding PWM output pin to greatly reduce radiated EMI. VP PWM Output 20 Ω L1 + C2 - 220 pF *Diode is Zetex ZHCS400 or equivalent C1 Figure 5. Output Filter - Half-Bridge The inductor, L1, and capacitor, C1, comprise the low-pass filter. Along with the nominal load impedance of the speaker, these values set the cutoff frequency of the filter. Table 3 shows the component values for L1 and C1 based on nominal speaker (load) impedance for a corner frequency (-3 dB point) of approximately 35 kHz. Load 4Ω 6Ω 8Ω L1 22 µH 33 µH 47 µH C1 1.0 µF 0.68 µF 0.47 µF Table 3. Low-Pass Filter Components - Half-Bridge C2 is the DC-blocking capacitor. Table 4 shows the component values for C2 based on corner frequency (-3 dB point) and a nominal speaker (load) impedances of 4 Ω, 6 Ω, and 8 Ω. This capacitor should also be chosen to have a ripple current rating above the amount of current that will passed through it. DS749A1 15 CS4412 Load 4Ω Corner Frequency 40 Hz 58 Hz 120 Hz 39 Hz 68 Hz 120 Hz 42 Hz 60 Hz 110 Hz C2 1000 µF 680 µF 330 µF 680 µF 390 µF 220 µF 470 µF 330 µF 180 µF 6Ω 8Ω Table 4. DC-Blocking Capacitors Values - Half-Bridge 4.4.2 Full-Bridge Output Filter (Stereo or Parallel) Figure 6 shows the output filter for a full-bridge configuration. The transient-voltage suppression circuit (snubber circuit) is comprised of a resistor (20 Ω) and capacitor (330 pF) and should be placed as close as possible to the corresponding PWM output pins to greatly reduce radiated EMI. The inductors, L1, and capacitor, C1, comprise the low-pass filter. Along with the nominal load impedance of the speaker, these values set the cutoff frequency of the filter. Table 5 shows the component values based on nominal speaker (load) impedance for a corner frequency (-3 dB point) of approximately 35 kHz. VP + PWM Output L1 *Diode is Zetex ZHCS400 or equivalent 20 Ω 330 pF - PWM Output C1 VP L1 Figure 6. Output Filter - Full-Bridge Load 4Ω 6Ω 8Ω L1 10 µH 15 µH 22 µH C1 1.0 µF 0.47 µF 0.47 µF Table 5. Low-Pass Filter Components - Full-Bridge 16 DS749A1 CS4412 4.5 Device Protection and Error Reporting The CS4412 has built-in protection circuitry for over-current, under-voltage, and thermal warning/overload conditions. The levels of the over-current error, thermal error, and VP under-voltage trip points are listed in the PWM Power Output Characteristics table on page 6. Automatic shut-down will occur whenever any of these preset thresholds are crossed. Each error and warning pin implements an active-low open-drain driver and requires an external pull-up for proper operation. 4.5.1 Over-current Protection Over-current errors are reported on the ERROCx/y pins. For example, an over-current error on OUT1 is reported by the ERROC1/2 pin. The power output of the channel which is reporting the over-current condition will be set to high-impedance until the error condition has been removed and the RSTx/y signal for that channel has been toggled from low to high. ERROCx/y 0 1 Reported Condition Over-current error on channel x or channel y. Operating current of channel x and y within allowable limits. Table 6. Over-current Error Conditions 4.5.2 Thermal Warning, Thermal Error, and Under-Voltage Error Table 7 shows the behavior of the TWR and ERRUVTE pins. When the junction temperature exceeds the junction thermal warning trip point, the TWR pin will be set low. If the junction temperature continues to increase beyond the junction thermal error trip point, the ERRUVTE pin will be set low. If the voltage on VP falls below the VP under-voltage error trip point, ERRUVTE will be set low. When the thermal error or VP under-voltage trip point is crossed, all power outputs will be set to highimpedance until the error condition has been removed and the RSTx/y signals have been toggled from low to high. TWR 0 0 1 1 ERRUVTE 0 1 0 1 Reported Condition Thermal warning and thermal error and/or under-voltage error. Thermal warning only. Under-voltage error. Junction temperature and VP voltage within normal limits. Table 7. Thermal and Under-Voltage Error Conditions DS749A1 17 CS4412 5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT 5.1 Power Supply and Grounding The CS4412 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. It is necessary to decouple the power supply by placing capacitors directly between the power and ground of the CS4412. Decoupling capacitors should be as close to the pins of the CS4412 as possible. The lowest value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS4412 to minimize inductance effects. The CRD4412 reference design demonstrates the optimum layout and power supply arrangements. 5.1.1 Integrated VD Regulator The CS4412 includes two internal linear regulators, one from the VD supply voltage to provide a fixed 2.5 V supply to its internal digital blocks, and another from the VD supply voltage to provide a fixed 2.5 V supply to its internal analog blocks. The LVD pin must be set to indicate the voltage present on the VD pin as shown in Table 8 below. LVD Low High Indicated VD Supply Level 2.5 V or 3.3 V Nominal 5 V Nominal Table 8. VD Supply Level Indication The output of the digital regulator is presented on the VD_REG pin and may be used to provide an external device with up to 3 mA of current at its nominal output voltage of 2.5 V. The output of the analog regulator is presented on the VA_REG pin and must only be connected to the bypass capacitors as shown in the typical connection diagrams. If a nominal supply voltage of 2.5 V is used as the VD supply (see the Recommended Operating Conditions table on page 5), the VD, VD_REG, and VA_REG pins must all be connected to the VD supply source. In this configuration, the internal regulators are bypassed and the external supply source is used to directly drive the internal digital and analog sections. 5.2 QFN Thermal Pad The CS4412 is available in a compact QFN package. The underside of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of thermal vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. The CRD4412 reference design demonstrates the optimum thermal pad and via configuration. 18 DS749A1 CS4412 6. PARAMETER DEFINITIONS Dynamic Range (DYR) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth, typically 20 Hz to 20 kHz. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. DS749A1 19 CS4412 7. PACKAGE DIMENSIONS 48L QFN (9 × 9 MM BODY) PACKAGE DRAWING D b e Pin #1 ID Pin #1 ID E E2 A1 A Top View Side View L D2 Bottom View DIM A A1 b D D2 E E2 e L MIN -0.0000 0.0118 0.2618 0.2618 0.0177 INCHES NOM --0.0138 0.3543 BSC 0.2677 0.3543 BSC 0.2677 0.0256 BSC 0.0217 MAX 0.0354 0.0020 0.0157 0.2736 0.2736 0.0276 MIN -0.00 0.30 6.65 6.65 0.45 MILLIMETERS NOM --0.35 9.00 BSC 6.80 9.00 BSC 6.80 0.65 BSC 0.55 NOTE MAX 0.90 0.05 0.40 6.95 6.95 0.70 1 1 1,2 1 1 1 1 1 1 JEDEC #: MO-220 Controlling Dimension is Millimeters. Notes: 1. Dimensioning and tolerance per ASME Y4.5M - 1994. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. 20 DS749A1 CS4412 8. THERMAL CHARACTERISTICS Parameter Junction to Case Thermal Impedance Symbol θJC Min - Typ 1 Max - Units °C/Watt 8.1 Thermal Flag This device is designed to have the metal flag on the bottom of the device soldered directly to a metal plane on the PCB. To enhance the thermal dissipation capabilities of the system, this metal plane should be coupled with vias to a large metal plane on the backside (and inner ground layer, if applicable) of the PCB. In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those immediately surrounding the CS4412. In addition to improving in electrical performance, this practice also aids in heat dissipation. The heat dissipation capability required of the metal plane for a given output power can be calculated as follows: θCA = [(TJ(MAX) - TA) / PD] - θJC where, θCA = Thermal resistance of the metal plane in °C/Watt TJ(MAX) = Maximum rated operating junction temperature in °C, equal to 150 °C TA = Ambient temperature in °C PD = RMS power dissipation of the device, equal to 0.15*PRMS-IN or 0.176*PRMS-OUT (assuming 85% efficiency) θJC = Junction-to-case thermal resistance of the device in °C/Watt DS749A1 21 CS4412 9. ORDERING INFORMATION Product CS4412 Description 30 W Quad HalfBridge Digital Amplifier Power Stage 1 x 30 W Reference Design Daughter Card 2 x 15 W Reference Design Main Board Package 48-QFN Pb-Free Grade Temp Range Container Rail -40° to +70°C Tape and Reel - Order# CS4412-CNZ CS4412-CNZR Yes Commercial CRD4412 - - - - CRD4412 CRD4525 - - - - - CRD4525 10.REVISION HISTORY Release A1 Initial Release Changes Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 22 DS749A1