CRD4412A

CS4412A 30 W Quad Half-Bridge Digital Amplifier Power Stage Features Configurable Outputs (10% THD+N) – 2 x 15 W into 8 Ω, Full-Bridge – 1 x 30 W into 4 Ω, Parallel Full-Bridge – 4 x 7 W into 4 Ω, Half-Bridge – 2 x 7 W into 4 Ω, Half-Bridge + 1 x 15 W into 8 Ω, Full-Bridge Space-Efficient Thermally-Enhanced QFN – No External Heat Sink Required > 100 dB Dynamic Range - System Level < 0.1% THD+N @ 1 W - System Level Built-In Protection with Error Reporting – Over-Current – Thermal Warning and Overload – Under-Voltage +8 V to +18 V High Voltage Supply PWM Popguard® for Quiet Startup No Bootstrap Required Low Quiescent Current Low Power Standby Mode Common Applications Integrated Digital Televisions Portable Media Player Docking Stations Mini/Micro Shelf Systems Powered Desktop Speakers General Description The CS4412A is a high-efficiency power stage for digital Class-D amplifiers designed to input PWM signals from a modulator such as the CS4525. The power stage outputs can be configured as four half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge channels, or one parallel full-bridge channel. The CS4412A integrates on-chip over-current, undervoltage, over-temperature protection and error reporting as well as a thermal warning indicator. The low RDS(ON) outputs can source up to 2.5 A peak current, delivering high efficiency which allows small device package and lower power supplies. The CS4412A is available in a 48-pin QFN package in Commercial grade (-10 to +70° C). The CRD4412A customer reference design is also available. Please refer to “Ordering Information” on page 24 for complete ordering information. 8 V to 18 V VP 2.5 V to 5 V In 1 In 2 In 3 In 4 Reset Hardware Configuration Current & Thermal Data Mode Configuration Non-Overlap Time Insertion Non-Overlap Time Insertion Gate Drive Gate Drive Amplifier Out 1 Amplifier Out 2 Control Logic Non-Overlap Time Insertion Gate Drive Amplifier Out 3 Amplifier Out 4 PGND Protection & Error Reporting Non-Overlap Time Insertion Gate Drive Advance Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) MAY '07 DS786A1 CS4412A TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 3 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5 RECOMMENDED OPERATING CONDITIONS .................................................................................... 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 5 PWM POWER OUTPUT CHARACTERISTICS ..................................................................................... 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 DIGITAL INTERFACE SPECIFICATIONS ............................................................................................. 7 DIGITAL I/O PIN CHARACTERISTICS ................................................................................................. 8 3. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 9 4. APPLICATIONS ................................................................................................................................... 13 4.1 Overview ........................................................................................................................................ 13 4.2 Reset and Power-Up ...................................................................................................................... 13 4.2.1 PWM Popguard Transient Control ........................................................................................ 13 4.2.2 Initial Pulse Edge Delay ........................................................................................................ 14 4.2.3 Recommended Power-Up Sequence .................................................................................... 14 4.2.4 Recommended Power-Down Sequence ............................................................................... 14 4.3 Output Mode Configuration ............................................................................................................ 15 4.4 Output Filters ................................................................................................................................. 16 4.4.1 Half-Bridge Output Filter ........................................................................................................ 16 4.4.2 Full-Bridge Output Filter (Stereo or Parallel) ......................................................................... 18 4.5 Device Protection and Error Reporting .......................................................................................... 19 4.5.1 Over-Current Protection ........................................................................................................ 19 4.5.2 Thermal Warning, Thermal Error, and Under-Voltage Error ................................................. 19 5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT ....................................................................... 20 5.1 Power Supply and Grounding ........................................................................................................ 20 5.1.1 Integrated VD Regulator ........................................................................................................ 20 5.2 QFN Thermal Pad .......................................................................................................................... 20 6. PARAMETER DEFINITIONS ................................................................................................................ 21 7. PACKAGE DIMENSIONS .................................................................................................................... 22 8. THERMAL CHARACTERISTICS ......................................................................................................... 23 8.1 Thermal Flag .................................................................................................................................. 23 9. ORDERING INFORMATION ................................................................................................................ 24 10. REVISION HISTORY .......................................................................................................................... 24 LIST OF FIGURES Figure 1.Stereo Full-Bridge Typical Connection Diagram ........................................................................... 9 Figure 2.2.1 Channel Typical Connection Diagram .................................................................................. 10 Figure 3.4 Channel Half-Bridge Typical Connection Diagram .................................................................. 11 Figure 4.Parallel Full-Bridge Typical Connection Diagram ....................................................................... 12 Figure 5.Output Filter - Half-Bridge ........................................................................................................... 16 Figure 6.Output Filter - Full-Bridge ............................................................................................................ 18 LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Typical Ramp Times for Typical VP Voltages ............................................................................. 13 Table 3. Output Mode Configuration Options ............................................................................................ 15 Table 4. Low-Pass Filter Components - Half-Bridge ................................................................................. 16 Table 5. DC-Blocking Capacitors Values - Half-Bridge ............................................................................. 17 Table 6. Low-Pass Filter Components - Full-Bridge ................................................................................. 18 Table 7. Over-current Error Conditions ..................................................................................................... 19 Table 8. Thermal and Under-Voltage Error Conditions ............................................................................. 19 Table 9. Power Supply Configuration and Settings ................................................................................... 20 2 DS786A1 CS4412A 1. PIN DESCRIPTION ERROC12 ERRUVTE ERROC34 RST34 RAMP PGND PGND 39 PGND 38 48 47 46 45 44 43 42 41 40 CNFG0 CNFG1 CNFG2 IN1 IN2 IN3 IN4 RST12 LVD GND VD_REG VD PGND 37 TWR GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Top-Down (Through Package) View 48-Pin QFN Package 36 35 34 33 32 31 30 29 28 27 26 25 VP OUT1 PGND PGND OUT2 VP VP OUT3 PGND PGND OUT4 VP Thermal Pad OCREF GND GND GND GND GND GND GND GND PGND PGND Pin Name CNFG0 CNFG1 CNFG2 IN1 IN2 IN3 IN4 RST12 RST34 LVD VD_REG VD OCREF Pin # 1 2 3 4 5 6 7 8 46 9 11 12 21 Pin Description Out Configuration Select (Input) - Used to set the PWM output configuration mode. See “Output Mode Configuration” on page 15. PWM Input (Input) - Logic-level switching inputs from a PWM modulator. Reset Input (Input) - Reset inputs for channels 1/2 and 3/4 respectively. Active low. VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying 5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, LVD must be GND. Core Digital Power (Output) - Internally generated low voltage power supply for digital logic. Digital Power (Input) - Positive power supply for the internal regulators and digital I/O. Over-current Reference (Input) - Sets over-current trigger level. Connect pin through a resistor to GND. See “Device Protection and Error Reporting” on page 19. This pins should not be left floating. DS786A1 RAMP_CAP 3 CS4412A Pin Name RAMP_CAP Pin # 24 10,13 14,15 16,17 18,19 20,47 48 25,30 31,36 22,23 27,28 33,34 37,38 39,40 26 29 32 35 41 42 43 44 45 - Pin Description Output Ramp Capacitor (Input) - Used by the PWM PopGuard Transient Control to suppress the initial pop in half-bridge-configured outputs. GND Ground (Input) - Ground for the internal logic and I/O. These pins should be connected to the common system ground. VP High Voltage Output Power (Input) - High voltage power supply for the individual output power half-bridge devices. Power Ground (Input) - Ground for the individual output power half-bridge devices. These pins should be connected to the common system ground. PGND OUT4 OUT3 OUT2 OUT1 TWR ERRUVTE ERROC12 ERROC34 RAMP Thermal Pad PWM Output (Output) - Amplified PWM power outputs. Thermal Warning Output (Output) - Thermal warning output. Open drain, active low. See “Device Protection and Error Reporting” on page 19. Thermal and Under-voltage Error Output (Output) - Error flag for thermal shutdown and undervoltage. Open drain, active low. See “Device Protection and Error Reporting” on page 19 Over-current Error Output (Output) - Over-current error flag for the associated outputs. Open drain, active low. See “Device Protection and Error Reporting” on page 19. Ramp-up/down Select (Input) - Set high to enable ramping. When set low, ramping is disabled. See “PWM Popguard Transient Control” on page 13. Thermal Pad - Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 20 for more information. 4 DS786A1 CS4412A 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = PGND = 0 V, all voltages with respect to ground. Parameters DC Power Supply Digital Core VD VD VD Power Stage Temperature Ambient Temperature Junction Temperature Commercial TA TJ -10 -10 +70 +125 °C °C VP 2.375 3.135 4.75 8.0 2.5 3.3 5.0 2.625 3.465 5.25 18.0 V V V V Symbol Min Nom Max Units ABSOLUTE MAXIMUM RATINGS GND = PGND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Power Stage Power Stage Digital Core Inputs Input Current Digital Input Voltage Temperature Ambient Operating Temperature - Power Applied Commercial Storage Temperature TA Tstg -20 -65 +85 +150 °C °C (Note 1) (Note 2) Iin VIND -0.3 ±10 VD + 0.4 mA V Outputs Switching and Under Load No Output Switching VP VP VD -0.3 -0.3 -0.3 19.8 23.0 6.0 V V V Symbol Min Max Units WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the PWM input pins will not cause SCR latch-up. 2. The maximum over/under voltage is limited by the input current. DS786A1 5 CS4412A PWM POWER OUTPUT CHARACTERISTICS Test Conditions (unless otherwise specified): GND = PGND = 0 V; All voltages with respect to ground; TA = 25° C; VD = 3.3 V; VP = 18 V; RL = 8 Ω for full-bridge, RL = 4 Ω for half-bridge and parallel full-bridge; PWM Switch Rate = 384 kHz; 10 Hz to 20 kHz Measurement Bandwidth; Input source is CS4525 PWM_SIG outputs; Performance measurements taken with a full-scale 997 Hz sine wave, an AES17 measurement filter; Half-Bridge measurements taken through the Half-Bridge Output Filter shown in Figure 5; Stereo Full-Bridge and Parallel FullBridge measurements taken through the Full-Bridge Output Filter shown in Figure 6;. Parameters Power Output per Channel Stereo Full-Bridge Half-Bridge Parallel Full-Bridge Total Harmonic Distortion + Noise Stereo Full-Bridge Half-Bridge THD+N Parallel Full-Bridge Dynamic Range Stereo Full-Bridge Half-Bridge Parallel Full-Bridge MOSFET On Resistance Efficiency Minimum Output Pulse Width Rise Time of OUTx Fall Time of OUTx PWM Output Over-Current Error Trigger Point ICE Junction Thermal Warning Trigger Point Junction Thermal Error Trigger Point VP Under-Voltage Error Falling Trigger Point VP Under-Voltage Error Rising Trigger Point TTW TTE VUVFALL VUVRISE TA = 25°C TA = 25°C RDS(ON) h PWmin tr tf DYR PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted Id = 0.5 A, TJ = 50°C PO = 2 x 15 W, RL = 8 Ω No Load Resistive Load Resistive Load TA = 25°C, OCREF = 16.2 kΩ TA = 25°C, OCREF = 18 kΩ TA = 25°C, OCREF = 22 kΩ 102 99 102 99 102 99 280 85 50 20 20 2.5 2.1 1.7 105 125 4.7 4.95 4.9 5.4 dB dB dB dB dB dB mΩ % ns ns ns A A A °C °C V V PO THD+N < 10% THD+N < 1% THD+N < 10% THD+N < 1% THD+N < 10% THD+N < 1% PO = 1 W PO = 0 dBFS = 11.3 W PO = 1 W PO = 0 dBFS = 5.0 W PO = 1 W PO = 0 dBFS = 22.6 W 15 12 7 5.5 30 23.5 0.05 0.10 0.12 0.28 0.1 0.3 W W W W W W % % % % % % Symbol Conditions Min Typ Max Units 6 DS786A1 CS4412A DC ELECTRICAL CHARACTERISTICS GND = PGND = 0 V; All voltages with respect to ground; PWM switch rate = 384 kHz; Unless otherwise specified. Parameters Normal Operation Power Supply Current Power Dissipation Power-Down Mode Power Supply Current VD_REG Characteristics Nominal Voltage DC current source 2.25 2.5 2.75 3 V mA (Notes 3, 5) VD = 3.3 V VD = 3.3 V (Note 4) VD = 3 .3 V 2 mA 20 66 mA mW Min Typ Max Units Notes: 3. Normal operation is defined as RST12 and RST34 = HI. 4. Power-Down Mode is defined as RST12 and RST34 = LOW with all input lines held static. 5. Power supply current increases with increasing PWM switching rates. DIGITAL INTERFACE SPECIFICATIONS GND = PGND = 0 V; All voltages with respect to ground; Unless otherwise specified. Parameters High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Input Leakage Current Input Capacitance Io = 2 mA Symbol VIH VIL VOH Iin Min 0.7*VD_REG 0.90*VD - Max VD 0.20*VD_REG ±10 8 Units V V V μA pF DS786A1 7 CS4412A DIGITAL I/O PIN CHARACTERISTICS The logic level for each input is set by its corresponding power supply and should not exceed the maximum ratings. Power Pin Supply Number VD 1 2 3 4 5 6 7 8 9 41 42 43 44 45 46 VP 35 32 29 26 Pin Name CNFG0 CNFG1 CNFG2 IN1 IN2 IN3 IN4 RST12 LVD TWR ERRUVTE ERROC12 ERROC34 RAMP RST34 OUT1 OUT2 OUT3 OUT4 I/O Input Input Input Input Input Input Input Input Input Output Output Output Output Input Input Output Output Output Output Driver 2.5 V - 5.0 V, Open Drain 2.5 V - 5.0 V, Open Drain 2.5 V - 5.0 V, Open Drain 2.5 V - 5.0 V, Open Drain 8 V - 18 V Power MOSFET 8 V - 18 V Power MOSFET 8 V - 18 V Power MOSFET 8 V - 18 V Power MOSFET Table 1. I/O Power Rails Receiver 2.5 V - 5.0 V 2.5 V - 5.0 V 2.5 V - 5.0 V 2.5 V - 5.0 V 2.5 V - 5.0 V 2.5 V - 5.0 V 2.5 V - 5.0 V 2.5 V - 5.0 V 2.5 V - 5.0 V 2.5 V - 5.0 V 2.5 V - 5.0 V - 8 DS786A1 CS4412A 3. TYPICAL CONNECTION DIAGRAMS +3.3 V or +5.0 V 10 µF 0.1 µF 470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 470 µF +8 V to +18 V * 12 25 30 31 36 VD VP VP VP VP Ch1_PWM Ch2_PWM 4 5 6 7 IN1 IN2 IN3 IN4 RAMP_CAP 24 * Since ramping is disabled for fullbridge applications, this capacitor can be omitted and RAMP_CAP can be connected directly to VP. CS4412A OUT1 35 See Section 4.2.1 for details. VD 1 2 CNFG0 CNFG1 CNFG2 LVD RAMP OUT2 32 Full-Bridge Output Filter See Figure 6. Channel 1 Audio Output Connect LVD to : VD if VD = 5 V GND if VD = 3.3 V 3 9 45 See Section 5.1.1 for details. OUT3 29 VD 22 kΩ 22 kΩ 22 kΩ 22 kΩ Full-Bridge Output Filter ERROC12 ERROC34 ERRUVTE TWR RST12 RST34 GND 10 GND 13 GND 14 OUT4 26 Channel 2 Audio Output 43 44 See Figure 6. System Control Logic 42 41 8 46 11 10 µF 0.1 µF VD_REG GND 15 GND 16 GND 17 GND 18 16.2 kΩ GND 19 21 OCREF GND 20 GND 47 Thermal Pad GND 48 22 DS786A1 PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D 23 27 28 33 34 37 38 39 40 Figure 1. Stereo Full-Bridge Typical Connection Diagram 9 CS4412A +3.3 V or +5.0 V 10 µF 0.1 µF 470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 470 µF +8 V to +18 V 33 nF 12 25 30 31 36 VD VP VP VP RAMP_CAP 24 Ch1_PWM Ch2_PWM Ch3_PWM 4 5 6 7 IN1 IN2 IN3 IN4 OUT1 35 VP CS4412A Half-Bridge Output Filter See Figure 5. Channel 1 Audio Output VD 1 2 CNFG0 CNFG1 CNFG2 LVD RAMP OUT2 32 Connect LVD to : VD if VD = 5 V GND if VD = 3.3 V 3 9 45 Half-Bridge Output Filter See Figure 5. See Section 5.1.1 for details. Channel 2 Audio Output VD 22 kΩ 22 kΩ 22 kΩ 22 kΩ 43 44 ERROC12 ERROC34 ERRUVTE TWR RST12 RST34 OUT3 29 System Control Logic 42 41 8 46 Full-Bridge Output Filter OUT4 26 GND 10 Channel 3 Audio Output See Figure 6. 11 10 µF 0.1 µF VD_REG GND 13 GND 14 GND 15 GND 16 GND 17 GND 18 16.2 k Ω GND 19 21 OCREF GND 20 GND 47 Thermal Pad GND 48 22 10 PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D 23 27 28 33 34 37 38 39 40 Figure 2. 2.1 Channel Typical Connection Diagram DS786A1 CS4412A +3.3 V or +5.0 V 10 µF 0.1 µF 470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 470 µF +8 V to +18 V 33 nF 12 25 30 31 36 VD VP VP VP RAMP_CAP 24 Ch1_PWM Ch2_PWM Ch3_PWM Ch4_PWM 4 5 6 7 IN1 IN2 IN3 IN4 OUT1 35 VP Half-Bridge Output Filter See Figure 5. CS4412A Channel 1 Audio Output VD 1 2 CNFG0 CNFG1 CNFG2 LVD RAMP OUT2 32 Connect LVD to : VD if VD = 5 V GND if VD = 3.3 V 3 9 45 Half-Bridge Output Filter See Figure 5. Channel 2 Audio Output See Section 5.1.1 for details. VD 22 kΩ 22 kΩ 22 kΩ 22 kΩ OUT3 29 ERROC12 ERROC34 ERRUVTE TWR RST12 RST34 OUT4 26 GND 10 Half-Bridge Output Filter See Figure 5. 43 44 Channel 3 Audio Output System Control Logic 42 41 8 46 Half-Bridge Output Filter See Figure 5. Channel 4 Audio Output 11 10 µF 0.1 µF VD_REG GND 13 GND 14 GND 15 GND 16 GND 17 GND 18 16.2 k Ω GND 19 21 OCREF GND 20 GND 47 Thermal Pad GND 48 22 Figure 3. 4 Channel Half-Bridge Typical Connection Diagram DS786A1 PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D 23 27 28 33 34 37 38 39 40 11 CS4412A +3.3 V or +5.0 V 10 µF 0.1 µF 470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF +8 V to +18 V 470 µF * 12 25 30 31 36 VD VP VP VP VP RAMP_CAP 24 PWM 4 5 6 7 IN1 IN2 IN3 IN4 * Since ramping is disabled for fullbridge applications, this capacitor can be omitted and RAMP_CAP can be connected directly to VP. See Section 4.2.1 for details. CS4412A VD 1 2 CNFG0 CNFG1 CNFG2 LVD RAMP OUT3 29 OUT4 26 OUT1 35 OUT2 32 Connect LVD to : VD if VD = 5 V GND if VD = 3.3 V 3 9 45 See Section 5.1.1 for details. Full-Bridge Output Filter See Figure 6. Audio Output VD 22 kΩ 22 kΩ 22 kΩ 43 44 ERROC12 ERROC34 ERRUVTE TWR RST12 RST34 GND 10 GND 13 GND 14 GND 15 System Control Logic 42 41 8 46 11 10 µF 0.1 µF VD_REG GND 16 GND 17 GND 18 16.2 k Ω GND 19 21 OCREF GND 20 GND 47 Thermal Pad GND 48 22 12 PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D PG N D 23 27 28 33 34 37 38 39 40 Figure 4. Parallel Full-Bridge Typical Connection Diagram DS786A1 CS4412A 4. APPLICATIONS 4.1 Overview The CS4412A is a high-efficiency power stage for digital Class-D amplifiers designed to be configured as four half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge channels, or one parallel full-bridge channel. The CS4412A integrates on-chip over-current, under-voltage, over-temperature protection and error reporting as well as a thermal warning indicator. The low RDS(ON) outputs can source up to 2.5 A peak current, delivering 85% efficiency. This efficiency provides for smaller device package, no external heat sink requirements, and smaller power supplies. 4.2 Reset and Power-Up Reliable power-up can be accomplished by keeping the device in reset until the power supplies and configuration pins are stable. It is also recommended that the RST12 and RST34 pins be activated if the voltage supplies drop below the recommended operating condition to prevent power-glitch related issues. When the RST12 or RST34 are low, the corresponding channels of the CS4412A enter a low-power mode; all of the channels’ internal states are reset and the corresponding power output pins are held in a highimpedance state. When RST12 or RST34 are high, the corresponding outputs will begin normal operation according to the RAMP, CNFG[2:0], and IN1 - IN4 pins. 4.2.1 PWM Popguard Transient Control The CS4412A uses PWM Popguard technology to minimize the effects of output transients during powerup and power-down for half-bridge configurations. This technique reduces the audio transients commonly produced by half-bridge, single-supply amplifiers when implemented with external DC-blocking capacitors connected in series with the audio outputs. When the device is configured for ramping (RAMP set high) and RST12 or RST34 is set high, the corresponding power outputs will ramp-up to the bias point (VP/2). This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up transient. The corresponding outputs will not begin normal operation until the ramp has reached the bias point. The time it takes to complete a ramp-up sequence will vary slightly from the applied VP voltage; typical ramp-up speeds achieved with a 1000 μF DC blocking capacitor are listed in Table 2. These times will scale with the value of the capacitor. VP Voltage 12 V 15 V 18 V Typical Ramp Time* 1.25 seconds 0.95 seconds 0.80 seconds * With 1000 μF DC Blocking Capacitor. Table 2. Typical Ramp Times for Typical VP Voltages DS786A1 13 CS4412A When the device is configured for ramping (RAMP set high) and RST12 or RST34 is set low, the corresponding outputs will begin to slowly ramp down from the bias point to PGND, allowing the DC-blocking capacitor to discharge. The ramp feature is intended for use with half-bridge outputs. For “2.1 channel” applications with stereo half-bridge and mono full-bridge (CNFG[2:0] = 001 or 101), the ramp will only be applied to OUT1 and OUT2 (the half-bridge channels); OUT3 and OUT4 (the full-bridge channel) will not ramp. The ramp feature requires a 33 nF capacitor on the RAMP_CAP pin to VP. For applications that do not enable the ramping feature, RAMP_CAP can be connected directly to VP. It is not necessary to complete a ramp-up/down sequence before ramping up/down again. 4.2.2 Initial Pulse Edge Delay After RST12 or RST34 is released, the CS4412A will continue to hold the corresponding power output pins in a high-impedance state until a pulse edge is sensed on a corresponding PWM input pin. This is done to prevent a possible DC output condition on the speakers if the PWM inputs are not yet modulating immediately following the release of the corresponding reset signal. This initial transition delay is independent for each input/output pin pair; each output corresponding to an inactive input will remain in a highimpedance state until its input receives a pulse edge even if other inputs are activated. The pulse edge must be from a digital low state to a digital high state. Once a pulse edge is detected, the corresponding output pin will activate and switch as dictated by the output mode configuration as described in section 4.3 on page 15 until either an error condition is detected or until its reset pin is set low. If the outputs are configured for ramping the CS4412A will perform a ramp-up sequence on OUT1/2 immediately following the release of RST12 and a ramp sequence on OUT3/4 immediately following the release of RST34. See section 4.2.1 on page 13 for more information on output ramping. If a pulse edge is detected on an input before the ramp-up sequence finishes on its corresponding output pin, the CS4412A will continue the ramp sequence and begin normal output operation immediately following its completion. If a pulse edge is not detected on an input by the time the ramp-up sequence has finished on its corresponding output pin, the output pin will be placed into and remain in a high-impedance state until a pulse edge is detected on the corresponding input. 4.2.3 Recommended Power-Up Sequence 1. Turn on the system power. 2. Hold RST12 and RST34 low until the power supply is stable. In this state, all associated outputs are held in a high-impedance state. 3. Release RST12 and RST34 high. 4. Start the PWM modulator output. 4.2.4 Recommended Power-Down Sequence 1. Mute the logic-level PWM inputs present on IN1 - IN4 by applying 50 % duty-cycle input signals. 2. Hold RST12 and RST34 low. 3. Power down the remainder of the system. 14 DS786A1 CS4412A 4.3 Output Mode Configuration Each OUTx pin will switch in association with the corresponding INx pin. For most configurations, OUTx will be non-inverted from INx; however, some INx pins can be configured for internal inversion to allow one PWM input to drive both the positive and negative sides of a full-bridge output. Unused OUTx pins must have their corresponding INx pin tied to ground. Table 3 shows the setting of the CNFG[2:0] inputs and the corresponding mode of operation. These pins should remain static during operation (RST12 or RST34 set high). CNFG2 CNFG1 CNFG0 Description Necessary Input Connections IN1 must provide the PWM data for the first full-bridge. Stereo Full-Bridge IN2 must be inverted from IN1 for full-bridge operation. 0 0 0 Tied Loads IN3 must provide the PWM data for the second full-bridge. IN4 must be inverted from IN3 for full-bridge operation. IN1 must provide the PWM data for the first half-bridge. Stereo Half-Bridge IN2 must provide the PWM data for the second half-bridge. 0 0 1 & Mono Full-Bridge IN3 must provide the PWM data for the mono full-bridge. Tied Loads* IN4 must be inverted from IN3 for full-bridge operation. IN1 must provide the PWM data for the mono full-bridge. Mono Parallel Full- IN2 must be wired directly to IN1 for parallel full-bridge operation. 0 1 0 Bridge Tied Load IN3 must be inverted from IN1 for parallel full-bridge operation. IN4 must be wired to IN3 for parallel full-bridge operation. IN1 must provide the PWM data for the first half-bridge. Quad Half-Bridge IN2 must provide the PWM data for the second half-bridge. 0 1 1 Tied Loads IN3 must provide the PWM data for the third half-bridge. IN4 must provide the PWM data for the fourth half-bridge. IN1 must provide the PWM data for the first full-bridge. Stereo Full-Bridge IN2 must be wired to IN1; the CS4412A will internally invert IN2. 1 0 0 Tied Loads IN3 must provide the PWM data for the second full-bridge. With Inversion IN4 must be wired to IN3; the CS4412A will internally invert IN4. Stereo Half-Bridge IN1 must provide the PWM data for the first half-bridge. & Mono Full-Bridge IN2 must provide the PWM data for the second half-bridge. 1 0 1 Tied Loads IN3 must provide the PWM data for the mono full-bridge. With Inversion* IN4 must be wired to IN3; the CS4412A will internally invert IN4. IN1 must be provided for half-bridge operation. Mono Parallel FullIN2 must be wired to IN1 for parallel full-bridge operation. 1 1 0 Bridge Tied Load IN3 must be wired to IN1; the CS4412A will internally invert IN3. With Inversion IN4 must be wired to IN1; the CS4412A will internally invert IN4. 1 1 1 Reserved The input connections are not applicable. * PWM Popguard Transient Control only affects OUT1 and OUT2. Table 3. Output Mode Configuration Options In Stereo Half-Bridge & Mono Full-Bridge configurations, the PWM Popguard Transient Control will only affect the two half-bridge outputs, OUT1 and OUT2. The full-bridge output will not ramp regardless of the state of the RAMP pin. See Section 4.2.1 on page 13 for more details about PWM Popguard Transient Control. DS786A1 15 CS4412A 4.4 Output Filters The filter placed after the PWM outputs can greatly affect the output performance. The filter not only reduces radiated EMI (snubber filter), but also filters high frequency content from the switching output before going to the speaker (low-pass LC filter). 4.4.1 Half-Bridge Output Filter Figure 5 shows the output filter for a half-bridge configuration. The transient-voltage suppression circuit (snubber circuit) is comprised of a resistor (20 Ω, ¼ W) and capacitors (220 pF) and should be placed as close as possible to the corresponding PWM output pin to greatly reduce radiated EMI. Each output pin must be connected to two Schottky diodes—one to ground and one to the VP supply. These diodes should be placed within 12 mm of the corresponding OUTx pin. The requirements of this diode are: 1. Rated IF (average rectifier forward current) is greater than or equal to 1.0 A. 2. Support up to 80° C of lead temperature with VF drop (forward voltage) less than or equal to 480 mV at the corresponding IF. 3. VR (reverse voltage) is greater than or equal to 20 V. VP L1 OUTx 20 Ω 220 pF *Diode is Rohm RB160M-30 or equivalent + C2 - C1 Figure 5. Output Filter - Half-Bridge The inductor, L1, and capacitor, C1, comprise the low-pass filter. Along with the nominal load impedance of the speaker, these values set the cutoff frequency of the filter. Table 4 shows the component values for L1 and C1 based on nominal speaker (load) impedance for a corner frequency (-3 dB point) of approximately 35 kHz. Load 4Ω 6Ω 8Ω L1 22 µH 33 µH 47 µH C1 1.0 µF 0.68 µF 0.47 µF Table 4. Low-Pass Filter Components - Half-Bridge 16 DS786A1 CS4412A C2 is the DC-blocking capacitor. Table 5 shows the component values for C2 based on corner frequency (-3 dB point) and a nominal speaker (load) impedances of 4 Ω, 6 Ω, and 8 Ω. This capacitor should also be chosen to have a ripple current rating above the amount of current that will passed through it. Load 4Ω Corner Frequency 40 Hz 58 Hz 120 Hz 39 Hz 68 Hz 120 Hz 42 Hz 60 Hz 110 Hz C2 1000 µF 680 µF 330 µF 680 µF 390 µF 220 µF 470 µF 330 µF 180 µF 6Ω 8Ω Table 5. DC-Blocking Capacitors Values - Half-Bridge DS786A1 17 CS4412A 4.4.2 Full-Bridge Output Filter (Stereo or Parallel) Figure 6 shows the output filter for a full-bridge configuration. The transient-voltage suppression circuit (snubber circuit) is comprised of a resistor (20 Ω) and capacitor (330 pF) and should be placed as close as possible to the corresponding PWM output pins to greatly reduce radiated EMI. The inductors, L1 and L2, and capacitor, C1, comprise the low-pass filter. Along with the nominal load impedance of the speaker, these values set the cutoff frequency of the filter. Table 6 shows the component values based on nominal speaker (load) impedance for a corner frequency (-3 dB point) of approximately 35 kHz. Each output pin must be connected to two Schottky diodes—one to ground and one to the VP supply. These diodes should be placed within 12 mm of the corresponding OUTx pin. The requirements of this diode are: 1. Rated IF (average rectifier forward current) is greater than or equal to 1.0 A. 2. Support up to 80° C of lead temperature with VF drop (forward voltage) less than or equal to 480 mV at the corresponding IF. 3. VR (reverse voltage) is greater than or equal to 20 V. VP L1 OUTX+ *Diode is Rohm RB160M-30 or equivalent 20 Ω 330 pF C1 VP L2 OUTX- Figure 6. Output Filter - Full-Bridge Load 4Ω 6Ω 8Ω L1, L2 10 µH 15 µH 22 µH C1 1.0 µF 0.47 µF 0.47 µF Table 6. Low-Pass Filter Components - Full-Bridge 18 DS786A1 CS4412A 4.5 Device Protection and Error Reporting The CS4412A has built-in protection circuitry for over-current, under-voltage, and thermal warning/overload conditions. The levels of the over-current error, thermal error, and VP under-voltage trigger points are listed in the PWM Power Output Characteristics table on page 6. Automatic shut-down will occur whenever any of these preset thresholds other than thermal warning are crossed. Each error and warning pin implements an active-low open-drain driver and requires an external 22 kΩ pull-up resistor for proper operation. 4.5.1 Over-Current Protection An over-current error condition will occur if the peak output current exceeds the Over-Current Error trigger point. Over-current errors for OUT1/2 and OUT3/4 are reported on the ERROC12 and ERROC34 pins respectively. The power output of the channel which is reporting the over-current condition will be set to high-impedance until the error condition has been removed and the reset signal for that channel has been toggled from low to high. ERROCxy 0 1 Reported Condition Over-current error on channel x or channel y. Operating current of channel x and y within allowable limits. Table 7. Over-current Error Conditions 4.5.2 Thermal Warning, Thermal Error, and Under-Voltage Error Table 8 shows the behavior of the TWR and ERRUVTE pins. When the junction temperature exceeds the junction thermal warning trigger point, the TWR pin will be set low. If the junction temperature continues to increase beyond the junction thermal error trigger point, the ERRUVTE pin will be set low. If the voltage on VP falls below the VP under-voltage error trigger point, ERRUVTE will be set low. When the thermal error or VP under-voltage trigger point is crossed, all power outputs will be set in a highimpedance state until the error condition has been removed and both the RST12 and RST34 signals have been toggled from low to high. TWR 0 0 1 1 ERRUVTE 0 1 0 1 Reported Condition Thermal warning and thermal error and/or under-voltage error. Thermal warning only. Under-voltage error. Junction temperature and VP voltage within normal limits. Table 8. Thermal and Under-Voltage Error Conditions DS786A1 19 CS4412A 5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT 5.1 Power Supply and Grounding The CS4412A requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. It is necessary to decouple the power supply by placing capacitors directly between the power and ground of the CS4412A. Decoupling capacitors should be as close to the pins of the CS4412A as possible. The lowest value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS4412A to minimize inductance effects. The CRD4412A reference design demonstrates the optimum layout and power supply arrangements. 5.1.1 Integrated VD Regulator The CS4412A includes an internal linear regulator to provide a fixed 2.5 V supply from the VD supply voltage for its internal digital logic. The LVD pin must be set to indicate the voltage present on the VD pin as shown in Table 9 below. VD Connection 5 V Supply 3.3 V Supply 2.5 V Supply VD_REG Connection Bypass Capacitors Only Bypass Capacitors Only VD and Bypass Capacitors LVD Connection VD GND GND Table 9. Power Supply Configuration and Settings The output of the digital regulator is presented on the VD_REG pin and may be used to provide an external device with up to 3 mA of current at its nominal output voltage of 2.5 V. If a nominal supply voltage of 2.5 V is used as the VD supply (see the Recommended Operating Conditions table on page 5), the VD and VD_REG must be connected to the VD supply source. In this configuration, the internal regulator is bypassed and the external supply source is used to directly drive the internal digital logic. 5.2 QFN Thermal Pad The CS4412A is available in a compact QFN package. The underside of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of thermal vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers; the copper in these ground planes will act as a heat sink for the CS4412A. The CRD4412A reference design demonstrates the optimum thermal pad and via configuration. 20 DS786A1 CS4412A 6. PARAMETER DEFINITIONS Dynamic Range (DYR) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth, typically 20 Hz to 20 kHz. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. DS786A1 21 CS4412A 7. PACKAGE DIMENSIONS 48L QFN (9 × 9 MM BODY) PACKAGE DRAWING D b e Pin #1 ID Pin #1 ID E E2 A1 A Top View Side View L D2 Bottom View INCHES DIM A A1 b D D2 E E2 e L 0.0177 0.2618 0.2618 MIN -0.0000 0.0118 NOM --0.0138 0.3543 BSC 0.2677 0.3543 BSC 0.2677 0.0256 BSC 0.0217 0.0276 0.45 JEDEC #: MO-220 Controlling Dimension is Millimeters. Notes: 1. Dimensioning and tolerance per ASME Y4.5M - 1994. 0.2736 6.65 0.2736 6.65 MAX 0.0354 0.0020 0.0157 MIN -0.00 0.30 MILLIMETERS NOM --0.35 9.00 BSC 6.80 9.00 BSC 6.80 0.65 BSC 0.55 0.70 6.95 6.95 MAX 0.90 0.05 0.40 NOTE 1 1 1,2 1 1 1 1 1 1 2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. 22 DS786A1 CS4412A 8. THERMAL CHARACTERISTICS Parameter Junction to Case Thermal Impedance Symbol θJC Min - Typ 1 Max - Units °C/Watt 8.1 Thermal Flag This device is designed to have the metal flag on the bottom of the device soldered directly to a metal plane on the PCB. To enhance the thermal dissipation capabilities of the system, this metal plane should be coupled with vias to a large metal plane on the backside (and inner ground layer, if applicable) of the PCB. In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those immediately surrounding the CS4412A. In addition to improving in electrical performance, this practice also aids in heat dissipation. The heat dissipation capability required of the metal plane for a given output power can be calculated as follows: θCA = [(TJ(MAX) - TA) / PD] - θJC where, θCA = Thermal resistance of the metal plane in °C/Watt TJ(MAX) = Maximum rated operating junction temperature in °C, equal to 150 °C TA = Ambient temperature in °C PD = RMS power dissipation of the device, equal to 0.15*PRMS (assuming 85% efficiency) θJC = Junction-to-case thermal resistance of the device in °C/Watt DS786A1 23 CS4412A 9. ORDERING INFORMATION Product CS4412A CRD4412A CRD4525 Description 30 W Quad Half-Bridge Digital Amplifier Power Stage 1 x 30 W Reference Design Daughter Card 2 x 15 W Reference Design Main Board Package Pb-Free 48-QFN Yes - Grade Commercial - Temp Range Container Rail -10° to +70°C Tape and Reel - Order# CS4412A-CNZ CS4412ACNZR CRD4412A CRD4525 10.REVISION HISTORY Release A1 Initial Release Changes Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 24 DS786A1