CS1500_1

Jul ?$shortyear> CONFIDENTIAL CS1500 Digital Power Factor Correction IC Features & Description  Digital EMI Noise Shaping  Excellent Efficiency Under All Load Conditions  Minimal External Devices Required  Optimized Digital Loop Compensation  Comprehensive Safety Features • Undervoltage Lockout (UVLO) • Output Overvoltage Protection • Input Current Limiting • Output Overpower Protection • Input Brownout Protection • Open/short Loop Protection for IAC & FB Pins • Thermal Shutdown Description The CS1500 is a high-performance power factor correction (PFC) controller for universal AC input, which uses a proprietary digital algorithm for discontinuous conduction mode (DCM) with variable on-time and variable frequency control, ensuring unity power factor. The CS1500 incorporates all the safety features necessary for robust and compact PFC stages. In addition, it has burst mode control to lower the light-load/standby losses to a minimum. Protection features such as overvoltage, overcurrent, overpower, open- and short-circuit protection, overtemperature, and brownout help protect the device during abnormal transient conditions. The digital controller optimizes the system stability and transient performance, simplifies the PFC design, reduces the external component count and BOM costs. The simple design and minimum cost makes CS1500 the ideal choice for PFC up to 300 watts. Pin Assignments NC STBY IAC FB 1 2 3 4 8 7 6 5 NC VDD GD GND 8-lead SOIC D1 D2 LB R AC R1a R1 b BR1 C1 8 4 2 6 R3 Q1 R FB R2a R2b 1 3 NC IAC VDD GND NC FB STBY GD C3 AC Mains C2 Regulated DC Output VDD 7 5 CS1500 A dvance Product Information Cirrus Logic, Inc. http://www.cirrus.com This document contains information for a product under development. Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Logic, Inc. 2010 (All Rights Reserved) JUL ‘10 DS849A7 Jul ?$shortyear> CONFIDENTIAL CS1500 Table 1. Pin Descriptions Pin Name NC STBY Pin # I/O Description NC — No connections Remote On/Off Control — A voltage below 0.8 V shuts down the IC (not latched) and brings the device into low power consumption mode. The input has an internal 600 kΩ pull-up resistor to the VDD pin and should be driven with an open-collector device. Rectifier Voltage Sense — A current proportional to the rectified line voltage (Vrect) is fed into this pin. The current is measured with an A/D converter. Link Voltage Sense — A current proportional to the output link voltage (Vlink) of the PFC is fed into this pin. The current is measured with an A/D converter. Ground — Current return for both the input signal portion of the IC and the gate driver. Gate Driver Output — The totem pole stage is able to drive the power MOSFET with a peak current of 0.5 A source and 1.0 A sink. The high-level voltage of this pin is clamped at VZ to avoid excessive gate voltages. IC Supply Voltage — Supply voltage of both the input signal portion of the IC and the gate driver. 1, 8 2 IN IAC 3 4 5 6 IN IN OUT FB GND GD VDD 7 IN 2 DS849A7 Jul ?$shortyear> CONFIDENTIAL 1. CHARACTERISTICS AND SPECIFICATIONS 1.1 Absolute Maximum Ratings Pin 7 1,2,3,4,8 3,4 6 6 Symbol VDD VGD IGD PD TA TJ TStg IC Supply Voltage Analog Input Maximum Voltage Analog Input Maximum Current Gate Drive Output Voltage Gate Drive Output Current Total Power Dissipation @ TA=50° C Operating Ambient Temperature Range1 Junction Temperature Operating Range Storage Temperature Range Parameter Value VZ -0.5 to VZ 50 -0.3 to VZ -1.0 / +0.5 600 CS1500 Unit V V mA V A mW ºC ºC ºC -40 to +125 -40 to +125 -65 to +150 1.2 Electrical Characteristics (TA = 25º C, VDD = 13V, -40º < TJ < +125º C, CL=1nF between pin GD and GND, all voltages are measured with respect to GND; all current are positive when flowing into the IC; unless otherwise specified). Recommended VDD = 10 – 15 V. Parameter VDD Supply Voltage Turn-on Threshold Voltage Turn-off Threshold Voltage (UVLO) UVLO Hysteresis Zener Voltage VDD Supply Current Start-up Supply Current Standby Supply Current Operating Supply Current PFC Gate Drive Maximum Operating Frequency6 Minimum Operating Frequency Maximum Duty Cycle6 Output Source Resistance Output Sink Resistance Rising Time Falling Time Output Voltage Low State Output Voltage High State 6 Condition VDD Increasing VDD Decreasing IDD = 20 mA VDD = VDD(on) STBY < 0.8 V CL=1nF, fSW(max)=70kHz VDD = 13V VDD = 13V VDD = 13V IGD = 100mA,VDD = 13V IGD = -200mA,VDD = 13V CL=1nF,VDD = 13V CL=1nF,VDD = 13V IGD = -200mA,VDD = 13V IGD = 100mA,VDD = 13V Symbol VDD(on) VDD(off) VHys VZ IST ISB IDD fSW(max) fSW(min) Dmax ROH ROL tr tf Vol Voh Min 8.4 7.1 16.8 - Typ 8.8 7.4 1.3 17.9 68 80 1.7 Max 9.3 7.9 18.5 80 112 1.9 Unit V V V V μA μA mA 62 20 64 11.3 66 22 66 9 6 32 15 0.9 11.8 70 23 68 60 30 1.3 - kHz kHz % Ω Ω ns ns V V DS849A7 3 Jul ?$shortyear> CONFIDENTIAL Parameter Feedback & Protection2,3 25º C 25º C, 115 VAC 25º C, 115 VAC IREF VO(startup) VO(nom) VOVP VOVP(Hy) 25º C, 115 VAC 25º C, 115 VAC 25º C, GDRV turns off 25º C, GDRV turns on VBP(th) VBR TSD TSD(Hy) 415 62 76 129 360 400 418 4 130 100 65 80 Condition Symbol Min Typ CS1500 Max Unit Reference Current 1 Output Voltage at Startup Mode Output Voltage at Normal Mode Overvoltage Protection Threshold Overvoltage Protection Hysteresis Overpower Protection Threshold Overpower Protection Recovery 2,4 2,4 421 69 83 μA V V V V % % Vrms Vrms Input Brownout Protection Threshold Input Brownout Recovery Threshold Thermal Protection 1 Thermal Shutdown Threshold Thermal Shutdown Hysteresis STBY Input 5 130 - 143 9 155 - ºC ºC Logic Threshold Low Logic Threshold High Vdd-0.8 - 0.8 - V V NOTES: 1. 2. Specifications guaranteed by design & characterization and correlation with statistical process controls. Specification are based upon a PFC system configured for AC input of 90-265 VAC (Sine), 45/65 Hz, Vlink= 400 V, RAC = 3 x 1.0 MΩ, RFB = 3 x 1.0 MΩ, C3 = 180 μF, LB = 360 μH, 90 W. For other Vlink voltages, refer to Section 4 Application Example. Detailed Calculation See Section 4 Application Example. Overpower protection is scaled to rated power. STBY is designed to be driven by an open collector. The input is internally pulled up with a 600 kΩ resistor. Normal operation mode, see Section 3.2. 3. 4. 5. 6. 1.3 Thermal Characteristics Parameter Thermal Resistance (Junction to Ambient)7. Thermal Resistance (Junction to Case)7. 7. The package thermal impedance is calculated in accordance with JESD 51. Value 159 39 Unit ºC / W ºC / W Symbol RθJA RθJC 4 DS849A7 Jul ?$shortyear> CONFIDENTIAL 2. TYPICAL ELECTRICAL PERFORMANCE 3.5 3 2.5 C L = 1 nF fSW(max) = 70 kHz TA = 25 °C 13 CS1500 12 IDD (mA) 11 2 1.5 1 0.5 Falling 0 0 2 4 6 8 10 12 14 16 18 20 Rising VDD (V) 10 9 Startup 8 UVLO 7 -50 0 50 100 150 VDD (V) TEMP (o C) Figure 1. Supply Current vs. Supply Voltage Figure 2. Start-up & UVLO vs. Temp 2 19 IDD = 20 mA UVLO Hysteresis (V) 1.5 18.5 VZ (V) -50 0 50 100 150 1 18 0.5 17.5 0 17 TEMP ( o C) -50 0 50 100 150 TEMP ( oC) Figure 3. UVLO Hysteresis vs. Temp Figure 4. VDD Zener Voltage vs. Temp DS849A7 5 Jul ?$shortyear> CONFIDENTIAL 100 Operating 1.6 CS1500 1.8 90 Supply Current (mA) Frequency (kHz) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 Start-up Standby VDD = 13 V CL = 1 nF fSW(max) = 70 kHz 80 70 60 50 40 30 20 Min Freq Max Freq Standby Start-up 10 0 150 0 -50 0 50 100 -60 -40 -20 0 20 40 60 80 100 120 140 TEMP ( o C) TEMP ( oC) Figure 5. Supply Current (ISB, IST, IDD) vs. Temp Figure 6. Min/Max Operating Frequency vs. Temp 14 12 Source 10 8 6 Sink 4 2 0 -60 425 420 OVP 415 Zout (Ohm) Vlink (V) 410 405 400 395 390 385 -50 Normal VDD = 13 V Isource = 100 mA Isink = 200 mA -40 Gate Resistor (ROH, ROL) Temp (oC) -20 0 20 40 60 80 100 120 140 0 50 100 150 Temperature (°C) Figure 7. Gate Resistance (ROH, ROL) vs. Temp Figure 8. OVP vs. Temp 6 DS849A7 Jul ?$shortyear> CONFIDENTIAL 3. INTRODUCTION NC CS1500 CS1500 8 Oscillator 2 STBY IAC VDD FB 3 7 ADC Processor Logic Protection 5 GND 4 NC 1 PWM Driver 6 GD Figure 9. CS1500 Block Diagram The CS1500 digital power factor controller operates in variable on-time, variable frequency, discontinuous conduction mode (DCM). The CS1500 uses a proprietary digital algorithm to maximize the efficiency and reduce the conductive EMI. The analog-to-digital converter (ADC) shown in the CS1500 block diagram in Figure 9 is used to sense the PFC output voltage ( Vlink ) and the rectified AC line voltage ( Vrect ) by measuring currents through their respective resistors. The magnitudes of these currents are measured as a proportion of a reference current (IREF) that functions as the reference for the ADCs. The digital signal is then processed in a control algorithm which determines the behavior of the CS1500 during start-up, normal operation, and under fault conditions, such as brownout, overvoltage, overcurrent, overpower, and over-temperature conditions. • DCM with Variable On-Time, Variable Switching Frequency The CS1500 PFC switching frequency varies with the Vrect on a cycle-by-cycle basis, and its digital algorithm calculates the on-time accordingly for unity power factor. Unlike traditional Critical Conduction Mode (CRM) PFC controller, CS1500 operates at its low switching frequency near the zero-crossing point of the AC input voltage, even no switching at all, and it operates at its high switching frequency at the peak of its AC input voltage (this is the opposite of the switching frequency profile for a CRM PFC controller), thus CS1500 reduces switching losses especially under light-load conditions, spreads conducted EMI energy peaks over a wide frequency band and increases overall system efficiency. • Optimized Digital Loop Compensation The proprietary digital control engine optimizes the feedback error signal using an adaptive control algorithm, improves system stability and transient response. No external feedback error signal compensation components are required. • Overcurrent Mitigation The CS1500s digital controller algorithm limits the ON time of the Power MOSFET by the following equation: 0.001126 T on ≤ -----------------------V rect Where Ton is the max time that the power MOSFET is turned on and Vrect is the rectified line voltage. In the event of a sudden line surge or sporadic, high dv/dt line voltages, this equation may not limit the ON time appropriately. For this type of line disturbance, additional protection mechanisms such as fusible resistors, fast-blow fuses, or other current-limiting devices are recommended. • Over Voltage Protection Under steady-state conditions, the voltage loop keeps PFC output voltage close to its nominal value. Under light load startup or feedback loop open conditions, the output voltage may pass the overvoltage protection threshold. The digital control engine initiates a fast response loop to shut down gate driving signal to reduce the energy delivered to the output for PFC capacitor protection. When the link voltage drop below VOVP-VOVP(Hy), PFC resumes normal operation. DS849A7 7 Jul ?$shortyear> CONFIDENTIAL 3.1 PFC Operating Frequency One key feature of the CS1500 is its operating frequency profile. Figure 10 illustrates how the frequency varies over half cycle of the line voltage in steady-state operation. When power is first applied to the CS1500, it first examines the line voltage and adapts its operating frequency to the exposed line voltage as shown in Figure 11. The operating frequency is varied in about a 2-to-1 ratio from the peak to the trough. During start-up the control algorithm limits the maximum ontime, provides nearly square-wave envelop current within every half line cycle by adjusting the operating frequency for fast startup behavior. 120 Switching Freq. (% of Max.) CS1500 The CS1500 is designed to function as a DCM (discontinuous conduction mode) controller, however it may operate in a quasi-CRM operation mode near the peak periods. For 90~265VAC main input applications, PFC can be also designed in quasi-CRM at a peak of 90VAC and full load as shown in Figure 12. DCM Quasi CRM DCM Quasi CRM DCM Inductor Current ILB IAC 100 t [ms] % of Max 80 Figure 12. DCM and quasi-CRM Operation with CS1500 60 40 Line Voltage (% of Max.) 3.2 Start-up vs. Normal Operation Mode CS1500 has two discrete operation modes: Start-up and Normal. Start-up mode will be activated when Vlink is less than 90% of nominal value and remains active until Vlink reaches 100% of nominal value, as shown in Figure 13. Startup mode is activated during initial system power-up. Any Vlink drop to less than 90% of nominal value, such as load change, can cause the system to enter Start-up Mode until Vlink is brought back into regulation. Vlink [V] Vin < 150 VAC 20 0 0 45 90 135 180 Rectified Line Voltage Phase (Deg.) Figure 10. Switching Frequency vs. Phase Angle 70 100% FSW max (kHz) 60 56 50 46 40 Burst Mode Startup Mode Vin > 150 VAC Normal Mode Startup Mode 90% Normal Mode 20 t [ms] 0 5 20 40 60 80 100 Figure 13. Start-up and Normal Modes % PO max Figure 11. Switching Frequency vs. Output Power Figure 11 illustrates how the operating frequency (as a percentage of maximum frequency) changes with output power and the peak of the line voltage. Burst mode (when Po below 5%) will be discussed in a later section. 3.3 Burst Mode Burst mode is utilized to improve system efficiency when the system output power (Po) is < 5% of nominal. Burst mode is implemented by intermittently disabling the PFC over a full half-line period cycle under light load conditions, as shown in Figure 14. 8 DS849A7 Jul ?$shortyear> CONFIDENTIAL CS1500 Resistor RFB (shown as R2a & R2b in Figure 21) sets the feedback current and is calculated as follows: Po [W] Burst Threshold Burst Mode Active V link – V dd R FB = --------------------------I ref [Eq.3] Vlink t [ms] Vin [V] Vin PFC Disable IFB RFB VDD 7 FET Vgs FB 4 t [ms] Figure 14. Burst Modes ADC 3.4 Output Power and PFC Boost Inductor Maximum output power in normal mode is defined by the following equation: 2 V link – ( V in ( min ) × 2 ) P = α × η × ( V in ( min ) ) × -------------------------------------------------------o 2 × f max × L B × V link Figure 15. Feedback Input Pin Model The ADC is used to measure the magnitude of the IFB current through resistor RFB. The magnitude of the IFB current is then compared to an internal reference current, Iref. By using digital loop compensation, the voltage feedback signal does not require an external compensation network. It is recommended that a ceramic capacitor of up to 2.2 nF be placed between the FB pin and the VDD pin to filter noise in the layout. [Eq.1] where, Vin(min), Vlink, and LB are user defined based on application requirements and maximum operating switching frequency fmax = 70kHz. α is a margin factor to guarantee rated power (Po) against tolerances and transients. α is typically set to 0.9. The PFC Boost Inductor (LB in Figure 21) value can be calculated using Equation 1 as follows: V link – ( V in ( min ) × 2 ) L B = α × η × ( V in ( min ) ) × -------------------------------------------------------2 × f max × P × V link o 2 3.7 IAC Signal Vrect IAC RAC VDD 7 [Eq.2] where Vin(min) is volts RMS, Vlink is volts DC, and 0.9. α is set to IAC 3 ADC 3.5 PFC Output Capacitor The value of the PFC output capacitor should be chosen based upon voltage ripple and hold-up requirements. This is described in more detail in the application section 4.1.6 PFC Output Capacitor on page 13. To ensure system stability with the digital controller, the recommended value of the capacitor is within the range of 0.5 μF / watt to 2.0 μF / watt. Figure 16. IAC Input Pin Model A current proportional to the AC input voltage is supplied to the IC on pin IAC and is used by the PFC control algorithm. Resistor RAC (shown as R1a & R1b in Figure 21) sets the IAC current and is calculated as follows: R AC = R FB [Eq.4] 3.6 Output Feedback & Regulation A current proportional to the PFC output voltage, Vlink, is supplied to the IC on pin FB and is used as a feedback control signal. This current is compared against a fixed-value internal reference current, Iref. For optimal performance, resistor RAC, RFB should use less than 1% tolerance resistor. Resistors can be separated in two DS849A7 9 Jul ?$shortyear> CONFIDENTIAL or more series elements if voltage breakdown or regulatory compliance is of concern. It is recommended that a ceramic capacitor of up to 2.2 nF be placed between the IAC pin and the VDD pin to filter noise in the layout. CS1500 protection is asserted, the IC stops gate drive, goes into a lowpower state, and restarts every 3 seconds. In the case of an intermittent or minor fault, the device will continue to regulate the output voltage (Vlink) to its nominal value. If the PFC remains in startup mode for longer than a given time, set by the digital controller, it senses an overload condition and initiates the overpower protection. The CS1500 has the ability to ensure nearly constant overpower constraint over a wide range of line voltages, as shown in Figure 19. 3.8 Brownout Protection Figure 17 illustrates the brownout protection mechanism whereby the CS1500 enters standby, and upon recovery from brownout, enters normal operation mode. In order to avoid the fault trigger, a digital filter is added for line voltage detection. The measured peak of the line voltage will be clamped to a threshold (128 V) set by the IC within half of a line cycle if it is higher than the threshold. It then decreases the voltage with a slew rate of 5 V / trough (8 ms). The CS1500 initiates a timer when the measured voltage falls below the lower brownout threshold. The IC asserts the brownout protection and stops the gate drive only if the timer reaches more than 56 ms, which is set by the algorithm based on minimum line frequency. During the brownout state, the device continues monitoring the input line voltage. The device exits the brownout state when the input voltage peak value exceeds the brownout upper threshold for at least 56 ms. The maximum response time of the brownout protection normally happens at light load conditions. It can be calculated by the following equation: T Brownout 8 ms = 8 ms + ----------- ( 128 V – V BP ( th ) ) + 56 ms 5V 8 = 8 + -- ( 128 – 95 ) + 56 5 = 116.8 ms In the brownout state, the PFC gate driver will restart every 3 seconds, trying to regulate Vlink to nominal value. TBrownout Brownout Thresholds Upper Lower Start Timer 56 ms 56 ms Vlink [V] 100% Overpower 90% Startup Mode Startup Mode Normal Mode Normal Mode Startup Mode Normal Mode t0 t0 + tovrpwr t [ms] Figure 18. Overpower Protection Mechanism L < LB Po / α Po L = LB L = LB / α [Eq.5] Po(max) 90 265 V AC(rms ) Figure 19. Maximal Output Power vs. Line Voltage 3.10 Exit Standby Overvoltage Protection Enter Standby Start Timer Figure 17. Brownout Sequence The overvoltage protection will trigger immediately and stop the gate drive when the current into the FB pin (IOVP) exceeds 105% of the reference current value (Iref). The IC resumes gate drive switching when the link voltage drops below VOVP – VOVP(HY). 3.9 Overpower Protection During normal operation, if the load is increased beyond the overpower threshold, the output voltage starts falling. When the output voltage is below the startup threshold voltage, the CS1500 switches to startup mode and the output voltage will rise back again to the nominal value and will operate in normal mode if the load is reduced to a normal level. Otherwise, the PFC oscillates between startup mode and normal mode and the digital engine declares the overpower condition. When the overpower 3.11 Open/short Loop Protection If the PFC output sense resistor RFB fails (open or short to GND), the measured output voltage decreases at a slew rate of about 2V / μs, which is determined by ADC sampling rate. The IC stops the gate drive when the measured output voltage is lower than the measured line voltage. The IC resumes gate drive switching when the current into the FB pin becomes larger than or equal to the current into the IAC pin and Vlink is 10 DS849A7 Jul ?$shortyear> CONFIDENTIAL greater than the peak of the line voltage (Vrect(pk)). The maximum response time of open/short loop protection for RFB is about 150 μs in the CS1500. If the PFC input sense resistor RAC fails (open or short to GND), the current reference signal supplied to the IC on pin IAC falls to zero. This failure is equivalent to a brownout condition and will be handled by the brownout protection mechanism described in Section 3.8. CS1500 shown in Figure 20. Since the pull-up resistor has a high impedance, the user may need to provide a filter capacitor (up to 1000 pF) on this pin. VDD 600 k Ω 3.12 Overcurrent Limiting Boost inductor saturation is a fatal condition for a PFC converter. To prevent inductor current saturation conditions, the IC utilizes a proprietary digital algorithm that keeps the boost inductor current away from its saturation current. The boost inductor should be designed for full load, minimal line voltage, maximum switching frequency, and with enough margin to prevent saturation in normal operation mode. STBY CS1500 CONFIDENTIAL 4. APPLICATION EXAMPLE The following sections describe an example application. The example is based upon the typical connection diagram illustrated in Figure 21. CS1500 Equations are provided to demonstrate how a user would calculate the values for the components shown in the diagram. D1 D2 LB R AC R1a R1 b BR1 C1 8 4 2 6 R3 Q1 R FB R2a R2b 1 3 NC IAC VDD GND NC FB STBY GD C3 AC Mains C2 Regulated DC Output VDD 7 5 CS1500 Figure 21. CS1500 Basic Application Circuit 4.1 PFC for Power Supply Application The following design example is for a universal main input, front-end PFC converter with the following parameters: R AC = R FB R AC = 3.0M Ω Maximum power dissipation in each sense resistor is calculated as follows (the equation ignores the voltage drop across RIAC & RIFB): V link P ( R FB ) = -------------R FB 400 P ( R FB ) = -----------------6 3 × 10 P ( R FB ) = 53.3mW [Eq.6] [ V in ( max ) ] P ( R AC ) max = ---------------------------R AC 265 P ( R AC ) max = -----------------6 3 × 10 P ( R AC ) max = 23.4mW 2 2 2 2 [Eq.7] Vin(min) Vin(max) Vlink Po 90 VAC 265 VAC 400 V 90 W 4.1.1 IAC and IFB Sensing Inputs [Eq.8] The rectified AC input voltage (Vrect) and boosted PFC output voltage (Vlink) are sensed as currents into the IC. The sensing currents are set by resistors RAC and RFB, respectively: V link – V dd = --------------------------I ref 400 – 12 = --------------------------–6 129 × 10 R FB R FB [Eq.9] R FB = 3.0M Ω 12 DS849A7 Jul ?$shortyear> CONFIDENTIAL 4.1.2 PFC Input Filter Capacitor 4.1.4 PFC MOSFET CS1500 To achieve unity power factor, a DCM PFC circuit needs an input filtering circuit to bypass the high-frequency current so that the input current consists of the low-frequency portion only. There are two main factors on PFC input filter capacitor selection: its voltage ripple and phase lag, which both will worsen power factor. The filtering capacitance is proportional to Po and it is suggested as follows: nF -o C 1 ≥ 3.3 ------ × P W C 1 ≥ 3.3 × 120 C 1 ≥ 390nF = 0.39 μ F Use 0.47 μF for tolerance. If a PI filter used for suppression of conducted EMI is located on the DC side of the input rectifier, the Vrect sense point has to be moved to the second capacitor. [Eq.10] In normal mode, the PFC MOSFET peak current is equal to the peak current in the PFC boost inductor: I FET ( pk ) = I LB ( pk ) I FET ( pk ) = 3.3A [Eq.14] 4.1.5 PFC Diode The PFC diode peak current in normal mode is the equal to the inductor peak current: I D ( pk ) = I LB ( pk ) I D ( pk ) = 3.3A The PFC Diode average current is calculated as follows: Po I D ( avg ) = ----------V link 90I D ( avg ) = --------400 I D ( avg ) = 0.225A [Eq.16] [Eq.15] 4.1.3 PFC Boost Inductor The value of the inductor in normal mode can be calculated by the following equation, with α = 0.9 as a derating factor to ensure the inductor is sized to guarantee DCM operation and provide a slightly higher power than required by the load: 2 V link – ( V in ( min ) × 2 ) L B = α × η × ( V in ( min ) ) × -------------------------------------------------------2 × f max × P × V link o [Eq.11] 400 – ( 90 × 2 ) L B = 0.9 × 0.95 × 90 × -----------------------------------------------------------------3 2 × ( 70 × 10 ) × 90 × 400 2 L B = 374 μ H Choose a 360 μH inductor. 4 × Po I LB ( pk ) = ----------------------------------------------------α × η × V in ( min ) × 2 4 × 90 I LB ( pk ) = ---------------------------------------------------0.9 × 0.95 × 90 × 2 I LB ( pk ) = 3.3A [Eq.12] 4.1.6 PFC Output Capacitor The value of the output capacitor is determined by several requirements. It must meet the voltage ripple and hold-up time requirements and the RMS current in the capacitor should not exceed its RMS current rating. The following equation defines the size of the output capacitor to meet the output voltage ripple requirements: PO C out ( rip ) = -------------------------------------------------------------------------------------2 π × f line ( min ) × V link × Δ V link ( rip ) [Eq.17] fline(min) is the minimum line frequency the design is required to support, Vlink is the output voltage from the PFC, ΔVlink(rip), is the output voltage ripple requirement in volts peak-to-peak. The equation will provide the value of the output capacitor needed to meet the ripple requirement. For 10 V of ripple and minimum line frequency of 45 Hz, the equation becomes: 90 C out ( rip ) = ------------------------------------------------ = 80 μ F u use u 100 μ F 2 π × 45 × 400 × 10 A second requirement that the output capacitor may be required to meet is hold-up time. The value of the capacitor η is the efficiency. The inductor should be designed so that its saturation current meets the following requirement, where 0.001126 is a predefined threshold for the current protection algorithm: 0.001126 I sat ≤ -----------------------L where L is the inductance in Henrys. [Eq.13] DS849A7 13 Jul ?$shortyear> CONFIDENTIAL needed to meet the hold-up time required is defined by the following equation: C out ( hold ) 2 × P O × t hold = ----------------------------------------------------------------------------------------Δ V out ( rip ) 2 2 V ------------------------ – ( V link ( min ) )  link –  2 [Eq.18] V ovp = V link × 1.05 V ovp = 400 × 1.05 V ovp = 420V CS1500 4.1.7 Overvoltage Protection Overvoltage protection is activated when Vlink exceeds 105% of the nominal value: [Eq.19] tHOLD is the magnitude of the hold-up time in seconds. For 10 ms of hold-up time and Vlink(min) of 300 V, the equation becomes: 2 × 90 × 0.010 C out ( hold ) = ------------------------------------------------------ = 27 μ F 2  400 – 10 – ( 300 ) 2 ---- 2 Choose a 100 μF capacitor. While in overvoltage protection mode, gate drive output is disabled. GD output is re-enabled when Vlink falls below its nominal value. 14 DS849A7 Jul ?$shortyear> CONFIDENTIAL 4.1.8 Summary of Component Values Designator R1a R1b R2a R2b R3 C1 C2 C3 BR1 D1 D2 LB Q1 CS1500 Value 1.5 MΩ 1.5 MΩ 1.5 MΩ 1.5 MΩ 4.7 Ω 0.47 μF 0.47 μF 100 μF, 450V 4A, 600V 1 A, 600 V 1 A, 600 V 360 μH 12 A, 500 V PFC Controller Description CS1500 SFR25 axial film res - 0.4W-1% SFR25 axial film res - 0.4W-1% SFR25 axial film res - 0.4W-1% SFR25 axial film res - 0.4W-1% SFR25 axial film res - 0.4W-1% ECQ2W474KH 50V Ceramic cap - X7R LLS2W101MELA GBU4J-BP 1N4005 STTH1R06 Premier Magnetics STP12NM50FP CS1500 DS849A7 15 Jul ?$shortyear> CONFIDENTIAL 5. PERFORMANCE PLOTS 100 Vin=230V CS1500 95 Vin=115V 90 Efficiency 85 80 75 70 0 10 20 30 40 50 60 70 80 90 100 110 Load (%) Figure 22. Efficiency vs. Load, Typical 100 90 80 70 THD(%) 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 Vin = 115 V in = 230 Load (% ) Figure 23. Distortion vs. Load, Typical 16 DS849A7 Jul ?$shortyear> CONFIDENTIAL CS1500 1 Vin = 115 0.9 Vin = 230 Power Factor 0.8 0.7 0.6 0.5 0.4 0 10 20 30 40 50 60 70 80 90 100 Load (% ) Figure 24. Power Factor vs. Load, Typical DS849A7 17 Jul ?$shortyear> CONFIDENTIAL CS1500 Figure 25. Load Transient — 20% to 80% (60 mA to 240 mA), 0.8 A/μsec Slew, 90 VAC Figure 26. Load Transient — 20% to 80% (60 mA to 240 mA), 0.8 A/μsec Slew, 260 VAC 18 DS849A7 Jul ?$shortyear> CONFIDENTIAL CS1500 Figure 27. Overload — 240 mA to 500 mA, 90 VAC Figure 28. Overload — 240 mA to 500 mA, 265 VAC DS849A7 19 Jul ?$shortyear> CONFIDENTIAL 6. DEFINITIONS Variable η α fline(min) IAC IFB IFET(pk) Irms Isat Ist IST LB Po Po(max) RAC RFB Vin(min) Vlink Vlink(min) ΔVlink(rip) Vrect The efficiency factor. A margin factor to guarantee rated power against tolerances and transients. The minimum AC line frequency. CS1500 Definition The current generated by Vrect that flows into the IAC pin. The current generated by Vlink that flows into the FB pin. The PFC MOSFET peak current, which is equal to the peak current in the PFC boost inductor. The magnitude of the RMS current. The boost inductor LB saturation current. The sum of the current into the IAC and FB pins. The startup current of the chip. The PFC boost inductor. The nominal output power from the CS1500 PFC circuit. The maximum value of the output power from the CS1500 PFC circuit. The sense resistor used to measure current into the IAC pin. The sense resistor used to measure current into the FB pin. The minimum specified line voltage for proper operation (volts RMS). The magnitude of the output voltage from the PFC. The magnitude of the output voltage from the PFC. ΔVlink(rip), is the output voltage ripple requirement in volts peak-to-peak The instantaneous value of the rectified line voltage (volts). 20 DS849A7 Jul ?$shortyear> CONFIDENTIAL 7. PACKAGE DRAWING 8L SOIC (150 MIL BODY) PACKAGE DRAWING CS1500 E H 1 b c D SEATING PLANE e A1 A L ∝ INCHES DIM A A1 B C D E e H L MIN 0.053 0.004 0.013 0.007 0.189 0.150 0.040 0.228 0.016 0° MAX 0.069 0.010 0.020 0.010 0.197 0.157 0.060 0.244 0.050 8° JEDEC # MS-012 ∝ MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.02 1.52 5.80 6.20 0.40 1.27 0° 8° 8. ORDERING INFORMATION Part # CS1500-FSZ Temperature Range -40 °C to +125 °C Package Description 8-lead SOIC, Lead (Pb) Free 9. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS1500-FSZ Peak Reflow Temp 260 °C MSL Ratinga 2 Max Floor Lifeb 365 Days a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. b. Stored at 30 °C, 60% relative humidity. DS849A7 21 Jul ?$shortyear> CONFIDENTIAL 10.REVISION HISTORY Revision A1 A2 A3 Date APR 2009 JUN 2009 DEC 2009 Changes Initial Advance Information release. CS1500 No substantive changes. Document number incremented to avoid confusion among previous, pre-released versions. Revised feature list & product description. Revised electrical characteristics to include brownout & open-loop protection. Modified definition table. Modified data sheet format. Updated to correspond to C1 silicon. Updated performance data. Updated with additional test bench data for EP level. Updated zener voltage, OPP threshold, brownout protection/recovery. Updated Fig.1 with new data. A4 A5 A6 A7 MAR 2010 MAY 2010 MAY 2010 JUL 2010 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. 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