CS1601-FSZ

CS1601 CS1601H Digital PFC Controller for Electronic Ballasts Features & Description  Low PFC System Cost  Best-in-class THD  Digital EMI Noise Shaping Reduces Conducted EMI  Adaptive Switching Frequency Control Minimizes Boost Inductor Size Overview The CS1601 and CS1601H are digital power factor correction (PFC) controllers designed to deliver the lowest PFC system cost in electronic ballast applications. The controller operates in a variable frequency discontinuous conduction mode (VFDCM) with zero-current switching (ZCS) optimized to deliver best-in-class THD and minimize the size and cost of magnetic components. The CS1601 operates at switching frequencies up to 70 kHz while the CS1601H operates at frequencies extending to 100kHz. The VF-DCM control algorithm varies both duty cycle and frequency. This spreads the EMI frequency spectrum, thus reducing conducted EMI filtering requirements. In addition, the maximum switching frequency is reached at the peak of the AC input, which allows for use of a smaller, more cost-effective boost inductor. Th e fee dback loop is closed through an integrated compensation network within the controller, eliminating the need for additional external components. Protection features such as overvoltage, overcurrent, open and short-circuit protection, overtemperature, and brownout protect the system during abnormal transient conditions.  High Efficiency Due to Zero-current Switching  Integrated Feedback Compensation Simplifies System Design  Comprehensive Safety Features • Undervoltage Lockout (UVLO) • Output Overvoltage Protection • Cycle-by-cycle Current Limiting • Input Voltage Brownout Protection • Open/Short Loop Protection for IAC & IFB Pins • Thermal Shutdown  Pin placement similar to traditional boundary mode (CRM) Controllers Applications & Description  LED Power Supply/Driver  Fluorescent Ballasts  HID Ballasts Vrec t LB Ordering Information See page 15. D1 Vlink BR1 BR1 R1 R2 R3 5 3 ZCD IAC VDD R5 R6 AC Mains 8 VDD 1 IFB GD CS C1 CS1601 CS1601H GND 7 4 Q1 C2 Regulated DC Output BR 1 BR 1 STBY R4 2 6 R7 P reliminary Product Information Cirrus Logic, Inc. http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Logic, Inc. 2011 (All Rights Reserved) JUN ’11 DS931PP6 CS1601 1. INTRODUCTION V DD 600k Voltage Regulator POR + V DD 8 VDD STBY 2 VDD 15k - VDD (on ) VDD (off) VZ Iref 24k ADC IFB 1 VDD 15k Iref 24k ADC 7 GD GND IAC 3 t LEB t ZCB 6 CS 4 600 VCS(th) + + - CS Threshold CS Clamp Zero Crossing Detect VCS(clamp ) - + - V ZCD(th) 5 ZCD Figure 1. CS1601 Block Diagram The CS1601 digital power factor correction (PFC) control IC is designed to deliver the lowest system cost by reducing the total number of system components and optimizing the EMI noise signature, which reduces the conducted EMI filter requirements. The CS1601 digital algorithm determines the behavior of the boost converter during startup, normal operation, and under fault conditions (overvoltage, overcurrent, and overtemperature). Figure 1 illustrates a high-level block diagram of the CS1601. The PFC processor logic regulates the power transfer by using an adaptive digital algorithm to optimize the PFC activeswitch (MOSFET) drive signal duty cycle and switching frequency. The adaptive controller uses independent analogto-digital converter (ADC) channels when sensing the feedback and feedforward analog signals required to implement the digital PFC control algorithm. The AC mains rectified voltage (on pin IAC) and PFC output link voltage (on pin IFB) are transformed by the PFC processor logic and used to generate the optimum PFC active-switch drive signal (GD) by calculating the optimal switching frequency and tON time on a cycle-by-cycle basis. An auxiliary winding is typically added to the PFC boost inductor to provide zero-current detection (ZCD) information. The ZCD acts as a demagnetization sensor used to monitor the PFC active-switching behavior and efficiency. The auxiliary voltage is normalized using an external attenuator and is connected to the ZCD pin, providing the CS1601 a mechanism to detect the valley/zero crossings. The ZCD comparator looks for the zero crossing on the auxiliary winding and switches when the auxiliary voltage is below zero. Switching in the valley of the oscillation minimizes the switching losses and reduces EMI noise. The PFC controller uses a current sensor for overcurrent protection. The boost inductor peak current is measured across an external resistor in the switching circuit on a cycleby-cycle basis. An overcurrent fault is generated when the sense voltage applied to the CS pin exceeds a predefined reference voltage. The CS1601 includes a supervisor & protection circuit to manage startup, shutdown, and fault conditions. The protection circuit is designed to prevent output overvoltage as a result of load and AC mains transients. The PFC power converter main rectified voltage (Vrect) and output link voltage (Vlink) are monitored for overvoltage faults which would lead to shutdown of the PFC controller. The PFC overvoltage protection is designed for auto-recovery, i.e. operation resumes once the fault clears. 2 DS931PP6 CS1601 2. PIN DESCRIPTION Link V oltage S ens e S tandby Rec tifier V oltage S ens e P FC Current S ens e IFB S TBY IAC CS 1 2 3 4 8 7 6 5 V DD GD GND ZCD IC S upply V oltage P FC Gate Driv er Ground P FC Zero-c urrent Detec t 8-lead S OIC Figure 2. CS1601 Pin Assignments Pin Name IFB STBY IAC Pin # I/O Description Link Voltage Sense — A current proportional to the output link voltage of the PFC is input into this pin. The current is measured with an ADC. Standby — A voltage below 0.8V puts the IC into a non-operating, low-power state. The input has an internal 600k pull-up resistor to the VDD pin. Rectifier Voltage Sense — A current proportional to the rectified line voltage is input into this pin. The current is measured with an ADC. PFC Current Sense — The current flowing in the PFC MOSFET is sensed through a resistor. The resulting voltage is applied to this pin and digitized for use by the PFC computational logic to limit the maximum current through the power FET. Zero-current Detect— Boost Inductor demagnetization sensing input for zero-current detection (ZCD) information. The pin is externally connected to the PFC boost inductor auxiliary winding through an external resistor divider. Ground — Common reference. Current return for both the input signal portion of the IC and the gate driver. PFC Gate Driver — The totem pole stage is able to drive the power MOSFET with a peak current of 0.5A source and 1.0A sink. IC Supply Voltage — Supply voltage of both the input signal portion of the IC and the gate driver. A storage capacitor is connected on this pin to serve as a reservoir for operating current for the device, including the gate drive current to the power transistor. This pin is clamped to a maximum voltage (Vz) by an internal zener function. 1 2 3 IN IN IN CS 4 IN ZCD 5 6 7 IN PWR OUT GND GD VDD 8 PWR DS931PP6 3 CS1601 3. CHARACTERISTICS AND SPECIFICATIONS 3.1 Electrical Characteristics Minimum/Maximum characteristics conditions: TJ = -40° to +125 °C, VDD = 10V to 15V, GND = 0V Typical characteristics conditions: TA = 25°C, VDD = 13V, GND = 0V All voltages are measured with respect to GND. Unless otherwise specified, all current are positive when flowing into the IC. Parameter VDD Supply Voltage Operating Range Turn-on Threshold Voltage Turn-off Threshold Voltage (UVLO) UVLO Hysteresis Zener Voltage VDD Supply Current Startup Supply Current Operating Supply Current 3 CS1601 CS1601H Standby Supply Current Reference Reference Current PFC Gate Drive Output Source Resistance Output Sink Resistance Rise Time 3 Fall Time 3 Output Voltage Low State Output Voltage High State Zero-current Detection (ZCD) ZCD Threshold ZCD Blanking ZCD Sink/Source Current Upper Voltage Clamp Overvoltage Protection (OVP) IFB Current at Startup Mode IFB Current at Normal Mode OVP Threshold OVP Hysteresis Condition After Turn-on VDD Increasing VDD Decreasing IDD = 20mA VDD = VDD(on) CL = 1nF, fsw = 70kHz CL = 1nF, fsw = 100kHz STBY < 0.8V Symbol VDD VDD(on) VDD(off) VHys VZ IST IDD ISB Iref Min 7.9 9.8 7.9 17.0 11.3 -2 - Typ 10.2 8.1 2.1 17.9 68 1.5 1.75 80 129 9 6 32 15 0.9 11.8 50 200 -1 VDD 116 129 139 2 Max 17.0 10.5 8.3 18.7 80 1.7 1.95 112 45 25 1.3 2 - Unit V V V V V A mA mA A A   ns ns V V mV ns mA V A A A A IGD = 100mA, VDD = 13V IGD = -200mA, VDD = 13V CL = 1nF, VDD = 13V CL = 1nF, VDD = 13V IGD = -200mA, VDD = 13V IGD = 100mA, VDD = 13V ROH ROL tr tf Vol Voh VZCD(th) tZCB VZCD = 50mV IZCD = 1mA IZCD VCLP IIFB(startup) IIFB(norm) - - Iref = 129 A Iref = 129 A IOVP IOVP(Hy) 4 DS931PP6 CS1601 Parameter Overcurrent Protection (OCP) Current Sense Reference Clamp Threshold on Current Sense Leading Edge Blanking Delay to Output Brownout Protection (BP) Input Brownout Protection Threshold Input Brownout Recovery Threshold Thermal Protection 1 Thermal Shutdown Threshold Thermal Shutdown Hysteresis STBY Input 2 Logic Threshold Low Logic Threshold High Condition Symbol VCS(clamp) VCS(th) tLEB tCS Min - Typ 1.0 0.5 300 60 31.6 39.6 Max 350 - Unit V V ns ns A A gate drive turns off gate drive turns on IBP(lower) IBP(upper) TSD TSD(Hy) 134 - 147 9 159 - °C °C VDD-0.8 - 0.8 - V V Notes: 1. Specifications guaranteed by design and are characterized and correlated using statistical process methods. 2. 3. STBY is designed to be driven by an open collector. The input is internally pulled up with a 600 k resistor. For test purposes, load capacitance (CL) is 1nF and is connected as shown in the following diagram. V DD VDD GD CS GND +15V TP Buffer S1 CL 1nF R1 R2 -15V GD OUT S2 R3 DS931PP6 5 CS1601 3.2 Absolute Maximum Ratings Pin 8 1,3,4,5 1,3,4,5 7 7 All Pins Symbol VDD VGD IGD PD IC Supply Voltage Analog Input Maximum Voltage Analog Input Maximum Current Gate Drive Output Voltage Gate Drive Output Current Total Power Dissipation @ TA = 50 °C Junction-to-Ambient Thermal Impedance Operating Ambient Temperature Range 1 Junction Temperature Operating Range Storage Temperature Range Electrostatic Discharge Capability ESD Human Body Model Machine Model Charged Device Model Parameter Value VZ -0.5 to VZ 50 -0.3 to VZ -1.0 / +0.5 600 107 -40 to +125 -40 to +125 -65 to +150 2000 200 500 Unit V V mA V A mW °C/W °C °C °C V JA TA TJ TStg Notes: 4. The CS1601 has an internal shunt regulator that limits the voltage on the VDD pin. VZ, the shunt regulation voltage, is defined in the VDD Supply Voltage section of the Characteristics and Specifications section on the previous page. 5. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at the rate of 50mW/ °C for variation over temperature. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 6 DS931PP6 CS1601 4. TYPICAL ELECTRICAL PERFORMANCE 2 1.8 fSW(max) = 100kHz Operating fSW(max) = 70kHz Supply Current (mA) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 Start-up 0 50 100 150 Figure 3. Supply Current vs. Supply Voltage Temperature (oC) Figure 4. Supply Current (ISB, IST, IDD) vs. Temp 11 10.5 10 Turn On 3 UVLO Hysteresis 2 VDD (V) 1 9.5 9 8.5 8 7.5 Turn Off 0 -40 0 40 80 120 7 -60 -10 40 90 140 Temperature (OC) Temperature (OC) Figure 6. Turn-on & Turn-off Threshold vs. Temp Figure 5. UVLO Hysteresis vs. Temp 0.5% 0.0% -0.5% Iref Drift -1.0% -1.5% -2.0% -2.5% -3.0% -50 0 50 100 150 Temperature (oC) Figure 7. Reference Current (Iref) Drift vs. Temp DS931PP6 7 CS1601 14 12 Source 10 8 6 4 2 0 -60 Sink VDD = 13 V Isource = 100 mA Isink = 200 mA Vlink (Normalized at 25OC) 106% OVP 104% 102% 100% Normal 98% 96% Zout (Ohm) -40 Gate Resistor (ROH, ROL) Temp (oC) -20 0 20 40 60 80 100 120 140 -50 0 Temperature (OC) 50 100 150 Figure 8. Gate Resistance (ROH, ROL) vs. Temp Figure 9. OVP vs. Temp 19 IDD = 20 mA 18.5 VZ (V) 18 17.5 17 -50 0 50 100 150 Temperature (oC) Figure 10. VDD Zener Voltage vs. Temp 8 DS931PP6 CS1601 5. GENERAL DESCRIPTION The CS1601 offers numerous features, options, and functional capabilities to the electronic product lighting designer. This digital PFC control IC is designed to replace legacy analog PFC controllers with minimal design effort. Figure 13 illustrates how the operating frequency of CS1601H changes with output power and the peak of the line voltage. 100 Vin< 182 VAC (Input Voltage 108 –305 VAC, Vlink = 460 V) Vin< 158 VAC (Input Voltage 90– 264 VAC, V link = 400V) 75 B ur s t M od e 5.1 PFC Operation One key feature of the CS1601 is its operating frequency profile. Figure 11 illustrates how the frequency varies over half cycle of the line voltage in steady-state operation. When power is first applied to the CS1601, it examines the line voltage and adapts its operating frequency to the line voltage as shown in Figure 11. The operating frequency is varied from the peak to the trough of the AC input. During startup, the control algorithm generates maximum power while operating in critical conduction mode (CRM), providing an approximate square-wave current envelop within every half-line cycle. 120 Switching Freq. (% of Max.) F SW m a x (k H z ) 50 Vin> 156 VAC (Input Voltage 108 –305 VAC , V link = 460V) Vin >136 VAC (Input Voltage 90 –264 VAC , Vlink = 400V) 25 0 5 20 40 60 80 100 % PO max Figure 13. CS1601H Max Switching Freq vs.Output Power When PO falls below 5%, the CS1601 changes to Burst Mode. (Refer to Burst Mode section for more information.) The CS1601 is designed to function as a DCM controller. However, during peak periods, the controller may interchange control methods and operate in a quasi-critical-conduction mode (quasi-CRM) at low line. For example, at 108VAC main input under full load, the PFC controller will function as a quasi-CRM controller at the peak of the AC line cycle, as shown in Figure 14. DCM Quasi CRM DCM Quasi CRM DCM 100 % of Max 80 60 40 20 0 0 45 90 135 180 Rectified Line Voltage Phase (Deg.) Line Voltage (% of Max.) Figure 11. Switching Frequency vs. Phase Angle Figure 12 illustrates how the operating frequency of CS1601 (as a percentage of maximum frequency) changes with output power and the peak of the line voltage. 70 60 Vin 136 VAC (Input Voltage 90 –264 VAC , Vlink = 400 V) t [ms] Figure 14. DCM and quasi-CRM Operation with CS1601 The zero-current detection (ZCD) of the boost inductor is achieved using an auxiliary winding. When the stored energy of the inductor is fully released to the output, the voltage on the ZCD pin decreases, triggering a new switching cycle. This quasi-resonant switching allows the active switch to be turned on with near-zero inductor current, resulting in a nearly lossless switch event. This minimizes turn-on losses and EMI noise created by the switching cycle. Power factor correction control is achieved during light load by using on-time modulation. F SW m ax 20 0 5 20 40 60 80 100 % PO max Figure 12. CS1601 Max Switching Freq vs. Output Power DS931PP6 9 CS1601 5.2 Startup vs. Normal Operation Mode The CS1601 has two discrete operation modes: startup and normal. Startup mode will be activated when Vlink is less than 90% of nominal value, VO(startup) and remains active until Vlink reaches 100% of nominal value, as shown in Figure 15. Startup mode is activated during initial system power-up. Any Vlink drop to less than VO(startup), such as a load change, can cause the system to enter startup mode until Vlink is brought back into regulation. Vlink [V] 100% Startup Mode Startup Mode 90% 5.4 Output Power and PFC Boost Inductor In normal operating mode, the nominal output power is estimated by the following equation. 2 V link –  V in  min   2  P =      V in  min    -------------------------------------------------------o 2  f max  L B  V link [Eq.1] where: Po  rated output power of the system efficiency of the boost converter (estimated as 100% by the PFC algorithm) Normal Mode Normal Mode Vin(min) minimum RMS line voltage measured after the rectifier and EMI filter. Vin(min) is equal to 90Vrms or 108 Vrms depending on the AC Line Voltage operating range. nominal PFC output voltage; Vlink = 400V when Vlink V i n ( m i n ) = 9 0 Vr m s o r V l i n k = 4 6 0 V w h e n Vin(min) = 108Vrms fmax LB  maximum switching frequency; for the CS1601 fmax = 70kHz and the CS1601H fmax = 100kHz boost inductor specified by rated power requirement margin factor to guarantee rated output power (Po) against boost inductor tolerances. t [ms] Figure 15. Startup and Normal Modes Startup mode is defined as a surge of current delivering maximum power to the output regardless of the load. During every active switch cycle, the 'ON' time is calculated to drive a constant peak current over the entire line cycle. However, the 'OFF' time is calculated based on the DCM/CCM boundary equation. Equation 1 is provided for explanation purposes only. Using substituted required design values for Vlink and fmax gives the following equation: 2 460V –  108V  2  P =      108V   -----------------------------------------------------------o 2  70kHz  L B  460V 5.3 Burst Mode Burst mode is utilized to improve system efficiency when the system output power (Po) is LB 108 VAC(rms) 305 Figure 17. Relative Effects of Varying Boost Inductance 10 DS931PP6 CS1601 5.5 PFC Output Capacitor The value of the PFC output capacitor should be chosen based upon voltage ripple and hold-up requirements. To ensure system stability with the digital controller, the recommended value of the capacitor is within the range of 0.25 F/watt to 0.5 F/watt with a Vlink voltage of 460V. For optimal performance, resistors RIAC & RIFB should use 1% tolerance or better resistors for best Vlink voltage accuracy. 5.7 Valley Switching The zero-current detection (ZCD) pin is monitored for demagnetization in the auxiliary winding of the boost inductor (L B ). The ZCD circuit is designed to detect the V Aux valley/zero crossings by sensing the voltage transformed onto the auxiliary winding of LB. LB N:1 5.6 Output IFB Sense & Input IAC Sense A current proportional to the PFC output voltage, V link, is supplied to the IC on pin IFB and is used as a feedback control signal. This current is compared against an internal fixedvalue reference current. The ADC is used to measure the magnitude of the IIFB current through resistor RIFB. The magnitude of the IIFB current is then compared to an internal reference current of (Iref) 129 A. V link R5 IFB R6 R IFB 8 V DD Vlink D2 FE T Drain IAux R3 IZ CD 5 CS1601 ZCD_below_zero + VAux CS1601 R4 ZCD + V th( Z CD) Demag Comparator Cp 15 k IFB - 24 k 1 ADC Figure 20. ZCD Input Pin Model The objective of zero-voltage switching is to initiate each MOSFET switching cycle when its drain-source voltage is at the lowest possible voltage potential, thus reducing switching losses. CS1601 uses an auxiliary winding on the PFC boost inductor to implement zero-voltage switching. Zero Crossing Detection Figure 18. IFB Input Pin Model Resistor RIFB sets the feedback current and is calculated as follows: 460V – V DD V link – V DD R IFB = ---------------------------- = -----------------------------[Eq.4] I ref 129mA By using digital loop compensation, the voltage feedback signal does not require an external compensation network. A current proportional to the AC input voltage is supplied to the IC on pin IAC and is used by the PFC control algorithm. V rec t R1 IAC R2 R IAC 8 V DD ZCD GD ‘ON’ ZCD_below _zero Figure 21. Zero-voltage Switch During each switching cycle, when the boost diode current reaches zero, the boost MOSFET drain-source voltage begins oscillating at the resonant frequency of the boost inductor and MOSFET parasitic output capacitance. The ZCD_below_zero signal transitions from high to low just prior to a local minimum of the MOSFET drain-source voltage oscillation. The zerocrossing detect circuit ensures that a ZCD_below_zero pulse will only be generated when the comparator output is continuously high for a nominal time period (tZCB) of 200ns. Therefore, any negative edges on the comparator's output due to spurious glitches will not cause a pulse to be generated. Due to the CS1601's variable-frequency control, the MOSFET switching cycle will not always be initiated at the first resonant CS1601 15 k IA C 24 k 3 ADC Figure 19. IAC Input Pin Model Resistor RIAC sets the IAC current and is derived as follows: R IAC = R IFB [Eq.5] DS931PP6 11 CS1601 table below depicts approximate values for R3 and R4 for a range of boost-to-auxiliary inductor turns ratio, N. The overpower protection may activate prior to brownout protection, depending on the load. TBrownout Brownout Thresholds Upper Lower Start Timer 56 ms 56 ms N 9 10 11 12 13 14 15 ~R3 46k 42k 37.5k 35.5k 32k 29.5k 27.5k ~R4 1.75k 1.75k 1.75k 1.75k 1.75k 1.75k 1.75k Enter Standby Start Timer Exit Standby Table 1. Aux Inductor Turns Ratio vs. R3 and R4 Resistors R3 and R4 were calculated using Vlink = 460V and Cp = 10pF. Equation 6 is used to calculate the cut-off frequency defined by the RC circuit at the ZCD pin. f c = 1   2   R3  R4  C p  where: fc Cp The cut-off frequency, fc, needs to be 10x the ringing frequency. Capacitance at the ZCD pin [Eq.6] Figure 22. Brownout Sequence The maximum response time of the brownout protection feature occurs at light-load conditions. It is calculated by Equation 7. 8 ms T Brownout = 8 ms + -----------  128 V – V BP  th   + 56 ms [Eq.7] 5V 8 = 8 + --  128 – 94.8  + 56 = 117ms 5 where: VBP(th) Brownout threshold voltage, VBP(th) = IBP(lower) xRIAC 5.9 Overvoltage Protection The overvoltage protection (OVP) will trigger immediately and stop the gate drive when the current into the IFB pin (IOVP) exceeds 105% of the reference current (Iref) value. The IC resumes gate drive switching when the measured current at IFB drops below IOVP – IOVP(Hy). Equation 8 is used to calculate the OVP threshold (VOVP). V OVP = R IFB  I OVP + V DD [Eq.8] 5.8 Brownout Protection The CS1601 brownout detection circuit monitors the peak of the Vrect input voltage and disables the PWM switching when it drops below a pre-determined threshold. Hysteresis and minimum detection time are provided to avoid brownout detection during short input transients. When brownout is detected, the CS1601 enters standby mode. On recovery from brownout, it re-enters normal operating mode. Current IAC is proportional to the AC input voltage Vrect , where Vrect = RIAC xIAC and RIAC = R1+R2 in Figure 19 on page 11. The digitized current applied to the IAC pin is monitored by the brownout protection algorithm. When Vrect drops below the brownout detection threshold, the CS1601 triggers a timer. The IC asserts the brownout protection and stops the gatedrive switching only if the timer exceeds 56ms. This is the equivalent of 7 rectified line cycles at 60Hz. During the brownout state, the device continues monitoring the input line voltage. The device exits the brownout state when IAC exceeds the brownout upper threshold for at least 56ms. Typical values for the lower (IBP(lower) ) and upper (IBP(upper) ) brownout thresholds are 31.6 A and 39.6 A, respectively. 5.10 Overcurrent Protection To limit boost inductor current through the FET and to prevent boost inductor saturation conditions, the CS1601 incorporates a cycle-by-cycle peak inductor current limit circuit using an external shunt resistor to ‘sense’ the FET source current accurately. The overcurrent protection (OCP) circuit is designed to monitor the current when the active switch is turned on. The OCP circuit is enabled after the leading-edge blanking time (tLEB). The shunt voltage is compared to a reference voltage, V c s ( t h ) , to determine whether an overcurrent condition exists. The OCP circuit triggers immediately, allowing the OCP algorithm to turn off the gate driver. The overcurrent protection circuit is also designed to monitor for a catastrophic overcurrent occurrence by sensing sudden and abnormal operating currents. A second OCP threshold, Vcs(clamp), determines whether a severe overcurrent condition exists. This immediately turns off the gate drive and the system enters a restart mode. The CS1601 inhibits all switching operations for approximately 1.6ms then attempts to restart normal operation. 12 DS931PP6 CS1601 5.11 Overpower Protection The CS1601 incorporates an internal Overpower Protection (OPP) algorithm. This provides protection from overload conditions. This algorithm uses the condition that output power is a function of the boost inductor (Section 5.4). Under moderate overload, Vlink may droop up to 10% while maintaining rated power and PFC. Further increasing the load current causes Vlink to drop below the startup threshold (~360V). Below this threshold, the circuit changes its operating mode to startup with more power available to raise Vlink. As Vlink reaches its nominal value, startup mode is canceled and power is now limited to the rated value. If the overload is still present, this cycle will repeat. If a sustained overload, or a repeated cycle of overload events is detected for greater than 112 mS, the CS1601 shuts down for 2.5 seconds, then attempts to restart. 5.13 Internal Overtemperature Protection An internal thermal sensor triggers a shutdown when the temperature exceeds 135°C (nominal) on the silicon. The sensor sends a signal to the core that supplies current to all internal digital logic, cutting off power from them. Once the temperature of the IC has dropped by 9°C (nominal), the sensor resets, allowing power to the logic. 5.14 Standby (STBY) Function The standby (STBY) pin provides a means by which an external signal can cause the CS1601 to enter a nonoperating, low-power state. The STBY input is intended to be driven by an open-collector/open-drain device. Internal to the pin, there is a pull-up resistor connected to the VDD pin as shown in Figure 23. Since the pull-up resistor has a high impedance, the user may need to provide a filter capacitor (up to 1000pF) on this pin. 8 5.12 Open/Short Loop Protection If the PFC output sense resistor, RIFB, fails (open or short to GND), the measured output voltage decreases at a slew rate of about 2 V/ s, which is determined by the ADC sampling rate. The IC stops the gate drive when the measured output voltage is lower than the measured line voltage. The IC resumes gate drive switching when the current into the IFB pin becomes larger than or equal to the current into the IAC pin and Vlink is greater than the peak of the line voltage (Vrect(pk)). The maximum response time of open/short loop protection for RIFB is about 150 s. If the PFC input sense resistor RIAC fails (open or short to GND), the current reference signal supplied to the IC on pin IAC falls to zero. VDD 600k STBY 2 CS1601 < 1 nF See Text 6 GND Figure 23. STBY Pin Connection When the STBY pin is not used, it is recommended that the pin be tied to VDD (pulled high). DS931PP6 13 CS1601 5.15 Eq. # Summary of Equations Equation Output Power (page 10) 2 V link –  V in  min   2  P =      V in  min    -------------------------------------------------------o 2  f max  L B  V link Variables/Recommended Values Po  Rated output power of the system. Efficiency of the boost converter (estimated as 100% by the PFC algorithm). Minimum RMS line voltage is 90Vrms, measured after the rectifier and EMI filter. Nominal PFC output voltage must be 400V. Maximum switching frequency is 70kHz. Boost inductor specified by rated power requirement. Margin factor to guarantee rated output power (Po) against boost inductor tolerances. Value of the IAC pin sense resistor(s). Value of the IFB pin sense resistor(s). Value of the fixed, internal reference current. The cut-off frequency, fc, needs to be 10x the ringing frequency or fc = 10MHz. Capacitance at the ZCD pin. Cp