CS2300-CP-CZZR

CS2300-CP Fractional-N Clock Multiplier with Internal LCO Features Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source Internal LC Oscillator for Timing Reference Highly Accurate PLL Multiplication Factor – Maximum Error less than 1 PPM in HighResolution Mode I²C® / SPI™ Control Port Configurable Auxiliary Output Minimal Board Space Required – No External Analog Loop-filter Components General Description The CS2300-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2300-CP is based on a hybrid analog-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchronization clock at frequencies as low as 50 Hz. The CS2300-CP supports both I²C and SPI for full software control. The CS2300-CP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) grade. Customer development kits are also available for device evaluation. Please see “Ordering Information” on page 31 for complete details. 3.3 V Frequency Reference I²C/SPI Software Control I²C / SPI PLL Output Lock Indicator Auxiliary Output LCO Fractional-N Frequency Synthesizer 6 to 75 MHz PLL Output N 50 Hz to 30 MHz Frequency Reference Output to Input Clock Ratio Digital PLL & Fractional N Logic Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) JUN '08 DS843PP1 CS2300-CP TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ................................................... 8 CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ................................................. 9 4. ARCHITECTURE OVERVIEW ............................................................................................................. 10 4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 10 4.2 Hybrid Analog-Digital Phase Locked Loop .................................................................................... 10 5. APPLICATIONS ................................................................................................................................... 12 5.1 Timing Reference Clock ................................................................................................................. 12 5.2 Frequency Reference Clock Input, CLK_IN ................................................................................... 12 5.2.1 CLK_IN Frequency Detector ................................................................................................. 12 5.2.2 CLK_IN Skipping Mode ......................................................................................................... 13 5.2.3 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 14 5.3 Output to Input Frequency Ratio Configuration ............................................................................. 15 5.3.1 User Defined Ratio (RUD) ..................................................................................................... 15 5.3.2 Manual Ratio Modifier (R-Mod) ............................................................................................. 16 5.3.3 Automatic Ratio Modifier (Auto R-Mod) ................................................................................. 16 5.3.4 Effective Ratio (REFF) .......................................................................................................... 17 5.3.5 Ratio Configuration Summary ............................................................................................... 18 5.4 PLL Clock Output ........................................................................................................................... 19 5.5 Auxiliary Output .............................................................................................................................. 19 5.6 Clock Output Stability Considerations ............................................................................................ 20 5.6.1 Output Switching ................................................................................................................... 20 5.6.2 PLL Unlock Conditions .......................................................................................................... 20 6. SPI / I²C CONTROL PORT ................................................................................................................... 21 6.1 SPI Control ..................................................................................................................................... 21 6.2 I²C Control ...................................................................................................................................... 21 6.3 Memory Address Pointer ............................................................................................................... 23 6.3.1 Map Auto Increment .............................................................................................................. 23 7. REGISTER QUICK REFERENCE ........................................................................................................ 23 8. REGISTER DESCRIPTIONS ................................................................................................................ 24 8.1 Device I.D. and Revision (Address 01h) ....................................................................................... 24 8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 24 8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 24 8.2 Device Control (Address 02h) ........................................................................................................ 24 8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 24 8.2.2 PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only .................................................. 24 8.2.3 Auto R-Modifier Enable (AutoRMod) ..................................................................................... 25 8.2.4 Auxiliary Output Disable (AuxOutDis) ................................................................................... 25 8.2.5 PLL Clock Output Disable (ClkOutDis) .................................................................................. 25 8.3 Device Configuration 1 (Address 03h) ........................................................................................... 25 8.3.1 R-Mod Selection (RModSel[2:0]) ........................................................................................... 25 8.3.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 26 8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 26 8.4 Global Configuration (Address 05h) ............................................................................................... 26 8.4.1 Device Configuration Freeze (Freeze) ................................................................................ 26 8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ....................................................... 26 2 DS843PP1 CS2300-CP 8.5 Ratio (Address 06h - 09h) .............................................................................................................. 27 8.6 Function Configuration 1 (Address 16h) ........................................................................................ 27 8.6.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 27 8.6.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 27 8.6.3 Enable Device Configuration Registers 3 (EnDevCfg3) ........................................................ 27 8.7 Function Configuration 2 (Address 17h) ........................................................................................ 28 8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 28 8.7.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 28 8.8 Function Configuration 3 (Address 1Eh) ........................................................................................ 28 8.8.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 28 9. CALCULATING THE USER DEFINED RATIO .................................................................................... 29 9.1 High Resolution 12.20 Format ....................................................................................................... 29 9.2 High Multiplication 20.12 Format ................................................................................................... 29 10. PACKAGE DIMENSIONS .................................................................................................................. 30 THERMAL CHARACTERISTICS ......................................................................................................... 30 11. ORDERING INFORMATION .............................................................................................................. 31 12. REFERENCES .................................................................................................................................... 31 13. REVISION HISTORY .......................................................................................................................... 31 LIST OF FIGURES Figure 1. Typical Connection Diagram ........................................................................................................ 5 Figure 2. Control Port Timing - I²C Format .................................................................................................. 8 Figure 3. Control Port Timing - SPI Format (Write Only) ............................................................................ 9 Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 10 Figure 5. Hybrid Analog-Digital PLL .......................................................................................................... 11 Figure 6. External Component Requirements for LCO ............................................................................. 12 Figure 7. CLK_IN removed for > 223 LCO cycles ..................................................................................... 13 Figure 8. CLK_IN removed for < 223 LCO cycles but > tCS ...................................................................... 13 Figure 9. CLK_IN removed for < tCS ......................................................................................................... 14 Figure 10. Low bandwidth and new clock domain .................................................................................... 14 Figure 11. High bandwidth with CLK_IN domain re-use ........................................................................... 15 Figure 12. Ratio Feature Summary ........................................................................................................... 18 Figure 13. PLL Clock Output Options ....................................................................................................... 19 Figure 14. Auxiliary Output Selection ........................................................................................................ 19 Figure 15. Control Port Timing in SPI Mode ............................................................................................. 21 Figure 16. Control Port Timing, I²C Write .................................................................................................. 22 Figure 17. Control Port Timing, I²C Aborted Write + Read ....................................................................... 22 LIST OF TABLES Table 1. PLL Input Clock Range Indicator ................................................................................................ 12 Table 2. Ratio Modifier .............................................................................................................................. 16 Table 3. Automatic Ratio Modifier ............................................................................................................. 16 Table 4. Example Audio Oversampling Clock Generation from CLK_IN .................................................. 17 Table 5. Example 12.20 R-Values ............................................................................................................ 29 Table 6. Example 20.12 R-Values ............................................................................................................ 29 DS843PP1 3 CS2300-CP 1. PIN DESCRIPTION VD GND CLK_OUT AUX_OUT CLK_IN 1 2 3 4 5 10 9 8 7 6 SDA/CDIN SCL/CCLK AD0/CS FILTN FILTP Pin Name VD GND CLK_OUT AUX_OUT CLK_IN FILTP FILTN AD0/CS SCL/CCLK SDA/CDIN # 1 2 3 4 5 6 7 8 9 Pin Description Digital Power (Input) - Positive power supply for the digital and analog sections. Ground (Input) - Ground reference. PLL Clock Output (Output) - PLL clock output. Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks, or a status signal, depending on register configuration. Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference. LCO Filter Connections (Input/Output) - These pins provide external supply filtering for the internal LC Oscillator. Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode. CS is the chip select signal in SPI Mode. Control Port Clock (Input) - SCL/CCLK is the serial clock for the serial control port in I²C and SPI mode. 10 Serial Control Data (Input/Output) - SDA is the data I/O line in I²C Mode. CDIN is the input data line for the control port interface in SPI Mode. 4 DS843PP1 CS2300-CP 2. TYPICAL CONNECTION DIAGRAM Note1 Notes: 1. Resistors required for I2C operation. 0.1 µF 2 kΩ 2 kΩ 1 µF +3.3 V VD SCL/CCLK System MicroController SDA/CDIN AD0/CS CS2300-CP Frequency Reference CLK_IN FILTP AUX_OUT FILTN GND CLK_OUT To circuitry which requires a low-jitter clock To other circuitry or Microcontroller 0.1 µF Figure 1. Typical Connection Diagram DS843PP1 5 CS2300-CP 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. (Note 1) Parameters DC Power Supply Ambient Operating Temperature (Power Applied) Commercial Grade TAC -10 +70 °C Symbol VD Min 3.1 Typ 3.3 Max 3.5 Units V Notes: 1. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. ABSOLUTE MAXIMUM RATINGS GND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Input Current Digital Input Voltage (Note 1) Ambient Operating Temperature (Power Applied) Storage Temperature Symbol VD IIN VIN TA Tstg Min -0.3 -0.3 -55 -65 Max 6.0 ±10 VD + 0.4 125 150 Units V mA V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Notes: 1. The maximum over/under voltage is limited by the input current except on the power supply pin. DC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade). Parameters Power Supply Current - Unloaded Power Dissipation - Unloaded Input Leakage Current Input Capacitance High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (IOH = -1.2 mA) Low-Level Output Voltage (IOH = 1.2 mA) (Note 2) (Note 2) Symbol ID PD IIN IC VIH VIL VOH VOL Min 70% 80% - Typ 18 59 8 - Max 23 76 ±10 30% 20% Units mA mW µA pF VD VD VD VD Notes: 2. To calculate the additional current consumption due to loading (per output pin), multiply clock output frequency by load capacitance and power supply voltage. For example, fCLK_OUT (49.152 MHz) * CL(15 pF) * VD (3.3 V) = 2.4 mA of additional current due to these loading conditions on CLK_OUT. 6 DS843PP1 CS2300-CP AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); CL = 15 pF. Parameters Clock Input Frequency (Auto R-Mod Disabled) Clock Input Frequency (Auto R-mod Enabled) Symbol fCLK_IN fCLK_IN Conditions Auto R Modifier = 1 Auto R Modifier = 0.5 Auto R Modifier = 0.25 fCLK_IN < 175 kHz fCLK_IN > 175 kHz (Notes 3, 4) (Note 4) Measured at VD/2 20% to 80% of VD 80% to 20% of VD (Note 5) (Notes 5, 6) (Notes 5, 7) Min 50 Hz 4 72 168 140 10 20 50 Hz 6 48 - Typ 50 1.7 1.7 35 50 150 100 1 Max 30 59 138 256 80 75 52 3.0 3.0 110 200 3 Units MHz kHz kHz kHz ns ns ms kHz MHz % ns ns ps rms ps rms ps rms UI ms Clock Input Pulse Width Clock Skipping Timeout Clock Skipping Input Frequency PLL Clock Output Frequency PLL Clock Output Duty Cycle Clock Output Rise Time Clock Output Fall Time Period Jitter Base Band Jitter (100 Hz to 40 kHz) Wide Band JItter (100 Hz Corner) PLL Lock Time - CLK_IN (Note 8) pwCLK_IN tCS fCLK_SKIP fCLK_OUT tOD tOR tOF tJIT tLC fCLK_IN < 200 kHz fCLK_IN > 200 kHz Notes: 3. tCS represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequency, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will result in larger values of tCS. 4. Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page 13 for more information. 5. fCLK_OUT = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11. 6. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd order 100 Hz to 40 kHz bandpass filter. 7. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd order 100 Hz Highpass filter. 8. 1 UI (unit interval) corresponds to tCLK_IN or 1/fCLK_IN. DS843PP1 7 CS2300-CP CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; CL = 20 pF. Parameter SCL Clock Frequency Bus Free-Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup Time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling Delay from Supply Voltage Stable to Control Port Ready (Note 9) Symbol fscl tbuf thdst tlow thigh tsust thdd tsud tr tf tsusp tack tdpor Min 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 100 Max 100 1 300 1000 - Unit kHz µs µs µs µs µs µs ns µs ns µs ns µs Notes: 9. Data must be held for sufficient time to bridge the transition time, tf, of SCL. VD t dpor Repeated Start Stop SDA t buf t hdst t high t hdst tf t susp SCL Stop Start t low t hdd t sud t sust tr Figure 2. Control Port Timing - I²C Format 8 DS843PP1 CS2300-CP CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; CL = 20 pF. Parameter CCLK Clock Frequency CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN Delay from Supply Voltage Stable to Control Port Ready (Note 11) (Note 12) (Note 12) (Note 10) Symbol fccllk tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2 tdpor Min 500 1.0 20 66 66 40 15 100 Max 6 100 100 - Unit MHz ns µs ns ns ns ns ns ns ns µs Notes: 10. tspi is only needed before first falling edge of CS after power is applied. tspi = 0 at all other times. 11. Data must be held for sufficient time to bridge the transition time of CCLK. 12. For fcclk < 1 MHz. VD tdpor CS t spi CCLK t r2 CDIN t css t scl t sch t csh t f2 t dsu tdh Figure 3. Control Port Timing - SPI Format (Write Only) DS843PP1 9 CS2300-CP 4. ARCHITECTURE OVERVIEW 4.1 Delta-Sigma Fractional-N Frequency Synthesizer The core of the CS2300 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolution for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to quickly tune to a new frequency. The reference for the synthesizer is an on chip LC Oscillator (LCO) which generates the necessary internal stable clocks. In very simplistic terms, the Fractional-N Frequency Synthesizer multiplies the LC Oscillator by the value of N to generate the PLL output clock. The desired output to input clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 4). The analog PLL based frequency synthesizer uses a low-jitter timing reference clock, the LCO, as a time and phase reference for the internal voltage controlled oscillator (VCO). The phase comparator compares the fractional-N divided clock with the original timing reference and generates a control signal. The control signal is filtered by the internal loop filter to generate the VCO’s control voltage which sets its output frequency. The delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio between the reference clock and the VCO output (thus the one’s density of the modulator sets the fractional value). This allows the design to be optimized for very fast lock times for a wide range of output frequencies without the need for external filter components. LC Oscillator Phase Comparator Internal Loop Filter Voltage Controlled Oscillator PLL Output Fractional-N Divider Delta-Sigma Modulator N Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer 4.2 Hybrid Analog-Digital Phase Locked Loop The addition of the Digital PLL and Fractional-N Logic (shown in Figure 5) to the Fractional-N Frequency Synthesizer creates the Hybrid Analog-Digital Phase Locked Loop with many advantages over classical analog PLL techniques. These advantages include the ability to operate over extremely wide frequency ranges without the need to change external loop filter components while maintaining impressive jitter reduction performance. In the Hybrid architecture, the Digital PLL calculates the ratio of the PLL output clock to the frequency reference and compares that to the desired ratio. The digital logic generates a value of N which is then applied to the Fractional-N frequency synthesizer to generate the desired PLL output frequency. Notice that the frequency and phase of the LCO does not affect the output of the PLL since the digital control loop will correct for the PLL output. A major advantage of the Digital PLL is the ease with which the loop filter bandwidth can be altered. The PLL bandwidth is automatically set to a wide-bandwidth mode to quickly achieve lock and then reduced for optimal jitter rejection. 10 DS843PP1 CS2300-CP Delta-Sigma Fractional-N Frequency Synthesizer LCO Phase Comparator Internal Loop Filter Voltage Controlled Oscillator PLL Output Fractional-N Divider Delta-Sigma Modulator Digital PLL and Fractional-N Logic N Digital Filter Frequency Reference Clock Frequency Comparator for Frac-N Generation Output to Input Ratio for Hybrid mode Figure 5. Hybrid Analog-Digital PLL DS843PP1 11 CS2300-CP 5. APPLICATIONS 5.1 Timing Reference Clock The internal LC oscillator is used to generate the internal timing reference clock (see section 4 “Architecture Overview” on page 10 for information on how this internal clock is used by the CS2300). A single 0.1 µF cap must be connected between the FILTP and FILTN pins and the FILTN pin must be connected to ground as shown in Figure 6. FILTN FILTP C Figure 6. External Component Requirements for LCO 5.2 Frequency Reference Clock Input, CLK_IN The frequency reference clock input (CLK_IN) is used by the Digital PLL and Fractional-N Logic block to dynamically generate a fractional-N value for the Frequency Synthesizer (see “Hybrid Analog-Digital PLL” on page 11). The Digital PLL first compares the CLK_IN frequency to the PLL output. The Fractional-N logic block then translates the desired ratio based off of CLK_IN to one based off of the internal LCO. This allows the low-jitter internal LCO to be used as the clock which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference clock through the Digital PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Characteristics” on page 7. 5.2.1 CLK_IN Frequency Detector The CLK_IN frequency range detector determines and indicates the ratio between the frequency of the internal LCO and the CLK_IN input signal. The result of the ratio measurement is available in the read-only FsDet[1:0] bits and is also used by the device to determine the Auto R-Mod value. FsDetect[1:0] 00 01 10 11 fLCO / fCLK_IN Ratio > 224 96 - 224 < 96 Reserved Table 1. PLL Input Clock Range Indicator Because fLCO is known, FsDet[1:0] can then be interpreted as a range for fCLK_IN. This feature is particularly useful when used in conjunction with the Auto R-Mod feature (see section 5.3.3 on page 16). Referenced Control Register Location FsDet[1:0]..............................“PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only” section on page 24 12 DS843PP1 CS2300-CP 5.2.2 CLK_IN Skipping Mode CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses for up to 20 ms (tCS) at a time (see “AC Electrical Characteristics” on page 7 for specifications). CLK_IN skipping mode can only be used when the CLK_IN frequency is below 80 kHz. The ClkSkipEn bit enables this function. Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 223 LCO cycles (518 ms to 634 ms) after CLK_IN is removed (see Figure 7). This is true as long as CLK_IN does not glitch or have an effective change in period as the clock source is removed, otherwise the PLL will interpret this as a change in frequency causing clock skipping and the 223 LCO cycle time-out to be bypassed and the PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and 223 LCO cycles pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See “PLL Clock Output” on page 19. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified time listed in the “AC Electrical Characteristics” on page 7 after which lock will be acquired and the PLL output will resume. 223 LCO cycles Lock Time 223 LCO cycles Lock Time CLK_IN ClkSkipEn=0 or 1 ClkOutUnl=0 CLK_IN ClkSkipEn=0 or 1 ClkOutUnl=1 PLL_OUT UNLOCK PLL_OUT UNLOCK = invalid clocks Figure 7. CLK_IN removed for > 2 23 LCO cycles If CLK_IN is removed and then reapplied within 223 LCO cycles but later than tCS, the ClkSkipEn bit will have no effect and the PLL output will continue until CLK_IN is re-applied (see Figure 8). Once CLK_IN is re-applied, the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl bit during this time. tCS Lock Time 223 LCO cycles 223 LCO cycles tCS Lock Time CLK_IN ClkSkipEn=0 or 1 ClkOutUnl=0 CLK_IN ClkSkipEn=0 or 1 ClkOutUnl=1 PLL_OUT UNLOCK PLL_OUT UNLOCK = invalid clocks Figure 8. CLK_IN removed for < 223 LCO cycles but > tCS If CLK_IN is removed and then re-applied within tCS, the ClkSkipEn bit determines whether PLL_OUT continues while the PLL re-acquires lock (see Figure 9). When ClkSkipEn is disabled and CLK_IN is removed the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl bit during this DS843PP1 13 CS2300-CP time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will remain continuous throughout the missing CLK_IN period including the time while the PLL re-acquires lock. tCS tCS Lock Time CLK_IN ClkSkipEn=1 ClkOutUnl=0 or 1 CLK_IN ClkSkipEn=0 ClkOutUnl=1 PLL_OUT UNLOCK PLL_OUT UNLOCK = invalid clocks Lock Time tCS CLK_IN ClkSkipEn=0 ClkOutUnl=0 PLL_OUT UNLOCK Figure 9. CLK_IN removed for < tCS Referenced Control Register Location ClkSkipEn..............................“Clock Skip Enable (ClkSkipEn)” on page 27 ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 28 5.2.3 Adjusting the Minimum Loop Bandwidth for CLK_IN The CS2000 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and 128 Hz using the ClkIn_BW[2:0] bits. The minimum loop bandwidth of the Digital PLL directly affects the jitter transfer function; specifically, jitter frequencies below the loop bandwidth corner are passed from the PLL input directly to the PLL output without attenuation. In some applications it is desirable to have a very low minimum loop bandwidth to reject very low jitter frequencies, commonly referred to as wander. In others it may be preferable to remove only higher frequency jitter, allowing the input wander to pass through the PLL without attenuation. Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other system clocks and associated data are derived will benefit from the maximum jitter and wander rejection of the lowest PLL bandwidth setting. See Figure 10. CLK_IN PLL BW = 1 Hz or PLL_OUT Wander and Jitter > 1 Hz Rejected Wander > 1 Hz Jitter MCLK Subclocks generated from new clock domain. MCLK LRCK SCLK SDATA D0 D1 LRCK SCLK SDATA D0 D1 Figure 10. Low bandwidth and new clock domain Systems in which some clocks and data are derived from the PLL_OUT signal while other clocks and data are derived from the CLK_IN signal will often require phase alignment of all the clocks and data in the system. See Figure 11. If there is substantial wander on the CLK_IN signal in these applications, it may be necessary to increase the minimum loop bandwidth allowing this wander to pass through to the 14 DS843PP1 CS2300-CP CLK_OUT signal in order to maintain phase alignment. For these applications, it is advised to experiment with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system timing errors due to wandering between the clocks and data synchronous to the CLK_IN domain and those synchronous to the PLL_OUT domain. CLK_IN PLL BW = 128 Hz or PLL_OUT Jitter > 128 Hz Rejected Wander < 128 Hz Passed to Output Wander < 128 Hz Jitter MCLK MCLK LRCK SCLK SDATA D0 D1 Subclocks and data re-used from previous clock domain. LRCK SCLK SDATA D0 D1 Figure 11. High bandwidth with CLK_IN domain re-use It should be noted that manual adjustment of the minimum loop bandwidth is not necessary to acquire lock; this adjustment is made automatically by the Digital PLL. While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] bits. Referenced Control Register Location ClkIn_BW[2:0] .......................“Clock Input Bandwidth (ClkIn_BW[2:0])” on page 28 5.3 5.3.1 Output to Input Frequency Ratio Configuration User Defined Ratio (RUD) The User Defined Ratio, RUD, is a 32-bit un-signed fixed-point number, stored in the Ratio register set, which determines the basis for the desired input to output clock ratio. The 32-bit RUD can be expressed in either a high resolution (12.20) or high multiplication (20.12) format selectable by the LFRatioCfg bit, with 20.12 being the default. The RUD for high resolution (12.20) format is encoded with 12 MSBs representing the integer binary portion with the remaining 20 LSBs representing the fractional binary portion. The maximum multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See “Calculating the User Defined Ratio” on page 29 for more information. The RUD for high multiplication (20.12) format is encoded with 20 MSBs representing the integer binary portion with the remaining 12 LSBs representing the fractional binary portion. In this configuration, the maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM. It is recommended that the 12.20 High-Resolution format be utilized whenever the desired ratio is less than 4096 since the output frequency accuracy of the PLL is directly proportional to the accuracy of the timing reference clock and the resolution of the RUD. Referenced Control Register Location Ratio......................................“Ratio (Address 06h - 09h)” on page 27 LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 28 DS843PP1 15 CS2300-CP 5.3.2 Manual Ratio Modifier (R-Mod) The manual Ratio Modifier is used to internally multiply/divide the RUD (the Ratio stored in the register space remains unchanged). The available options for RMOD are summarized in Table 2 on page 16. The R-Mod value selected by RModSel[2:0] is always used in the calculation for the Effective Ratio (REFF), see “Effective Ratio (REFF)” on page 17. If R-Mod is not desired, RModSel[2:0] should be left at its default value of ‘000’, which corresponds to an R-Mod value of 1, thereby effectively disabling the ratio modifier. RModSel[2:0] 000 001 010 011 100 101 110 111 Ratio Modifier 1 2 4 8 0.5 0.25 0.125 0.0625 Table 2. Ratio Modifier Referenced Control Register Location Ratio......................................“Ratio (Address 06h - 09h)” on page 27 RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 25 5.3.3 Automatic Ratio Modifier (Auto R-Mod) The Automatic R-Modifier uses the status of the CLK_IN Frequency Range Indicator (see section 5.2.1 on page 12) to implement a frequency dependent multiply of the currently addressed RUD as shown in Table 3. Like with R-Mod, the Ratio stored in the register space remain unchanged. The Automatic Ratio-Modifier is enabled by the AutoRMod bit. FsDetect[1:0] 00 01 10 fLCO / fCLK_IN > 224 96 - 224 < 96 Auto R Modifier 1 0.5 0.25 Table 3. Automatic Ratio Modifier It is important to note that Auto R-Mod (if enabled) is applied in addition to any R-Mod already selected by the RModSel[2:0] bits and is used to calculate the Effective Ratio (see Section 5.3.4 on page 17). Auto R-Mod can be used to generate the appropriate oversampling clock (MCLK) for audio A/D and D/A converters. For example, when the clock applied to CLK_IN is the audio sample rate, Fs (also known as the word, frame or Left/Right clock), and the internal LCO is known to be between 13.23 MHz and 16.17 16 DS843PP1 CS2300-CP MHz, then FsDetect[1:0] reflects the frequency range of the audio sample rate. An RUD of 512 generates the audio oversampling clocks as shown in Table 4. Speed Mode (used for audio converters) Single Speed Double Speed FsDetect[1:0] 00 01 Inferred Audio Sample Rate < [59 to 72] kHz >[59 to 72] kHz and [138 to 168] kHz Audio Oversampling Clock 512 x 256 x 10 Quad Speed 128 x Table 4. Example Audio Oversampling Clock Generation from CLK_IN Referenced Control Register Location Ratio......................................“Ratio (Address 06h - 09h)” on page 27 RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 25 AutoRMod .............................“Auto R-Modifier Enable (AutoRMod)” on page 25 5.3.4 Effective Ratio (REFF) The Effective Ratio (REFF) is an internal calculation comprised of RUD and the appropriate modifiers, as previously described. REFF is calculated as follows: REFF = RUD • RMOD • Auto R-Mod Ratio modifiers which would produce an overflow or truncation of REFF should not be used; For example if RUD is 1024 an RMOD of 8 would produce an REFF value of 8192 which exceeds the 4096 limit of the 12.20 format. In all cases, the maximum and minimum allowable values for REFF are dictated by the frequency limits for both the input and output clocks as shown in the “AC Electrical Characteristics” on page 7. DS843PP1 17 CS2300-CP 5.3.5 Ratio Configuration Summary The RUD is the user defined ratio stored in the register space. The resolution for the RUD is selectable by setting LFRatioCfg. R-Mod is applied if selected. The user defined ratio, ratio modifier, and automatic ratio modifier make up the effective ratio REFF, the final calculation used to determine the output to input clock ratio. The conceptual diagram in Figure 12 summarizes the features involved in the calculation of the ratio values used to generate the fractional-N value which controls the Frequency Synthesizer. LCO Frequency Synthesizer Effective Ratio REFF N PLL Output User Defined Ratio RUD Ratio Ratio Format 12.20 20.12 RModSel[2:0] Ratio Modifier Auto R-Mod Digital PLL & Fractional N Logic LFRatioCfg AutoRMod FsDet[1:0] Frequency Reference Clock (CLK_IN) Figure 12. Ratio Feature Summary Referenced Control Register Location Ratio......................................“Ratio (Address 06h - 09h)” on page 27 LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 28 RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 25 AutoRMod .............................“Auto R-Modifier Enable (AutoRMod)” on page 25 FsDet[1:0]..............................“PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only” section on page 24 18 DS843PP1 CS2300-CP 5.4 PLL Clock Output The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the ClkOutDis bit. The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state CLK_OUT may then be unreliable during an unlock condition. ClkOutUnl PLL Locked/Unlocked 0 0 2:1 Mux 1 0 PLL Clock Output PLLClkOut ClkOutDis 2:1 Mux PLL Output 1 PLL Clock Output Pin (CLK_OUT) Figure 13. PLL Clock Output Options Referenced Control Register Location ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 28 ClkOutDis ..............................“PLL Clock Output Disable (ClkOutDis)” on page 25 5.5 Auxiliary Output The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 14, to one of three signals: input clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is controlled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is then used to control the output driver type and polarity of the LOCK signal (see section 8.6.2 on page 27). If AUX_OUT is set to CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The driver for the pin can be set to high-impedance using the AuxOutDis bit. AuxOutSrc[1:0] Frequency Reference Clock (CLK_IN) AuxOutDis PLL Clock Output (PLLClkOut) 3:1 Mux Auxiliary Output Pin (AUX_OUT) PLL Lock/Unlock Indication (Lock) AuxLockCfg Figure 14. Auxiliary Output Selection Referenced Control Register Location AuxOutSrc[1:0]......................“Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 26 AuxOutDis .............................“Auxiliary Output Disable (AuxOutDis)” on page 25 AuxLockCfg...........................“AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 27 DS843PP1 19 CS2300-CP 5.6 5.6.1 Clock Output Stability Considerations Output Switching CS2300 is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an output, and the automatic disabling of the output(s) during unlock will not cause a runt or partial clock period. The following exceptions/limitations exist: • • • Enabling/disabling AUX_OUT when AuxOutSrc = 11 (unlock indicator). Switching AuxOutSrc[1:0] to or from 01 (PLL clock input) and to or from 11 (unlock indicator) (Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch). Changing the ClkOutUnl bit while the PLL is in operation. When any of these exceptions occur, a partial clock period on the output may result. 5.6.2 PLL Unlock Conditions Certain changes to the clock inputs and registers can cause the PLL to lose lock which will affect the presence the clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go unlocked: • • • Changes made to the registers which affect the Fraction-N value that is used by the Frequency Synthesizer. This includes all the bits shown in Figure 12 on page 18. Any discontinuities on the Timing Reference Clock, REF_CLK. Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature is enabled and the requirements of Clock Skipping are satisfied (see “CLK_IN Skipping Mode” on page 13). Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency. Step changes in CLK_IN frequency. • • 20 DS843PP1 CS2300-CP 6. SPI / I²C CONTROL PORT The control port is used to access the registers and allows the device to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to device inputs and outputs. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates with either the SPI or I²C interface, with the CS2300 acting as a slave device. SPI Mode is selected if there is a high-to-low transition on the AD0/CS pin after power-up. I²C Mode is selected by connecting the AD0/CS pin through a resistor to VD or GND, thereby permanently selecting the desired AD0 bit address state. In both modes the EnDevCfg1, EnDevCfg2, and EnDevCfg3 bits must be set to 1 for normal operation. WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation. Referenced Control Register Location EnDevCfg1 ............................“Enable Device Configuration Registers 1 (EnDevCfg1)” on page 26 EnDevCfg2 ............................“Enable Device Configuration Registers 2 (EnDevCfg2)” section on page 26 EnDevCfg3 ............................“Enable Device Configuration Registers 3 (EnDevCfg3)” section on page 27 6.1 SPI Control In SPI Mode, CS is the chip select signal; CCLK is the control port bit clock (sourced from a microcontroller), and CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The device only supports write operations. Figure 15 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first eight bits on CDIN form the chip address and must be 10011110. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. There is MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will automatically increment after each byte is read or written, allowing block writes of successive registers. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CCLK CHIP ADDRESS MAP BYTE 1 0 INCR DATA 1 0 7 6 1 0 7 DATA +n 6 1 0 CDIN 1 0 0 1 1 1 6 5 4 3 2 Figure 15. Control Port Timing in SPI Mode 6.2 I²C Control In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL. There is no CS pin. The AD0 pin forms the least-significant bit of the chip address and should be connected to VD or GND as appropriate. The state of the AD0 pin should be maintained throughout operation of the device. The signal timings for a read and write cycle are shown in Figure 16 and Figure 17. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS2300 after a Start condition consists of the 7-bit chip address field and a R/W bit (high for a read, low for a write). The DS843PP1 21 CS2300-CP upper 6 bits of the 7-bit address field are fixed at 100111 followed by the logic state of the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS2300 after each input byte is read and is input from the microcontroller after each transmitted byte. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) MAP BYTE 0 INCR DATA 1 0 7 6 1 0 7 DATA +1 6 1 0 7 DATA +n 6 1 0 SDA 1 0 0 1 1 1 AD0 6 5 4 3 2 ACK START ACK ACK ACK STOP Figure 16. Control Port Timing, I²C Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) MAP BYTE INCR STOP 1 0 1 CHIP ADDRESS (READ) 0 0 1 0 1 AD0 1 DATA 7 0 DATA +1 7 0 DATA + n 7 0 SDA 1 0 0 1 1 1 AD0 0 6 5 4 3 2 ACK START ACK START ACK ACK NO ACK STOP Figure 17. Control Port Timing, I²C Aborted Write + Read Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 16, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 100111x0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 100111x1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. 22 DS843PP1 CS2300-CP 6.3 Memory Address Pointer The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read or written. Refer to the pseudocode above for implementation details. 6.3.1 Map Auto Increment The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is read or written, allowing block reads or writes of successive registers. 7. REGISTER QUICK REFERENCE This table shows the register and bit names with their associated default values. EnDevCfg1, EnDevCfg2, and EnDevCfg3 bits must be set to 1 for normal operation. WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation. Adr p 24 02h Device Ctrl p 24 03h Device Cfg 1 p 25 05h Global Cfg p 26 06h - 32-Bit Ratio 09h 16h Funct Cfg 1 p 27 17h Funct Cfg 2 p 28 1Eh Funct Cfg 3 p 28 Name 7 6 5 4 3 2 1 0 Revision0 x ClkOutDis 0 EnDevCfg1 0 EnDevCfg2 0 MSB-7 MSB-15 LSB+8 LSB Reserved 0 Reserved 0 Reserved 0 01h Device ID Device4 Device3 Device2 Device1 Device0 Revision2 Revision1 0 0 0 0 0 x x Unlock FsDet1 FsDet0 Reserved AutoRMod Reserved AuxOutDis x x x 0 0 0 0 RModSel2 RModSel1 RModSel0 Reserved Reserved AuxOutSrc1 AuxOutSrc0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Freeze Reserved Reserved 0 0 0 0 0 0 0 MSB ........................................................................................................................... MSB-8 ........................................................................................................................... LSB+15 ........................................................................................................................... LSB+7 ........................................................................................................................... ClkSkipEn AuxLockCfg Reserved EnDevCfg3 Reserved Reserved Reserved 0 0 0 0 0 0 0 Reserved Reserved Reserved ClkOutUnl LFRatioCfg Reserved Reserved 0 0 0 0 0 0 0 Reserved ClkIn_BW2 ClkIn_BW1 ClkIn_BW0 Reserved Reserved Reserved 0 0 0 0 0 0 0 DS843PP1 23 CS2300-CP 8. REGISTER DESCRIPTIONS In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Reserved” registers must maintain their default state to ensure proper functional operation. The default state of each bit after a power-up sequence or reset is indicated by the shaded row in the bit decode table and in the “Register Quick Reference” on page 23. Control port mode is entered when the device recognizes a valid chip address input on its I²C/SPI serial control pins and the EnDevCfg1, EnDevCfg2, and EnDevCfg3 bits are set to 1. 8.1 Device I.D. and Revision (Address 01h) 6 Device3 5 Device2 4 Device1 3 Device0 2 Revision2 1 Revision1 0 Revision0 7 Device4 8.1.1 Device Identification (Device[4:0]) - Read Only I.D. code for the CS2300. Device[4:0] 00000 Device CS2300. 8.1.2 Device Revision (Revision[2:0]) - Read Only CS2300 revision level. REVID[2:0] 100 Revision Level B2. 8.2 Device Control (Address 02h) 7 Unlock 6 FsDet1 5 FsDet0 4 Reserved 3 AutoRMod 2 Reserved 1 AuxOutDis 0 ClkOutDis 8.2.1 Unlock Indicator (Unlock) - Read Only Indicates the lock state of the PLL. Unlock 0 1 PLL Lock State PLL is Locked. PLL is Unlocked. 8.2.2 PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only Indicates the range of the frequency of CLK_IN relative to the frequency of the internal LCO. For audio applications, this can be used to distinguish single-, double-, and quad-speed modes. FsDet[1:0] 00 01 10 11 Application: fLCO / fCLK_IN > 224. 96 to 224. < 96. Reserved. “CLK_IN Frequency Detector” on page 12 24 DS843PP1 CS2300-CP 8.2.3 Auto R-Modifier Enable (AutoRMod) Controls the automatic ratio modifier function. AutoRMod 0 1 Application: Automatic R-Mod State Disabled. Enabled. “Automatic Ratio Modifier (Auto R-Mod)” on page 16 8.2.4 Auxiliary Output Disable (AuxOutDis) This bit controls the output driver for the AUX_OUT pin. AuxOutDis 0 1 Application: Output Driver State AUX_OUT output driver enabled. AUX_OUT output driver set to high-impedance. “Auxiliary Output” on page 19 8.2.5 PLL Clock Output Disable (ClkOutDis) This bit controls the output driver for the CLK_OUT pin. ClkOutDis 0 1 Application: Output Driver State CLK_OUT output driver enabled. CLK_OUT output driver set to high-impedance. “PLL Clock Output” on page 19 8.3 Device Configuration 1 (Address 03h) 6 RModSel1 5 RModSel0 4 Reserved 3 Reserved 2 AuxOutSrc1 1 AuxOutSrc0 0 EnDevCfg1 7 RModSel2 8.3.1 R-Mod Selection (RModSel[2:0]) Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N. RModSel[2:0] 000 001 010 011 100 101 110 111 Application: R-Mod Selection Left-shift R-value by 0 (x 1). Left-shift R-value by 1 (x 2). Left-shift R-value by 2 (x 4). Left-shift R-value by 3 (x 8). Right-shift R-value by 1 (÷ 2). Right-shift R-value by 2 (÷ 4). Right-shift R-value by 3 (÷ 8). Right-shift R-value by 4 (÷ 16). “Manual Ratio Modifier (R-Mod)” on page 16 DS843PP1 25 CS2300-CP 8.3.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) Selects the source of the AUX_OUT signal. AuxOutSrc[1:0] 00 01 10 11 Application: Auxiliary Output Source Reserved. CLK_IN. CLK_OUT. PLL Lock Status Indicator. “Auxiliary Output” on page 19 Note: When set to 11, AuxLckCfg sets the polarity and driver type (“AUX PLL Lock Output Configuration (AuxLockCfg)” on page 27). 8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) This bit, in conjunction with EnDevCfg2 and EnDevCfg3, enables control port mode. All three bits must be set to 1 during initialization. EnDevCfg1 0 1 Application: Register State Disabled. Enabled. “SPI / I²C Control Port” on page 21 Note: EnDevCfg2 and EnDevCfg3 must also be set to enable control port mode (“SPI / I²C Control Port” on page 21). 8.4 Global Configuration (Address 05h) 6 Reserved 5 Reserved 4 Reserved 3 Freeze 2 Reserved 1 Reserved 0 EnDevCfg2 7 Reserved 8.4.1 Device Configuration Freeze (Freeze) Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h) but keeps them from taking effect until this bit is cleared. FREEZE 0 1 Device Control and Configuration Registers Register changes take effect immediately. Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without the changes taking effect until after the FREEZE bit is cleared. 8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) This bit, in conjunction with EnDevCfg1 and EnDevCfg3, enables control port mode. All three bits must be set to 1 during initialization. EnDevCfg2 0 1 Application: Register State Disabled. Enabled. “SPI / I²C Control Port” on page 21 Note: EnDevCfg1 and EnDevCfg3 must also be set to enable control port mode (“SPI / I²C Control Port” on page 21). 26 DS843PP1 CS2300-CP 8.5 Ratio (Address 06h - 09h) 6 5 4 3 2 1 ................................................................................................................................................... ................................................................................................................................................... ................................................................................................................................................... ................................................................................................................................................... 0 MSB-7 MSB-15 LSB+8 LSB 7 MSB MSB-8 LSB+15 LSB+7 These registers contain the User Defined Ratio as shown in the “Register Quick Reference” section on page 23. These 4 registers form a single 32-bit ratio value as shown above. See “Output to Input Frequency Ratio Configuration” on page 15 and “Calculating the User Defined Ratio” on page 29 for more details. 8.6 Function Configuration 1 (Address 16h) 6 AuxLockCfg 5 Reserved 4 EnDevCfg3 3 Reserved 2 Reserved 1 Reserved 0 Reserved 7 ClkSkipEn 8.6.1 Clock Skip Enable (ClkSkipEn) This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the CLK_IN has missing pulses. ClkSkipEn 0 1 Application: PLL Clock Skipping Mode Disabled. Enabled. “CLK_IN Skipping Mode” on page 13 Note: fCLK_IN must be < 80 kHz to use this feature. 8.6.2 AUX PLL Lock Output Configuration (AuxLockCfg) When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this bit is disregarded. AuxLockCfg 0 1 Application: AUX_OUT Driver Configuration Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition). Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition). “Auxiliary Output” on page 19 Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. Therefore, the pin polarity is defined relative to the unlock condition. 8.6.3 Enable Device Configuration Registers 3 (EnDevCfg3) This bit, in conjunction with EnDevCfg1 and EnDevCfg2, enables control port mode. All three bits must be set to 1 during initialization. EnDevCfg3 0 1 Application: Register State Disabled. Enabled. “SPI / I²C Control Port” on page 21 Note: EnDevCfg1 and EnDevCfg2 must also be set to enable control port mode (“SPI / I²C Control Port” on page 21). DS843PP1 27 CS2300-CP 8.7 Function Configuration 2 (Address 17h) 6 Reserved 5 Reserved 4 ClkOutUnl 3 LFRatioCfg 2 Reserved 1 Reserved 0 Reserved 7 Reserved 8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) Defines the state of the PLL output during the PLL unlock condition. ClkOutUnl 0 1 Application: Clock Output Enable Status Clock outputs are driven ‘low’ when PLL is unlocked. Clock outputs are always enabled (results in unpredictable output when PLL is unlocked). “PLL Clock Output” on page 19 8.7.2 Low-Frequency Ratio Configuration (LFRatioCfg) Determines how to interpret the 32-bit User Defined Ratio. LFRatioCfg 0 1 Application: Ratio Bit Encoding Interpretation 20.12 - High Multiplier. 12.20 - High Accuracy. “User Defined Ratio (RUD)” on page 15 8.8 Function Configuration 3 (Address 1Eh) 6 ClkIn_BW2 5 ClkIn_BW1 4 ClkIn_BW0 3 Reserved 2 Reserved 1 Reserved 0 Reserved 7 Reserved 8.8.1 Clock Input Bandwidth (ClkIn_BW[2:0]) Sets the minimum loop bandwidth when locked to CLK_IN. ClkIn_BW[2:0] 000 001 010 011 100 101 110 111 Application: Minimum Loop Bandwidth 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 128 Hz “Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 14 Note: In order to guarantee that a change in minimum bandwidth takes effect, these bits must be set prior to acquiring lock (removing and re-applying CLK_IN can provide the unlock condition necessary to initiate the setting change). In production systems these bits should be configured with the desired values prior to setting the EnDevCfg bits; this guarantees that the setting takes effect prior to acquiring lock. 28 DS843PP1 CS2300-CP 9. CALCULATING THE USER DEFINED RATIO Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User Defined Ratio. This section is for those who are not interested in the software or who are developing their systems without the aid of the evaluation kit. Most calculators do not interpret the fixed point binary representation which the CS2300 uses to define the output to input clock ratio (see Section 5.3.1 on page 15); However, with a simple conversion we can use these tools to generate a binary or hex value which can be written to the Ratio register. 9.1 High Resolution 12.20 Format To calculate the User Defined Ratio (RUD) to store in the register(s), divide the desired output clock frequency by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 220 to get the scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and write to the register. A few examples have been provided in Table 5. Desired Output to Input Clock Ratio (output clock/input clock) 12.288 MHz/10 MHz=1.2288 11.2896 MHz/44.1 kHz=256 Scaled Decimal Representation = (output clock/input clock) • 220 1288490 268435456 Hex Representation of Binary RUD 00 13 A9 2A 10 00 00 00 Table 5. Example 12.20 R-Values 9.2 High Multiplication 20.12 Format To calculate the User Defined Ratio (RUD) to store in the register(s), divide the desired output clock frequency by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 212 to get the scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and write to the register. A few examples have been provided in Table 6. Desired Output to Input Clock Ratio (output clock/input clock) 12.288 MHz/60 Hz=204,800 11.2896 MHz/59.97 Hz =188254.127... Scaled Decimal Representation = (output clock/input clock) • 212 838860800 771088904 Hex Representation of Binary RUD 32 00 00 00 2D F5 E2 08 Table 6. Example 20.12 R-Values DS843PP1 29 CS2300-CP 10.PACKAGE DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1) N D c E A2 A1 L E11 A ∝ e b END VIEW SIDE VIEW SEATING PLANE L1 123 TOP VIEW DIM A A1 A2 b c D E E1 e L L1 MIN -0 0.0295 0.0059 0.0031 ----0.0157 -- INCHES NOM -----0.1181 BSC 0.1929 BSC 0.1181 BSC 0.0197 BSC 0.0236 0.0374 REF MAX 0.0433 0.0059 0.0374 0.0118 0.0091 ----0.0315 -- MIN -0 0.75 0.15 0.08 ----0.40 -- MILLIMETERS NOM -----3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.60 0.95 REF NOTE MAX 1.10 0.15 0.95 0.30 0.23 ----0.80 -- 4, 5 2 3 Notes: 1. Reference document: JEDEC MO-187 2. D does not include mold flash or protrusions which is 0.15 mm max. per side. 3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max. 5. Exceptions to JEDEC dimension. THERMAL CHARACTERISTICS Parameter Junction to Ambient Thermal Impedance JEDEC 2-Layer JEDEC 4-Layer Symbol θJA θJA Min - Typ 170 100 Max - Units °C/W °C/W 30 DS843PP1 CS2300-CP 11.ORDERING INFORMATION Product CS2300-CP CS2300-CP CDK2000 Description Clocking Device Clocking Device Evaluation Platform Package 10L-MSOP 10L-MSOP - Pb-Free Yes Yes Yes Grade Commercial - Temp Range Container -10° to +70°C -10° to +70°C Rail Tape and Reel - Order# CS2300-CP-CZZ CS2300-CP-CZZR CDK-2000-LCO 12.REFERENCES 1. Audio Engineering Society AES-12id-2006: “AES Information Document for digital audio measurements Jitter performance specifications,” May 2007. 2. Philips Semiconductor, “The I²C-Bus Specification: Version 2,” Dec. 1998. http://www.semiconductors.philips.com 13.REVISION HISTORY Release A1 PP1 Initial Release Updated “AC Electrical Characteristics” on page 7 Changes Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. 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IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. DS843PP1 31 CS2300-CP 32 DS843PP1