CS230002-CZZR

CS2300-02 1x, 2x, 4x, and 8x Clock Multiplier with Internal LCO Features Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery 750 kHz to 30 MHz Clock Source Internal LCO Reference Clock 128 Hz Loop Filter Bandwidth Selectable Multiplication Factors – 1x, 2x, 4x, and 8x Output Enable Pin Lock Indicator Minimal Board Space Required – No External Analog Loop-filter Components Ordering Information The CS2300-02 is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) grade. Customer development kits are also available for custom device prototyping and device evaluation. Please see “Ordering Information” on page 2 for complete details. Pin-Out Diagram VD GND CLK_OUT LOCK CLK_IN 1 2 3 4 5 10 9 8 7 6 M0 M1 OUT_EN FILTN FILTP General Description The CS2300-02 is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2300-02 is based on a hybrid analog-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchronization clock with frequencies as low as 750 kHz. The CS2300-02 is a CS2300-OTP device that has been preconfigured at the factory. There are three hardware configuration pins available for mode and feature selection. Hardware Controls Settings M1 0 0 1 1 M0 0 1 0 1 PLL_OUT 1x CLK_IN 2x CLK_IN 4x CLK_IN 8x CLK_IN OUT_EN 0 1 CLK_OUT Enabled High Impedance FILTP 0.1 µF LOCK FILTN LCO PLL Lock Indicator 6 MHz to 75 MHz PLL Output Output Enable/Disable Fractional-N Frequency Synthesizer M[1:0] 00=1x 01=2x 10=4x 11=8x Output to Input Clock Ratio CLK_OUT Ratio Selection M1 M0 N OUT_EN 750 kHz to 30 MHz Frequency Reference CLK_IN 128 Hz BW Digital PLL & Fractional N Logic VD 0.1 µF 1 µF 3.3 V GND Advance Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) February '08 PS855A1 CS2300-02 1. PIN DESCRIPTIONS Pin Name VD GND CLK_OUT LOCK CLK_IN FILTP FILTN OUT_EN M1 M0 2. SPECIFICATIONS Please see the CS2300-OTP datasheet for package information, device characteristics, and specifications except where noted due to specific programming options. # 1 2 3 4 5 6 7 8 9 10 Pin Description Digital Power Ground PLL Clock Output Active Low PLL Lock Indicator Clock Input LCO Filter Connections Active Low CLK_OUT Enable Input Mode Selection Inputs 3. OPERATIONAL INFORMATION Complete operational information can be found in the CS2300-OTP datasheet. Specific operational details dictated by the programming of the CS2300-02 are included below. • The PLL clock output is forced to 0 when the PLL is unlocked, both upon loss of the CLK_IN signal or briefly when switching mode pin configurations. The minimum loop filter bandwidth once locked is 128 Hz. See the CS2300-OTP datasheet for additional pin description information. • 4. CONFIGURATION INFORMATION The CS2300-02 has been factory pre-programmed with a unique configuration. The following table outlines the specific configuration profile which can be compared to the CS2300-OTP datasheet for detailed functional descriptions. OTP Modal and Global Configuration Parameters Form Mode 0 Mode 1 Ratio 0 (dec) 1 2 Ratio 0 (hex) 00:10:00:00 00:20:00:00 RModSel1 0 0 RModSel0 0 0 AuxOutSrc1 1 1 AuxOutSrc0 1 1 AutoRMod 0 0 Global Configuration Set ClkSkipEn AuxLockCfg ClkOutUnl LFRatioCfg M2Cfg2 0 0 0 1 0 ClkIn_BW2 ClkIn_BW1 ClkIn_BW0 1 1 1 Mode 2 4 00:40:00:00 0 0 1 1 0 M2Cfg1 0 M2Cfg0 0 Mode 3 8 00:80:00:00 0 0 1 1 0 5. ORDERING INFORMATION Product CS2300-02 CDK-2000 Description Clocking Device Evaluation Platform Package 10L-MSOP - Pb-Free Yes Yes Grade Commercial - Temp Range Container Rail -10° to +70°C - Order# CS230002-CZZ Tape and CS230002-CZZR Reel CDK-2000-LCO PS855A1 2 CS2300-02 6. REVISION HISTORY Release A1 Initial Release Changes Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. 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IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. PS855A1 3