CS3001
CS3002
Precision Low-voltage Amplifier; DC to 2 kHz
Features & Description
Description
Offset: 10 μV Max
Low Drift: 0.05 μV/°C Max
Low Noise
The CS3001 single amplifier and the CS3002 dual amplifier are designed for precision amplification of lowlevel signals and are ideally suited to applications that
require very high closed-loop gains. These amplifiers
achieve excellent offset stability, super-high open-loop
gain, and low noise over time and temperature. The devices also exhibit excellent CMRR and PSRR. The
common mode input range includes the negative supply
rail. The amplifiers operate with any total supply voltage
from 2.7 V to 6.7 V (±1.35 V to ±3.35 V).
Low
– 6 nV/√Hz @ 0.5 Hz
– 0.1 to 10 Hz = 125 nVp-p
– 1/f corner @ 0.08 Hz
Open-loop
Voltage Gain
– 300 dB Typical
– 200 dB Minimum
Pin Configurations
Rail-to-rail
Output Swing
Slew Rate: 5 V/μs
CS3001
Applications
Thermocouple/Thermopile
Amplifiers
Load Cell and Bridge Transducer Amplifiers
Precision Instrumentation
Battery-powered Systems
PWDN
1
-In
2
+In
3
V-
4
CS3002
8
NC
Out A 1
-
7
V+
-In A 2
+
6
Output
+In A 3
5
NC
8-lead SOIC
8 V+
A
- +
7 Out B
B
+ -
6 -In B
V- 4
5 +In B
8-lead SOIC
CS3001
Noise vs. Frequency (Measured)
Dexter Research
Thermopile 1M
100
nV/√Hz
R2
64.9k
10
1
0.001
R1
100
0.01
0.1
1
C1
0.015μF
10
Frequency (Hz)
Thermopile Amplifier with a Gain of 650 V/V
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2009
(All Rights Reserved)
JUL ‘09
DS490F9
CS3001
CS3002
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS .............................................. 3
ELECTRICAL CHARACTERISTICS...................................................................3
ABSOLUTE MAXIMUM RATINGS .....................................................................4
2. TYPICAL PERFORMANCE PLOTS .............................................................. 4
3. CS3001/CS3002 OVERVIEW ......................................................................... 8
3.1 Open-loop Gain and Phase Response .................................................................8
3.2 Open-loop Gain and Stability Compensation .......................................................9
3.2.1 Discussion ...................................................................................................9
3.2.2 Gain Calculations Summary and Recommendations ...............................12
3.3 Powerdown (PDWN) ..........................................................................................12
3.4 Applications ........................................................................................................12
4.
5.
6.
7.
PACKAGE DRAWING .................................................................................. 14
ORDERING INFORMATION ........................................................................ 15
ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .. 15
REVISION HISTORY ................................................................................... 16
LIST OF FIGURES
Figure 1. Noise vs. Frequency (Measured) ........................................................................4
Figure 2. 0.01 Hz to 10 Hz Noise .......................................................................................4
Figure 3. Supply Current vs. Temperature, 3001 ...............................................................4
Figure 4. Noise vs. Frequency ...........................................................................................4
Figure 5. Offset Voltage Stability (DC to 3.2 Hz) ...............................................................4
Figure 6. Supply Current vs. Temperature, 3002 ...............................................................4
Figure 7. Supply Current vs. Voltage, 3001 .......................................................................5
Figure 8. Supply Current vs. Voltage, 3002 .......................................................................5
Figure 9. Open-loop Gain and Phase vs. Frequency .........................................................5
Figure 10. Open-loop Gain and Phase vs. Frequency (Expanded) ...................................6
Figure 11. Input Bias Current vs. Supply Voltage (CS3002) ..............................................6
Figure 12. Input Bias Current vs. Common Mode Voltage ................................................7
Figure 13. Voltage Swing vs. Output Current (2.7 V) .........................................................7
Figure 14. Voltage Swing vs. Output Current (5 V) ............................................................7
Figure 15. CS3001/CS3002 Open-loop Gain and Phase Response .................................8
Figure 16. Non-inverting Gain Configuration .....................................................................9
Figure 17. Non-inverting Gain Configuration with Compensation ....................................10
Figure 18. Loop Gain Plot: Unity Gain and with Pole-zero Compensation ......................11
Figure 19. Thermopile Amplifier with a Gain of 650 V/V ..................................................13
Figure 20. Load Cell Bridge Amplifier and A/D Converter ...............................................13
2
DS490F9
CS3001
CS3002
1. CHARACTERISTICS AND SPECIFICATIONS
ELECTRICAL CHARACTERISTICS V+ = +5 V, V- = 0V, VCM = 2.5 V (Note 1)
CS3001/CS3002
Parameter
Min
Typ
Max
Unit
Input Offset Voltage
(Note 2)
•
-
-
±10
µV
Average Input Offset Drift
(Note 2)
•
-
±0.01
±0.05
µV/ºC
Long Term Input Offset Voltage Stability
Input Bias Current
(Note 3)
TA = 25º C
•
-
±100
-
±1000
pA
pA
•
-
±200
-
±2000
pA
pA
Input Noise Voltage Density RS = 100 Ω, f0 = 1 Hz
RS = 100 Ω, f0 = 1 kHz
-
6
6
nV/ Hz
nV/ Hz
Input Noise Voltage
-
125
nVp-p
Input Noise Current Density f0 = 1 Hz
-
100
fA/ Hz
Input Noise Current
-
1.9
pAp-p
-0.1
-
(V+)-1.25
V
•
115
120
-
dB
•
120
136
-
dB
•
200
300
-
dB
•
+4.7
+4.99
-
V
V
5
-
V/µs
Input Offset Current
TA = 25º C
0.1 to 10 Hz
0.1 to 10 Hz
Input Common Mode Voltage Range
Common Mode Rejection Ratio (dc)
•
(Note 4)
Power Supply Rejection Ratio
Large Signal Voltage Gain RL = 2 kΩ to V+/2
Output Voltage Swing
RL = 2 kΩ to V+/2
RL = 100 kΩ to V+/2
(Note 5)
RL = 2 k, 100 pF
Slew Rate
Overload Recovery Time
-
100
-
µs
CS3001
CS3002
(Note 6)
•
•
•
-
2.1
3.6
2.8
4.8
15
mA
mA
µA
PWDN Threshold
(Note 6)
•
(V+) -1.0
-
-
V
Start-up Time
(Note 7)
•
-
9
12
ms
Supply Current
PWDN active (CS3001 Only)
Notes: 1. Symbol “•” denotes specification applies over -40 to +85 ° C.
2. This parameter is guaranteed by design and laboratory characterization. Thermocouple effects prohibit
accurate measurement of these parameters in automatic test systems.
3. 1000-hour life test data @ 125 °C indicates randomly distributed variation approximately equal to
measurement repeatability of 1 µV.
4. Measured within the specified common mode range limits.
5. Guaranteed within the output limits of (V+ -0.3 V) to (V- +0.3 V). Tested with proprietary production test
method.
6. PWDN input has an internal pullup resistor to V+ of approximately 800 kΩ and is the major source of
current consumption when PWDN is active low.
7. The device has a controlled start-up behavior due to its complex open loop gain characteristics. Startup time applies when supply voltage is applied or when PDWN is released.
DS490F9
3
CS3001
CS3002
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Min
Typ
[(V+) - (V-)]
Input Voltage
Storage Temperature Range
Max
Unit
6.8
V
V- -0.3
V+ +0.3
V
-65
+150
ºC
2. TYPICAL PERFORMANCE PLOTS
1000
Noise vs. Frequency (Measured)
nV/√Hz
nV/√Hz
100
100
10
10
1
0.001
0.01
0.1
1
1
10
10
100
1K
Frequency (Hz)
100
75
nV
nV
0
-50
1
2
3
4
5
6
7
8
9
10
-100
TIME (Sec)
Time (1 Hour)
Figure 4. Offset Voltage Stability (DC to 3.2 Hz)
Figure 3. 0.01 Hz to 10 Hz Noise
4.5
Supply Current (mA)
Supply Current (mA)
3
2.5
6.7 V
2
1
-40
5V
2.7 V
4.0
6.7 V
3.5
2.7 V
3.0
2.5
2.0
-20
0
20
40
60
80
Temperature (°C)
Figure 5. Supply Current vs. Temperature, CS3001
4
10M
σ = 13 nV
50
25
0
-25
-50
-75
50
0
1M
Figure 2. Noise vs. Frequency
100
1.5
100K
Frequency (Hz)
Figure 1. Noise vs. Frequency (Measured)
-100
10K
-40
-20
0
20
40
60
80
Temperature (°C)
Figure 6. Supply Current vs. Temperature, CS3002
DS490F9
CS3001
CS3002
Typical Performance Plots (Cont.)
3.8
Supply Current (mA)
Supply Current (mA)
2
1.9
1.8
1.7
1.6
1.5
2
3
4
5
6
7
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2
3
4
5
6
7
Supply Voltage (V)
Supply Voltage (V)
Figure 8. Supply Current vs. Voltage, CS3002
Figure 7. Supply Current vs. Voltage, CS3001
500
400
300
200
100
0
-100
-200
-300
-400
-500
GAIN
PHASE
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 9. Open-loop Gain and Phase vs. Frequency
DS490F9
5
CS3001
CS3002
Typical Performance Plots (Cont.)
100
Gain (dB)
80
60
40
20
0
Phase (Degrees)
-45
-90
-135
-180
-225
-270
-315
-360
10K
100K
10M
1M
Figure 10. Open-loop Gain and Phase vs. Frequency (Expanded)
Input Bias Current (pA)
-150
A1A1+
B1A2+
B1+
A2-
-100
-50
0
-50
-100
-150
-200
B2B2+
CM = 0 V
±1.35
±2
±2.5
±3.35
Supply Voltage (±V)
Figure 11. Input Bias Current vs. Supply Voltage
6
DS490F9
CS3001
CS3002
Bias Current
Normalized to CM = 2.5 V
Typical Performance Plots (Cont.)
3
2
1
0
-1
-2
-3
0
1
2
3
4
5
Common Mode Voltage (Vs = 5V)
Figure 12. Input Bias Current vs. Common Mode Voltage
V+
V+
-50
-50
-100
-150
+125°C
-200
+25°C
-250
+250
+125°C
+200
+25°C
+125°C
-200
+25°C
-250
+250
+125°C
+200
+25°C
+150
+150
-40°C
+100
-40°C
+100
+50
+50
V–
-40°C
-150
Output Voltage (mV)
Output Voltage (mV)
-100
-40°C
V–
0
1
2
3
Output Current (mA)
4
Figure 13. Voltage Swing vs. Output Current (2.7 V)
DS490F9
5
0
1
2
3
Output Current (mA)
4
5
Figure 14. Voltage Swing vs. Output Current (5 V)
7
CS3001
CS3002
3. CS3001/CS3002 OVERVIEW
The CS3001/CS3002 amplifiers are designed for
precision measurement of signals from DC to
2 kHz when operating from a supply voltage of
+2.7 V to +6.7 V (± 1.35 to ± 3.35 V). The amplifiers are designed with a patented architecture that
utilizes multiple amplifier stages to yield very high
open loop gain at frequencies of 10 kHz and below.
The amplifiers yield low noise and low offset drift
while consuming relatively low supply current. An
increase in noise floor above 2 kHz is the result of
intermediate stages of the amplifier being operated
at very low currents. The amplifiers are intended
for amplifying small signals with large gains in applications where the output of the amplifier can be
band-limited to frequencies below 2 kHz.
3.1
Open-loop Gain and Phase
Response
Figure 15 illustrates the open loop gain and phase
response of the CS3001/CS3002. The gain slope of
the amplifier is about –100 dB/decade between
500 Hz and 60 kHz and transitions to –20 dB/decade between 60 kHz and its unity gain crossover
frequency at about 4.8 MHz. Phase margin at unity
gain is about 70 degrees; gain margin is about
20 dB.
100
Gain (dB)
80
-100 dB/ dec
60
40
-20 dB/ dec
20
0
Phase (Degrees)
-45
-90
-135
-180
-225
-270
-315
-360
10K
100K
1M
10M
Figure 15. CS3001/CS3002 Open-loop Gain and Phase Response
8
DS490F9
CS3001
CS3002
3.2
Open-loop Gain and Stability Compensation
3.2.1
Discussion
The CS3001 and CS3002 achieve ultra-high open
loop gain. Figure 16 illustrates the amplifier in a
non-inverting gain configuration. The open loop
gain and phase plots indicate that the amplifier is
stable for closed-loop gains less than 50 V/V and
R1 ≤ 100 Ohms. For a gain of 50, the phase margin
is between 40° and 60° depending upon the loading
conditions. As shown in Figure 17, on page 10, the
operational amplifier has an input capacitance at
the + and – signal inputs of typically 50 pF. This
capacitance adds an additional pole in the loop gain
transfer function at a frequency of f = 1/(2πR*Cin)
where R is the parallel combination of R1 and R2
(R1 || R2). A higher value for R produces a pole at
a lower frequency, thus reducing the phase margin.
R1 is recommended to be less than or equal to 100
ohms, which results in a pole at 30 MHz or higher.
If a higher value of R1 is desired, a compensation
capacitor (C2) should be added in parallel with R2.
C2 should be chosen such that R2*C2 ≥ R1*Cin.
RS
V in
Vo
R2
R1
Figure 16. Non-inverting Gain Configuration
DS490F9
9
CS3001
CS3002
Vin
C in
50 pF
Vo
50 pF
C in
R2
Choose C2 so that R2 • C2 ≥ R1 • C in
R1
?
C2
Figure 17. Non-inverting Gain Configuration with Compensation
The feedback capacitor C2 is required for closedloop gains greater than 50 V/V. The capacitor in-
troduces a pole and a zero in the loop gain transfer
function,
s-
– 1 + ---
z 1
T = ----------------------- A ol
s
1 + ---
p 1
1
1
P 1 = ------------------------------------- ≅ ------------------------2π ( R 1 || R 2 )C 2 2π ( R 1 C 2 )
for
1
Z 1 = ----------------------------------2π ( A × R 1 )C 2
R
A = -----2R1
where
R2 » R1
1
Z 1 = -----------------------2π ( R 2 )C 2
This indicates that the separation of the pole and
the zero is governed by the closed loop gain. It is
required that the zero falls on the steep slope
(–100 dB/decade) of the loop gain plot so that there
10
is some gain higher than 0 dB (typically 20 dB) at
the hand-over frequency (the frequency at which
the slope changes from – 100 dB/decade to
–20 dB/decade).
DS490F9
CS3001
CS3002
The loop gain plot shown in Figure 18 illustrates
the unity gain configuration, and indicates how this
is modified when using the amplifier in a higher
gain configuration with compensation. If it is configured for higher gain, for example, 60 dB, the
x–axis will move up by 60 dB (line B). Capacitor
C2 adds a zero and a pole. The modified plot indicates the effects of introducing the pole and zero
due to capacitor C2. The pole can be located at any
frequency higher than the hand-over frequency, the
zero has to be at a frequency lower than the handover frequency so as to provide adequate gain mar-
gin. The separation between the pole and the zero
is governed by the closed loop gain. The zero (z1)
occurs at the intersection of the –100 dB/decade
and –80 dB/decade slopes. The point X in the figure should be at closed loop gain plus 20 dB gain
margin. The value for C2 = 1/(2π R1 P1). Setting
the pole of the filter to P1 = 1 MHz works very well
and is independent of gain. As the closed loop gain
is changed, the zero location is also modified if R1
remains fixed. Capacitor C2 can be increased in
value to limit the amplifier’s rising noise above
2 kHz.
|T| (Log gain)
-100 dB/dec
z1
p1
-80 dB/dec
X
Margin
B
Desired Closed
Loop Gain
-20 dB/dec
50kHz
1MHz
5MHz
FREQUENCY
Figure 18. Loop Gain Plot: Unity Gain and with Pole-zero Compensation
DS490F9
11
CS3001
CS3002
3.2.2
Gain Calculations Summary and
Recommendations
Condition #1: |Av| ≤ 50 and R1 ≤ 100 Ω
The Opamp is inherently stable for |Av| ≤ 50 and
R1 ≤ 100 Ω . No C2 compensation capacitor across
R2 is required.
•
•
Verify the Opamp Compensation:
Verify the opamp compensation using the openloop gain and phase response Bode plot in
Figure 15. Plot the calculated closed loop gain
transfer function and verify the following design
criteria are met:
•
|Av| = 1 configuration has 70° phase margin
and 20 dB gain margin.
|Av| = 50 configuration has phase margin between 40° for CLOAD ≤ 100 pF and 60° for
CLOAD = 0 pF.
•
Pole P1 > opamp internal 50 kHz crossover frequency
-
P1 = 1 / [2π (R1| |R2) • C2], where P1 = 1 MHz
-
To simplify the calculation, set the pole to
P1 = 1 MHz.
Z1 < opamp internal 50 kHz crossover frequency
-
Condition #2: |Av| ≤ 50 and R1 > 100 Ω
Compensation capacitor C2 across R2 is required.
Calculate C2 using the following formula:
•
C2 ≥ (R1 • Cin) / R2, where Cin = 50 pF
•
Z1 = 1 / (2π R2 • C2)
Gain margin above the open-loop gain transfer
function is required. A gain margin of +20 dB
above the open loop gain transfer function is
optimal.
Condition #3: |Av| > 50
Compensation capacitor C2 across R2 is required.
Calculate and verify a value for C2 using the following steps.
Calculate the Compensation Capacitor Value:
1) Calculate a value for C2 using the following
formula:
C2 = 1 / [2π (R1| |R2) • P1], where P1 = 1 MHz
To simplify the calculation, set the pole of the filter
to P1 = 1 MHz. P1 must be set higher than the
opamp’s internal 50 kHz crossover frequency.
2) Calculate a second value for C2 using the following formula:
C2 ≥ (R1 • Cin) / R2, where Cin = 50 pF
3) Use the larger of the two values calculated in
steps 1 & 2.
12
3.3
Powerdown (PDWN)
The CS3001 single amplifier provides a powerdown function on pin 1. If this pin is left open the
amplifier will operate normally. If the powerdown
is asserted low, the amplifier will go into a low
power state. There is a pull-up resistor (approximately 800 kΩ) inside the amplifier from pin 1 to
the V+ supply. The current through this pull-up resistor is the main source of current drain in the
powerdown state.
DS490F9
CS3001
CS3002
3.4
Applications
The CS3001 and CS3002 amplifiers are optimum
for applications that require high gain and low drift.
Figure 19 illustrates a thermopile amplifier with a
gain of 650 V/V. The thermopile outputs only a few
millivolts when subjected to infrared radiation. The
amplifier is compensated and bandlimited by C1 in
combination with R2.
Figure 20, on page 13 illustrates a load cell bridge
amplifier with a gain of 768 V/V. The load cell is
excited with +5 V and has a 1 mV/V sensitivity. Its
full scale output signal is amplified to produce a
fully differential ± 3.8 V into the CS5510/12 A/D
converter. This circuit operates from +5 V.
CS3001
D e x te r R e s e a r c h
T h e r m o p ile 1 M
R2
6 4 .9 k
C1
0 .0 1 5 μ F
R1
100
Figure 19. Thermopile Amplifier with a Gain of 650 V/V
T h e rm o p ile A m p lifie r w ith a G a in o f 6 5 0 V /V
+5 V
+5 V
VA
+5 V
0 .1 μ F
V+
+
x768
CS
VREF
100 Ω
A IN +
1 m V /V
-
350 Ω
1 4 0 kΩ
0 .2 2 μ F
μ
SDO
SCLK
C S 5 5 1 0 /1 2
+
365 Ω
-
1 4 0 kΩ
0 .0 4 7 μ F
C o u n te r /T im e r
0 .2 2 μ F
A IN 1
+
V-
100 Ω
S C L K = 1 0 k H z to 1 0 0
( 3 2 .7 6 8
S C L K = 1 0 k H) z t o 1 0 0 k H z
(3 2 .7 6 8 n o m in a l)
Figure 20. Load Cell Bridge Amplifier and A/D Converter
DS490F9
13
CS3001
CS3002
4. PACKAGE DRAWING
8L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1
b
c
D
SEATING
PLANE
∝
A
L
e
A1
INCHES
DIM
A
A1
B
C
D
E
e
H
L
∝
MIN
0.053
0.004
0.013
0.007
0.189
0.150
0.040
0.228
0.016
0°
MAX
0.069
0.010
0.020
0.010
0.197
0.157
0.060
0.244
0.050
8°
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.02
1.52
5.80
6.20
0.40
1.27
0°
8°
JEDEC #: MS-012
14
DS490F9
CS3001
CS3002
5. ORDERING INFORMATION
Model
CS3001-ISZ (lead free)
CS3002-ISZ (lead free)
Temperature
Package
-40 to +85 °C
8-pin SOIC (Lead Free)
6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
CS3001-ISZ (lead free)
CS3002-ISZ (lead free)
Peak Reflow Temp
MSL Rating*
Max Floor Life
260 °C
2
365 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
DS490F9
15
CS3001
CS3002
7. REVISION HISTORY
Revision
Date
F3
OCT 2004
Added lead-free device ordering information.
Changes
F4
AUG 2005
Added MSL specifications. Updated legal notice. Added leaded (Pb) devices.
F5
AUG 2006
Updated Typical Performance Plots.
F6
SEP 2006
Corrected error in Ordering Information section.
F7
NOV 2007
Added additional information regarding open-loop and gain stability compensation.
F8
OCT 2008
Minor, cosmetic correction to caption for Figure 10.
F9
JUL 2009
Removed lead-containing devices from ordering information.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER
OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE,
TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
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