CS3012-ISZR

CS3011 CS3012 Precision Low-voltage Amplifier; DC to 1 kHz Features & Description Description Offset: 10 μV Max  Low Drift: 0.05 μV/°C Max  Low Noise The CS3011 single amplifier and the CS3012 dual amplifier are designed for precision amplification of lowlevel signals and are ideally suited to applications that require very high closed-loop gains. These amplifiers achieve excellent offset stability, super-high open-loop gain, and low noise over time and temperature. The devices also exhibit excellent CMRR and PSRR. The common mode input range includes the negative supply rail. The amplifiers operate with any total supply voltage from 2.7 V to 6.7 V (±1.35 V to ±3.35 V).  Low – 12 nV/√Hz @ 0.5 Hz – 0.1 to 10 Hz = 250 nVp-p – 1/f corner @ 0.08 Hz  Open-loop Voltage Gain – 300 dB Typ – 200 dB Min Pin Configurations  Rail-to-rail Output Swing  Slew Rate: 2 V/μs CS3011 Applications PDWN 1  Thermocouple/Thermopile Amplifiers  Load Cell and Bridge Transducer Amplifiers  Precision Instrumentation  Battery-powered Systems 2 - +In 3 + V- 4 -In 8-lead SOIC CS3012 8 NC Out A 1 7 V+ -In A 2 6 Output 5 NC 8 V+ A - + 7 Out B B +In A 3 + - V- 4 6 -In B 5 +In B 8-lead SOIC Noise vs. Frequency (Measured) CS3011 nV/√Hz 100 Dexter Research Thermopile ST60 10 1 0.001 R2 64.9k 0.010 0.1 1 10 R1 100 Frequency (Hz) http://www.cirrus.com Copyright  Cirrus Logic, Inc. 2009 (All Rights Reserved) C1 0.015μF JUL ‘09 DS597F6 CS3011 CS3012 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS .................................................... 3 2. TYPICAL PERFORMANCE PLOTS ..................................................................... 4 3. CS3011/CS3012 OVERVIEW ............................................................................... 8 4. 5. 6. 7. 3.1 Open Loop Gain and Phase Response ......................................................................9 3.2 Open Loop Gain and Stability Compensation ...........................................................10 3.2.1 Discussion ................................................................................................10 3.2.2 Gain Calculations Summary and Recommendations .. .............................13 3.3 Powerdown (PDWN) .................................................................................................13 3.4 Applications ..............................................................................................................14 ORDERING INFORMATION .............................................................................. 15 ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ........ 15 PACKAGE DRAWING ........................................................................................ 16 REVISION HISTORY ......................................................................................... 17 LIST OF FIGURES Figure 1. Noise vs. Frequency (Measured) ................................................................ 4 Figure 2. 0.01 Hz to 10 Hz Noise ............................................................................... 4 Figure 3. Supply Current vs. Temperature, 3011 ....................................................... 4 Figure 4. Noise vs. Frequency ................................................................................... 4 Figure 5. Offset Voltage Stability (DC to 3.2 Hz) ........................................................ 4 Figure 6. Supply Current vs. Temperature, 3012 ....................................................... 4 Figure 7. Supply Current vs. Voltage, 3011 ............................................................... 5 Figure 8. Supply Current vs. Voltage, 3012 ............................................................... 5 Figure 9. Open Loop Gain and Phase vs Frequency ................................................. 5 Figure 10. Open Loop Gain and Phase vs Frequency (Expanded) ........................... 6 Figure 11. Input Bias Current vs Common Mode Voltage (CS3012) ......................... 6 Figure 12. Voltage Swing vs. Output Current (2.7 V) ................................................. 7 Figure 13. Voltage Swing vs. Output Current (5 V) .................................................... 7 Figure 14. CS3011/CS3012 Open Loop Gain and Phase Response ........................ 9 Figure 15. Non-Inverting Gain Configuration ........................................................... 10 Figure 16. Non-Inverting Gain Configuration with Compensation ............................ 11 Figure 17. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation .............. 12 Figure 18. Thermopile Amplifier with a Gain of 650 V/V .......................................... 14 Figure 19. Load Cell Bridge Amplifier and A/D Converter ........................................ 14 Figure 20. 2 DS597F6 CS3011 CS3012 1. CHARACTERISTICS AND SPECIFICATIONS ELECTRICAL CHARACTERISTICS V+ = +5 V, V- = 0V, VCM = 2.5 V (Note 1) CS3011/CS3012 Parameter Min Typ Max Unit Input Offset Voltage (Note 2) • - - ±10 µV Average Input Offset Drift (Note 2) • - ±0.01 ±0.05 µV/ºC • - ±50 - ±1000 pA • - ±100 - ±2000 pA - 12 12 nV/ Hz nVp-p Long Term Input Offset Voltage Stability (Note 3) Input Bias Current TA = 25º C Input Offset Current TA = 25º C Input Noise Voltage Density RS = 100 Ω, f0 = 1 Hz RS = 100 Ω, f0 = 1 kHz Input Noise Voltage 0.1 to 10 Hz nV/ Hz - 250 Input Noise Current Density f0 = 1 Hz - 100 fA/ Hz Input Noise Current - 1.9 • -0.1 - (V+)-1.25 pAp-p • 115 120 - dB • 120 136 - dB • 200 300 - dB • +4.7 +4.99 - V V 2 - V/µs - 600 - µs 0.9 1.7 1.4 2.4 15 mA mA µA 9 12 ms 0.1 to 10 Hz Input Common Mode Voltage Range Common Mode Rejection Ratio (dc) (Note 4) Power Supply Rejection Ratio Large Signal Voltage Gain RL = 2 kΩ to V+/2 Output Voltage Swing RL = 2 kΩ to V+/2 RL = 100 kΩ to V+/2 (Note 5) RL = 2 k, 100 pF Slew Rate Overload Recovery Time CS3011 CS3012 (Note 6) • • • - PWDN Threshold (Note 6) • (V+) -1.0 Start-up Time (Note 7) • - Supply Current PWDN active (CS3011 Only) V Notes: 1. Symbol “•” denotes specification applies over -40 to +85 ° C. 2. This parameter is guaranteed by design and laboratory characterization. Thermocouple effects prohibit accurate measurement of these parameters in automatic test systems. 3. 1000-hour life test data @ 125 °C indicates randomly distributed variation approximately equal to measurement repeatability of 1 µV. 4. Measured within the specified common mode range limits. 5. Guaranteed within the output limits of (V+ -0.3 V) to (V- +0.3 V). Tested with proprietary production test method. 6. PWDN input has an internal pullup resistor to V+ of approximately 800 kΩ and is the major source of current consumption when PWDN is active (low). 7. The device has a controlled start-up behavior due to its complex open loop gain characteristics. Startup time applies to when supply voltage is applied or when PDWN is released. DS597F6 3 CS3011 CS3012 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Min T yp [(V+) - (V-)] Input Voltage V- -0.3 Storage Temperature Range -65 Max Unit 6.8 V V+ +0.3 V +150 ºC 2. TYPICAL PERFORMANCE PLOTS 1k 1000 100 100 10 nV/ Hz nV/√Hz 100 10 10 1 0.001 0.010 0.1 1 10 11 1k 1000 10k 100k 1M 10M 10000 100000 100000 1E+07 Frequency 0 Freq u en c y σ = 13 nV 75 50 25 nV nV 0 -25 -50 -75 0 1 2 3 4 6 5 TIME (Sec) TIME (Sec) 8 7 9 -100 10 TIME(1HR) Figure 4. Offset Voltage Stability (DC to 3.2 Hz) 1.9 2.0 Supply Current (mA) Supply Current (mA) 100 100 Figure 3. 0.01 Hz to 10 Hz Noise 6.7 V 1.5 5V 1.0 2.7 V 0.5 0.0 -40 -20 0 20 40 60 80 Temperature (°C) Figure 5. Supply Current vs. Temperature, CS3011 4 100 Figure 2. Noise vs. Frequency Figure 1. Noise vs. Frequency (Measured) 200 150 100 50 0 -50 -100 -150 -200 10 10 Frequency (Hz) 1.7 6.7 V 1.5 1.3 2.7 V 1.1 0.9 0.7 0.5 -40 -20 0 20 40 60 80 Temperature (°C) Figure 6. Supply Current vs. Temperature, CS3012 DS597F6 CS3011 CS3012 Typical Performance Plots (Cont.) 1.5 Supply Current (mA) Supply Current (mA) 1 0.9 0.8 0.7 0.6 1.4 1.3 1.2 1.1 1 0.5 2 3 4 5 6 2 7 3 4 Gain (dB) Phase (Degrees) Figure 7. Supply Current vs. Voltage, CS3011 500 400 300 200 100 0 -100 -200 -300 -400 -500 5 6 7 Supply Voltage (V) Supply Voltage (V) Figure 8. Supply Current vs. Voltage, CS3012 GAIN PHASE 11 10 10 100 100 1k 1000 10k 100k 100000 1M 10M 10000 100000 1E+07 0 Frequency(Hz) (Hz) 100 K Frequency Figure 9. Open Loop Gain and Phase vs Frequency DS597F6 5 CS3011 CS3012 Typical Performance Plots (Cont.) 80 Gain (dB) 60 40 20 00 -45 Phase (degrees) -90 -135 -180 -225 -270 -315 -360 10000 10 K 100000 100 K Frequency 1000000 1M 10000000 10 M Figure 10. Open Loop Gain and Phase vs Frequency (Expand- CS3012 IB vs Common Bias Current (pA) 200 150 A- 100 50 B- 0 B+ -50 A+ -100 -150 -200 0 1 2 3 4 5 Common Mode Voltage (Vs = 5V) Figure 11. Input Bias Current vs Common Mode Voltage (CS3012) 6 DS597F6 CS3011 CS3012 Typical Performance Plots (Cont.) V+ V+ -50 -50 -100 -150 +25°C -200 -250 +250 +125°C +200 +25°C +150 +25°C -200 -250 +250 +125°C +200 +25°C +150 -40°C +100 -40°C +100 +50 V– -40°C +125°C -150 Output Voltage (mV) Output Voltage (mV) -100 -40°C +125°C +50 0 1 2 3 Output Current (mA) 4 Figure 12. Voltage Swing vs. Output Current (2.7 V) DS597F6 5 V– 0 1 2 3 Output Current (mA) 4 5 Figure 13. Voltage Swing vs. Output Current (5 V) 7 CS3011 CS3012 3. CS3011/CS3012 OVERVIEW The CS301 1/CS3012 amplifiers are de signed for precision measu rement o f sign als from DC to 1 kHz when opera ting from a supply voltage of +2.7 V to +6.7 V (± 1.35 to ± 3.35 V). The amplifiers are designed with a patented architecture that utilizes multiple amplifier stages to yield very high open loop gain at frequencies of 1 kHz and below. The amplifiers yield low noise and low offset dr ift 8 while consuming relatively low supply current . An increase in noise floor above 1 kHz is the result of intermediate stages of the amplifier being operated at very low currents. The amplifiers are intende d for amplifying small signals with large gains in applications where the output of the amplifier can be band-limited to frequencies below 1 kHz. DS597F6 CS3011 CS3012 3.1 Open Loop Gain and Phase Response Figure 14 illustrates the open loop gain and phase response of t he CS3011/CS3012. The gain slope of the amplifier is about –100 dB/decade between 500 Hz and 30 kHz and transitions to –2 0 dB/de- cade between 30 kHz and its unity gain crossover frequency at about 2.4 MHz. Phase margin at unity gain is abou t 70 degrees; gain marg in is abo ut 20 dB. 80 Gain (dB) 60 40 20 00 -45 Phase (degrees) -90 -135 -180 -225 -270 -315 -360 10000 10 K 100000 100 K 1000000 1M 10000000 10 M Figure 14. CS3011/CS3012 Open Loop Gain and Phase Response DS597F6 9 CS3011 CS3012 3.2 3.2.1 Open Loop Gain and Stability Compensation Discussion The CS3011 and CS3012 achieve ultra-high open loop gain. Figure 15 il lustrates the ampl ifier in a non-inverting gain configuration. Th e ope n lo op gain and phase plo ts indicate that the amplifier is stable for closed-loop gains less than 50 V/V. For a gain of 50, the phase margin is between 40° and 60° de pending upon the load ing conditions. As shown in Figure 16 on page 11, the op amp has an input ca pacitance at the + and – signal input s of typically 50 pF. This capacitance adds an addition- al pole in the loop gain transfer function at a frequency of f = 1/(2πR*Cin) where R is t he para llel combination of R1 and R2 (R1 || R2). A higher value for R produces a pole at a lower frequency, thus reducing the phase margin. R1 is recommended to be less than or equal to 100 ohms, which results in a pole at 30 MHz or higher. If a higher value of R1 is desired, a compensation capacitor (C2) should be added in parallel with R2. C2 should be chosen such that R2*C2 ≥ R1*Cin. RS V in Vo R2 R1 Figure 15. Non-Inverting Gain Configuration 10 DS597F6 CS3011 CS3012 Vin C in 50 pF Vo 50 pF C in R2 Choose C2 so that R2 • C2 ≥ R 1 • C in R1 ? C2 Figure 16. Non-Inverting Gain Configuration with Compensation The feedback capacitor C2 is required for closedloop gains greater than 50 V/V. The capacitor intro- duces a pole and a zero in th e loop gain transfer function. s –  1 + ----- z1 T = ----------------------- A ol s  1 + --- p  1 1 1 P 1 = ------------------------------------- ≅ ------------------------2π ( R 1 || R 2 )C 2 2π ( R 1 C 2 ) for 1 Z 1 = ----------------------------------2π ( A × R 1 )C 2 R A = -----2R1 where R2 » R1 1 Z 1 = -----------------------2π ( R 2 )C 2 This indicates that the sep aration of the pole and the zero is governed by the clo sed loop gain. It is required that th e ze ro falls o n the steep slo pe (–100 dB/decade) of the loop ga in plot so that DS597F6 there is some gain higher than 0 dB (typically 20 dB) at the ha nd-over frequency (the frequ ency at which the slope changes from – 100 dB/decade to –20 dB/decade). 11 CS3011 CS3012 The loop gain plot shown in Figure 17 i llustrates the unity gain configuration, and indicates how this is mo dified when using the amplifier in a hig her gain configuration with compensation. If it is configured for higher gain, for example, 60 dB, the x–axis will move up by 60 dB (line B). Capacitor C2 adds a zero and a pole. The modified plot indicates the effects of introducing the pole and zero due to capacitor C2 . The pole can be located at any frequency higher than the hand-over frequency, the zero has to be at a frequency lower than the handover freque ncy so as to provide ade quate ga in margin. The separation between the pole and the zero is governed by the closed loop gain. The zero (z1) occurs at the intersection o f the –100 dB/decade and –80 dB/decade slopes. The point X in the figure should be at closed loop gain plus 20 dB gain margin. The value for C2 = 1/(2πR1p1). Using p1 = 500 kHz works very well and is independent of ga in. As the closed loop ga in is change d, the zero location is also modified if R1 remains fixed. Cap acitor C2 ca n be incre ased in value to limit the amplifier’s rising noise above 1 kHz. |T| (Log gain) -100 dB/dec z1 p1 -80 dB/dec X Margin B -20 dB/dec Desired Closed Loop Gain 50kHz 500 kHz 1MHz 25 kHz 2.4 MHz 5MHz FREQUENCY Figure 17. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation 12 DS597F6 CS3011 CS3012 3.2.2 Gain Calculations Summary and Recommendations Condition #1: |Av| ≤ 50 and R1 ≤ 100 Ω The Opamp is inheren tly stable for |Av| ≤ 50 an d R1 ≤ 100 Ω . No C2 co mpensation cap acitor across R2 is required. • |Av| = 1 config uration ha s 7 0° pha se margin and 20 dB gain margin. • |Av| = 50 configuration ha s p hase ma rgin between 40° for C LOAD ≤ 100 pF and 60 ° for CLOAD = 0 pF. Condition #2: |Av| ≤ 50 and R1 > 100 Ω Verify the Opamp Compensation: Verify the opamp co mpensation using the ope nloop gain and pha se resp onse Bode plot in Figure 14. Plot the calculated clo sed loop gain transfer function and verify the following design criteria are met: • • - P1 = 1 / [2π (R1| |R2) • C2], where P1 = 1 MHz - To sim plify the ca lculation, set t he p ole t o P1 = 1 MHz. Z1 < opamp internal 50 kHz crossover frequency - • Compensation capacitor C2 across R2 is required. Calculate C2 using the following formula: • Pole P1 > opamp in ternal 50 kHz c rossover frequency Z1 = 1 / (2π R2 • C2) Gain margin above the open-loop gain transfer function is re quired. A g ain margin of +2 0 dB above t he op en loop g ain transfer fun ction is optimal. C2 ≥ (R1 • Cin) / R2, where Cin = 50 pF Condition #3: |Av| > 50 Compensation capacitor C2 across R2 is required. Calculate and verify a value for C2 using the following steps. Calculate the Compensation Capacitor Value: 1) Calculate a value for C2 using the following formula: C2 = 1 / [2π (R1| |R2) • P1], where P1 = 1 MHz To simplify the calculation, set the pole of the filter to P1 = 1 MHz. P1 must be set h igher than the opamp’s internal 50 kHz crossover frequency. 2) Calculate a second value for C2 using the following formula: C2 ≥ (R1 • Cin) / R2, where Cin = 50 pF 3) Use the la rger of t he two va lues calculated in steps 1 & 2. DS597F6 3.3 Powerdown (PDWN) The CS3011 single amplifier provides a powerdown function on pin 1. If this pin is left ope n the amplifier will operate normally. If the powerdown is asserted low, the amplifier enters a powered down state. Th ere is a pu ll-up resistor (approximately 800 k ohm) inside the amplifier from pin 1 to the V+ supply. The current through this pull-up resistor is the main source of current drain in the powerdown state. 13 CS3011 CS3012 3.4 Applications The CS3011 and CS3012 amplifiers are optimum for applications that require high gain and low drift. Figure 18 illustrates a thermopile amp lifier with a gain of 650 V/V. The thermopile outputs only a few millivolts when subjected to infrared radiation. The amplifier is compensated and bandlimited by C1 in combination with R2. Figure 19 on page 14 illustrates a load cell bridg e amplifier with a gain of 768 V/V. The load cell is excited with +5 V and has a 1 mV/V sensitivity. Its full scale output signal is am plified to produce a f ully differential ± 3.8 V into the CS5510/12 A/D converter. This circuit operates from +5 V. CS3011 Dexter Research Thermopile ST60 R2 64.9k C1 0.015μF R1 100 Figure 18. Thermopile Amplifier with a Gain of 650 V/V +5 V +5 V VA 0 .1 μ F + x768 V+ VREF CS 100 Ω 1 m V /V - 1 4 0 kΩ 0 .2 2 μ F μ SDO A IN + 350 Ω +5 V SCLK C S 5 5 1 0 /1 2 + 365 Ω - 1 4 0 kΩ 0 .0 4 7 μ F C o u n te r /T im e r 0 .2 2 μ F A IN 1 + 100 Ω V- S C L K = 1 0 k H z to 1 0 0 ( 3 2 .7 6 8 S C L K = 1 0 k H) z t o 1 0 0 k H z (3 2 .7 6 8 n o m in a l) Figure 19. Load Cell Bridge Amplifier and A/D Converter 14 DS597F6 CS3011 CS3012 4. ORDERING INFORMATION Model CS3011-ISZ CS3012-ISZ Temperature Package -40 to +85 °C 8-pin SOIC, Lead Free 5. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS3011-ISZ CS3012-ISZ Peak Reflow Temp MSL Rating* Max Floor Life 260 °C 2 365 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS597F6 15 CS3011 CS3012 6. PACKAGE DRAWING 8L SOIC (150 MIL BODY) PACKAGE DRAWING E H 1 b c D SEATING PLANE L e DIM A 0.0 A1 B C D E e H L ∝ ∝ A A1 MIN 53 0.004 0.013 0.007 0.189 0.150 0.040 0.228 0.016 0° INCHES MAX 0.069 0.010 0.020 0.010 0.197 0.157 0.060 0.244 0.050 8° MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.02 1.52 5.80 6.20 0.40 1.27 0° 8° JEDEC # : MS-012 16 DS597F6 CS3011 CS3012 7. REVISION HISTORY Revision Date F2 SEP 2004 Added lead-free device ordering information. F3 AUG 2005 Added MSL specifications. Updated legal notice. Added leaded (Pb) devices. F4 AUG 2006 Updated Typical Performance Plots. Removed Powerdown feature. F5 NOV 2007 Added additional information regarding open-loop and gain stability compensation. F6 JUL 2009 Removed lead-containing SOICs from ordering information. DS597F6 Changes 17 CS3011 CS3012 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. 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All other brand and product names in this document may be trademarks or service marks of their respective owners. 18 DS597F6