CS3301-ISZ

CS3301 Low-noise, Programmable Gain, Differential Amplifier Features & Desription Signal Bandwidth: DC to 2 kHz Selectable Gain: x1, x2, x4, x8, x16, x32, x64 Differential Inputs, Differential Outputs • • • • Multiplexed inputs: INA, INB, 800Ω termination Rough / fine charge outputs for CS5371/72 Max signal amplitude: 5 Vpp differential Low input bias: 500 pA Description The CS3301 is a low-noise differential input, differential output amplifier with programmable gain, optimized for amplifying signals from low-impedance sensors such as geophones. The gain settings are binary weighted (x1, x2, x4, x8, x16, x32, x64) and are selected using simple pin settings. Two sets of external inputs, INA and INB, simplify system design as inputs from a sensor and test DAC. An internal 800 Ω termination can also be selected for noise tests. Amplifier noise performance is outstanding with a noise density of 8.5 nV/ Hz over the 0.1 Hz to 2 kHz bandwidth. Distortion performance is also extremely good, typically -118 dB THD. Flat noise down to 0.1 Hz and low total harmonic distortion make this amplifier ideal for low-frequency, low-amplitude, differential signals requiring maximum dynamic range. Outstanding Noise Performance • 0.20 µVp-p between 0.1 Hz and 10 Hz • 8.5 nV/ Hz from 0.1 Hz to 2 kHz Low Total Harmonic Distortion • -118 dB THD typical (0.000126%) • -112 dB THD maximum (0.000251%) Low Power Consumption • Normal/LPWR/PWDN: 5.5 mA, 3.5 mA, 10 µA Single or Dual Power Supply Configurations • VA+ = +5 V; VA- = 0 V; VD = +3.3 V to +5 V ORDERING INFORMATION • VA+ = +2.5 V;VA- = -2.5 V;VD = +3.3 V See page 15. VA+ INA+ INB+ 400 Ω CLK VD 680 Ω 500 + - OUTR+ OUTF+ 500 680 Ω MUX0 MUX1 400 Ω GAIN0 GAIN1 GAIN2 680 Ω 500 + INAINBVA- OUTFOUTR680 Ω 500 LPWR PWDN DGND http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) DEC ‘07 DS595F3 CS3301 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS .............................................................................. 4 SPECIFIED OPERATING CONDITIONS ....................................................................................... 4 ABSOLUTE MAXIMUM RATINGS ................................................................................................. 4 THERMAL CHARACTERISTICS .................................................................................................. 5 ANALOG CHARACTERISTICS ..................................................................................................... 5 DIGITAL CHARACTERISTICS ...................................................................................................... 8 POWER SUPPLY CHARACTERISTICS ........................................................................................ 9 2. GENERAL DESCRIPTION ........................................................................................................... 10 2.1. Analog Signals ........................................................................................................................ 10 2.2.1. Analog Inputs.............................................................................................................. 10 2.3.2. Analog Outputs ........................................................................................................... 10 2.4.3. Differential Signals...................................................................................................... 11 2.5. Digital Signals ......................................................................................................................... 11 2.6.1. Clock Input.................................................................................................................. 11 2.7.2. Gain Selection ............................................................................................................ 11 2.8.3. Mux Selection ............................................................................................................. 11 2.9.4. Low Power Selection .................................................................................................. 11 2.10.5. Power Down Selection................................................................................................ 11 2.11.Power Supplies ..................................................................................................................... 11 2.12.1. Analog Power Supplies............................................................................................... 11 2.13.2. Digital Power Supplies................................................................................................ 12 2.14.Connection Diagram.............................................................................................................. 13 3. PIN DESCRIPTION ....................................................................................................................... 14 4. ORDERING INFORMATION ........................................................................................................ 15 5. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .................................. 15 6. PACKAGE DIMENSIONS ............................................................................................................. 16 2 DS595F3 CS3301 LIST OF FIGURES Figure 1. CS3301 Noise Performance ............................................................................................ 5 Figure 2. Digital Input Rise and Fall Times ..................................................................................... 8 Figure 3. Multi-Channel System Architecture................................................................................ 10 Figure 4. CS3301 Amplifier Connections ...................................................................................... 13 Figure 5. CS3301 Pin Assignments .............................................................................................. 14 LIST OF TABLES Table 1. Digital Selections for Gain and Input Mux Control ........................................................... 8 Table 2. Pin Descriptions ............................................................................................................. 14 REVISION HISTORY Revision PP2 F1 F2 F3 Date JUL 2003 AUG 2005 SEP 2005 DEC 2007 Final preliminary release. Updated legal notice. Added MSL data. Updated anti-alias resistor values, relative gain accuracy, CS4373A part number. Added watermark to indicate device is not recommended for new designs. Changes Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS595F3 3 CS3301 1. • • • CHARACTERISTICS AND SPECIFICATIONS Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C. DGND = 0 V, all voltages with respect to 0 V. SPECIFIED OPERATING CONDITIONS Parameter Unipolar Power Supplies Positive Analog Negative Analog Positive Digital Bipolar Power Supplies Positive Analog Negative Analog Positive Digital Thermal Ambient Operating Temperature Industrial (-IS) TA -40 85 °C (Note 1) (Note 2) VA+ VAVD 2.375 -2.625 3.135 2.5 -2.5 3.3 2.625 -2.375 3.465 V V V (Note 1) (Note 2) VA+ VAVD 4.75 -0.25 3.135 5.0 0 3.3 5.25 0.25 5.25 V V V Symbol Min Nom Max Unit Notes: 1. VA- must be the most negative voltage to avoid potential SCR latch-up conditions. 2. VD must conform to Digital Supply Differential under Absolute Maximum Ratings. ABSOLUTE MAXIMUM RATINGS Parameter DC Power Supplies Positive Analog Negative Analog Digital [(VA+) - (VA-)] [(VD) - (VA-)] (Note 3) (Note 3) (Note 3) Symbol VA+ VAVD VADIFF VDDIFF IIN IIN IOUT PDN VINA VIND TA TSTG Min -0.3 -6.8 -0.3 (VA-)-0.5 -0.5 -40 -65 Max 6.8 0.3 6.8 6.8 6.8 +10 +50 +25 500 (VA+)+0.5 (VD)+0.5 85 150 Parameter V V V V V mA mA mA mW V V ºC ºC Analog Supply Differential Digital Supply Differential Input Current, Power Supplies Output Current Power Dissipation Analog Input Voltages Digital Input Voltages Input Current, Any Pin Except Supplies Ambient Operating Temperature (Power Applied) Storage Temperature Range WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 3. Transient currents up to 100 mA will not cause SCR latch-up. 4 DS595F3 CS3301 THERMAL CHARACTERISTICS Parameter Allowable Junction Temperature Junction to Ambient Thermal Impedance Ambient Operating Temperature (Power Applied) ΘJA TA Symbol Min - Typ 65 - Max 135 - Unit ºC ºC / W ºC -40 +85 ANALOG CHARACTERISTICS CS3301 Parameter Noise Performance, Normal Input Voltage Noise Input Voltage Noise Density Input Current Noise Density Noise Performance, Low Power (LPWR=1) Input Voltage Noise Input Voltage Noise Density Input Current Noise Density Distortion Performance, Normal Total Harmonic Distortion Linearity Total Harmonic Distortion Linearity (Note 5, 6) (Note 5, 6) (Note 5, 6) (Note 5, 6) THD LIN THD LIN -118 0.000126 Symbol f0 = 0.1 Hz to 10 Hz f0 = 0.1 Hz to 2 kHz (Note 4) f0 = 0.1 Hz to 10 Hz f0 = 0.1 Hz to 2 kHz (Note 4) VNPP VND IND VNPP VND IND Min - Typ 0.20 8.5 200 0.25 10.0 100 Max 0.40 12.0 0.50 15.0 -112 0.000251 Unit µVp-p nV/ Hz fA/ Hz µVp-p nV/ Hz fA/ Hz dB % dB % Distortion Performance, Low Power (LPWR=1) -118 0.000126 -110 0.000316 Notes: 4. Guaranteed by design and/or characterization. 5. Tested with a full scale input signal of 31.25 Hz. 6. Noise in the harmonic bins dominates THD and linearity measurements for x16, x32, x64 gains. CS3301 In-Band Noise 20 Noise Density (nV/rtHz) Noise Density (nV/rtHz) 300 250 200 150 100 50 0 CS3301 Wide Band Noise 15 10 5 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (Hz) 0.1 1 10 100 1000 10000 100000 1E+06 Frequency (Hz) Figure 1. CS3301 Noise Performance DS595F3 5 CS3301 ANALOG CHARACTERISTICS (CONT.) CS3301 Parameter Gain Gain, Differential Gain, Common Mode Gain Accuracy, Absolute Gain Accuracy, Relative Gain Drift Offset Offset Voltage, Input Referred Offset After Calibration, Absolute Offset Calibration Range Offset Voltage Drift (Note 11) OFST +5 +1 100 0.1 +15 µV µV % F.S. µV / ºC (Note 12) OFSTCAL (Note 13) OFSTRNG (Note 4, 10) OFSTTC (Note 7) (Note 8) (Note 9) (Note 4, 10) GAIN GAINCM GAINABS GAINREL GAINTC x1 x1 +1 +0.2 5 x64 +2 +0.5 % % ppm / ºC Symbol Min Typ Max Unit 7. Common mode signals pass through the differential amplifier architecture. 8. Absolute gain accuracy tests the matching of x1 gain across multiple CS3301 devices. 9. Relative gain accuracy tests the tracking of x1,x2,x4,x16,x32,x64 gain relative to x8 gain on a single CS3301 device. 10. Specification is for the parameter over the specified temperature range and is for the CS3301 device only. It does not include the effects of external components. 11. Offset voltage is tested with the amplifier inputs connected to the internal 800Ω termination. 12. The absolute offset after calibration specification applies to the effective offset voltage of the CS3301 output when used with the CS5371/72 modulator and CS5376A digital filter, and is measured from the digitally calibrated output codes of the CS5376A. 13. The CS3301 offset calibration is performed digitally with the CS5371/72 modulator and CS5376A digital filter and includes the full scale signal range. Calibration offsets of greater than + 5% of full scale will begin to subtract from system dynamic range. 6 DS595F3 CS3301 ANALOG CHARACTERISTICS (CONT.) CS3301 Parameter Analog Input Characteristics Input Signal Frequencies Input Voltage Range (Signal + Vcm) (Note 14) Full Scale Input, Differential x1 x2 - x64 x1 x2 x4 x8 x16 x32 x64 BW VIN VINFS DC (VA-)+0.7 (VA-)+0.7 Symbol Min Typ 1, 50 1 500 -130 100 680 0.24 - Max 2000 (VA+)-1.25 (VA+)-1.75 Unit Hz V Vp-p Vp-p Vp-p mVp-p mVp-p mVp-p mVp-p GΩ, pF MΩ pA dB dB Vp-p V Ω Ω/°C mA nF 90 (VA-)+0.5 5 2.5 1.25 625 312.5 156.25 78.125 1200 5 (VA+)-0.5 Input Impedance, Differential Input Impedance, Common Mode Input Bias Current Crosstalk, Multiplexed Inputs Common to Differential Mode Rejection Analog Output Characteristics Full Scale Output, Differential Output Voltage Range (Signal + Vcm) Output Impedance Output Impedance Drift Output Current Load Capacitance (Note 16) (Note 16) (Note 4) (Note 4, 15) ZINDIFF ZINCM IIN XT CDMR VOUT VRNG ZOUT ZTC IOUT CL - 3.33 100 Notes: 14. No signals operating from external power supplies should be applied to pins of the device prior to its own supplies being established. Connecting any terminal to voltages greater than VA+ or less than VAmay cause destructive latch-up. 15. Ratio of common mode input amplitude vs. differential mode output amplitude for a perfectly matched common mode input signal. Characterized with a 50 Hz, 500 mVpeak common mode sine wave applied to the analog inputs. 16. Output impedance characteristics are primarily determined by the integrated anti-alias resistors. Values are approximate and can vary up to +/- 10% depending on process parameters. DS595F3 7 CS3301 DIGITAL CHARACTERISTICS CS3301 Parameter Digital Characteristics High Level Input Drive Voltage Low Level Input Drive Voltage Input Leakage Current Digital Input Capacitance Rise Times, Digital Inputs Except CLK Fall Times, Digital Inputs Except CLK Master Clock Specifications Master Clock Frequency Master Clock Duty Cycle Master Clock Rise Time Master Clock Fall Time Master Clock Jitter (In-Band or Aliased In-Band) Master Clock Jitter (Out-of-Band) (Note 18) fCLK fDTY tRISE tFALL JTRIB JTROB 2.0 40 2.048 2.2 60 25 25 300 1 MHz % ns ns ps ns (Note 17) (Note 17) VIH VIL IIN CIN tRISE tFALL 0.6*VD 0.0 +1 9 VD 0.8 +10 100 100 V V µA pF ns ns Symbol Min Typ Max Unit Notes: 17. Device is intended to be driven with CMOS logic levels. 18. When CLK is tied to DGND, an internal oscillator provides a master clock at approximately 2 MHz. CLK should be driven for synchronous system operation. t rise t fa ll 0 .9 * V D 0 .1 * V D Figure 2. Digital Input Rise and Fall Times Input Selection 800 Ω termination INA only INB only INA + INB MUX1 0 1 0 1 MUX0 0 0 1 1 Gain Selection x1 x2 x4 x8 x16 x32 x64 reserved GAIN2 0 0 0 0 1 1 1 1 GAIN1 0 0 1 1 0 0 1 1 GAIN0 0 1 0 1 0 1 0 1 Table 1. Digital Selections for Gain and Input Mux Control 8 DS595F3 CS3301 POWER SUPPLY CHARACTERISTICS CS3301 Parameter Power Supply Current, Normal Analog Power Supply Current Digital Power Supply Current Analog Power Supply Current Digital Power Supply Current Analog Power Supply Current Digital Power Supply Current Power Supply Rejection Power Supply Rejection Ratio (Note 4, 20) PSRR 95 120 dB (Note 19) (Note 19) (Note 19) (Note 19) (Note 19) (Note 19) IA ID IA ID IA ID 5.25 0.2 3.5 0.2 9 2 6.8 0.25 4.75 0.25 11 8 mA mA mA mA µA µA Symbol Min Typ Max Unit Power Supply Current, Low Power (LPWR=1) Power Supply Current, Power Down (PWDN=1) Notes: 19. All outputs unloaded. Analog inputs connected to the internal 800 Ω termination. Digital inputs forced to VD or DGND respectively. 20. Power supply rejection characterized with a 50 Hz, 400 mVp-p sine wave applied separately to each supply. DS595F3 9 CS3301 2. GENERAL DESCRIPTION 2.1 2.1.1 The CS3301 is a low-noise chopper-stabilized CMOS differential input, differential output amplifier for precision analog signals between DC and 2 kHz. It has multiplexed inputs, rough/fine charge outputs, and programmable gains of x1, x2, x4, x8, x16, x32, and x64. The amplifier’s performance makes it ideal for low-frequency, high dynamic range applications requiring low distortion and minimal power consumption. It’s optimized for use in acquisition systems designed around the CS5371/72 single/dual ∆Σ modulators and the CS5376A quad digital filter. Figure 3 shows the system architecture of a 4channel acquisition system using four CS3301, two CS5372, one CS4373A, and one CS5376A. Analog Signals Analog Inputs The amplifier analog inputs are designed for differential sensors. Input multiplexing simplifies system connections by providing separate inputs for a sensor and test DAC (INA, INB) as well as an internal termination for noise tests. The MUX0, MUX1 digital pins determine which multiplexed input is connected to the amplifier. 2.1.2 Analog Outputs The amplifier analog outputs are separated into rough charge / fine charge signals to easily connect to the CS5371/72 inputs. Each output also includes a series resistor, requiring only two differential capacitors to create the CS5371/72 input anti-alias filter. Geophone or Hydrophone Sensor M U X CS3301 CS3302 AMP CS5371 CS5372 ∆Σ Modulator System Telemetry Geophone or Hydrophone Sensor M U X CS3301 CS3302 AMP CS5376A µController or Configuration EEPROM Digital Filter Geophone or Hydrophone Sensor M U X CS3301 CS3302 AMP CS5371 CS5372 ∆Σ Modulator Communication Interface Geophone or Hydrophone Sensor M U X CS3301 CS3302 AMP CS4373A Switch Switch MUX MUX Test DAC Figure 3. Multi-Channel System Architecture 10 DS595F3 CS3301 2.1.3 Differential Signals 2.2.2 Gain Selection Analog signals into and out of the CS3301 are differential, consisting of two halves with equal but opposite magnitude varying about a common mode voltage. A full scale 5 Vpp differential signal centered on a -0.15 V common mode can have: SIG+ = -0.15 V + 1.25 V = 1.1 V SIG- = -0.15 V - 1.25 V = -1.4 V SIG+ is +2.5 V relative to SIGFor the reverse case: SIG+ = -0.15 V - 1.25 V = -1.4 V SIG- = -0.15 V + 1.25 V = 1.1 V SIG+ is -2.5 V relative to SIGThe total swing for SIG+ relative to SIG- is (+2.5 V) - (-2.5 V) = 5 Vpp. A similar calculation can be done for SIG- relative to SIG+. Note that a 5 Vpp differential signal centered on a -0.15 V common mode voltage never exceeds 1.1 V and never drops below -1.4 V on either half of the signal. By definition, differential voltages are to be measured with respect to the opposite half, not relative to ground. A multimeter differentially measuring between SIG+ and SIG- in the above example would properly read 1.767 Vrms, or 5 Vpp. 2.2 2.2.1 The CS3301 supports gain ranges of x1, x2, x4, x8, x16, x32, and x64. They are selected using the GAIN0, GAIN1, and GAIN2 pins as shown in Table 1 on page 8. 2.2.3 Mux Selection The analog inputs to the amplifier are multiplexed, with external signals applied to the INA+, INA- or INB+, INB- pins. An internal termination is also available for noise tests. Input mux selection is made using the MUX0 and MUX1 pins as shown in Table 1 on page 8. Although a mux selection is provided to enable the INA and INB switches simultaneously, significant current should not be driven through them in this mode. The CS3301 mux switches will maintain good linearity only with minimal signal currents. 2.2.4 Low Power Selection For applications where power is critical, a lowpower mode can be selected. This mode reduces amplifier power consumption at the expense of slightly degraded performance. Low power mode is selected using the LPWR pin, which is active high. 2.2.5 Power Down Selection Digital Signals Clock Input The clock signal is used by the chopperstabilization circuitry of the amplifier analog inputs. The CLK pin can be driven by an external clock source for synchronous operation, or CLK can be grounded to run from its own internally generated clock signal. The CLK pin is connected to a clock detect circuit which will disable the internal clock and use an external clock if one is supplied. If the internal clock signal is to be used, the CLK pin should be connected to DGND. A power-down mode is available to shut down the amplifier when not in use. When enabled, all internal circuitry is disabled, the analog inputs and outputs go high-impedance, and the device enters a micro-power state. Power down mode is selected using the PWDN pin, which is active high. 2.3 2.3.1 Power Supplies Analog Power Supplies The analog power pins of the CS3301 are to be supplied with a total of 5 V between VA+ and VA-. This voltage is typically from a bipolar ±2.5 V power supply. When using bipolar power supplies, the analog signal common mode voltage should be biased to 0 V. The analog power supplies are rec- DS595F3 11 CS3301 ommended to be bypassed to system ground using 0.1 µF X7R type capacitors. The VA- supply is connected to the CMOS substrate and as such must remain the most negative applied voltage to prevent potential latch-up conditions. Care should be taken to ensure analog input voltages do not drop more than -0.3 V below the VA- supply. Care should also be taken to establish the VA- supply before analog signals are applied to the device. It is recommended to clamp the VAsupply to system ground using a reversed biased Schottky diode to prevent possible latch-up conditions related to mismatched supply rail initialization. 2.3.2 Digital Power Supplies The digital power supply across the VD and DGND pins is flexible and can be set to interface with 3.3V or 5V logic. The digital power supply should be bypassed to system ground using a 0.01 µF X7R type capacitor. 12 DS595F3 CS3301 2.4 Connection Diagram Figure 4 shows a connection diagram for the CS3301 amplifier when used with the CS5372 dual ∆Σ modulator and CS5376A digital filter. The diagram shows differential sensors, a test DAC, and analog outputs with anti-alias capacitors; power supply connections including recommended bypassing; and digital control connections back to the CS5376A GPIO pins. 3 2 GPIO (x3) GPIO (x2) GPIO GPIO MCLK PWDN LPWR CLK To CS5376A Digital Control GAIN MUX VA+ VA+ 0.1µF VD VD CS3301 Differential Amplifier VADGN D INAINBINB+ OUTROUTFOUTF+ OUTR+ VA+ 0.1µF VD 0.01µF 0.01µF VA0.1µF VA+ VD MDATA1 MFLAG1 PWDN1 INA+ INR+ INF+ 0.02µF C0G 0.02µF C0G Differential Sensor INFINRVREF+ MCLK MSYNC CS4373A Test DAC 2.5 V Reference VREF- CS5372 ∆Σ Modulator Differential Sensor 0.02µF C0G 0.02µF C0G INRINFINF+ INR+ LPWR OFST INA+ INA- INB- INB+ OUTR- OUTF- OUTF+ OUTR+ MDATA2 MFLAG2 PWDN2 VADGND VA+ VA+ 0.1µF VD VD CS3301 Differential Amplifier VADGN D GAIN MUX PWDN LPWR CLK 0.01µF VA0.1µF VA0.1µF 2 3 MCLK GPIO GPIO GPIO (x2) GPIO (x3) To CS5376A Digital Control Figure 4. CS3301 Amplifier Connections DS595F3 13 CS3301 3. PIN DESCRIPTION Positive Analog Power Supply Negative Analog Rough Output Negative Analog Fine Output Negative Analog Power Supply Non-Inverting Input A Inverting Input A Inverting Input B Non-Inverting Input B Test Mode Output Positive Analog Fine Output Positive Analog Rough Output Test Mode Select VA+ OUTROUTFVAINA+ INAINBINB+ TESTOUT OUTF+ OUTR+ TEST0 1 2 3 4 24 23 22 21 MUX0 MUX1 GAIN0 GAIN1 GAIN2 PWDN LPWR TEST1 VD DGND TEST2 CLK Input Mux Select Input Mux Select Gain Range Select Gain Range Select Gain Range Select Power Down Mode Enable Low Power Mode Enable Test Mode Select Positive Digital Power Supply Digital Ground Test Mode Select Clock Input 5 6 7 20 19 18 8 9 10 11 12 17 16 15 14 13 Figure 5. CS3301 Pin Assignments Pin Name VA+ VAVD DGND INA+, INAINB+, INBOUTR+, OUTROUTF+, OUTFGAIN0, GAIN1, GAIN2 CLK LPWR PWDN MUX0, MUX1 TEST0 TEST1, TEST2 TESTOUT Pin # I/O Pin Description 1 4 16 15 5, 6 8, 7 11, 2 10, 3 22, 21, 20 13 18 19 24, 23 12 17, 14 9 I I I I I I O O I I I I I I I O Positive analog supply voltage. Negative analog supply voltage. Positive digital supply voltage. Digital ground. Channel A differential analog inputs. Selected via MUX pins. Channel B differential analog inputs. Selected via MUX pins. Rough charge differential analog outputs. Fine charge differential analog outputs. Gain range select. See Gain Selection table in Digital Characteristics section. Master clock input. Connect to DGND to use internal oscillator. Low power mode enable. Active high. Power down mode enable. Active high. Analog input select. See Input Selection table in Digital Characteristics section. Test mode select, factory use only. Connect to VA- during normal operation. Test mode select, factory use only. Connect to DGND during normal operation. Test mode output, factory use only. Connect to VA- during normal operation. Table 2. Pin Descriptions 14 DS595F3 CS3301 4. ORDERING INFORMATION Model Temperature Package CS3301-IS CS3301-ISZ (lead free) -40 to +85 °C 24-pin SSOP 5. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp 240 °C 260 °C MSL Rating* 2 3 Max Floor Life 365 Days 7 Days CS3301-IS CS3301-ISZ (lead free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS595F3 15 CS3301 6. PACKAGE DIMENSIONS 24 PIN SSOP PACKAGE DRAWING N D E11 A2 A1 L E A e b2 SIDE VIEW END VIEW SEATING PLANE 123 TOP VIEW INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.024 0.025 0° MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.027 0.040 8° ∝ MILLIMETERS MIN MAX -2.13 0.05 0.25 1.62 1.88 0.22 0.38 7.90 8.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03 0° 8° NOTE 2,3 1 1 Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. 16 DS595F3