CS3310_05

CS3310 Stereo Digital Volume Control Features Complete Digital Volume Control — 2 Independent Channels — Serial Control — 0.5 dB Step Size Description The CS3310 is a complete stereo digital volume control designed specifically for audio systems. It features a 16bit serial interface that controls two independent, lowdistortion audio channels. The CS3310 includes an array of well-matched resistors and a low noise active output stage that is capable of driving a 600 Ω load. A total adjustable range of 127 dB, in 0.5 dB steps, is achieved through 95.5 dB of attenuation and 31.5 dB of gain. The simple 3-wire interface provides daisy-chaining of multiple CS3310's for multi-channel audio systems. The device operates from ±5 V supplies and has an input/output voltage range of ±3.75 V. ORDERING INFORMATION CS3310-KS CS3310-KSZ, Lead Free 0° to 70° C 0° to 70° C 16-pin Plastic SOIC 16-pin Plastic SOIC Wide Adjustable Range — -95.5 dB Attenuation — +31.5 dB Gain Low Distortion & Noise — 0.001% THD+N — 116 dB Dynamic Range Noise Free Level Transitions Channel-to-Channel Crosstalk Better Than 110 dB AINL 16 + MUX 8 8 14 8 1 2 16 3 Serial to Parallel Register 7 6 AOUTL MUTE ZCEN CS SDATAI SDATAO SCLK AGNDL AGNDR 15 10 8 Control Register 8 MUX 9 12 VA+ 13 VA+ 4 VD+ 5 DGND 11 AINR AOUTR Cirrus Logic, Inc. www.cirrus.com Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) SEPTEMBER '05 DS82F1 1 CS3310 ANALOG CHARACTERISTICS (TA = 25 °C, VA+, VD+ = 5 V ± 5%; VA- = -5V ± 5%; Rs = 0; RL = 2 kΩ; CL = 20 pF; 10 Hz to 20 kHz Measurement Bandwidth; unless otherwise specified) Parameter DC Characteristics Step Size Gain Error (31.5 dB Gain) Gain Matching Between Channels Input Resistance Input Capacitance AC Characteristics Total Harmonic Distortion plus Noise (V in = 2V rms, 1 kHz) Dynamic Range Input/Output Voltage Range Output Noise Digital Feedthrough (Peak Component) Interchannel Isolation (1 kHz) Output Buffer Offset Voltage Load Capacitance Short Circuit Current Unity Gain Bandwidth, Small Signal Power Supplies Supply Current (No Load, AIN = 0 V) IA+ IAID+ PD PSRR 7.0 7.0 450 72 80 9.0 9.0 800 94 mA mA µA mW dB (Note 2) (Note 1) VOS 2 0.25 20 0.75 100 mV pF mA MHz (Note 1) (Note 2) (Note 2) THD+N 110 (VA-)+1.25 -80 -100 0.001 116 4.2 -110 .0025 (VA+)-1.25 8.4 % dB V µVrms dB dB RIN CIN 8 0.5 ±0.05 ±0.05 10 10 dB dB dB kΩ pF Symbol Min Typ Max Unit Power Consumption Power Supply Rejection Ratio (250 Hz) Notes: 1. Measured with input grounded and Gain = 1. Will increase as a function of Gain settings >1. 2. This parameter is guaranteed by design and/or characterization. 2 DS82F1 CS3310 DIGITAL CHARACTERISTICS Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current (I O = 200µA) (I O = 3.2mA) (TA = 25 °C, VA+ , VD+ = 5V ± 5%, VA- = -5V ± 5% ) Symbol VIH VIL VOH VOL Iin Min 2.0 -0.3 VD-1.0 Typ 1.0 Max VD+0.3 +0.8 0.4 10 Unit V V V V µA SWITCHING CHARACTERISTICS Parameter Serial Clock Serial Clock MUTE Input Timing SDATAI Set Up Time SDATAI Hold Time CS Valid to SCLK Rising SCLK Falling to CS High Output Timing CS Low to Output Active SCLK Falling to Data Valid CS High to SDATAO Inactive (TA = 25 °C; VA+, VD+ = +5V ± 5%; VA- = -5V ± 5%; CL = 20 pF) Symbol SCLK Min 0 80 80 2.0 20 20 30 35 Typ Max 35 60 100 Unit MHz ns ns ms ns ns ns ns ns ns ns Pulse Width High Pulse Width Low Pulse Width Low tph tpl tSDVS tSDH tCSVS tLTH tCSH tSSD tCSDH CS t CSVS SCLK t SDH SDATAI t CSDH SDATAO MSB t CSH t SSD t SDVS t LTH Figure 1. Serial Port Timing Diagram DS82F1 3 CS3310 RECOMMENDED OPERATING CONDITIONS (DGND = 0V; all voltages with respect to ground) Parameter DC Power Supplies: Positive Digital Positive Analog Negative Analog (VD+) - (VA+) (Note 3) Ambient Operating Temperature VD+ VA+ VA TA 4.75 4.75 -4.75 -0.3 0 5.0 5.0 -5.0 25 VA+ 5.25 -5.25 0.0 70 V V V V °C Symbol Min Typ Max Unit Notes: 3. Applying power to VD+ prior to VA+ creates a SCR latch-up condition. Refer to Figure 2 for the recommended power connections. ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to ground.) Parameter DC Power Supplies: Positive Digital Positive Analog Negative Analog Input Current, Any Pin Except Supply Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature VD+ VA+ VAIin VIND TA TSTG -0.3 -0.3 0.3 -0.3 -55 -65 (VA+)+ 0.3 6.0 -6.0 ±10 (VA+) + 0.3 +125 +150 V V V mA V °C °C Symbol Min Max Unit 4 DS82F1 CS3310 10 ** 12 VA+ 0.1 µ F 13 10 µ F + 0.1 µ F 1 ZCEN 4 VD+ 0.1 µ F + +5V ANALOG 10 µ F 2 CS 3 CONTROLLER 6 SCLK 8 MUTE VA- 0.1 µ F 10 µ F + -5V ANALOG SDATAI CS3310 7 SDATAO TO ANOTHER CS3310 OR CONTROLLER * AOUTL 14 11 47 kΩ 16 AUDIO SOURCE AINL 9 AINR DGND 5 AGNDL 15 AOUTR AGNDR 10 AUDIO OUTPUTS *Required to terminate SDATAI due to high impedance state of SDATAO when CS is high. **Refer to Note 3. Figure 2. Recommended Connection Diagram DS82F1 5 CS3310 GENERAL DESCRIPTION The CS3310 is a stereo, digital volume control designed for audio systems. The levels of the left and right analog input channels are set by a 16-bit serial data word; the first 8 bits address the right channel and the remaining 8 bits address the left channel, as detailed in Table 1. Resistor values are decoded to 0.5 dB resolution by an internal multiplexer for a total attenuation range of -95.5 dB. An output amplifier stage provides a programmable gain of up to 31.5 dB in 0.5 dB steps. This results in an overall 8-bit adjustable range of 127 dB. The CS3310 operates from ±5 V supplies and accepts inputs up to ±3.75 V. Once in operation, the CS3310 can be brought to a muted state with the mute pin, MUTE, or by writing all zeros to the volume control registers. The device contains a simple three wire serial interface which accepts 16-bit data. This interface also supports daisy-chaining capability. SYSTEM DESIGN Very few external components are required to support the CS3310. Normal power supply decoupling components are all that is required, as shown in Figure 2. Serial Data Interface The CS3310 has a simple, three wire interface that consists of three input pins: SDATAI, serial data input; SCLK, serial data clock and CS, the chip select input. SDATAO, serial data output, enables the user to read the current volume setting or provide daisy-chaining of multiple CS3310’s. The 16-bit serial data is formatted MSB first and clocked into SDATAI by the rising edge of SCLK with CS low as shown in Figure 3. The data is latched by the rising edge of CS and the analog output levels of both left and right channels are set. The existing data in the volume control data register is clocked out SDATAO on the falling edge of SCLK. This data can be used to read current gain/attenuation levels or to daisy chain multiple CS3310’s. See Figure 1 for proper setup and hold times for CS, SDATAI, SCLK, and SDATAO. SCLK and SDATAI should be active only during volume setting operations to achieve optimum dynamic range. Daisy Chaining Digitally controlled, multi-channel audio systems often result in complex address decoding which complicates PCB layout. This is greatly simplified with the daisy-chaining capability of the CS3310. 6 DS82F1 CS3310 CS SCLK SDATAI R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0 R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0 L0 = Left Channel Least Significant Bit R0 = Right Channel Least Significant Bit L7 = Left Channel Most Significant Bit R7 = Right Channel Most Significant Bit SDATAI is latched internally on the rising edge of SCLK SDATAO transitions after the falling edge of SCLK SDATAO bits reflect the data previously loaded into the CS3310 SDATAO Figure 3. Serial Port Timing In single device operation, volume control data is loaded into the 16-bit shift register by holding the CS pin low for sixteen SCLK pulses and then latched on the rising edge of CS. The previous contents of the shift-register are shifted through the register and out SDATAO during the process. Multi-channel operation can be implemented as shown in Figure 4 by connecting the SDATAO of device #1 to the SDATAI pin of device #2. In this manner multiple CS3310s can be loaded from a single serial data line without complex addressing schemes. Volume control data is loaded by holding CS low for 16 x N SCLK pulses, where N is the number of devices in the chain. The 16 bits clocked into device #1 on SCLK pulses 1-16 are clocked into device #2 on SCLK pulses 1732. The CS3310s are simultaneously updated on the rising edge of CS following 16 x N SCLK pulses Notice that a 47 kohm resistor is required to terminate SDATAI, as shown in Figure 4, due to the high impedance state of SDATAO when CS is high.. 3 SDATAI 16 AUDIO SIGNAL 9 SCLK 6 2 CONTROLLER AINL AINR CS CS3310 #1 AOUTL SDATAO 7 47 k 3 AOUTR 14 11 SDATAI 16 AUDIO SIGNAL 9 AINL AINR CS3310 #2 SCLK CS 6 2 AOUTL 14 11 SDATAO 7 AOUTR Figure 4. Daisy Chaining Diagram DS82F1 7 CS3310 Changing the Analog Output Level Care has been taken to ensure that there are no audible artifacts in the analog output signal during volume control changes. The gain/attenuation changes of the CS3310 occur at zero crossings to eliminate glitches during level transitions. The zero crossing for the left channel is the voltage potential at the AGNDL pin; the voltage potential at the AGNDR pin defines the right channel zero crossing. A volume control change occurs after chip select latches the data in the volume control data register and two zero crossings are detected. If two zero crossings are not detected within 18 ms of the change in CS, the new volume setting is implemented. The zero crossing enable pin, ZCEN, enables or disables the zero crossing detection function as well as the 18 ms time-out circuit. Input Code (Left or Right Channel) Gain or Attenuation (dB) 11111111 11111110 • • 11000000 • 00000010 00000001 00000000 +31.5 +31.0 • • 0 • -95.0 -95.5 Software Mute Table 1. Input Code Definition Analog Inputs and Outputs The maximum input level is limited by the common-mode voltage capabilities of the internal opamp. Signals approaching the analog supply voltages may be applied to the AIN pins if the internal attenuator limits the output signal to within 1.25 volts of the analog supply rails. The outputs are capable of driving 600 Ω loads to within 1.25 volts of the analog supply rails and are short circuit protected to 20 mA. As with any adjustable gain stage the affects of a DC offset at the input must be considered. Capacitively coupling the analog inputs may be required to prevent “clicks and pops” which occur with gain changes if an appreciable offset is present. Source Impedance Requirements The CS3310 requires a low source impedance to achieve maximum performance. The ESD protection diodes on the analog input pins are reversed biased during normal operation. A characteristic of a reversed biased diode is a non-linear voltage dependent capacitance which can be 8 DS82F1 CS3310 a source of distortion if the source impedance becomes appreciable relative to the reversed biased diode capacitance. Source impedances equal to or less than 600 ohms will avoid this distortion mechanism for the CS3310. Mute Muting can be achieved by either hardware or software control. Hardware muting is accomplished via the MUTE input and software muting by loading all zeroes into the volume control register. MUTE disconnects the internal buffer amplifiers from the output pins and terminates AOUTL and AOUTR with 10 kΩ resistors to ground. The mute is activated with a zero crossing detection (independent of the zero cross enable status) or an 18 ms timeout to eliminate any audible “clicks” or “pops”. MUTE also initiates an internal offset calibration. A software mute is implemented by loading all zeroes into the volume control register. The internal amplifier is set to unity gain with the amplifier input connected to the maximum attenuation point of the resistive divider, AGND. A “soft mute” can be accomplished by sequentially ramping down from the current volume control setting to the maximum attenuation code of all zeroes. Power-Up Considerations Upon initial application of power, the MUTE pin of the CS3310 should be set low to initiate a power-up sequence. This sequence sets the serial shift register and the volume control register to zero and performs an offset calibration. The device should remain muted until the supply voltages have settled to ensure an accurate calibration. The device also includes an internal power-on reset circuit that requires approximately 100 µs to settle and will ignore any attempts to address the internal registers during this period. The offset calibration minimizes internally generated offsets and ignores offsets applied to the AIN pins. External clocks are not required for calibration. Although the device is tolerant to power supply variation, the device will enter a hardware mute state if the power supply voltage drops below approximately ±3.5 volts. A power-up sequence will be initiated if the power supply voltage returns to greater than ±3.5 volts. Applying power to VD+ prior to VA+ creates a SCR latch-up condition. Refer to Figure 2 for the recommended power connections. DS82F1 9 CS3310 PCB Layout, Grounding and Power Supply Decoupling As with any high performance device which contains both analog and digital circuitry, careful attention to power supply and grounding arrangements must be observed to optimize performance. Figure 2 shows the recommended power arrangements with VA+ connected to a clean +5 volt supply and VA- connected to a clean -5 volt supply. VD+ powers the digital interface circuitry and should be powered from VA+, as shown in Figure 2, to avoid potentially destructive SCR latchup. Decoupling capacitors should be located as near to the CS3310 as possible, see Figure 5. Figure 5. Recommended 2-Layer PCB Layout Analog Ground Plane 10 Ω + 10 µ F 10 µ F + VA+ VA10 µ F + 0.1 µ F 0.1 µ F 0.1 µ F The printed circuit board layout should have separate analog and digital regions with individual ground planes. The CS3310 should reside in the analog region as shown in Figure 5. Care should be taken to ensure that there is minimal resistance in the analog ground leads to the device to prevent any change in the defined attenuation settings. Extensive use of ground plane fill on both the analog and digital sections of the circuit board will yield large reductions in radiated noise effects. Performance Plots Figure 8 displays the CS3310 frequency response with a 3.75 Vp output. Figure 9 shows the frequency response with a 0.375 Vp output. Figure 6 is the Total Harmonic Distortion + Noise vs. amplitude at 1 kHz. The upper trace is the THD+N vs. amplitude of the CS3310 The lower trace is the THD+N of the Audio Precision System One generator output connected directly to the analyzer input. The System One panel settings are identical to the previous test. This indicates that the THD+N contribution of the Audio Precision actually degrades the measured performance of the CS3310 below 2.7 Vrms signal levels. 10 DS82F1 CS3310 Figure 7 is a 16k FFT plot demonstrating the crosstalk performance of the CS3310 at 20 kHz. Both channels were set to unity gain. The right channel input is grounded with the left channel driven to 2.65 Vrms output at 20 kHz. The FFT plot is of the right channel output. This indicates channel to channel crosstalk of -130 dB at 20 kHz. Figure 10 is a series of plots which display the unity-gain THD+N vs. Frequency for 600 Ω, 2 kΩ and infinite load conditions. The output was set to 2 Vrms. The Audio Precision System One was bandlimited to 22 kHz Figure 11 is a series of plots which display the unity-gain THD+N vs. Frequency for 1, 2 and 2.8 Vrms output levels. The output load was open circuit. The Audio Precision System One was bandlimited to 22 kHz. DS82F1 11 CS3310 . THD+N% vs AMPL (Vrms) AMPL (dBr) vs FREQ (Hz) 0 -20 1 .1 -40 -60 -80 .01 -100 -120 .001 -140 -160 .0001 0.1 1 3 -180 20.00 2.06k 4.11k 6.15k 8.19k 10.2k 12.3k 14.3k 16.4k 18.4k 20.5k 22.5k Figure 6. THD+N vs. AMP AMPL (dBr) vs FREQ (Hz) 1.0 1.0 Figure 7. 20 kHz Crosstalk AMPL (dBr) vs FREQ (Hz) 0.5 0.5 0.0 0.0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 -2.0 -2.0 10 100 1k 10k 100k 200k 10 100 1k 10k 100k 200k Figure 8. Frequency Response Full Scale Input 0.1000 Figure 9. Frequency Response -20 dB Input 0.1000 0.0100 600Ω 0.0100 2kΩ 2.8 VRMS 0.0010 OPEN 0.0010 2 VRMS 1 VRMS 0.0001 20 100 1k 10k 20k 0.0001 20 100 1k 10k 20k Figure 10. THD+N vs. Frequency LOAD = 600 Ω, 2 kΩ, open ckt Figure 11. THD+N vs. Frequency Output levels of 1, 2, and 2.8 Vrms 12 DS82F1 CS3310 PIN DESCRIPTION Zero Crossing Enable Chip Select Serial Data Input Positive Digital Power Digital Ground Serial Clock Input Serial Data Output Mute ZCEN CS SDATAI VD+ DGND SCLK SDATAO MUTE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 AINL AGNDL AOUTL VAVA+ AOUTR AGNDR AINR Left Channel Input Left Analog Ground Left Channel Output Negative Analog Power Positive Analog Power Right Channel Output Right Analog Ground Right Channel Input Power Supply Connections VA+ - Positive Analog Power, Pin 12. Positive analog supply. Nominally +5 volts. VA- - Negative Analog Power, Pin 13. Negative analog supply. Nominally -5 volts. AGNDL - Left Channel Analog Ground, Pin 15. Analog ground reference for the left channel. AGNDR - Right Channel Analog Ground, Pin 10. Analog ground reference for the right channel. VD+ - Positive Digital Power, Pin 4. Positive supply for the digital section. Nominally +5 volts. Applying power to VD+ prior to VA+ creates a SCR latch-up condition. Refer to Figure 2 for the recommended power connections. DGND - Digital Ground, Pin 5. Digital ground for the digital section. DS82F1 13 CS3310 Analog Inputs and Outputs AINL, AINR - Left and Right Channel Analog Inputs, Pins 16, 9. Analog input connections for the left and right channels. Nominally ±3.75 volts for a full scale input. AOUTL, AOUTR - Left and Right Channel Analog Outputs, Pins 14, 11. Analog outputs for the left and right channels. Nominally ±3.75 volts for a full scale output. Digital Pins SDATAI - Serial Data Input, Pin 3. Serial input data that sets the analog output level of the left and right channels. The data is formatted in a 16-bit word. The first eight bits clocked into this pin control the analog output level for the right channel, and the second eight bits clocked into the device control the analog output level for the left channel. The data is clocked into the CS3310 by the rising edge of SCLK. SDATAO - Serial Data Output, Pin 7. Serial output data that provides daisy-chaining of multiple CS3310’s. This serial output will output the previous sixteen bits of volume control data that were clocked into the SDATAI pin. SDATAO will enter a High Impedance State when CS is High. SCLK - Serial Input Clock, Pin 6. Serial clock that clocks in the individual bits of serial data from the SDATAI pin. This clock is also used to clock out the individual bits from the SDATAO pin. The SDATAI data is latched on the rising edge, and SDATAO data is clocked out on the falling edge. CS - Chip Select, Pin 2. When high, the SDATAO output is held in a high impedance state. A falling transition defines the start of the 16-bit volume control word into the device. The 16-bit input data is latched into the control register on the rising edge of CS. MUTE - Mute, Pin 8. Forces both the left and right analog output channels to ground. An offset calibration is initiated following the low transition of MUTE. Calibration requires a minimum mute period of 2 ms. 14 DS82F1 CS3310 ZCEN - Zero Crossing Enable, Pin 1. This pin enables or disables the zero crossing detection and time-out function used during analog output level transitions. A high level on this pin enables the zero crossing detection function. A low level on this pin disables the zero crossing detection. PARAMETER DEFINITIONS Dynamic Range Full scale (RMS) signal to broadband noise ratio. The broadband noise is measured over the specified bandwidth with the input grounded. Units in decibels. Total Harmonic Distortion plus Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with the input under test grounded and a full-scale signal applied to the other channel. Units in decibels. DS82F1 15 CS3310 PACKAGE DIMENSIONS 16L SOIC (300 MIL BODY) PACKAGE DRAWING E H 1 b c D SEATING PLANE e A1 A L ∝ INCHES DIM A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.398 0.291 0.040 0.394 0.016 0° MAX 0.104 0.012 0.020 0.013 0.413 0.299 0.060 0.419 0.050 8° JEDEC #: MS-013 ∝ MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 7.40 7.60 1.02 1.52 10.00 10.65 0.40 1.27 0° 8° 16 DS82F1 CS3310 Revision PP1 PP2 PP3 PP4 F1 Date April 1991 December 1992 February 1999 July 2004 September 2005 Initial release Update specifications Update specifications Changes Update specifications and bring into new template. Add lead free part. Added “Lead Free” to Ordering Information on front page. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. 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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS82F1 17