CS4216-KL

Semiconductor Corporation CS4216 General Description The CS4216 is an MwaveTM audio codec. The CS4216 Stereo Audio Codec is a monolithic CMOS device for computer multimedia, automotive, and portable audio applications. It performs A/D and D/A conversion, filtering, and level setting, creating 4 audio inputs and 2 audio outputs for a digital computer system. The digital interfaces of left and right channels are multiplexed into a single serial data bus with word rates up to 50 kHz per channel. Up to 4 CS4216 devices can be attached to a single hardware bus. Both the ADCs and the DACs use delta-sigma modulation with 64X oversampling. The ADCs include a digital decimation filter which eliminates the need for external anti-aliasing filters. The DACs include output smoothing filters on-chip. Ordering Information: CS4216-KL 0° to 70°C CS4216-KQ 0° to 70°C CDB4216 Evaluation Board 44-pin PLCC 44-pin TQFP 16-Bit Stereo Audio Codec Features • CMOS Stereo Audio Input/Output System Delta-Sigma A/D Converters Delta-Sigma D/A Converters Input Anti-Aliasing and Output Smoothing Filters Programmable Input Gain and Output Attenuation • Sample Frequencies of 4 kHz to 50 kHz • CD Quality Noise and Distortion < 0.01 %THD • Internal 64X Oversampling • Low Power Dissipation: 80 mA 1 mA Power-Down Mode RESET POW ER CONTROL PDN D IG IT A L F IL T E R S D /A OUTPUT A T TE N U A TIO N LO U T OUTPUT MUTE ROUT DO 1 M F 5 :D O 2 /IN T M F 2 :D O 3 /F 2 /C D IN M F 1 :D O 4 /F 1 /C D O U T D I1 M F 6 :D I2 /F 1 M F 3 :D I3 /F 3 /C C L K M F 4 :D I4 /M A /C C S R EFG N D R EF BYP REFBUF L IN 1 L IN 2 INPUT GAIN INPUT MUX R IN 1 R IN 2 SM ODE3 SM ODE2 SM ODE1 S D IN SDOUT SC LK SSYNC D /A S E R IA L IN T E R F A C E C O N T R O L V O LTAG E R EFERE NC E D IG ITA L F IL T E R S M F 7:S F S 1 /F 2 M F 8:S F S 2 /F 3 C L K IN A /D A /D VD VA DGND AGND Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 Copyright © Crystal Semicondutor Corporation 1993 (All Rights Reserved) Oct ’93 DS83F2 1 CS4216 RECOMMENDED OPERATING CONDITIONS spect to 0V.) Parameter Power Supplies: Operating Ambient Temperature Digital Analog (AGND, DGND = 0V, all voltages with reMin 4.75 4.75 0 Typ 5.0 5.0 25 Max 5.25 5.25 70 Units V V °C Symbol VD VA TA ANALOG CHARACTERISTICS( TA = 25°C; VA, VD = +5V; Input Levels: Logic 0 = 0V, Logic 1 = VD; 1 kHz Input Sine Wave; CLKIN = 24.576 MHz; SM1; Conversion Rate = 48 kHz; SCLK = 12.288 MHz; Measurement Bandwidth is 10 Hz to 20 kHz; Unless otherwise specified.) Parameter * Symbol Min Typ Max Units Analog Input Characteristics - Minimum gain setting (0 dB); unless otherwise specified. ADC Resolution ADC Differential Nonlinearity Instantaneous Dynamic Range Total Harmonic Distortion Interchannel Isolation Interchannel Gain Mismatch Frequency Response Programmable Input Gain Span Gain Step Size Absolute Gain Step Error Gain Drift Offset Error Full Scale Input Voltage Input Resistance Input Capacitance (Notes 1,2) (Note 1) DC Coupled Inputs AC Coupled Inputs (Note 1) (Note 1) IDR THD 16 80 -0.5 21 2.5 20 85 80 22.5 1.5 100 ±10 ±150 2.8 ±0.9 0.01 ±0.5 +0.2 24 0.75 ±100 ±400 3.1 15 Bits LSB dB % dB dB dB dB dB dB ppm/°C LSB LSB Vpp kΩ pF Notes: 1. This specification is guaranteed by characterization, not production testing. 2. Input resistance is for the input selected. Non-selected inputs have a very high (>1M Ω) input resistance. * Parameter definitions are given at the end of this data sheet. MwaveTM is a trademark of the IBM Corporation. Specifications are subject to change without notice. 2 DS83F2 CS4216 ANALOG CHARACTERISTICS Parameter * (Continued) Symbol Min Typ Max Units Analog Output Characteristics - Minimum Attenuation; Unless Otherwise Specified. DAC Resolution DAC Differential Nonlinearity Total Dynamic Range Instantaneous Dynamic Range Total Harmonic Distortion Interchannel Isolation Interchannel Gain Mismatch Frequency Response Programmable Output Attenuation Span Attenuation Step Size Absolute Attenuation Step Error Gain Drift REFBUF Output Voltage Offset Voltage Full Scale Output Voltage Deviation from Linear Phase Out of Band Energy (Note 4) (Note 1) (22 kHz to 100 kHz) (Note 5) Maximum output current= 400 µA (Note 1) (Note 3) (Note 3) (Note 3) (Note 4) (Note 4) (Note 1) TDR IDR THD 16 80 -0.5 -45 1.9 2.5 93 83 80 -46.5 1.5 100 2.2 10 2.8 -60 ±0.9 0.02 ±0.5 +0.2 0.75 2.5 3.1 1 Bits LSB dB dB % dB dB dB dB dB dB ppm/°C V mV Vpp Degree dB Power Supply Power Supply Current Power Supply Rejection (Note 6) Operating Power Down (1 kHz) 80 40 100 1 mA mA dB Notes: 3. Tested in SM3, Slave sub-mode, 128 BPF. 4. 10 kΩ, 100 pF load. 5. REFBUF load current must be DC. To drive dynamic loads, REFBUF must be buffered. AC variations in REFBUF current may degrade ADC and DAC performance. 6. Typically current: VA = 30mA, VD = 50mA. Power supply current does not include output loading. * Parameter definitions are given at the end of this data sheet. DS83F2 3 CS4216 SWITCHING CHARACTERISTICS (TA = 25°C; VA, VD = +5V, outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD) Parameter Input clock (CLKIN) frequency CLKIN low time CLKIN high time Sample Rate DI pins setup time to SCLK edge DI pins hold time from SCLK edge DO pins delay from SCLK edge SCLK and SSYNC output delay from CLKIN rising SCLK period SCLK high time SCLK low time SDIN, SSYNC setup time to SCLK edge SDIN, SSYNC hold time from SCLK edge SDOUT delay from SCLK edge Output to Hi-Z state Output to non-Hi-Z RESET pulse width low CCS low to CCLK rising CDIN setup to CCLK falling CCLK low to CDIN invalid (hold time) CCLK high time CCLK low time CCLK Period CCLK rising to CDOUT data valid CCLK rising to CDOUT Hi-Z CCLK falling to CCS high SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) tcslcc tdiscc tccdih tcclhh tcclhl tcclkw tccdov tccdot tcccsh bit 64 (Note 1) bit 1 (Note 1) Master Mode (Note 1) Master Mode (Note 7) Slave Mode Slave Mode Slave Mode Slave Mode Slave Mode (Note 1) (Note 1) (Note 1) SM1: SM2, SM3, SM4: Symbol CLKIN CLKIN tckl tckh Fs ts2 th2 tpd2 tpd3 tsckw tsckh tsckl ts1 th1 tpd1 thz tnz Min 2.048 1.024 15 15 4 10 8 30 75 30 30 15 10 15 500 25 15 10 25 25 75 0 Typ 24.576 12.288 1/(Fs*bpf) Max 25.6 12.8 50 50 28 12 30 30 Units MHz MHz ns ns kHz ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 7. When the CS4216 is in master mode (SSYNC and SCLK outputs), the SCLK duty cycle is 50%. The equation is based on the selected sample frequency (Fs) and the number of bits per frame (bpf). 4 DS83F2 CS4216 Frame Sync SSYNC [SM1, SM2\ t sckl SCLK [SM1,SM2\ t sckw SCLK [SM3,SM4\ t sckh t sckl t s1 SSYNC [SM3,SM4\ t s1 SDIN [SM1,SM2,SM3\ (SM4) t h1 Bit 1 t pd1 [SM1,SM2,SM3\ SDOUT (SM4) t nz * Optional Bit 1 Bit 2 t pd1 Bit 2 Bit 32 (Bit 32) Bit 33 (Bit 1) Bit 63 (Bit 31) Bit 64 (Bit 32) Bit 32 (Bit 32) Bit 33 (Bit 1) Bit 63 (Bit 31) Bit 64 (Bit 32) t hz t h1 t sckh t s1 t h1 t s1 t h1 *Word Sync *Word Sync Serial Audio Port Timing M F 4 :C C S M F 1 :C D O U T ADV t cslcc t cclkh t ccd ih 0 1 M SK 2 DO1 3 L A tt4 4 t cclkl t ccd o v LCL M F 3 :C C L K t disc c M F 2 :C D IN t cc lkw L A tt3 5 L A tt2 6 L A tt1 7 L A tt0 8 R A tt4 9 R A tt3 10 R A tt2 11 M F 4 :C C S t c ccs h M F 1 :C D O U T 0 0 1 Err1 Err0 LCL RCL D I1 ADV t cc do t M F 3 :C C L K M F 2 :C D IN R G a in 2 R G ain1 R G ain0 22 23 24 0 25 0 26 0 27 0 28 0 29 0 30 0 31 0 32 Serial Mode 4. Control Data Serial Port Timing DS83F2 5 CS4216 SCLK* t s2 DIx t pd2 DOx * SCLK is inverted for SM1 and SM2 DI/DO Timing SCLK SSYNC (Master Mode) SCLK & SSYNC Output Timing (Master Mode) t h2 CLKIN t pd3 t ckl t ckh DIGITAL CHARACTERISTICS (TA = 25°C; VA, VD = 5V) Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage at I0 = -2.0 mA Low-level Output Voltage at I0 = +2.0 mA Input Leakage Current Output Leakage Current Output Capacitance Input Capacitance (Digital Inputs) (High-Z Digital Outputs) COUT CIN Symbol VIH VIL VOH VOL Min VD-1.0 VD-0.3 Typ Max 1.0 0.1 10 10 15 15 Units V V V V µA µA pF pF 6 DS83F2 CS4216 A/D Decimation Filter Characteristics Parameter Passband Frequency Response Passband Ripple Transition Band Stop Band Stop Band Rejection Group Delay Group Delay Variation vs. Frequency (Fs is conversion freq.) Symbol Min 0 -0.5 0.45Fs ≥ 0.55Fs 80 Typ 16/Fs Max 0.45Fs +0.2 ±0.2 0.55Fs 0.0 Units Hz dB dB Hz Hz dB s µs D/A Interpolation Filter Characteristics Parameter Passband Frequency Response Passband Ripple Transition Band Stop Band Stop Band Rejection Group Delay Group Delay Variation vs. Frequency (Fs is conversion freq.) Symbol Min 0 -0.5 0.45Fs ≥ 0.55Fs 74 Typ 16/Fs Max 0.45Fs +0.2 ±0.1 0.55Fs 0.1/Fs Units Hz dB dB Hz Hz dB s µs ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.) Parameter Power Supplies: Input Current Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Warning: (Power Applied) Digital Analog (Except Supply Pins) Symbol VD VA Min -0.3 -0.3 -0.3 -0.3 -55 -65 Typ Max 6.0 6.0 ±10.0 VA+0.3 VD+0.3 +125 +150 Units V V mA V V °C °C Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. DS83F2 7 CS4216 F errite B ead +5V S upply + 1 µF 0 .1 µ F 2.0 + 1 µF 0 .1 µ F 24 VD VA 15 R IN 2 ROUT 600 + +5V A nalog If a s eparate +5V A na log supply is use d, rem ove the 2.0 o hm re sistor > 1.0 µ F 40 k 0 .0 0 2 2 µ F NPO R ig ht A u dio O utpu t 4 Line In 2 R ight 26 S ee A nalog Inputs s ection for sugg ested inp ut ciruits. LO U T 16 600 + > 1.0 µ F 40 k L eft A u dio O utpu t L in e In 2 L eft 28 LIN 2 21 R E F BY P 22 CS4216 R E FG N D 0.0 0 2 2 µ F NPO + 0 .1 µ F 10 µ F Line In 1 R ig ht 25 R IN 1 C LKIN R E SE T 3 2 T o O ptional Input B uffe rs 20 0 .4 7 µ F PDN R EFBU F SDO UT 13 43 42 44 1 33 37 D I1 DO1 C on troller S D IN SC LK S S YN C LIN 1 L in e In 1 L eft 27 40 P aralle l Bits or S ub -M ode S ettings or C ontrol P ort 39 35 36 38 34 M F1:D O 4/F 1/C D O U T M F2:D O 3/F 2/C D IN M F3:D I3/F3/C C LK M F 4:D I4/M A/C C S M F5:D O 2/IN T M F6:D I2/F 1 AG N D 23 DGND 5 R efer to the A nalog Inputs section for term inatin g unu sed line inp uts. A ll other unused in puts should b e tied to G N D . A ll N C pins sh ould be le ft floating. SMODE3 41 32 29 31 30 M ode S etting SMODE2 SMODE1 M F7 :S FS 1 M F8:S FS 2 N ote: A G N D and D G N D pins M U S T be o n th e sam e gro und plane Figure 1. Typical Connection Diagram 8 DS83F2 CS4216 OVERVIEW The CS4216 contains two analog-to-digital converters, two digital-to-analog converters, adjustable input gain, and adjustable output level control. Since the converters contain all the required filters in digital or sampled analog form, the filters’ frequency responses track the sample rate of the CS4216. Only a single-pole RC filter is required on the analog inputs and outputs. The RC filter acts as a charge reserve for the switched-capacitor input and buffers op-amps from a switched-capacitor load. Communication with the CS4216 is via a serial port, with separate pins for data into the device, and data from the device. The filters and converters operate over a sample rate range of 4 kHz to 50 kHz. 56 pF Line In Right 0.47 uF 20 k 10 k _ + 150 0.01 uF NPO 5k REFBUF RINx (PLCC pin 25 or 26) Example Op-Amps are MC34072 or LT1013 0.47 uF _ 0.47 uF 20 k Line In Left Op-amps are run from VA+5V and AGND + 10 k 150 0.01 uF NPO LINx (PLCC pin 27 or 28) 56 pF Figure 2. DC Coupled Input. FUNCTIONAL SPECIFICATIONS Analog Inputs and Outputs Line In 0.47 uF Right RINx (PLCC pin 25 or 26) 0.01 uF NPO Figure 1 illustrates the suggested connection diagram to obtain full performance from the CS4216. The line level inputs, LIN1 or LIN2 and RIN1 or RIN2, are selected by an internal input multiplexer. This multiplexer is a source selector and is not designed for switching between inputs at the sample rate. Unused analog inputs that are not selected have a very high input impedance, so they may be tied to AGND directly. Unused analog inputs that are selected should be tied to AGND through a 0.1 µF capacitor. This prevents any DC current flow. The analog inputs are single-ended and internally biased to the REFBUF voltage (nominally 2.2 V). The REFBUF output pin can be used to level shift an input signal centered around 0 Volts as shown in Figure 2. The input buffers shown have a gain of 0.5, yielding a full scale input sensitivity of 2 Vrms with the CS4216 proDS83F2 150 NPO 0.01 uF Line In Left 0.47 uF 150 LINx (PLCC pin 27 or 28) Figure 3. AC Coupled Input grammable gain set to 0. If the source impedance is very low, then the inputs can be AC coupled with a series 0.47 µF capacitor, eliminating the need for external op-amps (see Figure 3). However, the use of AC coupling capacitors will increase DC offset at 0dB gain (see Analog Characteristics Table). The analog outputs are also single-ended and centered around the REFBUF pin. AC coupling capacitors of >1 µF are recommended. 9 CS4216 Offset Calibration Both input and output offset voltages are minimized by internal calibration. Offset calibration occurs after exiting a reset or power down condition. During calibration, which takes 194 frames, output data from the ADCs will be all zeros, and will be flagged as invalid. Also, the DAC outputs will be muted. After power down mode or power up, RESET should be held low for a minimum of 50 ms to allow the voltage reference to settle. Input Gain and Output Level Setting Input gain is adjustable from 0 dB to +22.5 dB in 1.5 dB steps. In serial modes SM1 and SM2, the output level attenuation is adjustable from 0 dB to -22.5 dB. In serial modes SM3 and SM4, the output level attenuation is adjustable from 0 dB to -46.5 dB. Both input and output gain adjustments are internally made on zerocrossings of the analog signal, to minimize "zipper" noise. The gain change automatically takes effect if a zero crossing does not occur within 512 frames. Muting and the ADC Valid Counter The mute function allows the output channels to be silenced. It is the controlling processor’s responsibility to reduce the signal level to a low value before muting, to avoid an audible click. The outputs should be muted before changing the sample frequency. The serial data stream contains a "Valid Data" indicator for the A/D converters which is false until enough clocks have passed since reset, or low-power (power down mode) operation to have valid A/D data from the filters, i.e., until calibration time plus the full latency of the digital filters has passed. SSYNC SCLK (SM3) Start of Frame DI pins latched DO pins update Figure 4. Digital Input/Output Timing Parallel Digital Input/Output Pins Parallel digital inputs are general purpose pins whose value is reflected in the serial data output stream to the processor. Parallel digital outputs provide a way to control external devices using bits in the serial data input stream. All parallel digital pins, with the exception of DI1 and DO1, are multifunction and are defined by the serial mode selected. Serial modes 1 and 2 define all multifunction pins as general purpose digital inputs and outputs. In Serial mode 3 only two digital inputs and two digital outputs are available. In serial mode 4 only one digital input and digital output exists. Figure 4 shows when the DI pins are latched, and when the DO pins are updated in SM3 and SM4. Reset and Power Down Modes Reset places the CS4216 into a known state and must be held low for at least 50 ms after powerup or a hard power down. Reset must also occur when the codec is in master mode and a change in sample frequency is desired. In reset, the digital outputs are driven low. Reset sets all control data register bits to zero. Hard power down mode may be initiated by bringing the PDN pin low. All analog outputs will be driven to the REFBUF voltage which will then decay to zero. All digital outputs will be driven low and then will go to a high impedance state. Minimum power consumption will occur if CLKIN is held low. After leaving the power down state, RESET should be held low for 50 ms to allow the analog voltage reference to settle before calibration is started. DS83F2 10 CS4216 Alternatively, soft power down may be initiated, in slave mode, by reducing the SCLK frequency below the minimum CLKIN/12. In soft power down the analog outputs are muted and the serial data from the codec will indicate invalid data and the appropriate error code. The parallel bit I/O is still functional in soft power down mode. This is, in effect, a low power mode with only the parallel bit I/O unit functioning. audio data which reduces the number of bits on the audio port from 64 to 32 per codec. The serial port protocol is based on frames consisting of 1, 2, or 4 sub-frames. The frame rate is the system sample rate. Each sub-frame is used by one CS4216 device. Up to 4 CS4216s may be attached to the same serial control lines. SFS1 and SFS2 are tied low or high to indicate to each CS4216 which sub-frame is allocated for it to use. Serial Data Format In serial modes 1, 2, and 3, the audio serial port uses 4 pins: SDOUT, SDIN, SCLK and SSYNC. SDIN carries the D/A converters’ input data and control bits. Input data is ignored for frames not allocated to the selected CS4216. SDOUT carries the A/D converters’ output data and status bits. SDOUT goes to a high-impedance state during frames not allocated to the selected CS4216. SCLK clocks data in to and out of the CS4216. The rising edge of SCLK clocks data out on SDOUT. The falling edge latches data on SDIN into the port (SCLK polarity is inverted in Serial Modes 1&2). SSYNC indicates the start of a frame and/or sub-frame. SCLK and SSYNC must be synchronous to the master clock. Serial mode 4 is similar to serial mode 3 with the exception of the control information. In serial mode 4 the control information is entered through a separate asynchronous control port. Therefore, the audio serial port only contains SMODE PINS 3 2 1 0 0 0 0 1 † Audio Serial Interface In serial modes 1, 2, and 3, a sub-frame is 64 bits in length and consists of two 16-bit audio values and two 16-bit control fields. In serial mode 4 a sub-frame is 32 bits in length and only contains the two 16-bit audio values; the control data is loaded through a separate port. The audio data is MSB first, 2’s complement format. The sub-frame bit assignments for serial modes 1, 2, and 3, are numbered 1 through 64 and are shown in Figures 5 and 6. Control data bits all reset to zero. CS4216 SERIAL INTERFACE MODES The CS4216 has 4 serial port modes, selected by the SMODE1, SMODE2 and SMODE3 pins. In all modes, CLKIN, SCLK and SSYNC must be derived from the same clock source. SM1 is an easy interface to ASICs that use a change in the SCLK-to-CLKIN ratio to determine the sample SCLK & SSYNC Slave Master Frequency CLKIN = 512×Fs SCLK = 256×Fs CLKIN/SCLK = 256×Fs CLKIN = 256×Fs Serial Mode SM1 SM2 SM3 SM4 SCLK Bit Center Rising Sub-frame Width 64 bits Bits per Frame (BPF) 256 0 0 1 1 x 0 1 0 1 x Rising 64 bits Falling 64 bits Factory Test mode Falling 32 bits† 256 Slave 64/128/256 Master/Slave 32/64/128† Master/Slave Contains audio data only. Control information is entered through a separate serial port. Table 1. Serial Port Modes DS83F2 11 CS4216 INPUT DATA BIT DEFINITIONS Sub-frame bits 1 to 16 Left DAC Audio Data, MSB first, 2’s complement coded. Sub-frame Bits 17 to 24 17 0 EXP 18 0 19 0 20 0 21 22 EXP MUTE 23 ISL 24 ISR Sub-frame Bits 33 to 48 Right DAC audio data MSB first, 2’s complement coded. Sub-frame Bits 49 to 50 Must be zero. Sub-frame Bits 51 to 60 51 52 53 54 55 56 57 58 59 60 * LA4 LA3 LA2 LA1 LA0 RA4 RA3 RA2 RA1 RA0 † 0 0 LA3 LA2 LA1 LA0 RA3 RA2 RA1 RA0 Expand bit Reserved. Must be set to zero. MUTE Mute D/A Outputs 0 - Normal Outputs 1 - Mute Outputs ISL Select Left Input Mux 0 - Select LIN1 1 - Select LIN2 Select Right Input Mux 0 - Select RIN1 1 - Select RIN2 LA4-LA0 Sets left output attenuation †SM1, 2 *SM3,4 LA3 is the MSB. LA4 is the MSB. 0000 = no attenuation 00000 = no attenuation 1111 = -22.5 dB 11111 = -46.5 dB LA0 represents 1.5 dB. RA4-RA0 Sets right output attenuation *SM3,4 †SM1, 2 RA4 is the MSB. RA3 is the MSB. 00000 = no attenuation 0000 = no attenuation 11111 = -46.5 dB 1111 = -22.5 dB RA0 represents 1.5 dB. ISR Sub-frame Bits 25 to 32 25 LG3 26 LG2 27 LG1 28 LG0 29 30 31 32 RG3 RG2 RG1 RG0 LG3-LG0 Sets left input gain. LG3 is the MSB. LG0 represents 1.5 dB. 0000 = no gain. 1111 = +22.5 dB gain RG3-RG0 Sets right input gain. RG3 is the MSB. RGO represents 1.5 dB. 0000 = no gain Sub-frame Bits 61 to 64 61 62 63 64 DO1 DO2 DO3 DO4 DO1-DO4 Set the logic level on the 4 digital output pins. In SM3 DO3 and DO4 are not available. In SM4 DO2, DO3, & DO4 are not available. Sub-frame Sub-frame Word A 01 16 17 21 22 23 24 25 28 29 32 33 Word B 51 52 53 60 61 64 XX 48 55 56 57 DAC - Left Word 0000 In 3 Left 0 3 Right 0 M Sel. A/D Gain A/D Gain MSB DAC - Right Word 3 Left 0 3 Right 0 D/A Att. 0 0 0 0 D/A Att. MSB SM1 and SM2 DAC - Left Word 0000 In 3 Left 0 3 Right 0 M Sel. A/D Gain A/D Gain SM3 MSB DAC - Right Word 00 4 Left 0 4 Right 0 D/A Att. D/A Att. MSB EXP Figure 5. Serial Data Input Format - SM1, SM2, and SM3. 12 DS83F2 DO1 DO2 LSB LSB DO1 DO2 DO3 DO4 LSB EXP LSB CS4216 OUTPUT DATA BIT DEFINITIONS Sub-frame Bits 1 to 16 Left ADC Audio Data, MSB first, 2’s complement coded. Sub-frame Bits 25 to 32 25 ER3 26 ER2 27 ER1 28 ER0 29 Ver3 30 Ver2 31 Ver1 32 Ver0 Sub-frame Bits 17 to 24 17 ADV 18 19 RESERVED 20 21 0 22 ADV 23 LCL 24 RCL ADC Valid data bit. 0 - Invalid ADC data 1 - Valid ADC data Indicates ADC has completed initialization after power-up, low power mode, or mute. ER3-ER0 Error Word 0000 - Normal – No errors. 0001 - Input Sub-frame Bit 21 is set. Control data will not be loaded 0010 - Sync Pulse is incorrect. Causes the analog output to mute. 0011 - SCLK is outside the allowable range. Analog output mutes. Ver3-Ver0 CS4216 Version Number 0000 = "A" (see Appendix A) 0001 = "B", "C", . . . (This data sheet) Sub-frame Bits 33 to 48 Right ADC Audio Data, MSB first, 2’s complement coded. Sub-frame Bits 49 to 60 These bits are reserved, and can be 0 or 1. Sub-frame Bits 61 to 64 61 DI1 DI1-DI4 62 DI2 63 DI3 64 DI4 LCL Left ADC clipping indicator 0 - Normal 1 - Clipping RCL Right ADC clipping indicator 0 - Normal 1 - Clipping RESERVED bits can be 0 or 1 These bits follow the state of the Digital Input pins. In SM3 DI3 and DI4 are used and unavailable. In SM4 DI2, DI3, & DI4 are not available as input bits. Sub-frame Sub-frame Word A 32 33 16 17 21 22 23 24 25 28 29 01 Word B 52 53 55 56 57 60 61 D I1 D I2 64 XX M SB LSB LSB ADC - Left Word . XXXX0 Error ADC - Right Word XXXX00010000 SM1 and SM2 MSB ADC - Left Word LSB XXXX0 Error ADC - Right Word LSB 3 0 03 Version MSB ADV LCL RCL XXXX00010000 SM3 Figure 6. Serial Data Output Format - SM1, SM2, and SM3. DS83F2 13 D I1 D I2 D I3 D I4 3 0 03 Version MSB ADV LC L RCL 48 CS4216 frequency. SM2 is similar to SM1 except that CLKIN is not used and SCLK becomes the master clock and is fixed at 256×Fs. SM3 was designed as an easy interface to general purpose DSPs and provides extra features such as one more bit of attenuation, a master mode, and variable frame sizes. SM4 is similar to SM3 but splits the audio data from the control data thereby reducing the audio serial bus bandwidth by half. The control data is transmitted through a control serial port in SM4. Table 1 lists the serial port modes available, along with some of the differences between modes. The first three columns in Table 1 select the serial mode. The "SCLK Bit Center" column indicates whether SCLK is rising or falling in the center of a bit period. The "Sub-frame Width" column indicates how many bits are in an individual codec’s sub-frame. SM4 differs from all other modes by separating the control data from the audio data. In both SM1 and SM2, there are 256 bits per frame which allows up to four codecs to occupy the same bus. In SM3 and SM4, the number of bits per frame is programmable. In SM1 and SM2, SCLK and SSYNC must be generated externally; whereas, in SM3 and SM4 the CS4216 can optionally generate those signals. In all modes, SCLK and SSYNC must be synchronous to the master clock. The last column in Table 1 lists the master frequency used by the codec. In SM1, the master frequency, input on CLKIN, is 512 times the highest sample frequency available. In SM2, the master frequency is fixed at 256 times the sample frequency and, in this mode, SCLK is the master clock. In SM3, the master frequency is 256 times the highest frequency available and is input on CLKIN or SCLK, based on the submode used. In SM4, the master frequency is also 256 times the highest frequency available and is input on CLKIN. SERIAL MODE 1, SM1 Serial Mode 1 is a slave mode selected by setting SMODE3 = SMODE2 = SMODE1 = 0. SCLK and SYNC must be synchronous the master clock. SM1 uses a two bit wide (minimum) frame sync with an optional word sync. In this mode, SSYNC low for one SCLK period followed by SSYNC high for a minimum of two SCLK periods indicates the beginning of a frame. The first bit of the frame starts with the rising edge of SSYNC. An optional word sync, being one SCLK period high, may be used to indicate the start of a new 32-bit word. Figures 5 and 6 contain the serial data format for SM1. In this serial mode, the ratio of two clocks are used to select sample frequency. These are the master clock CLKIN and the serial clock SCLK. CLKIN should be set to 512×Fsmax, where Fsmax is the maximum required sample rate. SCLK must be externally set to a value of CLKIN/N, such that SCLK equals 256 times the desired sample rate. The codec uses the ratio between CLKIN and SCLK to set the internal sample frequency and causes the CS4216 to go into soft power down mode if the SCLK frequency drops to 0 0 1 0 0 0 0 0 TS1 DIP SWITCHES CS4216 Multifunction Pins MF1 DO4 DO4 BPF2 DIV1 CDOUT CDOUT CDOUT CDOUT MF2 DO3 DO3 BPF1 DIV2 CDIN CDIN CDIN CDIN MF3 DI3 DI3 DI3 DIV3 CCLK CCLK CCLK CCLK MF4 DI4 DI4 MA=0 MA=1 CCS CCS CCS CCS MF5 DO2 DO2 DO2 DO2 INT INT INT INT MF6 DI2 DI2 DI2 DI2 BPF2=0 BPF2=1 DIV1 DIV1 MF7 TS1 TS1 TS1 TS1 BPF1 TS1 DIV2 DIV2 MF8 TS2 TS2 TS2 BPF1 TS1 TS2 DIV3 DIV3 Table 4. CS4216 Pin Decode 42 DS83DB4 CDB4216 VD VD (+5V) D3 P6KE DGND Ferrite Bead L1 + 47 uF C7 0.1 uF C28 R26 2Ω VA VA (+5V) + D4 P6KE AGND + 10 uF C36 4 21 0.1 uF C35 24 VA LOUT 16 C32 + 1 uF NPO R28 47.5 k 0.1 uF C30 47 uF C29 + 1 uF C3 0.1 uF C5 0.1 uF C6 + 1 uF C4 VD REFBYP Microphone Input Buffer See Figure 3 28 26 20 27 25 3 41 32 See Figure 5 29 31 30 LIN2 RIN2 REFBUF LIN1 RIN1 604 C31 2200 pF C33 R27 LOUT Line Input Buffer See Figure 2 See Figure 7, 8 CS4216 U1 2200 pF ROUT 15 R29 604 NPO + C34 R30 47.5 k ROUT 1 uF CLKIN SMODE3 SMODE2 SMODE1 MF7 MF8 DGND 5 REFGND 22 RESET 2 See Figure 6 MF4 MF3 MF6 36 35 34 See Figure 5 AGND 23 Figure 1. CS4216 and Power Supplies DS83DB4 43 CDB4216 setting the MF8 pin high. Since the part is in slave mode, the sampling rate must be set by the ratio between CLKIN and SCLK. Assuming that CLKIN has a frequency of 11.2896MHz, this ratio must be eight to give a sampling rate of 22.05kHz (refer to the CS4216 data sheet). In all slave modes, SSYNC and SCLK must be synchronous to the master clock. LOOPBACK MODE The CDB4216/8 may be configured in a simple loop back mode that only requires a power source to operate. No controller of any type is necessary. This mode allows a quick and simple verification of codec operation by sampling the LIN1 and RIN1 inputs, then looping the digital data back to the LOUT and ROUT line outputs. Set SPF2=SPF1=MA=1 and shunt SDOUT to SDIN on stake header J15. This mode uses SM4 with all control settings set to zero, so no gain or attenuation is available. POWER SUPPLY CIRCUITRY Figure 1 illustrates a portion of the CDB4216/8 schematic and includes the CS4216/8 along with power supply decoupling and circuitry. The evaluation board supports various power supply arrangements. The factory configuration powers the analog portion of the CS4216/8, along with input buffers, from the VA binding post, which needs a clean +5 Volts. The digital portions of the CS4216/8 are factory configured to obtain power through a 2Ω resistor from the VA supply. The digital buffers and PLDs obtain power from the VD binding post, which also needs +5 Volts. Although binding posts exist for both digital and analog grounds, only one needs to be connected if a single supply is used for both VA and VD. Note that the CS4216/8 is entirely on the analog ground plane, close to the ground plane split as required by the CS4216/8 Data Sheets. Also note that the two ground planes are connected near the two ground binding posts. 44 Space for a ferrite bead, L1, is provided so that the board may be modified to power the codec from the digital supply. Selection of L1 will depend on the noise characteristics of the digital supply used. ANALOG INPUTS The analog inputs consist of a pair of line level inputs and a pair of 1/4" mono jacks for two microphones. BNC-to-phono adapters are included to allow testing of the line inputs using coax or standard audio cables. The line-level inputs are connected to the CS4216/8’s LIN1 and RIN1 pins. As shown in Figure 2, the line-level inputs go through a buffer set to a gain of 0.5 which allows input signals of up to 2 VRMS. When placed in serial mode 4 with loop back, the LIN1 and RIN1 inputs are used for analog inputs. The microphone inputs are connected to the CS4216/8’s LIN2 and RIN2 pins. The two microphone inputs are single-ended and are designed to work with both condenser and dynamic microphones. The microphone input buffer, shown in Figure 3, has a gain of 23 dB thereby defining a full-scale input voltage to the microphone jacks of 71 mVRMS. Another 22 dB of programmable gain is available on the CS4216/8 to amplify smaller microphone signals. An analog patch area with analog power and ground, included on the CDB4216/8, provides space to develop other input buffer circuits. Space for headers are included, J19 and J20, to connect to the LIN2 and RIN2 inputs. To use these headers, the microphone traces must be cut. ANALOG OUTPUTS The CS4216/8 drives the line outputs into an RC filter and then to a pair of BNCs labeled DS83DB4 CDB4216 R20 1k C23 + 10 uF VA 1 uF + RIN2 C21 2 3 R21 13 k C16 1000 pF NPO C26 0.1 uF 1 U2 MC33178 J20 RMIC R24 150 C17 0.01 uF NPO C19 0.47 uF CS4216 26 RIN2 8 4 R18 47.5 k 20 + 1 uF J19 LMIC R25 150 C18 0.01 uF NPO C37 0.1 uF C20 0.47 uF 28 REFBUF LIN2 (Mono) C22 + 1 uF R22 C24 + 10 uF 1k R19 C25 47.5 k 5 7 6 C15 LIN2 1000 pF NPO R23 13 k Figure 2. Microphone Input Buffer C8 R12 C10 + 20 k 56 pF NPO VA 7 R16 150 R11 5k R17 150 C9 0.1 uF LIN1 10 k 6_ 8 5+ 4 CS4216 1 uF R14 C12 0.47 uF C11 + U2 LT1013 3 + 2_ R13 10 k C27 56 pF NPO 1 27 LIN1 C13 0.01 uF NPO 20 REFBUF C37 0.1 uF C14 0.01 uF NPO 25 RIN1 20 k RIN1 (Mono) 1 uF R15 Figure 3. Line Input Buffer DS83DB4 45 CDB4216 LOUT and ROUT. As with the line inputs, BNCto-phono adapters are provided for flexibility. The line outputs can drive an impedance of 10 kΩ or more, which is the typical input impedance of most audio gear. AUDIO PORT HEADER The CDB4216/8 is primarily designed to evaluate the CS4216/8 in single chip mode, i.e. only one codec on the serial bus. This is the factory default state of the CDB4216/8. The audio port header J15 provides all buffered signals necessary to connect to the serial port of a DSP or other controller (see Figure 4). SDOUU6 74HC243 SSYNC SSYNC SCLK 1 44 R10 10 R39 J17 20 SDOUT SDIN 43 42 J16 11 9 R41 20k MF1b 5 MF2 MF2 39 3 17 J18 38 6 14 B U MF5 VD R46 13 12 U7 DO1 37 4 16 74HC541 8 R42 47.5k 28k PDN R9 TUB can provide an unbuffered version of SDOUT which can be used when connecting multiple codecs on the same bus. The default configuration does not connect SDOUTUB which may be connected to the SDOUT of the CS4216/8 through J17 jumper. The eval board supports both master and slave sub-modes. In master sub-modes, SSYNC and SCLK are output (and buffered) from the CS4216/8. In slave sub-modes, SSYNC and SCLK must be provided externally and must be synchronous to the master clock CLKIN. R44 10 OEA 8 9 10 11 OEB B3 B2 B1 B0 A3 A2 A1 A0 1 13 6 5 4 3 CFSIN SCLK CS4216 R31 20 R32 20 J15 SDOUTUB SDOUT SDIN SCLK SSYNC J13 DI4 DI3 DI2 DI1 DO4 DO3 7 13 R40 20 DI1 33 MF1a 18 2 DI4 R49 DI1 DI3 DI2 MF1 40 15 13 4 9 100 8 VD R38 806 D2 DO1 Q1 1 19 U7 OE1 DO2 DO1 MF5 PDN 237k OE2 74HC541 Figure 4. Serial Port Headers 46 DS83DB4 SWX DIV1 DIV2 DIV3 TS1 TS2 BPF1 BPF2 MA SPF1 SPF2 LB DS83DB4 VD C39 12 SW3 20 20 14 13 24 24 R53 27k R54 27k 0.1uF R47 27k VD 0.1uF 1 C40 VD MF5 PDN RESET J14 U10 PALCE22V10Z 1 2 3 4 5 MF1b RESET PDN INT CCS CCLK CDIN CDOUT 13 1 19 2 18 U9 3 17 PALCE16V8Z 4 16 5 15 6 14 7 13 8 12 9 10 SWX SWY 21 19 18 17 16 MF1a MF2 MF4 MF3 MF6 6 7 8 9 10 11 12 R45 10k 1 DI4 DI3 DI2 DI1 27k VD 2 3 4 5 6 7 8 9 10 R33 47k 1 R48 6 5 4 3 2 1 R37 47k R36 47k R35 47k 16 14 R49 100 3 23456 VD 1 SMODE1 MF8 MF7 SMODE2 SMODE3 CFSIN 98765432 VD R34 10k 1 CDB4216 Figure 5. DIP Switch Decode + Digital Header 47 CDB4216 CONTROL PORT HEADER The Control Port Header J14 contains the control port pins, available only in SM4, and the PDN and RESET pins. Serial mode 4, SM4, splits the serial data to the codec into two separate serial ports, the audio port and the control port. The control port pins are available on this header. Since CDOUT is buffered and always driven, it cannot be used on a shared serial port. Although the INT pin on the codec is open drain, the default factory configuration for the eval board is an on-board pull-up resistor and a buffer. Therefore, the INT header pin cannot share an interrupt pin on a processor since it is buffered and will always be driven. By cutting a trace in the J18 jumper, the unbuffered INT signal, labeled U, can be supplied to the header. When using the control port, the LB VD R1 CS4216 RESET 2 8 VD 9 10 11 U11 74HC132 D1 1N4148 47.5k 12 13 R2 47.5k R3 RESET 100 R4 100 + C1 1 uF SW1A RESET is also buffered and controls the RESET pin on the codec (see Figure 6). RESET has a pull-up resistor on the board defining the default state as not reset or active. This pin only needs to be controlled when the reset feature on the codec is needed. Since the codec requires a reset at power up, a power-up reset circuit is included on the board. A reset switch is also included to allow resetting the device without having to remove the power supply. The power-up reset plus switch are logically ORed with the RESET pin on header J14. DIGITAL I/O HEADER The Digital I/O Header, J13 shown in Figure 4, contains the four digital inputs, DI1-DI4, and the four digital outputs, DO1-DO4. Note that all digital I/O except DI1 and DO1 are multifunction pins and may not be available in a particular mode. Since DO1 is always a digital output, an LED is connected to DO1 providing a visual indication that software is writing this bit correctly. When the LED is on, DO1 is high. In SM1 and SM2 all four digital inputs and outputs are available. In SM3 master sub-modes, only the first two inputs and outputs are functional. In SM3 slave sub-modes, three inputs and two outputs are functional. In SM4 only DO1 and DI1 are functional. See the CS4216/8 Data Sheet for more details. CLOCKS The CDB4216/8 provides an on-board default clock oscillator of 11.2896 MHz (see Figure 7). This allows all 44.1 kHz and derivative sample frequencies in SM3 Master sub-mode, SM3 Slave sub-mode, SM4, and the I2S mode. The CS4218 SM3-MM and SM3-MS modes require a master clock of 16xFsmax. If using SM1, a master clock with a frequency that is 512xFsmax must be supplied. SM2 uses SCLK as the master clock ant it must be 256xFsmax. A CLKIN BNC allows the eval board to be driven from an exterDS83DB4 Figure 6. Reset Circuit switch must be off or the control serial port will be blocked. PDN and RESET PDN is buffered and controls the PDN pin on the CS4216. PDN contains an on-board pull-up resistor defining the default state as powered. This pin only needs to be controlled when the power down feature is used. 48 CDB4216 VD C2 0.1 uF 14 7 VD 11.2896 MHz 8 Oscillator Module R5 47.5k J1 INT EXT 1 2 CS4216 3 4 5 6 R8 10 3 CLKIN CLKIN R7 5k U11B R6 U11A 74HC132 47.5k Figure 7. Default Clock Circuit nal source. To select the CLKIN BNC, the J1 jumper must be placed in the EXT position. When the J1 jumper is in the INT position, the on-board oscillator is used as the master clock. Both clock sources are buffered to guarantee a clean signal and proper clock levels to the codec. If sample frequencies other than the ones provided are needed, the oscillator can be replaced with the proper frequency oscillator. The board accepts crystals and provides the socket Y1 (refer to Figure 8). When using a crystal, U8 must contain an HCU04 unbuffered CMOS inverter. The U8 socket is designed to accept either the HCU04 or a crystal oscillator, and can alternate between the two. LAYOUT ISSUES Figure 11 contains the silk screen, Figure 12 contains the component-side copper layer, and Figure 13 contains the solder-side copper layer of the CDB4216/8 evaluation board. These plots are included to provide an example of how to correctly layout a PCB for the codec. Grounding and Power Y1 C44 33 pF VD 13 C2 0.1uF 14 7 1 U8 74HCUO4 2 3 4 5 6 R55 10M 12 11 10 9 8 CLKIN-J1 C43 33 pF Figure 8. Optional Clock Circuit DS83DB4 49 CDB4216 N otice in Figure 12 and Figure 13 how the ground plane split is positioned. The split is next to the part - NOT UNDER IT. The AGND and DGND pins are connected to the ground plane fill inside the codec pad layout on the component-side layer. This is recommended because AGND and DGND are connected on the codec die and must have a zero impedance between them. Notice how each ground connection has at least four points in thermal relief. The main board grounds at the terminal connections have eight points in thermal relief. This helps minimize the impedance to the main ground terminal from any particular ground pin, reducing the chance of noise coupling. Another important design consideration is the ground plane fill between traces on both layers, which minimizes coupling of radiated energy. Ground fill on the digital side of the board helps reduce the amount of noisy digital energy radiated to the sensitive analog side and to a host system. Ground fill on the analog side helps reduce the amount of radiated digital energy that is coupled into the analog circuitry. All ground plane fills must be connected to their respective grounds - floating ground fill is worse than no fill. All power and ground traces are as thick as the surface mount pads they connect. Thick traces minimize impedance, thereby reducing the chance of noise coupling. Decoupling Notice how the decoupling capacitors are placed as close as possible to the codec. The 0.1µF capacitors are placed closer than the 10µF or 1µF capacitors. This reduces lead inductance at high frequencies and allows the smaller valued capacitors to attenuate unwanted signals more effectively. 50 DS83DB4 Sockets The CDB4216/8 was designed to accommodate either the 44-pin PLCC package or the 44-pin TQFP package. Each evaluation board is shipped with a PLCC codec loaded into a surface mount socket. Notice how the socket pads match the footprint of the PLCC package. Using this socket in a design allows for testing with the socket mounted, and the option to surface mount the codec directly for cost reduction during board production. CDB4216 ;PALASM Design Description ;---------------------------------- Declaration Segment -----------TITLE CDB4216 PATTERN 4216S_B REVISION 4.0B AUTHOR C. Sanchez, M. Jordan COMPANY Crystal Semiconductor DATE 5/28/93 CHIP _4216s_b PALCE16V8 ;---------------------------------- PIN Declarations --------------PIN 1 /SPF2 COMBINATORIAL ; INPUT PIN 2 /SPF1 COMBINATORIAL ; INPUT PIN 3 /MA COMBINATORIAL ; INPUT PIN 4 /BPF2 COMBINATORIAL ; INPUT PIN 5 /BPF1 COMBINATORIAL ; INPUT PIN 6 /TS2 COMBINATORIAL ; INPUT PIN 7 /TS1 COMBINATORIAL ; INPUT PIN 8 /DIV3 COMBINATORIAL ; INPUT PIN 9 /DIV2 COMBINATORIAL ; INPUT PIN 10 GND PIN 11 NC PIN 12 /CFSIN COMBINATORIAL ; OUTPUT PIN 13 NC PIN 14 NC PIN 15 SMODE3 COMBINATORIAL ; OUTPUT PIN 16 SMODE2 COMBINATORIAL ; OUTPUT PIN 17 MF7 COMBINATORIAL ; OUTPUT PIN 18 MF8 COMBINATORIAL ; OUTPUT PIN 19 SMODE1 COMBINATORIAL ; OUTPUT PIN 20 VCC ;----------------------------------- Boolean Equation Segment -----EQUATIONS /CFSIN = SPF2 * MA SMODE3 = SPF2 * SPF1 SMODE2 = SPF2 * /SPF1 + SPF2 * SPF1 * + SPF2 * SPF1 * + SPF2 * SPF1 * + SPF2 * SPF1 * + SPF2 * SPF1 * /MA MA * BPF1 * TS1 MA * BPF1 * TS2 MA * BPF2 * TS1 MA * BPF2 * TS2 SMODE1 = /SPF2 * SPF1 + SPF2 * SPF1 * MA * BPF1 + SPF2 * SPF1 * MA * BPF2 MF8 = /SPF2 * TS2 + SPF2 * /SPF1 * MA * BPF2 + SPF2 * /SPF1 * MA * BPF1 + SPF2 * /SPF1 * /MA * BPF2 * TS2 + SPF2 * SPF1 * /MA * /BPF2 * BPF1 * TS1 Figure 9. PALCE16V8H PAL Equations. DS83DB4 51 CDB4216 + SPF2 * SPF1 * /MA * /BPF2 * BPF1 * TS2 + SPF2 * SPF1 * /MA * BPF2 * TS2 + SPF2 * SPF1 * MA * DIV3 MF7 = /SPF2 * TS1 + SPF2 * /SPF1 * /MA * /BPF2 * BPF1 * TS1 + SPF2 * /SPF1 * /MA * /BPF2 * BPF1 * TS2 + SPF2 * /SPF1 * /MA * BPF2 * TS1 + SPF2 * /SPF1 * MA * TS1 + SPF2 * SPF1 * /MA * /BPF2 * BPF1 + SPF2 * SPF1 * /MA * BPF2 * TS1 + SPF2 * SPF1 * MA * DIV2 Figure 9. Continued. 52 DS83DB4 CDB4216 ;PALASM Design Description ;---------------------------------- Declaration Segment -----------TITLE CDB4216 PATTERN 4216L_B REVISION 2.0B AUTHOR C. Sanchez COMPANY Crystal Semiconductor DATE 4/27/93 CHIP _4216l_b PALCE22V10Z ;---------------------------------- PIN Declarations --------------PIN 1 /SPF2 COMBINATORIAL ; INPUT PIN 2 /SPF1 COMBINATORIAL ; INPUT PIN 3 /MA COMBINATORIAL ; INPUT PIN 4 /BPF2 COMBINATORIAL ; INPUT PIN 5 /BPF1 COMBINATORIAL ; INPUT PIN 6 /DIV3 COMBINATORIAL ; INPUT PIN 7 /DIV2 COMBINATORIAL ; INPUT PIN 8 /DIV1 COMBINATORIAL ; INPUT PIN 9 DI4 COMBINATORIAL ; INPUT PIN 10 DI3 COMBINATORIAL ; INPUT PIN 11 DI2 COMBINATORIAL ; INPUT PIN 12 GND PIN 13 CDIN COMBINATORIAL ; INPUT PIN 14 CCLK COMBINATORIAL ; INPUT PIN 15 NC PIN 16 MF6 COMBINATORIAL ; OUTPUT PIN 17 MF3 COMBINATORIAL ; OUTPUT PIN 18 MF4 COMBINATORIAL ; OUTPUT PIN 19 MF2 COMBINATORIAL ; OUTPUT PIN 20 /CCS COMBINATORIAL ; INPUT PIN 21 MF1 COMBINATORIAL ; OUTPUT PIN 22 NC PIN 23 NC PIN 24 VCC ;----------------------------------- Boolean Equation Segment -----EQUATIONS MF1 = SPF2 * /SPF1 * MA * DIV1 + SPF2 * /SPF1 * /MA * BPF2 MF1.TRST = SPF2 * /SPF1 MF2 = SPF2 * /SPF1 * MA * DIV2 + SPF2 * /SPF1 * /MA * BPF1 + SPF2 * SPF1 * CDIN MF2.TRST = SPF2 MF3 = /SPF2 * DI3 + SPF2 * /SPF1 * /MA * DI3 + SPF2 * /SPF1 * MA * DIV3 + SPF2 * SPF1 * CCLK MF4 = /SPF2 * DI4 Figure 10. PALCE22V10Z PAL Equations. DS83DB4 53 CDB4216 + SPF2 * /SPF1 * MA + SPF2 * SPF1 * /CCS MF6 = /SPF2 * DI2 + /SPF1 * DI2 + SPF2 * SPF1 * MA * DIV1 + SPF2 * SPF1 * /MA * BPF2 Figure 10. Continued. 54 DS83DB4 44 pin PLCC NO. OF TERMINALS E1 E MILLIMETERS INCHES DIM MIN NOM MAX 4.20 2.29 0.33 4.45 2.79 0.41 MIN NOM MAX A A1 B 4.57 0.165 0.175 0.180 3.04 0.090 0.110 0.120 0.53 0.013 0.016 0.021 D/E 17.40 17.53 17.65 0.685 0.690 0.695 D1 D D1/E1 16.51 16.59 16.66 0.650 0.653 0.656 D2/E2 14.99 15.50 16.00 0.590 0.610 0.630 e 1.19 1.27 1.35 0.047 0.050 0.053 B e A1 D2/E2 A 44 PIN TQFP D D1 DIM A A1 A2 b E1 E 44 LEAD TQFP MILLIMETERS MIN NOM MAX 1.60 0.05 1.35 0.30 0.09 1.40 0.37 0.145 0.15 1.45 0.002 0.053 0.014 0.004 0.055 0.016 0.006 MIN INCHES NOM MAX 0.063 0.006 0.057 0.018 0.008 0.45 0.20 12.25 10.10 c D/E 11.75 D1/E1 9.90 e 0.70 0.45 0° 12.0 10.0 0.80 0.60 3.5° 0.462 0.390 0.026 0.018 0.472 0.394 0.031 0.024 3.5° 0.482 0.398 0.036 0.030 7° 0.004 0.90 0.75 7° ∝ ccc 1 L 0° 0.10 ∝ c e L A2 A b A1 ccc • Notes • Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation