CS4221-KSZR

CS4220 CS4221 24-Bit Stereo Audio Codec with 3V Interface Features Description l 100 The CS4220/1 is a highly integrated, high performance, 24-bit, audio codec providing stereo analog-to-digital and stereo digital-to-analog converters using delta-sigma conversion techniques. The device operates from a single +5 V power supply, and features low power consumption. Selectable de-emphasis filter for 32, 44.1, and 48 kHz sample rates is also included. dB Dynamic Range A/D Converters l 100 dB Dynamic Range D/A Converters l 105 dB DAC Signal-to-Noise Ratio (EIAJ) l Analog Volume Control (CS4221 only) l Differential Inputs / Outputs l On-chip Anti-aliasing and Output Smoothing Filters l De-emphasis for 32, 44.1 and 48 kHz l Supports Master and Slave Modes l Single +5 V power supply l On-Chip Crystal Oscillator l 3 - 5 V Digital Interface The CS4221 also includes an analog volume control capable of 113.5 dB attenuation in 0.5 dB steps. The analog volume control architecture preserves dynamic range during attenuation. Volume control changes are implemented using a “soft” ramping or zero crossing technique. Applications include digital effects processors, DAT, and multitrack recorders. ORDERING INFORMATION CS4220-KS -10 to +70 °C CS4221-KS -10 to +70 °C CDB4220/1 28-pin SSOP 28-pin SSOP Evaluation Board I (DIF1) (DIF0) (DEM0) (DEM1) SCL/CCLK SDA/CDIN AD0/CS I 2 C/SPI SDOUT VD VA Voltage Reference Left DAC Right DAC Volume Control * Volume Control * Analog Low Pass and Output Stage Digital Filters with De-Emphasis Digital Filters SDIN Serial Audio Data Interface SCLK MCLK Control Port RST LRCK VL AOUTL+ AOUTL- AOUTR+ AOUTR- Left ADC AINLAINL+ Right ADC AINRAINR+ Clock OSC XTI XTO DGND ( ) = CS4220 Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com AGND * = CS4221 This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Logic, Inc. 1999 (All Rights Reserved) APR ‘00 DS284PP3 1 CS4220 CS4221 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 ANALOG CHARACTERISTICS ............................................................................................... 4 ABSOLUTE MAXIMUM RATINGS .......................................................................................... 6 RECOMMENDED OPERATING CONDITIONS ...................................................................... 6 SWITCHING CHARACTERISTICS ......................................................................................... 7 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4221) .................... 8 SWITCHING CHARACTERISTICS - CONTROL PORT - I2C MODE (CS4221) ..................... 9 2. TYPICAL CONNECTION DIAGRAM — CS4220 ................................................................... 10 3. TYPICAL CONNECTION DIAGRAM — CS4221 ................................................................... 11 4. REGISTER QUICK REFERENCE - CS4221 .......................................................................... 12 5. REGISTER DESCRIPTIONS - CS4221 .................................................................................. 13 5.1 ADC Control (address 01h) .............................................................................................. 13 5.1.1 Power Down ADC (PDN) ....................................................................................... 13 5.1.2 Left and Right channel High Pass Filter Defeat (HPDR-HPDL) ............................. 13 5.1.3 Left and Right Channel ADC Muting (ADMR-ADML) ............................................. 13 5.1.4 Calibration Control (CAL) ....................................................................................... 13 5.1.5 Calibration Status (CALP) (Read Only) .................................................................. 13 5.1.6 Clocking Error (CLKE) (Read Only) ....................................................................... 14 5.2 DAC Control (address 02h) .............................................................................................. 14 5.2.1 Mute on Consecutive Zeros (MUTC) ...................................................................... 14 5.2.2 Mute Control (MUTR-MUTL) .................................................................................. 14 5.2.3 Soft RAMP Control (SOFT) .................................................................................... 14 5.2.4 Soft RAMP Step Rate (RMP) ................................................................................. 15 5.3 Left Channel Output Attenuator Level (address 03h) ...................................................... 15 5.4 Right Channel Output Attenuator Level (address 04h) ................................................... 15 5.4.1 Attenuation level (ATT7-ATT0) ............................................................................... 15 5.5 DSP Port Mode (address 05h) ......................................................................................... 16 5.5.1 De-emphasis Control (DEM) .................................................................................. 16 5.5.2 Serial Input/Output Data SCLK Polarity Select (DSCK) ......................................... 16 5.5.3 Serial Data Output Format (DOF) .......................................................................... 16 5.5.4 Serial Data Input Format (DIF) ............................................................................... 16 5.6 Converter Status Report (Read Only) (address 06h) ....................................................... 17 5.6.1 Left and Right Channel Acceptance Bit (ACCR-ACCL) ......................................... 17 5.6.2 Left and Right Channel ADC Output Level (LVR and LVL) .................................... 17 5.7 Master Clock Control (address 07h) ................................................................................ 17 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ I2C is a registered trademark of Philips Semiconductor. SPI is a registered trademark of International Business Machines Corporation. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS284PP3 CS4220 CS4221 5.7.1 Master Clock Control (MCK) .................................................................................. 17 6. PIN DESCRIPTIONS — CS4220 ............................................................................................ 18 7. PIN DESCRIPTIONS — CS4221 ............................................................................................ 20 8. APPLICATIONS ..................................................................................................................... 22 8.1 Overview .......................................................................................................................... 22 8.2 Grounding and Power Supply Decoupling ....................................................................... 22 8.3 High Pass Filter ............................................................................................................... 22 8.4 Analog Outputs ................................................................................................................ 22 8.5 Master vs. Slave Mode .................................................................................................... 22 8.6 De-emphasis ................................................................................................................... 22 8.7 Power-up / Reset / Power Down Calibration ................................................................... 22 8.8 Control Port Interface (CS4221 only) .............................................................................. 23 8.8.1 SPI Mode ............................................................................................................ 23 8.8.2 I2C Mode ............................................................................................................. 23 8.9 Memory Address Pointer (MAP) ...................................................................................... 24 8.9.1 Auto-Increment Control (INCR) .............................................................................. 24 8.9.2 Register Pointer (MAP) .......................................................................................... 24 9. ADC/DAC FILTER RESPONSE ............................................................................................. 28 10. PARAMETER DEFINITIONS ................................................................................................ 29 11. PACKAGE DIMENSIONS .................................................................................................... 30 LIST OF FIGURES Figure 1. Serial Audio Port Data I/O Timing .................................................................................. 7 Figure 2. SPI Control Port Timing ................................................................................................. 8 Figure 3. I2C Control Port Timing .................................................................................................. 9 Figure 4. CS4220 Recommended Connection Diagram ............................................................. 10 Figure 5. CS4221 Recommended Connection Diagram ............................................................. 11 Figure 6. Control Port Timing, SPI mode .................................................................................... 24 Figure 7. Control Port Timing, I2C mode ..................................................................................... 24 Figure 8. Serial Audio Format 0 (I2S) ......................................................................................... 25 Figure 9. Serial Audio Format 1 .................................................................................................. 25 Figure 10. Serial Audio Format 2 ................................................................................................ 25 Figure 11. Serial Audio Format 3 ................................................................................................ 26 Figure 12. Optional Input Buffer .................................................................................................. 26 Figure 13. Single-ended Input Application .................................................................................. 26 Figure 14. 2- and 3-Pole Butterworth Filters ............................................................................... 27 Figure 15. Hybrid Digital/Analog Attenuation .............................................................................. 27 Figure 16. De-emphasis Curve ................................................................................................... 27 Figure 17. Hybrid Analog/Digital Attenuation .............................................................................. 27 Figure 18. ADC Filter Response ................................................................................................. 28 Figure 19. ADC Passband Ripple ............................................................................................... 28 Figure 20. ADC Transition Band ................................................................................................. 28 Figure 21. DAC Filter Response ................................................................................................. 28 Figure 22. DAC Passband Ripple ............................................................................................... 28 Figure 23. DAC Transition Band ................................................................................................. 28 LIST OF TABLES Table 1. Example Volume Settings ............................................................................................... 15 Table 2. Common Clock Frequencies........................................................................................... 18 Table 3. Digital Interface Format - DIF1 and DIF0 ....................................................................... 19 Table 4. De-emphasis Control ...................................................................................................... 19 Table 5. Common Clock Frequencies........................................................................................... 20 DS284PP3 3 CS4220 CS4221 1. CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (TA = 25° C; VA, VD = +5 V; Full Scale Input Sine wave, 997 Hz; Fs = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in Figures 4 and 5; SPI mode, Format 0, unless otherwise specified.) CS4220/1 - KS Parameter Symbol Min Typ Max Unit - - 24 Bits - 0.003 - % 95 92 100 97 - dB - -92 -87 dB - 90 - dB - - 0.1 dB - - 0 LSB 1.9 2.0 2.1 Vrms - 100 - ppm/°C 10 - - kΩ Input Capacitance - - 15 pF Common Mode Input Voltage A/D Decimation Filter Characteristics Passband Passband Ripple Stopband Stopband Attenuation Group Delay (Fs = Output Sample Rate) - 2.3 - V 0 - 21.8 kHz - - ±0.01 dB Analog Input Characteristics ADC Resolution Total Harmonic Distortion Dynamic Range THD A-weighted unweighted Total Harmonic Distortion + Noise (Note 1) THD+N Interchannel Isolation (1 kHz) Interchannel Gain Mismatch Offset Error with High Pass Filter Full Scale Input Voltage (Differential) Gain Drift Input Resistance (Note 2) (Note 2) 30 - 6114 kHz (Note 3) 80 - - dB tgd - 15/Fs - s ∆tgd - - 0 µs -3 dB (Note 2) - 3.7 20 - Hz (Note 2) - 10 - Degree - - 0 dB (Note 4) Group Delay Variation vs. Frequency High Pass Filter Characteristics Frequency Response -0.1 dB Phase Deviation @ 20 Hz Passband Ripple Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms). 2. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the 0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.625x Fs. 3. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency (n x 6.144 MHz ±21.8 kHz where n = 0,1,2,3...). 4. Group delay for Fs = 48 kHz, tgd = 15/48 kHz = 312 µs. 4 DS284PP3 CS4220 CS4221 ANALOG CHARACTERISTICS (CONTINUED) CS4220/1 - KS Parameter Symbol Min Typ Max Unit Analog Output Characteristics - Minimum Attenuation, 10 kΩ, 100 pF load; unless otherwise specified. DAC Resolution 24 Bits Signal-to-Noise, Idle-Channel Noise (CS4221 only) DAC 97 105 dB muted, A-weighted Dynamic Range DAC not muted, A-weighted 95 100 dB DAC not muted, unweighted 92 97 Total Harmonic Distortion THD 0.003 % Total Harmonic Distortion + Noise THD+N -92 -87 dB Interchannel Isolation (1 kHz) 90 dB Interchannel Gain Mismatch 0.1 dB Attenuation Step Size All Outputs 0.35 0.5 0.65 dB Programmable Output Attenuation Span 110 113.5 dB Differential Offset Voltage ±10 mV Common Mode Output Voltage 2.4 V Full Scale Output Voltage 1.8 1.9 2.0 Vrms Gain Drift 100 ppm/° C Out-of-Band Energy Fs/2 to 2 Fs -60 dBFs Analog Output Load Resistance 10 kΩ Capacitance 100 pF Combined Digital and Analog Filter Characteristics Frequency Response10 Hz to 20 kHz ±0.1 dB Deviation from Linear Phase ±0.5 Degree Passband: to 0.01 dB corner (Notes 5 and 6) 0 21.8 kHz Passband Ripple (Note 6) ±0.01 dB Stopband (Notes 5 and 6) 26.2 kHz Stopband Attenuation (Note 7) 70 dB Group Delay (Fs = Input Word Rate) tgd 16/Fs s Power Supply Power Supply Current VA 46 60 mA VD 9 20 VL 3 5 Total Power Down 0.4 Power Supply Rejection Ratio 1 kHz 65 dB Notes: 5. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 48 kHz, the 0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.5465x Fs. 6. Digital filter characteristics. 7. Measurement bandwidth is 10 Hz to 3 Fs. DS284PP3 5 CS4220 CS4221 DIGITAL CHARACTERISTICS (TA = 25° C; VA, VD = 4.75V - 5.25V) Parameter Symbol Min Max Unit VIH VIH 2.8 2.0 VL + 0.3 VL + 0.3 V V Low-level Input Voltage VIL -0.3 0.8 V High-level Output Voltage at IO = -2.0 mA VOH VL - 1.0 - V Low-level Output Voltage at IO = 2.0 mA VOL - 0.5 V Digital Inputs - 10 µA High Impedance Digital Outputs - 10 µA High-level Input Voltage VL = 5V VL = 3V Input Leakage Current Output Leakage Current ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to 0 V.) Parameter Power Supplies Symbol Min Max Unit VD VA -0.3 -0.3 6.0 6.0 V - ±10 mA Digital Analog Input Current (Note 8) Analog Input Voltage (Note 9) -0.7 VA + 0.7 V Digital Input Voltage (Note 9) -0.7 VD + 0.7 V Power Applied -55 +125 °C -65 +150 °C Ambient Temperature Storage Temperature RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V, all voltages with respect to 0 V.) Parameter Power Supplies Ambient Operating Temperature Digital Analog Digital | VA - VD | Symbol Min Typ Max Unit VD VA VL 4.75 4.75 2.7 - 5.0 5.0 5.0 - 5.25 5.25 5.25 0.4 V TA -10 25 70 °C Notes: 8. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 9. The maximum over or under voltage is limited by the input current. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 6 DS284PP3 CS4220 CS4221 SWITCHING CHARACTERISTICS (TA = 25° C; VA, VD = 4.75 V - 5.25 V; outputs loaded with 30 pF) Parameter Symbol Min Typ Max Unit Fs 4 - 50 kHz 1.024 - 26 MHz Audio ADC’s and DAC’s Sample Rate XTI Frequency XTI = 256, 384, or 512 Fs XTI Pulse Width High XTI = 512 Fs XTI = 384 Fs XTI = 256 Fs 13 21 31 - - ns XTI Pulse Width Low XTI = 512 Fs XTI = 384 Fs XTI = 256 Fs 13 21 31 - - ns - 500 - psRMS 10 - - ms ns XTI Jitter Tolerance RST Low Time (Note 10) SCLK falling edge to SDOUT output valid DSCK = 0 LRCK edge to MSB valid tdpd - - 1 ---------------------- + 20 (384) Fs tlrpd - - 45 ns SDIN setup time before SCLK rising edge DSCK = 0 tds 25 - - ns SDIN hold time after SCLK rising edge DSCK = 0 tdh 25 - - ns SCLK Period tsckw 1 ---------------------(128) Fs - - ns SCLK High Time tsckh 40 - - ns SCLK Low Time tsckl 40 - - ns SCLK rising to LRCK edge DSCK = 0 tlrckd 35 - - ns LRCK edge to SCLK rising DSCK = 0 tlrcks 40 - - ns Notes: 10. After powering up the CS4220/1, PDN should be held low for 10 ms to allow the power supply to settle. LRCK t lrckd t lrcks t sckh t sckl SCLK* t sckw SDIN t lrpd SDOUT t ds t dh t dpd MSB MSB-1 *SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1. Figure 1. Serial Audio Port Data I/O Timing DS284PP3 7 CS4220 CS4221 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4221) (TA = 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 30 pF) Parameter Symbol Min Max Unit fsck - 6 MHz SPI Mode (SPI/I2C = 0) CCLK Clock Frequency RST rising edge to CS falling (Note 11) tsrs 41 - µs CCLK edge to CS falling (Note 12) tspi 500 - ns CS High Time between transmissions tcsh 1.0 - µs CS falling to CCLK edge tcss 20 - ns CCLK Low Time tscl 66 - ns CCLK High Time tsch 66 - ns CDIN to CCLK rising setup time tdsu 40 - ns CCLK rising to DATA hold time (Note 13) tdh 15 - ns Rise time of CCLK and CDIN (Note 14) tr2 - 100 ns Fall time of CCLK and CDIN (Note 14) tf2 - 100 ns Notes: 11. Not tested but guaranteed by design. 12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 13. Data must be held for sufficient time to bridge the transition time of CCLK. 14. For FSCK < 1 MHz. RST t srs CS t spi t css t scl t sch t csh CCLK t r2 t f2 CDIN t dsu t dh Figure 2. SPI Control Port Timing 8 DS284PP3 CS4220 CS4221 SWITCHING CHARACTERISTICS - CONTROL PORT - I2C MODE (CS4221) (TA = 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 30 pF) Parameter Symbol Min Max Unit fscl - 100 kHz tirs 50 - µs Bus Free Time between transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low Time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup time for repeated Start Condition tsust 4.7 - µs thdd 0 - µs 2 ® I C Mode (SPI/I2C = 1) SCL Clock Frequency RST rising edge to Start (Note 15) SDA hold time for SCL falling (Note 16) tsud 250 - ns Rise time of SCL SDA setup time to SCL rising trc - 25 ns Fall time of SCL tfc - 25 ns Rise time of SDA trd - 1 µs tfd - 300 ns tsusp 4.7 - µs Fall time of SDA Setup time for Stop Condition Notes: 15. Not tested but guaranteed by design. 16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. RST t irs Stop Repeated Start Start t rd t fd Stop SDA t buf t t high t hdst t fc hdst t susp SCL t low t hdd t sud t sust t rc Figure 3. I2C Control Port Timing DS284PP3 9 CS4220 CS4221 2. TYPICAL CONNECTION DIAGRAM — CS4220 Ferrite Bead +5V Supply 2Ω +2.7 - 5V + 1 µF 150Ω 150Ω 150Ω 150Ω 0.1 µF 0.1 µF + 1 µF 21 VA 20 AINL+ 2.2 nF 19 17 6 VD VL AOUTL+ AOUTL- AINL- AOUTR+ AOUTRAINR+ DEM1 2.2 nF 16 DEM0 AINR- CS4220 XTI 0.1 µF + 1 µF 13 25 26 Analog Filter 24 23 Analog Filter 18 12 Digital Audio Source 3 40 pF Mode Selection 10 11 27 1 14 Rs = 500 Ω 15 28 * Required for Master Mode only XTO 2 40 pF DIF1 DIF0 RST NC SCLK NC LRCK NC SDIN NC SDOUT DGND 7 AGND 22 5 Rs 4 Rs 9 Rs 8 Rs External Clock Input Eliminate the crystal and capacitors when using an external clock input Audio DSP * 47 kΩ Figure 4. CS4220 Recommended Connection Diagram (Also see Recommended Layout Diagram) 10 DS284PP3 CS4220 CS4221 3. TYPICAL CONNECTION DIAGRAM — CS4221 Ferrite Bead +5V Supply 2Ω +2.7 - 5V + 1 µF 150Ω 150Ω 150Ω 150Ω 0.1 µF 0.1 µF + 1 µF 21 VA 20 6 VD VL AINL+ AOUTL+ AOUTL- 2.2 nF 19 17 AOUTR+ AOUTR- AINL- 0.1 µF + 1 µF 13 25 26 Analog Filter 24 23 Analog Filter AINR+ 2.2 nF 16 CS4221 AINR- XTI 3 40 pF Microcontroller 10 11 12 27 18 1 R s = 500 Ω * Required for Master Mode only 14 15 28 XTO SCL/CCLK SDA/CDIN AD0/CS RST I2C/SPI SCLK NC LRCK NC SDIN NC SDOUT NC AGND 22 DGND 2 40 pF 5 Rs 4 Rs 9 Rs 8 Rs External Clock Input Eliminate the crystal and capacitors when using an external clock input Audio DSP * 47 kΩ 7 Figure 5. CS4221 Recommended Connection Diagram (Also see Recommended Layout Diagram) DS284PP3 11 CS4220 CS4221 4. REGISTER QUICK REFERENCE - CS4221 Addr Function 0h Reserved default 1h ADC Control default 2h DAC Control default 3h-4h Output Attenuator Level default 5h DSP Port Mode default 6h Converter Status Report default 7h Master Clock Control default 12 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 PDN HPDR HPDL ADMR ADML CAL CALP CLKE 0 0 0 0 0 0 0 0 Reserved MUTC MUTR MUTL SOFT Reserved RMP1 RMP0 0 0 0 0 0 0 0 0 ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0 Reserved 0 ACCR 0 DEM1 0 ACCL 0 DEM0 0 LVR2 0 DSCK 0 LVR1 0 DOF1 0 LVR0 0 DOF0 0 LVL2 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 DIF1 0 LVL1 0 DIF0 0 LVL0 0 MCK1 0 MCK0 0 0 DS284PP3 CS4220 CS4221 5. REGISTER DESCRIPTIONS - CS4221 Note: All registers are read/write in I2C mode and write-only in SPI mode, unless otherwise noted. 5.1 ADC Control (address 01h) 7 PDN 0 5.1.1 6 HPDR 0 5 HPDL 0 4 ADMR 0 3 ADML 0 2 CAL 0 1 CALP 0 0 CLKE 0 POWER DOWN ADC (PDN) Default = 0 0 - Disabled 1 - Enabled Function: The ADC will enter a low-power state when this function is enabled. 5.1.2 LEFT AND RIGHT CHANNEL HIGH PASS FILTER DEFEAT (HPDR-HPDL) Default = 0 0 - Disabled 1 - Enabled Function: The internal high-pass filter is defeated when this function is enabled. Control of the internal highpass filter is independent for the left and right channel. 5.1.3 LEFT AND RIGHT CHANNEL ADC MUTING (ADMR-ADML) Default = 0 0 - Disabled 1 - Enabled Function: The output for the selected ADC channel will be muted when this function is enabled. 5.1.4 CALIBRATION CONTROL (CAL) Default = 0 0 - Disabled 1 - Enabled Function: The device will automatically perform an offset calibration when brought out of reset, which last approximately 50 ms. When this function is enabled, a rising edge on the reset line will initiate an offset calibration. 5.1.5 CALIBRATION STATUS (CALP) (READ ONLY) Default = 0 0 - Calibration done 1 - Calibration in progress DS284PP3 13 CS4220 CS4221 5.1.6 CLOCKING ERROR (CLKE) (READ ONLY) Default = 0 0 - No error 1 - Error 5.2 DAC Control (address 02h) 7 Reserved 0 5.2.1 6 MUTC 0 5 MUTR 0 4 MUTL 0 3 SOFT 0 2 Reserved 0 1 RMP1 0 0 RMP0 0 MUTE ON CONSECUTIVE ZEROS (MUTC) Default = 0 0 - Disabled 1 - Enabled Function: The DAC output will mute following the reception of 512 consecutive audio samples of static 0 or -1 when this function is enabled. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The muting function is affected, similar to volume control changes, by the SOFT bit in the DAC Control register. 5.2.2 MUTE CONTROL (MUTR-MUTL) Default = 0 0 - Disabled 1 - Enabled Function: The output for the selected DAC channel will be muted when this function is enabled. The muting function is affected, similar to volume control changes, by the SOFT bit in the DAC Control register. 5.2.3 SOFT RAMP CONTROL (SOFT) Default = 0 0 - Soft Ramp level changes 1 - Zero Cross level changes Function: Soft Ramp level changes will be implemented by incrementally ramping, in 0.5 dB steps, from the current level to the new level. The rate of change defaults to 0.5 dB per 8 left/right clock periods and is adjustable through the RMP bits in the DAC Control register. Zero Cross level changes will be implemented in a single step from the current level to the new level. The level change takes effect on a zero crossing to minimize audible artifacts. If the signal does not encounter a zero crossing, the level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate). Zero crossing is independently monitored and implemented for each channel. The ACCR and ACCL bits in the Converter Status Report register indicate when a level change has occurred for the right and left channel. 14 DS284PP3 CS4220 CS4221 5.2.4 SOFT RAMP STEP RATE (RMP) Default = 00 00 - 1 step per 8 LRCK’s 01 - 1 step per 4 LRCK’s 10 - 1 step per 16 LRCK’s 11 - 1 step per 32 LRCK’s Function: The rate of change for the Soft Ramp function is adjustable through the RMP bits. 5.3 Left Channel Output Attenuator Level (address 03h) 5.4 Right Channel Output Attenuator Level (address 04h) 7 ATT7 0 5.4.1 6 ATT6 0 5 ATT5 0 4 ATT4 0 3 ATT3 0 2 ATT2 0 1 ATT1 0 0 ATT0 0 ATTENUATION LEVEL (ATT7-ATT0) Default = 00h Function: The Output Attenuator Level registers allow for attenuation of the DAC outputs in 0.5 dB increments from 0 to 113.5 dB. Level changes are implemented with an analog volume control until the residual output noise is equal to the noise floor in the mute state. At this point, volume changes are performed digitally. This technique is superior to purely digital volume control because the noise is attenuated by the same amount as the signal, thus preserving dynamic range, see Figure 16. Volume changes are performed as dictated by the SOFT bit in the DAC Control register. ATT0 represents 0.5 dB of attenuation and settings greater than 227 (decimal value) will mute the selected DAC output. Binary Code Decimal Value Volume Setting 00000000 0 0 dB 11100011 227 -113.5 dB 11100100 228 Muted Table 1. Example Volume Settings DS284PP3 15 CS4220 CS4221 5.5 DSP Port Mode (address 05h) 7 6 DEM1 0 Reserved 0 5.5.1 5 DEM0 0 4 DSCK 0 3 DOF1 0 2 DOF0 0 1 DIF1 0 0 DIF0 0 DE-EMPHASIS CONTROL (DEM) Default = 00 00 - 44.1 kHz de-emphasis setting 01 - 48 kHz de-emphasis setting 10 - 32 kHz de-emphasis setting 11 - De-emphasis disabled Function: Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates, see Figure 15. 5.5.2 SERIAL INPUT/OUTPUT DATA SCLK POLARITY SELECT (DSCK) Default = 0 0 - Data valid on rising edge of SCLK 1 - Data valid on falling edge of SCLK Function: This function selects the polarity of the SCLK edge used to clock data in and out of the serial audio port. 5.5.3 SERIAL DATA OUTPUT FORMAT (DOF) Default = 00 00 - I2S compatible 01 - Left justified 10 - Right justified, 24-bit 11 - Right justified, 20-bit Function: The required relationship between the left/right clock, serial clock and output serial data is defined by the Serial Data Output Format, and the options are detailed in Figures 8-11. Note: If the format selected is Right-Justified, SCLK must be 64 Fs when operating in slave mode. 5.5.4 SERIAL DATA INPUT FORMAT (DIF) Default = 00 00 - I2S compatible 01 - Left justified 10 - Right justified, 24-bit 11- Right justified, 20-bit Function: The required relationship between the left/right clock, serial clock and input serial data is defined by the Serial Data Input Format, and the options are detailed in Figures 8-11. 16 DS284PP3 CS4220 CS4221 5.6 Converter Status Report (Read Only) (address 06h) 7 ACCR 0 5.6.1 6 ACCL 0 5 LVR2 0 4 LVR1 0 3 LVR0 0 2 LVL2 0 1 LVL2 0 0 LVL0 0 LEFT AND RIGHT CHANNEL ACCEPTANCE BIT (ACCR-ACCL) Default = 0 0 - Requested setting valid 1 - New setting loaded Function: The ACCR and ACCL bits indicate when a change in the Output Attenuator Level has occurred for the left and right channels, respectively. The value will be high when a new setting is loaded into the Output Attenuator Level registers. The value will return low when the requested attenuation setting has taken effect. 5.6.2 LEFT AND RIGHT CHANNEL ADC OUTPUT LEVEL (LVR AND LVL) Default = 000 000 - Normal output levels 001 - -6 dB level 010 - -5 dB level 011 - -4 dB level 100 - -3 dB level 101 - -2 dB level 110 - -1 dB level 111 - Clipping Function: The analog-to-digital converter is continually monitoring the peak digital signal output for both the left and right channel, prior to the digital limiter. The maximum output value is stored in the LVL and LVR bits. The LVL and LVR bits are ‘sticky’, so they are reset after each read is performed. 5.7 Master Clock Control (address 07h) 7 Reserved 0 5.7.1 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 MCK1 0 0 MCK0 0 MASTER CLOCK CONTROL (MCK) Default = 00 00 - XTI = 256 Fs for Master Mode 01 - XTI = 384 Fs for Master Mode 10 - XTI = 512 Fs for Master Mode Function: The MCK bits allow for control of the Master Clock, XTI, input frequency. Note: These bits are not valid when operating in slave mode. DS284PP3 17 CS4220 CS4221 6. PIN DESCRIPTIONS — CS4220 CS4220 NC XTI, XTO NC 1 28 NC XTO 2 27 RST XTI 3 26 AOUTL- LRCK 4 25 AOUTL+ SCLK 5 24 AOUTR+ VD 6 23 AOUTR- DGND 7 22 AGND SDOUT 8 21 VA SDIN 9 20 AINL+ DIF1 10 19 AINL- DIF0 11 18 DEM1 DEM0 12 17 AINR+ VL 13 16 AINR- NC 14 15 NC 1,14,15, 28 No Connect - These pins are not connected internally and should be tied to DGND to minimize noise coupling. 2,3 Crystal Connections (Input/Output) - Input and output connections for the crystal used to clock the CS4220. Alternatively, a clock may be input into XTI. This is the clock source for the delta-sigma modulator and digital filters. The frequency of this clock must be either 256x, 384x, or 512x Fs in Slave Mode and 256x in Master Mode. Fs (kHz) 32 44.1 48 256x 8.1920 11.2896 12.2880 XTI (MHz) 384x 12.2880 16.9344 18.4320 512x 16.3840 22.5792 24.5760 Table 2. Common Clock Frequencies LRCK 4 Left/Right Clock (Input) - Determines which channel is currently being input/output of the serial audio data pins SDIN/SDOUT. The frequency of the Left/Right clock must be equal to the input sample rate. Although the outputs for each ADC channel are transmitted at different times, Left/Right pairs represent simultaneously sampled analog inputs. The required relationship between the left/right clock, serial clock and serial data is defined by the DIF1-0 pins. The options are detailed in Figures 8 - 11. SCLK 5 Serial Data Clock (Input) - Clocks the individual bits of the serial data into the SDIN pin and out of the SDOUT pin. The required relationship between the left/right clock, serial clock and serial data is defined by the DIF1-0 pins. The options are detailed in Figures 8 - 11. VD 6 Digital Power (Input) - Positive power supply for the digital section. Typically 5.0 VDC. DGND 7 Digital Ground (Input) - Digital ground for the digital section. SDOUT 8 Serial Data Output (Output) - Two’s complement MSB-first serial data is output on this pin. The required relationship between the left/right clock, serial clock and serial data is defined by the DIF1-0 pins. The options are detailed in Figures 8 - 11. SDIN 9 Serial Data Input (Input) - Two’s complement MSB-first serial data is input on this pin. The required relationship between the left/right clock, serial clock and serial data is defined by the DIF1-0 pins. The options are detailed in Figures 8 - 11. 18 DS284PP3 CS4220 CS4221 DIF0, DIF1 10,11 Digital Interface Format (Input) - The required relationship between the left/right clock, serial clock and serial data is defined by the Digital Interface Format. The options are detailed in Figures 8 - 11. DIF1 0 0 1 1 DIF0 0 1 0 1 DESCRIPTION I S, up to 24-bit data Left Justified, up to 24-bit data Right Justified, 24-bit Data Right Justified, 20-bit Data 2 FORMAT 0 1 2 3 FIGURE 8 9 10 11 Table 3. Digital Interface Format - DIF1 and DIF0 DEM0, DEM1 12,18 De-Emphasis Select (Input) - Controls the activation of the standard 50/15 µs de-emphasis filter. 32, 44.1, or 48 kHz sample rate selection defined in Table 4. DEM0 0 0 1 1 DEM1 0 1 0 1 De-Emphasis 32 kHz 44.1 kHz 48 kHz Disabled Table 4. De-emphasis Control 13 Digital Logic Power (Input) - Positive power supply for the digital interface section. Typically 3.0 to 5.0 VDC. AINR-, AINR+ 16,17 Differential Right Channel Analog Input (Input) - The full scale analog input level (differential) is specified in the Analog Characteristics specification table and may be AC coupled or DC coupled into the device, see Figure 12 for optional line input buffer. AINL-, AINL+ 19,20 Differential Left Channel Analog Input (Input) - The full scale analog input level (differential) is specified in the Analog Characteristics specification table and may be AC coupled or DC coupled into the device, see Figure 12 for optional line input buffer. VL VA 21 Analog Power (Input) - Positive power supply for the analog section. Nominally +5 Volts. AGND 22 Analog Ground (Input) - Analog ground reference. AOUTR-, AOUTR+ 23, 24 Differential Right Channel Analog Output (Output) - The full scale analog output level (differential) is specified in the Analog Characteristics specification table. AOUTL-, AOUTL+ 25, 26 Differential Left Channel Analog Output (Output) - The full scale analog output level (differential) is specified in the Analog Characteristics specification table. RST DS284PP3 27 Reset (Input) - When low, the device enters a low power mode and all internal registers are reset, including the control port. When high, the control port becomes operational and normal operation will occur. 19 CS4220 CS4221 7. PIN DESCRIPTIONS — CS4221 CS4221 NC XTI, XTO NC 1 28 NC XTO 2 27 RST XTI 3 26 AOUTL- LRCK 4 25 AOUTL+ SCLK 5 24 AOUTR+ VD 6 23 AOUTR- DGND 7 22 AGND SDOUT 8 21 VA SDIN 9 20 AINL+ SCL/CCLK 10 19 AINL- SDA/CDIN 11 18 I2C/SPI AD0/CS 12 17 AINR+ VL 13 16 AINR- NC 14 15 NC 1,14,15, 28 No Connect - These pins are not connected internally and should be tied to DGND to minimize noise coupling. 2,3 Crystal Connections (Input/Output) - Input and output connections for the crystal used to clock the CS4221. Alternatively a clock may be input into XTI. This is the clock source for the delta-sigma modulator and digital filters. The frequency of this clock must be either 256x, 384x, or 512x Fs. The default XTI setting in Master Mode is 256x, but this may be changed to 384x or 512x through the Control Port. Fs (kHz) 32 44.1 48 256x 8.1920 11.2896 12.2880 XTI (MHz) 384x 12.2880 16.9344 18.4320 512x 16.3840 22.5792 24.5760 Table 5. Common Clock Frequencies LRCK 4 Left/Right Clock (Input) - Determines which channel is currently being input/output of the serial audio data pins SDIN/SDOUT. The frequency of the Left/Right clock must be equal to the input sample rate. Although the outputs for each ADC channel are transmitted at different times, Left/Right pairs represent simultaneously sampled analog inputs. The required relationship between the left/right clock, serial clock and serial data is defined by the DSP Port Mode (05h) register. The options are detailed in Figures 8 - 11. SCLK 5 Serial Data Clock (Input) - Clocks the individual bits of the serial data into the SDIN pin and out of the SDOUT pin. The required relationship between the left/right clock, serial clock and serial data is defined by the DSP Port Mode (05h) register. The options are detailed in Figures 8 - 11. VD 6 Digital Power (Input) - Positive power supply for the digital section. Typically 5.0 VDC. DGND 7 Digital Ground (Input) - Digital ground for the digital section. SDOUT 8 Serial Data Output (Output) - Two’s complement MSB-first serial data is output on this pin. The required relationship between the left/right clock, serial clock and serial data is defined by the DSP Port Mode (05h) register. The options are detailed in Figures 8 - 11. 20 DS284PP3 CS4220 CS4221 SDIN 9 Serial Data Input (Input) - Two’s complement MSB-first serial data is input on this pin. The required relationship between the left/right clock, serial clock and serial data is defined by the DSP Port Mode (05h) register. The options are detailed in Figures 8 - 11. SCL/CCLK 10 Serial Control Port Clock (Input) - Clocks the serial control bits into and out of the CS4221. In I2C mode, SCL requires an external pull-up resistor according to the I2C specification. SDA/CDIN 11 Serial Control Port Data (Input/Output)- SDA is a data I/O line in I2C mode and requires an external pull-up resistor according to the I2C specification. CDIN in the input data line for the serial control port in SPI mode. AD0/CS 12 Address Bit/Control Chip Select (Input) - In I2C mode, AD0 is a chip address bit. In SPI mode, CS is used to enable the control port interface on the CS4221. The CS4221 control port interface is defined by the SPI/I2C pin. VL 13 Logic Power (Input) - Positive power supply for the digital interface section. Typically 3.0 to 5.0 VDC. AINR-, AINR+ I2C/SPI AINL-, AINL+ 16,17 18 19,20 Differential Right Channel Analog Input (Input) - The full scale analog input level (differential) is specified in the Analog Characteristics specification table and may be AC coupled or DC coupled into the device, see Figure 12 for optional line input buffer. Control Port Format (Input) - When this pin is high, I2C mode is selected, when low, SPI is selected. Differential Left Channel Analog Input (Input) - The full scale analog input level (differential) is specified in the Analog Characteristics specification table and may be AC coupled or DC coupled into the device, see Figure 12 for optional line input buffer. VA 21 Analog Power (Input) - Positive power supply for the analog section. Typically 5.0 VDC. AGND 22 Analog Ground (Input) - Analog ground reference. AOUTR-, AOUTR+ 23, 24 Differential Right Channel Analog Outputs (Output) - The full scale analog output level (differential) is specified in the Analog Characteristics specification table. AOUTL-, AOUTL+ 25, 26 Differential Left Channel Analog Outputs (Output) - The full scale analog output level (differential) is specified in the Analog Characteristics specification table. 27 Reset (Input) - When low, the device enters a low power mode and all internal registers are reset, including the control port. When high, the control port becomes operational and normal operation will occur. RST DS284PP3 21 CS4220 CS4221 8. APPLICATIONS 8.1 Overview The CS4220 is a stand-alone device controlled through dedicated pins. The CS4221 is controlled with an external microcontroller using the serial control port. 8.2 Grounding and Power Supply Decoupling As with any high resolution converter, the CS4220/1 requires careful attention to power supply and grounding arrangements to optimize performance. Figures 4 and 5 shows the recommended power arrangement with VA, VD and VL connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be used on each supply pin. 8.3 High Pass Filter The operational amplifiers in the input circuitry driving the CS4220/1 may generate a small DC offset into the A/D converter. The CS4220/1 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. 8.4 Analog Outputs The recommended off-chip analog filter is either a 2nd order Butterworth or a 3rd order Butterworth, if greater out-of-band noise filtering is desired. The CS4220/1 DAC interpolation filter has been precompensated for an external 2nd order Butterworth filter with a 3 dB corner at Fs, or a 3rd order Butterworth filter with a 3 dB corner at 0.75 Fs to provide a flat frequency response and linear phase over the passband (see Figure 14 for Fs = 48 kHz). If the recommended filter is not used, small frequency response magnitude and phase errors will occur. In addition to providing out-of-band noise attenua22 tion, the output filters shown in Figure 14 provide differential to single-ended conversion. 8.5 Master vs. Slave Mode The CS4220/1 may be operated in either master mode or slave mode. In master mode, SCLK and LRCK are outputs which are internally derived from MCLK. The device will operate in master mode when a 47 kΩ pulldown resistor is present on SDOUT at startup or after reset, see Figure 5. LRCK and SCLK are inputs to the CS4220/1 when operating in slave mode. See Figures 8-11 for the available clocking modes. 8.6 De-emphasis The CS4220/1 includes digital de-emphasis for 32, 44.1, or 48 kHz sample rates. The frequency response of the de-emphasis curve, as shown in Figure 15, will scale proportionally with changes in samples rate, Fs. The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis as a means of noise reduction. De-emphasis control is achieved with the DEM1/0 pins on the CS4220 or through the DEM1-0 bits in the DSP Port Mode Byte (#5) on the CS4221. 8.7 Power-up / Reset / Power Down Calibration Upon power up, the user should hold RST = 0 for approximately 10 ms. In this state, the control port is reset to its default settings and the part remains in the power down mode. At the end of RST, the device performs an offset calibration which lasts approximately 50 ms after which the device enters normal operation. In the CS4221, a calibration may also be initiated via the CAL bit in the ADC Control Byte (#1). The CALP bit in the ADC Control Byte is a read only bit indicating the status of the calibration. Reset/Power Down is achieved by lowering the RST pin causing the part to enter power down. DS284PP3 CS4220 CS4221 Once RST goes high, the control port is functional and the desired settings should be loaded. The CS4220/1 will also enter power down mode if the master clock source stops for approximately 10 µs or if the LRCK is not synchronous to the master clock. The control port will retain its current settings. The CS4220/1 will mute the analog outputs and enter the power down mode if the supply drops below approximately 4 volts. 8.8 Control Port Interface (CS4221 only) The control port is used to load all the internal settings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and I2C, with the CS4221 operating as a slave device. The control port interface format is selected by the SPI/I2C pin. 8.8.1 SPI Mode In SPI mode, CS is the CS4221 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller and the chip address is 0010000. All signals are inputs and data is clocked in on the rising edge of CCLK. The CS4221 has a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, then the MAP will stay constant for successive writes. If INCR is set to a 1, then MAP will auto increment after each byte is written, allowing block writes of successive registers. Register reading from the CS4221 is not supported in the SPI mode. 8.8.2 I2C Mode In I2C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 7. There is no CS pin. Pin AD0 forms the partial chip address and should be tied to VD or DGND as desired. The upper 6 bits of the 7 bit address field must be 001000. In order to communicate with the CS4221, the LSB of the chip address field (first byte sent to the CS4221) should match the setting of the AD0 pin. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the Memory Address Pointer will be output. Setting the auto increment bit in MAP, allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. Figure 6 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write indicator (R/W), which must be low to write. Register reading from the CS4221 is not supported in the SPI mode. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into a register designated by the MAP. DS284PP3 23 CS4220 CS4221 8.9 Memory Address Pointer (MAP) 7 INCR 0 8.9.1 6 5 4 3 Reserved Reserved Reserved Reserved 0 0 0 0 2 MAP2 0 1 MAP1 0 0 MAP0 0 AUTO-INCREMENT CONTROL (INCR) Default = 0 0 - Disabled 1 - Enabled 8.9.2 REGISTER POINTER (MAP) Default = 000 CS CCLK CHIP ADDRESS MAP 0010000 CDIN R/W DATA MSB LSB byte 1 MAP = Memory Address Pointer byte n Figure 6. Control Port Timing, SPI mode SDA 001000 ADDR AD0 R/W ACK DATA 1-8 ACK DATA 1-8 ACK SCL Start Stop Figure 7. Control Port Timing, I2C mode 24 DS284PP3 CS4220 CS4221 Left Channel LRCK Right Channel SCLK SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Master Slave 2 2 I S, up to 24-bit data XTI = 256, 384, 512 Fs (CS4223 - 256 Fs only) LRCK = 4 to 50 kHz SCLK = 64 Fs I S, up to 24-bit data XTI = 256, 384, 512 Fs LRCK = 4 to 50 kHz SCLK = 48,64, 128 Fs Figure 8. Serial Audio Format 0 (I2S) Left Channel LRCK Right Channel SCLK SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 Master +5 +4 +3 +2 +1 LSB Slave Left-justified, up to 24-bit data XTI = 256, 384, 512 Fs (CS4223 - 256 Fs only) LRCK = 4 to 50 kHz SCLK = 64 Fs Left-justified, up to 24-bit data XTI = 256, 384, 512 Fs LRCK = 4 to 50 kHz SCLK = 48, 64, 128 Fs Figure 9. Serial Audio Format 1 LRCK Right Channel Left Channel SCLK SDATA 0 23 22 21 20 19 18 7 6 5 4 3 2 1 0 23 22 21 20 19 18 7 6 5 4 3 2 1 0 32 clocks Master Slave Right-justified, 24-bit data XTI = 256, 384, 512 Fs (CS4223 - 256 Fs only) LRCK = 4 to 50 kHz SCLK = 64 Fs Right-justified, 24-bit data XTI = 256, 384, 512 Fs LRCK = 4 to 50 kHz SCLK = 64 Fs Figure 10. Serial Audio Format 2 DS284PP3 25 CS4220 CS4221 LRCK Right Channel Left Channel SCLK SDATA 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 clocks Master Slave Right-justified, 20-bit data XTI = 256, 384, 512 Fs (CS4223 - 256 Fs only) LRCK = 4 to 50 kHz SCLK = 64 Fs Right-justified, 20-bit data XTI = 256, 384, 512 Fs LRCK = 4 to 50 kHz SCLK = 64 Fs Figure 11. Serial Audio Format 3 Figure 12. Optional Input Buffer Input + 150 Ω 10 µF AINR+ 2.2 nF CS4223/4 AINR- 4.7 µF + 0.1 µF Figure 13. Single-ended Input Application 26 DS284PP3 CS4220 CS4221 Figure 14. 2- and 3-Pole Butterworth Filters Gain dB Analog 0 T1 = 50 µs T2 = 15 µs -10 dB A mplitude (dB) Signal 0 dB Noise 0 F1 F2 Frequency Figure 15. De-emphasis Curve DS284PP3 Digital Attenuation (dB) -113.5 Figure 16. Hybrid Analog/Digital Attenuation 27 CS4220 CS4221 9. ADC/DAC FILTER RESPONSE Figure 17. ADC Filter Response 28 Figure 18. ADC Passband Ripple Figure 19. ADC Transition Band Figure 20. DAC Filter Response Figure 21. DAC Passband Ripple Figure 22. DAC Transition Band DS284PP3 CS4220 CS4221 10. PARAMETER DEFINITIONS Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels. ADCs are measured at -1 dBFS as suggested in AES17-1991 Annex A and DACs are measured at 0 dBFS. Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the rms analog output level with 1 kHz full scale digital input to the rms analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. Units in decibels. Interchannel Isolation A measure of crosstalk between channels. Measured for each channel at the converter’s output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in decibels. Gain Error The deviation from the nominal full scale output for a full scale input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error For the ADCs, the deviation in LSB's of the output from mid-scale with the selected inputs tied to a common potential. For the DAC's, the differential output voltage with mid-scale input code. Units are in volts. DS284PP3 29 CS4220 CS4221 11. PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING N D E11 A2 E e b2 SIDE VIEW A ∝ A1 L END VIEW SEATING PLANE 1 2 3 TOP VIEW DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0° INCHES NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4° MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8° MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0° MILLIMETERS NOM -0.15 1.75 -10.20 7.80 5.30 0.65 0.90 4° NOTE MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03 8° 2,3 1 1 JEDEC #: MO-150 Controlling Dimension is Millimeters Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. 30 DS284PP3 • Notes •