CS4228A-KS

CS4228A 24-Bit, 96 kHz Surround Sound Codec Features ! Six Description The CS4228A codec provides two analog-to-digital and six digital-to-analog Delta-Sigma converters, along with volume controls, in a compact 28-pin SSOP device. Combined with an IEC958 (SPDIF) receiver (like the CS8414) and surround sound decoder (such as one of the CS492x or CS493xx families), it is ideal for use in DVD player, A/V receiver and car audio systems supporting multiple standards such as Dolby Digital AC-3, AAC, DTS, Dolby ProLogic, THX, and other multi-channel formats. A flexible serial audio interface allows operation in Left Justified, Right Justified, I2S, or One Line Data modes. ORDERING INFORMATION CS4228A-KS -10° to +70°C CDB4228A 28-pin SSOP Evaluation Board 24-bit D/A converters - 100 dB dynamic range - -90 dB THD+N ! Two 24-bit A/D converters - 97 dB dynamic range - -88 dB THD+N ! Sample rates up to 100 kHz ! Pop-free digital output volume controls - 90.5 dB range, 0.5 dB resolution (182 levels) - Variable smooth ramp rate, 0.125 dB steps ! Mute control pin for off-chip muting circuits ! On-chip anti-alias and output filters ! De-emphasis filters for 32, 44.1 and 48 kHz I SCL/CCLK SDA/CDIN AD0/CS MUTEC RST VD VL VA CONTROL PORT MUTE CONTROL FILT ANALOG LOW PASS AND OUTPUT STAGE DIGITAL FILTERS WITH DE-EMPHASIS LRCK SCLK SDIN1 SDIN2 SDIN3 SERIAL AUDIO DATA INTERFACE DIGITAL VOLUME DIGITAL VOLUME DIGITAL VOLUME DIGITAL VOLUME DIGITAL VOLUME DIGITAL VOLUME ∆Σ DAC #1 ∆Σ DAC #2 ∆Σ DAC #3 ∆Σ DAC #4 ∆Σ DAC #5 ∆Σ DAC #6 FL FR SL SR CENTER SUB SDOUT DIGITAL FILTERS LEFT ADC RIGHT ADC AINL+ AINLAINR+ AINR- CLOCK MANAGER MCLK DGND AGND www.cirrus.com Copyright  Cirrus Logic, Inc. 2003 (All Rights Reserved) MAR ‘03 DS511F1 1 CS4228A TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 SPECIFIED OPERATING CONDITIONS ................................................................................. 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4 ANALOG CHARACTERISTICS ................................................................................................ 5 POWER AND THERMAL CHARACTERISTICS....................................................................... 7 DIGITAL CHARACTERISTICS ................................................................................................. 7 SWITCHING CHARACTERISTICS .......................................................................................... 8 SWITCHING CHARACTERISTICS - CONTROL PORT......................................................... 10 2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 12 3. FUNCTIONAL DESCRIPTION ............................................................................................... 13 3.1 Overview .......................................................................................................................... 13 3.2 Analog Inputs ................................................................................................................... 13 3.2.1 Line Level Inputs ................................................................................................. 13 3.2.2 High Pass Filter ................................................................................................... 13 3.3 Analog Outputs ................................................................................................................ 14 3.3.1 Line Level Outputs .............................................................................................. 14 3.3.2 Digital Volume Control ........................................................................................ 14 3.4 Mute Control .................................................................................................................... 15 3.5 Clock Generation ............................................................................................................. 15 3.5.1 Clock Source ....................................................................................................... 15 3.5.2 Synchronization ................................................................................................... 15 3.6 Digital Interfaces .............................................................................................................. 15 3.6.1 Serial Audio Interface Signals ............................................................................. 15 3.6.2 Serial Audio Interface Formats ............................................................................ 16 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. 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Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system. DTS is a registered trademark of the Digital Theater Systems, Inc. Dolby, Dolby Digital, AC-3, AAC, and Pro Logic are registered trademarks of Dolby Laboratories, Inc. THX is a registered trademark of Lucasfilms Ltd. 2 CS4228A 3.7 Control Port Signals ......................................................................................................... 18 3.7.1 SPI Mode ............................................................................................................ 18 3.7.2 I2C Mode ............................................................................................................ 18 3.8 Control Port Bit Definitions .............................................................................................. 19 3.9 Power-up/Reset/Power Down Mode ............................................................................... 19 3.10 Power Supply, Layout, and Grounding .......................................................................... 20 REGISTER QUICK REFERENCE .......................................................................................... 21 REGISTER DESCRIPTIONS .................................................................................................. 22 5.1 Memory Address Pointer (MAP) ..................................................................................... 22 5.2 CODEC Clock Mode ........................................................................................................ 22 5.3 Chip Control ..................................................................................................................... 22 5.4 ADC Control .................................................................................................................... 23 5.5 DAC Mute1 Control ......................................................................................................... 23 5.6 DAC Mute2 Control ......................................................................................................... 24 5.7 DAC De-emphasis Control .............................................................................................. 24 5.8 Digital Volume Control ..................................................................................................... 24 5.9 Serial Port Mode .............................................................................................................. 25 5.10 Chip Status .................................................................................................................... 25 PIN DESCRIPTION ................................................................................................................. 26 PARAMETER DEFINITIONS .................................................................................................. 29 PACKAGE DIMENSIONS ...................................................................................................... 31 4. 5. 6. 7. 8. LIST OF FIGURES Figure 1. Serial Audio Port Master Mode Timing ............................................................................ 9 Figure 2. Serial Audio Port Slave Mode Timing .............................................................................. 9 Figure 3. SPI Control Port Timing ................................................................................................. 10 Figure 4. I2C Control Port Timing ................................................................................................. 11 Figure 5. I2C Mode SCL Buffer Example...................................................................................... 11 Figure 6. Recommended Connection Diagram............................................................................. 12 Figure 7. Optional Line Input Buffer .............................................................................................. 13 Figure 8. Passive Output Filter with Mute ..................................................................................... 14 Figure 9. Butterworth Output Filter with Mute ............................................................................... 14 Figure 10. I2S Serial Audio Formats ............................................................................................. 16 Figure 11. Left Justified Serial Audio Formats .............................................................................. 16 Figure 12. Right Justified Serial Audio Formats............................................................................ 17 Figure 13. One Line Data Serial Audio Format ............................................................................. 17 Figure 14. Control Port Timing, SPI Slave Mode Write................................................................. 18 Figure 15. Control Port Timing, I2C Slave Mode Write ................................................................. 19 Figure 16. Control Port Timing, I2C Slave Mode Read................................................................. 19 LIST OF TABLES Table 1. Serial Audio Port Input Channel Allocations ................................................................... 16 Table 2. User Registers ................................................................................................................ 21 Table 3. Common Master Clock Frequencies.............................................................................. 27 3 CS4228A 1. CHARACTERISTICS AND SPECIFICATIONS (Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at TA = 25°C, VA = 5.0V, VD = 5.0V) SPECIFIED OPERATING CONDITIONS ground.) Parameter DC Power Supply ((AGND, DGND = 0V; all voltages with respect to Symbol Min 4.75 4.75 3.0* -10 Typ 5.0 5.0 Max 5.25 5.25 5.25 2.00 70 Units V V V V °C Digital Analog Interface VD - VL (Note 12) (-KS) VD VA VL TA Specified Temperature Range ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to ground.) Parameter DC Power Supply Digital Analog Interface VD - VL (Note 1) (Note 2) Input Pins Bidirectional Pins (Notes 2 and 3) (Power Applied) Symbol VD VA VL Min -0.3 -0.3 -0.3 -0.7 -0.7 -0.7 -55 -65 Max 6.0 6.0 6.0 2.0 ±10 VA + 0.7 VL + 2.5 VL + 0.7 +125 +150 Units V V V V mA V V V °C °C Input Current Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 2. The maximum over or under voltage is limited by the input current. 3. Bidirectional pins configured as inputs. Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 4 CS4228A ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL = 10 kΩ, CL = 15 pF) Base Rate Mode Parameter Dynamic Range, -60 dBFS input Total Harmonic Distortion + Noise Interchannel Isolation Interchannel Gain Mismatch Offset Error (with high pass filter) Full Scale Input Voltage (Differential): Gain Drift Input Resistance Input Capacitance A/D Decimation Filter Characteristics Passband Passband Ripple Stopband Stopband Attenuation Group Delay Group Delay Variation vs. Frequency High Pass Filter Characteristics Frequency Response: Phase Deviation Passband Ripple -3 dB (Note 7) -0.13 dB 3.4 20 10 0 3.4 20 10 0 Hz Hz Degree dB (Note 5) (Note 6) tgd ∆ tgd (Note 5) 0.022 30.0 80 17/Fs 21.77 0.022 0.01 0 45 6114 72.41 17/Fs 43.54 0.05 6071 0 kHz dB kHz dB s µs (A weighted) (unweighted) (Note 4) THD+N Symbol Min 91 5.24 10 Typ 97 94 -88 100 0.1 5.66 100 Max -83 0 6.09 15 High Rate Mode Min 91 5.24 10 Typ 97 94 -88 100 0.1 5.66 100 Max -83 0 6.09 15 Units dB dB dB dB dB LSB Vp-p ppm/°C kΩ pF Analog Input Characteristics - Minimum gain setting (0 dB) Differential Input; unless otherwise specified. @ 20 Hz (Note 7) Notes: 4. Referenced to typical full-scale differential input voltage (2 Vrms). Tested at -1 dBFS 5. Filter characteristics scale with output sample rate. 6. The analog modulator samples the input at 128 times Fs. For example, to obtain an output sample rate of 48 kHz the input must be sampled at 6.144 MHz. There is no rejection of input signals which are multiples of the sampling frequency (n × 6.144 MHz ±20.0 kHz where n = 0,1,2,3...). 7. High Pass Filter characteristics are specified for Fs=44.1 kHz. 5 CS4228A ANALOG CHARACTERISTICS Parameter Dynamic Range, -60 dBFS input (A weighted) (unweighted) (Continued) Base Rate Mode Symbol Min 93 3.42 Minimum Load Resistance: Maximum Load Capacitance: Combined Digital and Analog Filter Characteristics Frequency Response Deviation from Linear Phase Passband: to 0.01 dB corner Passband Ripple Stopband Stopband Attenuation Analog Loopback Performance Signal-to-noise Ratio (CCIR-2K weighted, -20 dB FS input) CCIR-2K 90 90 dB Group Delay (Fs = Input Word Rate) (Notes 8, 9) (Note 9) (Notes 8, 9) (Notes 8, 10) tgd 10 Hz to 20 kHz 0 26.2 70 ±0.1 ±0.5 29/Fs 21.77 ±0.01 0 62.5 65 ±0.1 ±0.5 17/Fs 43.54 ±0.01 dB Degrees kHz dB kHz dB s Typ 100 97 -90 95 0.1 10 3.7 100 10 100 Max -83 3.98 High Rate Mode Min 93 3.42 Typ 100 97 -90 95 0.1 10 3.7 100 10 100 Max -83 3.98 Units dB dB dB dB dB mV Vp-p ppm/°C kΩ pF Analog Output Characteristics - Minimum Attenuation, 10 kΩ, 10 pF load; unless otherwise specified. Total Harmonic Distortion + Noise (unweighted) THD+N Interchannel Isolation Interchannel Gain Mismatch Offset Voltage Full Scale Output Voltage Gain Drift Analog Output Load 8. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz, the 0.01 dB passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs. 9. Digital filter characteristics. 10. Measurement bandwidth is 10 Hz to 3 Fs. 6 CS4228A POWER AND THERMAL CHARACTERISTICS Parameters Power Supplies Power Supply Current (Note 11, Note 12) normal operation, VA= VD =VL =5V BRM Symbol Min Typ Max Units IA ID IL IA ID IL - 35 78 0.3 0.2 0.4 0.2 42 105 2 1 15 0.5 mA mA mA mA mA mA power-down state (all supplies) (Note 13) BRM Power Dissipation VA= VD = VL = 5V Package Thermal Resistance Power Supply Rejection Ratio (Note 11) normal operation power-down (Note 13) TSSOP (-KS) (1 kHz, 10 mVrms) θJA θJC PSRR - 567 4 56 37 50 715 12.5 - mW mW °C/Watt °C/Watt dB Notes: 11. Current consumption increases with increasing FS and increasing MCLK. Variance between speed modes is small. 12. VD current consumption increases (ID normal and ID_pdn) when VD - VL > 1.5V. When VD - VL = 1.7V, ID typically increases by 2 mA and when VD - VL = 2V, ID typically increases by 12 mA. 13. Power down mode is defined as RST pin = Low with clocks running. DIGITAL CHARACTERISTICS Parameter High-level Input Voltage Low-level Input Voltage High-level Input Voltage Low-level Input Voltage High-level Output Voltage at VL = 5V VL = 3.3V Low-level Output Voltage at VL = 5V VL = 3.3V Input Leakage Current Output Leakage Current (AGND, DGND = 0V, all voltages with respect to ground.) Symbol VL=5V VL=3.3V VIH VIL VIH VIL VOH VOH VOH VOL VOL VOL Min 0.7 x VL 2.2 VL - 1.0 VL - 0.7 2.3 Max 0.3 x VL 1.0 0.4 0.2 0.4 10 10 Units V V V V V V V V V V µA µA I0 = -2.0 mA I0 = -100 µA I0 = -2.0 mA I0 = 2.0 mA I0 = 100 µA I0 = -2.0 mA (Digital Inputs) (High-Impedance Digital Outputs) 7 CS4228A SWITCHING CHARACTERISTICS Parameter Audio ADC's and DAC's Sample Rate MCLK Frequency MCLK Duty Cycle BRM HRM (Note 14) BRM MCLK =128, 384 Fs MCLK = 256, 512 Fs HRM MCLK = 64, 192 Fs MCLK = 128, 256 Fs (Note 15) (Note 16) tdpd tlrpd tds tdh (Note 17) (Note 17) tsck tsck 1 --------------------( 128 ) Fs 1 -----------------( 64 ) Fs (Inputs: Logic 0 = 0V, Logic 1 = VL) Symbol Fs Min 30 60 3.84 40 40 40 40 1 Typ 50 50 50 50 Max 50 100 25.6 60 60 60 60 50 20 10 30 Units kHz kHz MHz % % % % ms ns ns ns ns ns ns RST Low Time SCLK Falling Edge to SDOUT Output Valid LRCK Edge to MSB Valid SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge SCLK Period BRM SCLK Period HRM Master Mode SCLK Falling to LRCK Edge SCLK Duty Cycle Slave Mode SCLK High Time SCLK Low Time SCLK rising to LRCK Edge LRCK Edge to SCLK Rising tmslr +10 50 - ns % ns ns ns ns tsckh tsckl tlrckd tlrcks 50 50 25 25 - Notes: 14. See Cl1:0 register on page 22 for settings. 15. After powering up the CS4228A, RST should be held low for 1 ms after the power supplies and clocks are settled. 16. Scales with sample rate Fs. 50 ns valid at 48 kHz, more time at slower Fs and less time at faster Fs. 17. See DCK1:0 register on page 25 for settings. 8 CS4228A SC LK ( o u tp u t) t m s lr LRCK ( o u tp u t) SDOUT Figure 1. Serial Audio Port Master Mode Timing LR C K ( in p u t) t lr c k d SC LK ( in p u t) t lr c k s t sckh tsckl S D IN 1 S D IN 2 S D IN 3 t lr p d SDOUT td s td h MSB td p d M S B -1 Figure 2. Serial Audio Port Slave Mode Timing 9 CS4228A SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: Logic 0 = 0V, Logic 1 = VL) Parameter SPI Mode (SDOUT > 47 kΩ to GND) CCLK Clock Frequency CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 18) (Note 19) (Note 19) fsck tcsh tcss tscl tsch tdsu tdh tr2 tf2 1.0 20 66 66 40 15 30 100 6 MHz µs ns ns ns ns ns ns ns Symbol Min Max Units Notes: 18. Data must be held for sufficient time to bridge the transition time of CCLK. 19. For FSCK < 1 MHz CS t css CCLK t r2 C D IN t scl t s ch t csh t f2 t dsu t dh Figure 3. SPI Control Port Timing 10 CS4228A SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: Logic 0 = 0V, Logic 1 = VL) Parameter I C Mode (SDOUT < 47 kΩ to ground) SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup Time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition (Note 21) (Note 20) fscl tbuf thdst tlow thigh tsust thdd tsud tr tf tsusp 4.7 4.7 4.0 4.7 4.0 4.7 0 250 30 300 100 kHz µs µs µs µs µs µs ns ns ns µs 2 Symbol Min Max Units Notes: 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 21. Pin 11 (SCL/CCLK) of the CS4228A does not have sufficient hysteresis to enable the use of standard two-wire mode configurations with a resistor pull-up. This issue can be worked around by placing a Schmitt Trigger buffer, for example a 74VHC14, on the SCL line just prior to the CS4228A. See Figure 5. This will not affect the operation of the bus in either mode, as pin 6 is an input only. Stop SDA t buf S ta rt R epe a te d S ta rt Stop t hdst t high t hdst tf t susp SCL t t t sud t sust tr lo w hdd Figure 4. I2C Control Port Timing V+ SCL P in 1 1 Figure 5. I2C Mode SCL Buffer Example 11 CS4228A 2. TYPICAL CONNECTION DIAGRAM Ferrite B ead +5V S upply + 1 µF 0.1 µ F Ferrite B ead + 0.1 µ F 1 µF VL +5 V S upply Ferrite B ead + 0.1 µ F 1 µF +3.0V to +5V S upply 21 VA 8 VD 9 VL FL 23 AN AL O G FILTE R Front Left 22 µ F 150 Ω + 19 F ro m A n alog Inp ut S tage 2.2 nf 100 µ F 22 µ F A IN LFR 24 AN AL O G FILTE R Front Right + 20 0.1 µ F A IN L+ SL AN AL O G FILTE R Surround Left + 150 Ω 25 17 2.2 nf 100 µ F AIN R AIN R + C S4228A SR 26 AN AL O G FILTE R Surround Right + 16 0.1 µ F C E N TE R 27 1 µF AN AL O G FILTE R Center 0.1 µ F + 18 FILT AN AL O G FILTE R Subwoofer SUB 28 VL VL M U TE C VL LR C K 6 2.2 K * 12 M icrocontroller 11 13 14 S D A /C D IN S C L/C C LK A D 0/C S RST S D IN 2 2 S D IN 3 1 SDOUT 4 50 Ω 50 Ω 50 Ω 15 50 Ω S C LK S D IN 1 5 3 50 Ω 50 Ω D igital Au dio P eripheral or DSP A ll unused logic inputs should be tied to 0 V. 33 K * AGND 22 DGND 7 M C LK 10 * R equired for 2-w ire m ode only E xternal C lock Input N ote : M C L K Logic H igh is V L N ote: A G N D and D G N D pin s should both be tied to a com m on ground p lane. Figure 6. Recommended Connection Diagram 12 CS4228A 3. FUNCTIONAL DESCRIPTION 3.1 Overview The CS4228A is a 24-bit audio codec comprised of 2 analog-to-digital converters (ADC) and 6 digitalto-analog converters (DAC), all implemented using single-bit delta-sigma techniques. Other functions integrated with the codec include independent digital volume controls for each DAC, digital DAC de-emphasis filters, ADC high-pass filters, an onchip voltage reference, and a flexible serial audio interface. All functions are configured through a serial control port operable in SPI mode and in I2C mode. Figure 6 shows the recommended connections for the CS4228A. positive or negative input as long as the unused input is connected to ground through capacitors as shown. When operated with single-ended inputs, distortion will increase at input levels higher than -1 dBFS. Figure 7 shows an example of a differential input circuit. Muting of the stereo ADC is possible through the ADC Control Byte. The ADC output data is in 2’s complement binary format. For inputs above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively. 3.2.2 High Pass Filter 3.2 3.2.1 Analog Inputs Line Level Inputs AINR+, AINR-, AINL+, and AINL- are the line level analog inputs (See Figure 6). These pins are internally biased to a DC operating voltage of approximately 2.3 VDC. AC coupling the inputs preserves this bias and minimizes signal distortion. Figure 6 shows operation with a single-ended input source. This source may be supplied to either the Digital high pass filters in the signal path after the ADCs remove any DC offsts present on the analog inputs. The high pass filter helps prevent audible “clicks” when switching between audio sources downstream from the ADCs. The high pass filter response, given in “High Pass Filter Characteristics”, scales linearly with sample rate. Thus, for High Rate Mode, the -3 dB frequency at a 96 kHz sample rate will be equal to 96/44.1 times that at a sample rate of 44.1 kHz. 4.7 k 10 µ F 10 k signal + 10 k 10 k 150 AIN - + 2.2 nf 10 k VA + ~ 8.5 k 10 µ f 150 AIN + + 0.1 µ F Figure 7. Optional Line Input Buffer 13 CS4228A The high pass filters can be disabled by setting the HPF bit in the ADC Control register. When asserted, any DC present at the analog inputs will be represented in the ADC outputs. The high pass filter may also be “frozen” using the HPFZ bit in the ADC Control register. In this condition, it will remember the DC offset present at the ADC inputs at the moment the HPFZ bit was asserted, and will continue to remove this DC level from the ADC outputs. This is useful in cases where it is desirable to eliminate a fixed DC offset while still maintaining full frequency response down to DC. lution. Volume control changes do not occur instantaneously. Instead they ramp in increments of 0.125 dB at a variable rate controlled by the RMP1:0 bits in the Digital Volume Control register. Each output can be independently muted via mute control bits MUT6-1 in the DAC Mute1 Control register. When asserted, MUT attenuates the corresponding DAC to its maximum value (90.5 dB). When MUT is deasserted, the corresponding DAC 3.3 3.3.1 Analog Outputs 10 k Line Level Outputs 10 k MUTEC MUN2IIIT1 The CS4228A contains on-chip buffer amplifiers capable of producing line level outputs. These amplifiers are biased to a quiescent DC level of approximately 2.3V. This bias, as well as variations in offset voltage, are removed using off-chip AC load coupling. The delta-sigma conversion process produces high frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an off-chip low pass filter. For most applications, a simple passive filter as shown in Figure 8 can be used. Note that this circuit also serves to block the DC present at the outputs. Figure 9 gives an example of a filter which can be used in applications where greater out of band attenuation is desired. The 2-pole Butterworth filter has a -3 dB frequency of 50 kHz, a passband attenuation of 0.1 dB at 20 kHz, providing optimal out-of-band filtering for sample rates from 44.1 kHz to 96 kHz. The filter has and a gain of 1.56, providing a 2 Vrms output signal. AOUT 22 µ F + MUTEDRV 560 Line Out 100 k C C=142µF Fs 2SC2878 or 2SC3326 2.2 k Figure 8. Passive Output Filter with Mute 1 nf 3.57 k AOUT 3.57 k 1 nf GND 5 6 _ 7 + MC33078 + 10 µ f MUTE Line Out 2 VRMS MUTE DRV 10 µ f + 3.57 k 2k 100 pf 2-Pole Butterworth Filter 3.3.2 Digital Volume Control Figure 9. Butterworth Output Filter with Mute Each DAC’s output level is controlled via the Digital Volume Control register operating over the range of 0 to 90.5 dB attenuation with 0.5 dB reso14 CS4228A returns to the attenuation level set in the Digital Volume Control register. The attenuation is ramped up and down at the rate specified by the RMP1:0 bits. To achieve complete digital attenuation of an incoming signal, Hard Mute controls are provided. When asserted, Hard Mute will send zero data to a corresponding pair of DACs. Hard Mute is not ramped, so it should only be asserted after setting the two corresponding MUT bits to prevent high frequency transients from appearing on the DAC outputs. Hard Mute is controlled by the HMUTE56/34/12 bits in the DAC Mute2 Control register. is determined by the CI1:0 bits in the CODEC Clock Mode register. 3.5.2 Synchronization 3.4 Mute Control The Mute Control pin is typically connected to an external mute control circuit as shown in Figure 8 and Figure 9. The Mute Control pin is asserted during power up, power down, and when serial port clock errors are present. The pin can also be controlled by the user via the control port, or automatically asserted when zero data is present on all six DAC inputs. To prevent large transients on the output, it is desirable to mute the DAC outputs before the Mute Control pin is asserted. Please see the MUTEC pin in the Pin Descriptions section for more information. The serial port is internally synchronized with MCLK. If from one LRCK cycle to the next, the number of MCLK cycles per LRCK cycle changes by more than 32, the CS4228A will undergo an internal reset of its data paths in an attempt to resynchronize. Consequently, it is advisable to mute the DACs and clear the DIGPDN bit when changing from one clock source to another to avoid the output of undesirable audio signals as the device resynchronizes. It is adviseable to ensure that MCLK complies with the Switching Characteristics at all times when switching clock sources without resetting the part. 3.6 3.6.1 Digital Interfaces Serial Audio Interface Signals 3.5 Clock Generation The master clock, MCLK, is supplied to the CS4228A from an external clock source. If MCLK stops for 10 µs, the CS4228A will enter Power Down Mode in which the supply current is reduced as specified under “Power Supply”. In all modes it is required that the number of MCLK periods per SCLK and LRCK period be constant. The serial audio data is presented in 2's complement binary form with the MSB first in all formats. The serial interface clock, SCLK, is used for both transmitting and receiving audio data. SCLK can be generated by the CS4228A (master mode) or it can be input from an external source (slave mode). Mode selection is made with the DMS1:0 bits in the Serial Port Mode register. The number of SCLK cycles in one sample period can be set using the DCK1:0 bits as detailed in the Serial Port Mode register. The Left/Right clock (LRCK) is used to indicate left and right data frames and the start of a new sample period. It may be an output of the CS4228A (master mode), or it may be generated by an external source (slave mode). The frequency of LRCK is the same as the system sample rate, Fs. SDIN1, SDIN2, and SDIN3 are the data input pins. SDOUT, the data output pin, carries data from the two 24-bit ADC's. The serial audio port may also be operated in One Line Data Mode in which all 6 3.5.1 Clock Source The CS4228A internal logic requires an external master clock, MCLK, that operates at multiples of the sample rate frequency, Fs. The MCLK/Fs ratio 15 CS4228A channels of DAC data is input on SDIN1 and the stereo ADC data is output on SDOUT. Table 1 outlines the serial port input to DAC channel allocations. DAC Inputs SDIN1 left channel right channel single line SDIN2 left channel right channel SDIN3 left channel right channel DAC #1 DAC #2 All 6 DAC channels (BRM) DAC #3 DAC #4 DAC #5 DAC #6 3.6.2 Serial Audio Interface Formats The digital audio port supports 6 formats, shown in Figure 10, 11, 12 and 13. These formats are selected using the DDF2:0 bits in the Serial Port Mode register. In One Line Data Mode, all 6 DAC channels are input on SDIN1. One Line Data Mode is only available in BRM. See Figure 13 for channel allocations. Table 1. Serial Audio Port Input Channel Allocations LR CK L e ft C h a n n e l R ig h t C h a n n e l SCLK S D IN x 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 5 14 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 I2S Mode, Data Valid on Rising Edge of SCLK Bits/Sample 16 18 to 24 SCLK Rate(s) 32, 48, 64, 128 Fs 32, 64 Fs 48, 64, 128 Fs 64 Fs Notes BRM, 48 Fs available in slave mode only HRM BRM, 48 Fs available in slave mode only HRM Figure 10. I2S Serial Audio Formats LR C K SCLK S D IN 1/2/3 SDOUT L e ft C h a n n e l R ig h t C h a n n e l M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LS B M SB -1 -2 -3 -4 +5 +4 +3 +2 +1 LS B Left Justified Mode, Data Valid on Rising Edge of SCLK Bits/Sample 16 18 to 24 SCLK Rate(s) 32, 48, 64, 128 Fs 32, 64 Fs 48, 64, 128 Fs 64 Fs Notes BRM, 48 Fs available in slave mode only HRM BRM, 48 Fs available in slave mode only HRM Figure 11. Left Justified Serial Audio Formats 16 CS4228A LRCK Left Channel Right Channel SCLK SDINx 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Right Justified Mode, Data Valid on Rising Edge of SCLK Bits/Sample 16 20 24 SCLK Rate(s) 32, 48, 64, 128 Fs 32, 64 Fs 48, 64, 128 Fs 64 Fs 48, 64, 128 Fs 64 Fs Notes BRM, 48 Fs available in slave mode only HRM BRM, 48 Fs available in slave mode only HRM BRM, 48 Fs available in slave mode only HRM Figure 12. Right Justified Serial Audio Formats 64 clks LRCK SCLK SDIN1 MSB DAC1 20 clks LSB MSB DAC3 20 clks LSB MSB DAC5 20 clks LSB MSB DAC2 20 clks ADCR LSB MSB DAC4 20 clks LSB MSB DAC6 20 clks LSB MSB 64 clks Left Channel Right Channel SDOUT ADCL 20 clks 20 clks One Line Data Mode, Data Valid on Rising Edge of SCLK Bits/Sample 20 SCLK Rate(s) 128 Fs Notes 6 inputs, 2 outputs, BRM only Figure 13. One Line Data Serial Audio Format 17 CS4228A 3.7 Control Port Signals bytes contain the data which will be placed into the registers designated by the MAP. The CS4228A has a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is zero, then the MAP will stay constant for successive writes. If INCR is 1, then the MAP will increment after each byte is written, allowing block reads, or writes, of successive registers. Internal registers are accessed through the control port. The control port may be operated asynchronously with respect to audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no register access is required. The control port has 2 operating modes: SPI mode and I2C mode. In both modes the CS4228A operates as a slave device. Mode selection is determined by the state of the SDOUT pin when RST transitions from low to high: high for SPI, low for I2C mode. SDOUT is internally pulled high to VL. A resistive load from SDOUT to GND of less than 47 kΩ will enable I2C mode after a hardware reset. 3.7.2 I2C Mode 3.7.1 SPI Mode In I2C mode, SDA is a bidirectional data line. Data is clocked into and out of the port by the SCL clock. The signal timing is shown in Figure 15 and 16. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4228A after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write). The AD0 pin determines the LSB of the chip address field. The upper 6 bits of the address field must be 00100 and the seventh bit must match AD0. If the operation is to be a write, the second byte is the Memory Address Ponter (MAP), which selects the register to be written. The succeeding byte(s) are data. If the operation is to be a read, the second byte is sent from the chip to the controller and contains the contents of the register pointed to by the current value of the MAP. In SPI mode, CS is the CS4228A chip select signal, CCLK is the control port bit clock input, and CDIN is the input data line. There is no data output line, therefore all registers are write-only in SPI mode. Data is clocked in on the rising edge of CCLK. Figure 13 shows the operation of the control port in SPI mode. The first 7 bits on CDIN, after CS goes low, form the chip address (0010000). The eighth bit is a read/write indicator (R/W), which should always be low to write. The next 8 bits set the Memory Address Pointer (MAP) which is the address of the register that is to be written. The following CS (input) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CCLK (input) CHIP ADDRESS (WRITE) MAP BYTE INCR DATA 2 1 0 7 6 5 4 3 2 1 0 7 6 5 DATA +n 4 3 2 1 0 CDIN (input) 0 0 1 0 0 0 0 0 6 5 4 3 MSB R/W Figure 14. Control Port Timing, SPI Slave Mode Write 18 CS4228A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) MAP BYTE INCR DATA 2 1 0 7 6 1 0 7 DATA +1 6 1 0 7 DATA +n 6 1 0 SDA 0 0 1 0 0 0 AD0 0 6 5 4 3 ACK START ACK ACK ACK STOP Figure 15. Control Port Timing, I2C Slave Mode Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) MAP BYTE INCR STOP 1 0 0 CHIP ADDRESS (READ) 0 1 0 0 0 AD0 1 DATA 7 0 DATA +1 7 0 DATA + n 7 0 SDA 0 0 1 0 0 0 AD0 0 6 5 4 3 2 ACK START ACK START ACK ACK NO ACK STOP Figure 16. Control Port Timing, I2C Slave Mode Read Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in Figure 16, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 001000x0 chip address & write operation. Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 001000x1 chip address & read operation. Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. 3.8 Control Port Bit Definitions All registers are read/write, except the Chip Status register which is read-only. For more detailed information, see the bit definition tables. 3.9 Power-up/Reset/Power Down Mode Upon power up, the user should hold RST = 0 until the power supplies and clocks stabilize. In this state, the control registers are reset to their default settings, and the device remains in a low power mode in which the control port is inactive. The part may be held in a low power reset state by clearing the DIGPDN bit in the Chip Control register. In this state, the digital portions of the CODEC are in reset, but the control port is active and the desired register settings can be loaded. Normal operation is achieved by setting the DIGPDN bit to 1, at which time the CODEC powers up and normal operation begins. 19 CS4228A The CS4228A will enter a stand-by mode if the master clock source stops for approximately 10 µs or if the number of MCLK cycles per LRCK period varies by more than 32. Should this occur, the control registers retain their settings. The CS4228A will mute the analog outputs, assert the MUTEC pin and enter the Power Down Mode if the supply drops below approximately 4V. AGND and DGND pins should both be tied to a solid ground plane surrounding the CS4228A. The system analog and digital ground planes should not be separated under normal circumstances. A solid ground plane underneath the part is recommended. Decoupling capacitors should be mounted and routed in such a way as to minimize the circuit path length from the CS4228A supply pin or FILT pin, through the capacitor, and back to the applicable CS4228A AGND or DGND pin. The small value ceramic capacitors should be closest to the part. In some cases, ferrite beads in the VL, VD and VA supply lines, and low-value resistances (~ 50 Ω) in series with the LRCK, SCLK, SDIN and SDOUT lines can help reduce coupling of digital signals into the analog portions of the CS4228A. Both capacitors on the FILT pin should be as close to the CS4228A as possible. Any noise that couples onto the FILT pin will couple directly onto all of the analog outputs. Please see the CDB4228 evaluation board data sheet for recommended layout of the decoupling components. 3.10 Power Supply, Layout, and Grounding The CS4228A requires careful attention to power supply and grounding details. VA is normally supplied from the system 5 VDC analog supply. VD is from a 5 VDC digital supply. VL should be from the supply used for the devices digitally interfacing with the CS4228A. Attention should be placed on the VL and VD power up sequence such that the VD supply is applied at the same time or after VL supply is applied (see “Specified Operating Conditions” on page 4). 20 CS4228A 4. REGISTER QUICK REFERENCE Addr Function 7 INCR 1 0x01 CODEC Clock Mode default=0x04 HRM 0 6 Reserved 0 0 5 Reserved 0 4 MAP4 0 0 3 MAP3 0 CI1 0 2 MAP2 0 CI0 1 1 MAP1 0 Reserved 0 0 MAP0 1 Reserved 0 MAP Memory Address Pointer Reserved Reserved Reserved 0 0x02 Chip Control default=0x80 DIGPDN Reserved Reserved ADCPDN DACPDN56 DACPDN34 DACPDN12 Reserved 1 MUTL 0 MUT6 1 MUTEC 1 DEMS1 1 Vol7 0 Vol7 0 Vol7 0 Vol7 0 Vol7 0 Vol7 0 DCK1 1 CLKERR X 0 MUTR 0 MUT5 1 MUTCZ 0 DEMS0 0 Vol6 0 Vol6 0 Vol6 0 Vol6 0 Vol6 0 Vol6 0 DCK0 0 ADCOVL X 0 HPF 0 MUT4 1 Reserved 0 DEM6 0 Vol5 0 Vol5 0 Vol5 0 Vol5 0 Vol5 0 Vol5 0 DMS1 0 Reserved 0 0 HPFZ 0 MUT3 1 Reserved 0 DEM5 0 Vol4 0 Vol4 0 Vol4 0 Vol4 0 Vol4 0 Vol4 0 DMS0 0 Reserved 0 0 Reserved 0 MUT2 1 HMUTE56 0 DEM4 0 Vol3 0 Vol3 0 Vol3 0 Vol3 0 Vol3 0 Vol3 0 Reserved 0 Reserved 0 0 Reserved 0 MUT1 1 HMUTE34 0 DEM3 0 Vol2 0 Vol2 0 Vol2 0 Vol2 0 Vol2 0 Vol2 0 DDF2 1 Reserved 0 0 Reserved 0 RMP1 0 HMUTE12 0 DEM2 0 Vol1 0 Vol1 0 Vol1 0 Vol1 0 Vol1 0 Vol1 0 DDF1 0 Reserved 0 0 Reserved 0 RMP0 0 Reserved 0 DEM1 0 Vol0 0 Vol0 0 Vol0 0 Vol0 0 Vol0 0 Vol0 0 DDF0 0 Reserved 0 0x03 ADC Control default=0x00 0x04 DAC Mute1 Control default=0xFC 0x05 DAC Mute2 Control default=0x80 0x06 DAC De-emphasis Control default=0x80 0x07 DAC 1 Volume Cntrl default=0x00 0x08 DAC 2 Volume Cntrl default=0x00 0x09 DAC 3 Volume Cntrl default=0x00 0x0A DAC 4 Volume Cntrl default=0x00 0x0B DAC 5 Volume Cntrl default=0x00 0x0C DAC 6 Volume Cntrl default=0x00 0x0D Serial Port Mode default=0x84 0x0E Chip Status read only 7 6 5 4 3 2 1 0 Table 2. User Registers 21 CS4228A 5. REGISTER DESCRIPTIONS All registers are read/write except for Chip Status, which is read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in the tables underneath each bit’s label. Default values are also marked in the text with an asterisk. 5.1 Memory Address Pointer (MAP) Not a register 7 INCR 1 6 RESERVED 0 0 5 4 MAP4 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 1 INCR memory address pointer auto increment control 0MAP is not incremented automatically. *1 internal MAP is automatically incremented after each read or write. Memory address pointer (MAP). Sets the register address that will be read or written by the control port. MAP4:0 5.2 CODEC Clock Mode Address 0x01 7 HRM 0 6 0 5 RESERVED 0 4 0 3 CI1 0 2 CI0 1 1 RESERVED 0 0 0 HRM Sets the sample rate mode for the ADCs and DACs *0 Base Rate Mode (BRM) supports sample rates up to 50 kHz 1High Rate Mode (HRM) supports sample rates up to 100 kHz. Typically used for 96 kHz sample rate. Specifies the ratio of MCLK to the sample rate of the ADCs and DACs (Fs) CI1:0 0 *1 2 3 BRM (Fs) 128 256 384 512 HRM (Fs) 64 128 192 256 CI1:0 5.3 Chip Control Address 0x02 7 DIGPDN 1 6 RESERVED 0 0 5 4 ADCPDN 0 3 DACPDN56 0 2 DACPDN34 0 1 DACPDN12 0 0 RESERVED 0 DIGPDN Power down the digital portions of the CODEC 0Digital power down. *1 Normal operation Power down the analog section of the ADC *0 Normal 1ADC power down. ADCPDN 22 CS4228A DACPDN12 Power down the analog section of DAC 1 and 2 *0 Normal 1Power down DAC 1 and 2. Power down the analog section of DAC 3 and 4 *0 Normal 1Power down DAC 3 and 4. Power down the analog section of DAC 5 and 6 *0 Normal 1Power down DAC 5 and 6. DACPDN34 DACPDN56 5.4 ADC Control Address 0x03 7 MUTL 0 6 MUTR 0 5 HPF 0 4 HPFZ 0 3 0 2 RESERVED 0 0 0 1 0 MUTL, MUTR ADC left and right channel mute control *0 Normal 1Selected ADC output muted ADC DC offset removal. See “High Pass Filter” for more information *0 Enabled 1Disabled ADC DC offset averaging freeze. See “High Pass Filter” for more information *0 Normal. The DC offset average is dynamically calculated and subtracted from incoming ADC data. 1Freeze. The DC offset average is frozen at the current value and subtracted from incoming ADC data. Allows passthru of DC information. HPF HPFZ 5.5 DAC Mute1 Control Address 0x04 7 MUT6 1 6 MUT5 1 5 MUT4 1 4 MUT3 1 3 MUT2 1 2 MUT1 1 1 RMP1 0 0 RMP0 0 MUT6 - MUT1 Mute control for DAC6 - DAC1 respectively. When asserted, the corresponding DAC is digitally attenuated to its maximum value (90.5 dB). When deasserted, the corresponding DAC attenuation value returns to the value stored in the corresponding Digital Volume Control register. The attenuation value is ramped up and down at the rate specified by RMP1:0. 0Normal output level *1 Selected DAC output fully attenuated. Attenuation ramp rate. *0 0.5 dB change per 4 LRCKs 10.5 dB change per 8 LRCKs 20.5 dB change per 16 LRCKs 30.5 dB change per 32 LRCKs RMP1:0 23 CS4228A 5.6 DAC Mute2 Control Address 0x05 7 MUTEC 1 6 MUTCZ 0 5 RESERVED 0 0 4 3 HMUTE56 0 2 HMUTE34 0 1 HMUTE12 0 0 RESERVED 0 MUTEC Controls the MUTEC pin 0Normal operation *1 MUTEC pin asserted low Automatically asserts the MUTEC pin on consecutive zeros. When enabled, 512 consecutive zeros on all six DAC inputs will cause the MUTEC pin to be asserted low. A single non-zero value on any DAC input will cause the MUTEC pin to deassert. *0 Disabled 1Enabled Hard mute the corresponding DAC pair. When asserted, zero data is sent to the corresponding DAC pair causing an instantaneous mute. To prevent high frequency transients on the outputs, a DAC pair should be fully attenuated by asserting the corresponding MUT6-MUT1 bits in the DAC Mute Control register or by writing 0xFF to the corresponding Digital Volume Control registers before asserting HMUTE. *0 Normal operation 1DAC pair is muted MUTCZ HMUTE56/34/12 5.7 DAC De-emphasis Control Address 0x06 6 DEMS0 0 5 DEM6 0 4 DEM5 0 3 DEM4 0 2 DEM3 0 1 DEM2 0 0 DEM1 0 7 DEMS1 1 DEMS1:0 Selects the DAC de-emphasis response curve. 0Reserved 1De-emphasis for 48 kHz *2 De-emphasis for 44.1 kHz 3De-emphasis for 32 kHz De-emphasis control for DAC6 - DAC1 respectively *0 De-emphasis off 1De-emphasis on DEM6 - DEM1 5.8 7 0 Digital Volume Control Addresses 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C 6 0 5 0 4 VOLn 0 0 0 0 0 3 2 1 0 VOL6 - VOL1 Address 0x0C - 0x07 sets the attenuation level for DAC 6 - DAC1 respectively. The attenutation level is ramped up and down at the rate specified by RMP1:0 in the DAC Volume Control Setup register. 0 - 181 represents 0 to 90.5 dB of attenuation in 0.5 dB steps. 24 CS4228A 5.9 Serial Port Mode Address 0x0D 7 DCK1 1 6 DCK0 0 5 DMS1 0 4 DMS0 0 3 RESERVED 0 2 DDF2 1 1 DDF1 0 0 DFF0 0 DCK1:0 Sets the number of Serial Clocks (SCLK) per Fs period (LRCLK) DCK1:0 0 1 2 3 BRM (Fs) 32 (1) 48 (2) *64 128 HRM (Fs) (3) (3) 32 (1) 64 Notes: 1. All formats will default to 16 bits 2. Slave mode only 3. Invalid mode DMS1:0 Sets the master/slave mode of the serial audio port *0 Slave (External LRCLK, SCLK) 1Reserved 2Reserved 3Master (No 48 Fs SCLK in BRM) Serial Port Data Format 0Right Justified, 24-bit 1Right Justified, 20-bit 2Right Justified, 16-bit 3Left Justified, maximum 24-bit *4 I2S compatible, maximum 24-bit 5One-line Data Mode, available in BRM only 6Reserved 7Reserved DDF2:0 5.10 Chip Status Address 0x0E 6 ADCOVL X 5 0 4 0 3 RESERVED 0 0 0 0 2 1 0 7 CLKERR X CLKERR Clocking system status, read only 0No Error 1No MCLK is present, or a request for clock change is in progress ADC overflow bit, read only 0No overflow 1ADC overflow has occurred ADCOVL 25 CS4228A 6. PIN DESCRIPTION Serial Audio Data In 3 Serial Audio Data In 2 Serial Audio Data In 1 Serial Audio Data Out Serial Clock Left/Right Clock Digital Ground Digital Power Digital Interface Power Master Clock SDIN3 SDIN2 SDIN1 SDOUT SCLK LRCK DGND VD VL MCLK SCL/CCLK SCL/CCLK SDA/CDIN SDA/CDIN AD0/CS Reset AD0/CS RST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SUB SR SL FR FL AGND VA AINL+ AINLFILT AINRAINR+ MUTEC Analog Out #6,Subwoofer Analog Out #4, Surround Right Analog Out #3, Surround Left Analog Out #2, Front Right Analog Out #1, Front Left Analog Ground Analog Power Left Channel Analog Input+ Left Channel Analog InputInternal Voltage Filter Right Channel Analog InputRight Channel Analog Input+ Mute Control CENTER Analog Out #5, Center SDIN1, SDIN2, SDIN3 1, 2, 3 Serial Audio Data In (Input) - Two's complement MSB-first serial audio data is input on this pin. The data is clocked into SDIN1, SDIN2, SDIN3 via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Serial Mode Register. The options are detailed in Figures 10, 11, 12, and 13. Serial Audio Data Out (Output) - Two's complement MSB-first serial data is output on this pin. The data is clocked out of SDOUT via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Serial Mode Register. The options are detailed in Figures 10, 11, 12 and 13. The state of the SDOUT pin during reset is used to set the Control Port Mode (I2C or SPI). When RST is low, SDOUT is configured as an input, and the rising edge of RST latches the state of the pin. A weak internal pull up is present such that a resistive load less than 47 kΩ will pull the pin low, and the control port mode is I2C. When the resistive load on SDOUT is greater than 47 kΩ during reset, the control port mode is SPI. Serial Clock (Bidirectional) - Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins, and out of the SDOUT pin. The pin is an output in master mode, and an input in slave mode. In master mode, SCLK is configured as an output. MCLK is divided internally to generate SCLK at the desired multiple of the sample rate. In slave mode, SCLK is configured as an input. The serial clock can be provided externally, or the pin can be grounded and the serial clock derived internally from MCLK. The required relationship between the Left/Right clock, serial clock and serial audio data is defined by the Serial Port Mode register. The options are detailed in Figures 10, 11, 12 and 13. SDOUT 4 SCLK 5 26 CS4228A LRCK 6 Left/Right Clock (Bidirectional) - The Left/Right clock determines which channel is currently being input or output on the serial audio data output, SDOUT. In Master mode, LRCK is an output, in Slave Mode, LRCK is an input whose frequency must be equal to Fs and synchronous to the Master clock. Audio samples in Left/Right pairs represent simultaneously sampled analog inputs whereas Right/Left pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Serial Port Mode register. The options are detailed in Figures 10, 11, 12 and 13 Digital Ground (Input) - Digital Ground Reference. Digital Power (Input) - Digital Power Supply. Digital Interface Power (Input) - Digital interface power supply. All digital output voltages and input threshholds scale with VL. Master Clock (Input) - The master clock frequency must be either 128x, 256x, 384x or 512x the input sample rate in Base Rate Mode (BRM) and either 64x, 128x, 192x, or 256x the input sample rate in High Rate Mode (HRM). Table 3 illustrates several standard audio sample rates and the required master clock frequencies. The MCLK/Fs ratio is set by the CI1:0 bits in the CODEC Clock Mode register. Sample Rate (kHz) 64x 32 44.1 48 64 4.0960 88.2 5.6448 96 6.1440 MCLK (MHz) HRM BRM 128x 192x 256x 128x 256x 384x 512x 4.0960 8.1920 12.2880 16.3840 5.6448 11.2896 16.9344 22.5792 6.1440 12.2880 18.4320 24.5760 8.1920 12.2880 16.3840 11.2896 16.9344 22.5792 12.2880 18.4320 24.5760 - DGND VD VL MCLK 7 8 9 10 Table 3. Common Master Clock Frequencies SCL/CCLK SDA/CDIN 11 12 Serial Control Interface Clock (Input) - Clocks the serial control data into or out of SDA/CDIN. Serial Control Data I/O (Bidirectional/Input) - In I2C mode, SDA is a bidirectional control port data line. A pull up resistor must be provided for proper open drain output operation. In SPI mode, CDIN is the control port data input line. The state of the SDOUT pin during reset is used to set the control port mode. Address Bit 0 / Chip Select (Input) - In I2C mode, AD0 is the LSB of the chip address. In SPI mode, CS is used as a enable for the control port interface. Reset (Input) - When low, the device enters a low power mode and all internal registers are reset to the default settings, including the control port. The control port can not be accessed when reset is low. When high, the control port and the CODEC become operational. Mute Control (Output) - The Mute Control pin goes low during the following conditions: power-up initialization, power-down, reset, no master clock present, or if the master clock to left/right clock frequency ratio is incorrect. The Mute Control pin can also be user controlled by the MUTEC bit in the DAC Mute2 Control register. Mute Control can be automatically asserted when 512 consecutive zeros are detected on all six DAC inputs, and automatically deasserted when a single non-zero value is sent to any of the six DACs. The mute on zero function is controlled by the MUTCZ bit in the DAC Mute2 Control register. The MUTEC pin is intended to be used as a control for an external mute circuit to achieve a very low noise floor during periods when no audio is present on the DAC outputs, and to prevent the clicks and pops that can occur in any single supply system. Use of the Mute Control pin is not mandatory but recommended. ADO/CS RST 13 14 MUTEC 15 27 CS4228A AINR+, AINR-, AINL+, AINL16, 17, 19, 20 Differential Analog Inputs (Input) - The analog signal inputs are presented differentially to the modulators via the AINR+/- and AINL+/- pins. The + and - input signals are 180° out of phase resulting in a nominal differential input voltage of twice the input pin voltage. These pins are biased to the internal reference voltage. A passive anti-aliasing filter is required for best performance, as shown in Figure 6. The inputs can be driven at -1 dB FS single-ended if the unused input is connected to ground through a large value capacitor. A single ended to differential converter circuit can also be used for slightly better performance. Internal Voltage Filter (Output) - Filter for internal circuits. An external capacitor is required from FILT to analog ground, as shown in Figure 6. FILT is not intended to supply external current. FILT+ has a typical source impedance of 250 kΩ and any current drawn from this pin will alter device performance. Care should be taken during board layout to keep dynamic signal traces away from this pin. Analog Power (Input) - Power for the analog and reference circuits. Analog Ground (Input) - Analog ground reference. Analog Outputs (Output) - Analog outputs from the DACs. The full scale analog output level is specified in the Analog Characteristics specifications table. The amplitude of the outputs is controlled by the Digital Volume Control registers 0x07 - 0x0C. FILT 18 VA AGND FR, FL, SR, SL SUB, CENTER 21 22 23, 24, 25, 26, 27, 28 28 CS4228A 7. PARAMETER DEFINITIONS Dynamic Range The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels. ADCs are measured at -1 dBFs as suggested in AES 17-1991 Annex A. Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the RMS analog output level with 1 kHz full scale digital input to the RMS analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of the test signal. Units in decibels. Interchannel Isolation A measure of crosstalk between channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in decibels. 29 CS4228A Gain Error The deviation from the nominal full scale output for a full scale input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For the DACs, the deviation of the output from zero (relative to CMOUT) with midscale input code. Units are in Volts. 30 CS4228A 8. PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING N D E11 A2 A1 A E ∝ L e b2 SIDE VIEW END VIEW SEATING PLANE 123 TOP VIEW DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0° INCHES NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4° MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8° MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0° MILLIMETERS NOM -0.15 1.75 -10.20 7.80 5.30 0.65 0.90 4° NOTE MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03 8° 2, 3 1 1 JEDEC #: MO-150 Controlling Dimension is Millimeters Notes: 1.“D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2.Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. 31