CS4239

CS4239 Advanced Product Databook FEATURES s Compatible with Sound Blaster™, Sound Blaster Pro™, and Windows Sound System™ s Integrated CrystalClear™ 3D Stereo Enhancement s Enhanced Stereo Full Duplex Operation s Dual Type-F DMA Support s Industry Leading Delta-Sigma Data Converters (86 dB FS A) s Default Internal PnP Resources s 3.3 V or 5 V ISA Bus Operation s APM and ACPI Compliant Power Management s Asynchronous Digital Serial Interface (ZVPORT) s CS4610 Audio Accelerator Interface s CS9236 Wavetable Interface s CS4236B/CS4237B/CS4238B Register Compatible CrystalClear™ Portable ISA Audio System DESCRIPTION The CS4239 is a single chip multimedia audio system that is a pin-compatible upgrade to the CS423xB for many designs. The product includes an integrated FM synthesizer and a Plug-and-Play interface. In addition, the CS4239 includes hardware master volume control pins as well as extensive power management and 3D sound technology. The CS4239 adds a Zoom-Video asynchronous digital serial interface to the industry standard CS423xB. The CS4239 is compatible with the Microsoft® Windows Sound System standard and will run software written to the Sound Blaster and Sound Blaster Pro interfaces. The CS4239 is fully compliant with Microsoft’s PC ’97 and PC ’98 audio requirements. ORDERING INFO CS4239-JQ 100 pin TQFP, 14x14x1.4mm CS4239-KQ 100 pin TQFP, 14x14x1.4mm XTALI XTALO VREF VREF INPUT MIXER OSCILLATOR SD SA IOR IOW AEN IOCHRDY IRQ DRQ DACK ISA BUS INTERFACE FIFO Stereo ADC1 Σ GAIN L/RAUX1 GAIN PLUG AND PLAY CODEC REG I/F GAIN FIFO Stereo DAC1 ATTN OUTPUT MIXER FM Synthesizer Stereo DAC2 L/RAUX2 CMAUX2 MIC Config IO IRQ DMA MIN Decode Logic Σ MPU-401 UART with FIFOS WSS SBPRO Registers 3D Enhancement ATTN L/ROUT SA 24 kHz 10 - Fs ≤ 12 kHz 11 - reserved DEN Playback PIO Enable: This bit determines whether the playback data is transferred via DMA or PIO. 0 - DMA transfers 1 - PIO transfers CPIO Capture PIO Enable: This bit determines whether the capture data is transferred via DMA or PIO. 0 - DMA transfers 1 - PIO transfers 38 DS253PP2 CS4239 CrystalClear Portable ISA Audio System XCTL1-XCTL0 XCTL Control: These bits are reflected on the XCTL1,0 pins of the part. NOTE: XCTL1 is multiplexed with other functions; therefore, it may not be available on a particular design. 0 - TTL logic low on XCTL1,0 pins 1 - TTL logic high on XCTL1,0 pins PUR Playback underrun: This bit is set when playback data has not arrived from the host in time to be played. As a result, if DACZ = 0, the last valid sample will be sent to the DACs. This bit is set when an error occurs and will not clear until the Status register (R2) is read. Capture overrun: This bit is set when the capture data has not been read by the host before the next sample arrives. The old sample will not be overwritten and the new sample will be ignored. This bit is set when an error condition occurs and will not clear until the Status register (R2) is read. TM Error Status and Initialization (I11, Read Only) Default = 00000000 D7 COR COR D6 PUR D5 ACI D4 DRS D3 D2 D1 ORL1 D0 ORL0 ORR1 ORR0 ORL1-ORL0 Overrange Left Detect: These bits determine the overrange on the left ADC channel. These bits are updated on a sample by sample basis. 0 - Less than -1.5 dB 1 - Between -1.5 dB and 0 dB 2 - Between 0 dB and 1.5 dB overrange 3 - Greater than 1.5 dB overrange The SER bit in the Status register (R2) is simply a logical OR of the COR and PUR bits. This enables a polling host CPU to detect an error condition while checking other status bits. MODE and ID (I12) Default = 100x1010 D7 1 ORR1-ORR0 Overrange Right Detect: These bits determine the overrange on the Right ADC channel. 0 - Less than -1.5 dB 1 - Between -1.5 dB and 0 dB 2 - Between 0 dB and 1.5 dB overrange 3 - Greater than 1.5 dB overrange D6 CMS1 D5 CMS0 D4 res D3 1 D2 0 D1 1 D0 0 res Reserved. Must write 0. Could read as 0 or 1. Codec Mode Select bits: Enables the Extended registers and functions of the part. 00 - MODE 1 01 - Reserved 10 - MODE 2 11 - MODE 3 CMS1,0 DRS DRQ Status: This bit indicates the current status of the DRQs assigned to the WSS Codec. 0 - Capture AND Playback DRQs are presently inactive 1 - Capture OR Playback DRQs are presently active ACI Auto-calibrate In-Progress: This bit indicates the state of calibration. 0 - Calibration not in progress 1 - Calibration is in progress Reserved (I13) Default = xxxxxxxx D7 rbc D6 rbc D5 rbc D4 rbc D3 rbc D2 rbc D1 res D0 rbc rbc res Reserved, backwards compatible. Reserved. Must write 0. Could read as 0 or 1. DS253PP2 39 CS4239 CrystalClear Portable ISA Audio System SPE DSP Serial Port Enable. When set, audio data from the ADCs is sent out SDOUT and audio data from SDIN is sent to the DACs. MCE in R0 must be set to change this bit. This bit is initialized through the Hardware Configuration data. 1 - Enable serial port 0 - Disable serial port. SF1,SF0 DSP Serial Format. Selects the format of the serial port when enabled by SPE. MCE in R0 must be set to change these bits. These bits are initialized through the Hardware Configuration data. 0 1 2 3 PMCE 64-bit enhanced. Figure 6. 64-bit. Figure 7. 32-bit. Figure 8. ADC/DAC. Figure 9. TM Playback Upper Base (I14) Default = 00000000 D7 PUB7 D6 PUB6 D5 PUB5 D4 PUB4 D3 PUB3 D2 PUB2 D1 PUB1 D0 PUB0 PUB7-PUB0 Playback Upper Base: This register is the upper byte which represents the 8 most significant bits of the 16-bit Playback Base register. Reads from this register return the same value which was written. The Current Count registers cannot be read. When set for MODE 1 or SDC, this register is used for both the Playback and Capture Base registers. Playback Lower Base (I15) Default = 00000000 D7 PLB7 D6 PLB6 D5 PLB5 D4 PLB4 D3 PLB3 D2 PLB2 D1 PLB1 D0 PLB0 PLB7-PLB0 Lower Base Bits: This register is the lower byte which represents the 8 least significant bits of the 16-bit Playback Base register. Reads from this register return the same value which was written. When set for MODE 1 or SDC, this register is used for both the Playback and Capture Base registers. Playback Mode Change Enable. When set, it allows modification of the stereo/mono and audio data format bits (D7-D4) for the playback channel, I8. MCE in R0 must be used to change the sample frequency. Capture Mode Change Enable. When set, it allows modification of the stereo/mono and audio data format bits (D7-D4) for the capture channel, I28. MCE in R0 must be used to change the sample frequency in I8. CMCE Alternate Feature Enable I (I16) Default = 0000eee0 D7 rbc D6 res D5 D4 D3 SF1 D2 SF0 D1 SPE D0 DACZ CMCE PMCE DACZ DAC Zero: This bit will force the output of the playback channel to AC zero when an underrun error occurs 1 - Go to center scale 0 - Hold previous valid sample Alternate Feature Enable II (I17) Default = 0000x000 D7 TEST D6 TEST D5 TEST D4 TEST D3 rbc D2 res D1 rbc D0 HPF HPF High Pass Filter: This bit enables a DC-blocking high-pass filter in the digital filter of the ADC. This filter forces the ADC offset to 0. 0 - disabled 1 - enabled 40 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TEST Factory Test. These bits are used for factory testing and must remain at 0 for normal operation. TM Control/RAM Access (I20) Default = xxxxxxxx D7 CR7 Left DAC2 Volume (I18) Default = 00000111 D7 D6 D5 D4 D3 D2 D1 LD2A1 D6 CR6 D5 CR5 D4 CR4 D3 CR3 D2 CR2 D1 CR1 D0 CR0 D0 LD2A0 LD2OM LD2IM rbc LD2A4 LD2A3 LD2A2 Note: When AUX1R in X18 is set, this register also controls the volume for the LAUX1 analog input. See I2 description for volume description of LAUX1. LD2A4-LD2A0 Left DAC2 Attenuation. The least significant bit represents 1.5 dB, with 01000 = 0 dB. The total range is +12 dB to -33.0 dB with 11111 = muted. See Table 8. LD2IM Left DAC2 Input Mute. When set, the left DAC2 to the input mixer is muted. Left DAC2 Output Mute. When set, the left DAC2 to the output mixer is muted. This register is identical to CTRLbase+5. For backwards compatibility, this register is not enabled until PAE in X18 is set. When PAE is clear, this register is read/writable, but does nothing. CR7-CR0 This register controls the loading of the part’s internal RAM as well as internal processor commands. See the Hostload Procedure section as well as CTRLbase+5 register description for more details. RAM Access End (I21) Default = xxxxxxxx D7 RE7 D6 RE6 D5 RE5 D4 RE4 D3 RE3 D2 RE2 D1 RE1 D0 RE0 LD2OM Right DAC2 Volume (I19) Default = 11000111 D7 D6 D5 rbc This register is identical to CTRLbase+6. For backwards compatibility, this register is not enabled until PAE in X18 is set. When PAE is clear, this register is read/writable, but does nothing. RE7-RE0 A 0 written to this location resets the previous location, I20, from data download mode, to command mode. D4 D3 D2 D1 D0 RD2OM RD2IM RD2A4 RD2A3 RD2A2 RD2A1 RD2A0 Note: When AUX1R in X18 is set, this register also controls the volume for the RAUX1 analog input. See I3 description for volume description of RAUX1. RD2A4-RD2A0 Right DAC2 Attenuation. The least significant bit represents 1.5 dB, with 01000 = 0 dB. The total range is +12 dB to -33.0 dB with 11111 = muted. See Table 8. RD2IM Right DAC2 Input Mute. When set, the Right DAC2 to the input mixer is muted. Right DAC2 Output Mute. When set, the right DAC2 to the output mixer is muted. Alternate Sample Frequency Select (I22) Default = 00000000 D7 SRE D6 DIV5 D5 DIV4 D4 DIV3 D3 DIV2 D2 DIV1 D1 DIV0 D0 CS2 CS2 Clock 2 Base Select. This bit selects the base clock frequency used for generating the audio sample rate. Note that the part uses only one crystal to generate both clock base frequencies. This bit can be disabled by setting IFSE in X11. 0 - 24.576 MHz base 1 - 16.9344 MHz base RD2OM DS253PP2 41 CS4239 CrystalClear Portable ISA Audio System DIV5 - DIV0 Clock Divider. These bits select the audio sample frequency for both capture and playback. These bits can be overridden by IFSE in X11. Fs = (2*XT)/(M*N) XT = 24.576 MHz CS2 = 0 XT = 16.9344 MHz CS2 = 1 N = DIV5-DIV0 16 ≤ N ≤ 49 for XT = 24.576 MHz 12 ≤ N ≤ 33 for XT = 16.9344 MHz (M set by OSM1,0 in I10) M = 64 for Fs > 24 kHz M = 128 for 12 kHz < Fs ≤ 24 kHz M = 256 for Fs ≤ 12 kHz SRE Alternate Sample Rate Enable. When this bit is set to a one, bits 0-3 of I8 will be ignored, and the sample frequency is then determined by CS2, DIV5-DIV0, and the oversampling mode bits OSM1, OSM0 in I10. Note that this register can be overridden (disabled) by IFSE in X11. TM Alternate Feature Status (I24) Default = x0000000 D7 res D6 rbc D5 CI D4 PI D3 CU D2 CO D1 PO D0 PU PU Playback Underrun: When set, indicates the DAC has run out of data and a sample has been missed. Playback Overrun: When set, indicates that the host attempted to write data into a full FIFO and the data was discarded. Capture Overrun: When set, indicates that the ADC had a sample to load into the FIFO but the FIFO was full. In this case, this bit is set and the new sample is discarded. Capture Underrun: Indicates the host has read more data out of the FIFO than it contained. In this condition, the bit is set and the last valid byte is read by the host. Playback Interrupt: Indicates an interrupt is pending from the playback DMA count registers. Capture Interrupt: Indicates an interrupt is pending from the capture DMA count registers. PO CO CU Extended Register Access (I23) Default = xxxxxxxx D7 XA3 PI D6 XA2 D5 XA1 D4 XA0 D3 XRAE D2 XA4 D1 res D0 rbc CI XA4 Extended Register Address bit 4. Along with XA3-XA0, enables access to extended registers X16 through X31. MODE 3 only. Extended Register Access Enable. Setting this bit converts this register from the extended address register to the extended data register. To convert back to an address register, R0 must be written. MODE 3 only. Extended Register Address. Along with XA4, sets the register number (X0-X31) accessed when XRAE is set. MODE 3 only. See the WSS Extended Register section for more details. XRAE The PI and CI bits are reset by writing a "0" to the particular interrupt bit or by writing any value to the Status register (R2). XA3-XA0 42 DS253PP2 CS4239 CrystalClear Portable ISA Audio System MIM Mono Input Mute. In MODE 3, MIM mutes the MIN analog input to the left output mixer channel. MIMR in X4 mutes MIN analog input to the right output mixer channel. In MODE 2, MIM mutes both left and right channels. The mono input provides mix for the "beeper" function in most personal computers. This bit is initialized through the Hardware Configuration data, Serial Port Control byte. 0 - no mute 1 - muted TM Compatibility ID (I25) Default = 00000011 D7 V2 D6 V1 D5 V0 D4 CID4 D3 CID3 D2 CID2 D1 CID1 D0 CID0 CID4-CID0 Chip Identification. Distinguishes between this chip and previous codec chips that support this register set. This register is fixed to indicate code compatibility with the CS4236. X25 or C1 should be used to further differentiate between parts that are compatible with the CS4236. 00011 - CS4236, CS423xB, CS4239 00010 - CS4232/CS4232A 00000 - CS4231/CS4231A Version number. As enhancements are made to the part, the version number is changed so software can distinguish between the different versions. 000 - Compatible with the CS4236 These bits are fixed for compatibility with the CS4236. Register X25 or C1 may be used to differentiate between the CS4236 and newer chips. LOS1,0 All Chips: Left Master Output Volume (I27) Default = 00100011 D7 D6 LOS1 D5 LOS0 D4 LOG4 D3 LOG3 D2 LOG2 D1 LOG1 D0 LOG0 V2-V0 LOM When Hardware Volume is enabled, VCEN in C8 or X24 is set, this register will change based on external buttons. LOG4-LOG0 Left Output, LOUT, Master Gain. LOG0 is the least significant bit and represents -2 dB, with 00011 = 0 dB. The span is nominally +6 dB to -56 dB. See Table 9. Left Output Mixer Select. These bits select and attenuation into the left output Master Gain stage, LOG4-0. 00 - -16 dB 01 - 0 dB 10 - -8 dB 11 - -24 dB LOM Left Output Mute. When set to 1, the left output, LOUT, is muted. Mono Input Control (I26) Default = exxxeeee D7 MIM D6 rbc D5 rbc D4 res D3 MIA3 D2 MIA2 D1 MIA1 D0 MIA0 MIA3-MIA0 Mono Input Attenuation. When MIM is 0, these bits set the level of MIN summed into the mixer. These bits are initialized through the Hardware Configuration data, Serial Port Control byte. 0000 = 0 dB. 0001-1111 = -9 dB DS253PP2 43 CS4239 CrystalClear Portable ISA Audio System ROS1,0 Right Output Mixer Select. These bits select and attenuation into the right output Master Gain stage, ROG4-0. 00 - -16 dB 01 - 0 dB 10 - -8 dB 11 - -24 dB ROM Right Output Mute. When set to 1, the right output, ROUT, is muted. TM Capture Data Format (I28) Default = x0x0xxxx D7 rbc D6 16B D5 rbc D4 S/M D3 res D2 res D1 res D0 res S/M Stereo/Mono Select: This bit determines how the capture audio data stream is formatted. Selecting stereo will result with alternating samples representing left and right audio channels. Selecting mono only captures data from the left audio channel. MCE (R0) or CMCE (I16) must be set to modify S/M. See Changing Audio Data Formats section for more details. 0 - Mono 1 - Stereo Capture Upper Base (I30) Default = 00000000 D7 CUB7 D6 CUB6 D5 CUB5 D4 CUB4 D3 CUB3 D2 CUB2 D1 CUB1 D0 CUB0 CUB7-CUB0 16B selects between 8-bit unsigned and 16-bit signed data for capture. The capture data format can be different than the playback data format. MCE (R0) or CMCE (I16) must be set to modify this register. See Changing Audio Data Formats section for more details. 0 - 8-bit unsigned data 1 - 16-bit signed data Capture Upper Base: This register is the upper byte which represents the 8 most significant bits of the 16-bit Capture Base register. Reads from this this register returns the same value that was written. Capture Lower Base (I31) Default = 00000000 D7 CLB7 D6 CLB6 D5 CLB5 D4 CLB4 D3 CLB3 D2 CLB2 D1 CLB1 D0 CLB0 CLB7-CLB0 Right Master Output Volume (I29) Default = 00100011 D7 ROM Lower Base Bits: This register is the lower byte which represents the 8 least significant bits of the 16-bit Capture Base register. Reads from this register returns the same value which was written. D6 ROS1 D5 ROS0 D4 ROG4 D3 ROG3 D2 ROG2 D1 ROG1 D0 ROG0 When Hardware Volume is enabled, VCEN in C8 or X24 is set, this register will change based on external buttons. ROG4-ROG0 Right Output, ROUT, Master Gain. ROG0 is the least significant bit and represents -2 dB, with 00011 = 0 dB. The span is nominally +6 dB to -56 dB. See Table 9. 44 DS253PP2 CS4239 CrystalClear Portable ISA Audio System Address WSSbase+0 WSSbase+1 Reg. R0 R1 I23 Register Name Reset Address Address/Data access Indexed Address/Data TM WSS EXTENDED REGISTERS T he Windows Sound System codec contains three sets of registers: R0-R3, I0-I31, and X0X31. R0-R3 are directly mapped to the ISA bus through WSSbase+0 through WSSbase+3 respectively. R0 and R1 provide access to the indirect registers I0-I31. The third set of registers are extended registers X0-X31 that are indirectly mapped through the WSS register I23. I23 acts as both the extended address and extended data register. These extended registers are only available when in MODE 3. Accessing the X registers requires writing the register address to I23 with XRAE set. When XRAE is set, I23 changes from an address register to a data register. Subsequent accesses to I23 access the extended data register. To convert I23 back to the extended address register, R0 must be written which internally clears XRAE. Assuming the part is in MODE 3, the following steps access the X registers: 1. Write 17h to R0 (to access I23). R1 is now the extended address register. 2. Write the desired X register address to R1 with XRAE = 1. R1 is now the extended data register. 3. Write/Read X register data from R1. To read/write a different X register: 4. Write 17h to R0 again. (resets XRAE) R1 is now the extended address register. 5. Write the new X register address to R1 with XRAE = 1. R1 is now the new extended data register. 6. Read/Write new X register data from R1. Extended Register Access (I23) D7 XA3 D6 XA2 D5 XA1 D4 XA0 D3 XRAE D2 XA4 D1 res D0 rbc Table 11. WSS Extended Register Control Index X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 Register Name Reserved, backwards compatible Reserved, backwards compatible MIC Volume MIC Volume (same as X2) Synthesis and Input Mixer Control Right Input Mixer Control Left FM Synthesis Mute Right FM Synthesis Mute Left DSP Serial Port Mute Right DSP Serial Port Mute Reserved, backwards compatible DAC1 Mute and IFSE Enable Independent ADC Sample Freq. Independent DAC Sample Freq. Reserved, backwards compatible Reserved, backwards compatible Left Wavetable Serial Port Mute Right Wavetable Serial Port Mute 3D Enable & RAM Port Enable FM Volume Scaling Reserved Reserved Reserved (C2) 3D Space Control (C8) Wavetable & Volume Control Chip Version and ID (Cb+0) Joystick Control (Cb+1) E2PROM Interface (Cb+2) Power Down Control 1 (C9) Power Down Control 2 (Cb+7) Global Status Reserved Table 12. WSS Extended Registers DS253PP2 45 CS4239 CrystalClear Portable ISA Audio System TM Control Registers for the Extended Registers ADDRESS WSSbase+0 R0 WSSbase+1 R1 I23 D7 INIT ID7 XA3 D6 MCE ID6 XA2 D5 TRD ID5 XA1 D4 IA4 ID4 XA0 D3 IA3 ID3 XRAE D2 IA2 ID2 XA4 D1 IA1 ID1 - D0 IA0 ID0 - Extended Registers: (X0-X31) XA4 - XA0 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 (C2) X24 (C8) X25 X26 (Cb+0) X27 (Cb+1) X28 (Cb+2) X29 (C9) X30 (Cb+7) X31 D7 LMIM RMIM MIMR LFMM RFMM LSPM RSPM LD1IM SRAD7 SRDA7 LWM RWM PAE SPC3 VCIE V2 ICH PDWN RESET CWSS - D6 LMOM RMOM LIS1 RIS1 RD1IM SRAD6 SRDA6 FMS2 SPC2 VCF1 V1 SRC ICTRL - D5 MBST MBST LIS0 RIS0 IFSE SRAD5 SRDA5 AUX1R FMS1 SPC1 V0 CONSW VREF ISB - D4 MG4 MG4 IFM SRAD4 SRDA4 3DEN FMS0 SPC0 CID4 MIX IWSS - D3 MG3 MG3 SRAD3 SRDA3 DSPD1 WTEN CID3 ADC IMPU - D2 MG2 MG2 SRAD2 SRDA2 PSH VCEN CID2 DIN/EEN DAC MIXCD WDT - D1 MG1 MG1 SRAD1 SRDA1 ZVEN DMCLK CID1 JR1 DOUT PROC DAC2 IMV - D0 MG0 MG0 SRAD0 SRDA0 DLEN BRES CID0 JR0 CLK FM SPORT ZVA - Table 13. Extended Register Bit Summary 46 DS253PP2 record PnP ISA Interface playback DS253PP2 Wavetable Enable C8 s CS9236 or CS4610 SERIAL PORT Mute X2L, X3R DSP Port Enable I16 s s s 20dB Gain X2 Gain X2 s s s s s MIC * Mute I2L, I3R s Analog Input Mixer ADC1 * Gain I2L I3R s s s s s AUX1 (LINE IN) Σ Atten. X4L X5R Mute I4L, I5R s Gain I4L I5R s s s s s s AUX 2 (CDROM) s s Mute I18L I19R s Loopback Enable I0L, I1R s s DSPD1 Enable X18 Loop Enable X18 Atten. I6L I7R Mute X16L X17R s Mute X11L X11R s s Mute X2L, X3R s s * Mute I2L, I3R s DAC1 s Mute I6L I7R s Mute I4L, I5R CrystalClear Portable ISA Audio System s Mute X8L X9R s Gain I18L I19R s s s s s ZVPort Enable X18 s s s s s s s DAC2 Mute I18L I19R s Σ s s Atten. X27L X29R Gain I27L Mute I27L I29R I29R s s s s s s LINE OUT TM Σ Mute X6L X7R s Analog Output Mixer Mute I26L X4R s Atten. I26 s s s s FM Syn. Enable X4 s * I2/I3 can be remapped to be controlled through I18/I19. CS4239 ZVPORT MIN UP/DOWN/MUTE Figure 4. Mixer Block Diagram 47 CS4239 CrystalClear Portable ISA Audio System TM Reserved (X0) Default = xxxxxxxx D7 rbc Right Channel MIC (X3) Default = 01011111 D4 rbc D6 rbc D5 rbc D3 rbc D2 rbc D1 rbc D0 rbc D7 D6 D5 D4 MG4 D3 MG3 D2 MG2 D1 MG1 D0 MG0 RMIM RMOM MBST rbc Reserved, backwards compatible. MG4-MG0 Reserved (X1) Default = xxxxxxxx D7 rbc Microphone gain. The least significant bit represents 1.5 dB, with 01111 = 0 dB. These are the same bits as in X2. See Table 9. Microphone 20 dB boost. When set to 1, the MIC input is gained by 20 dB. This is the same bit as in X2. Microphone Right Output Mixer Mute. When set to 1, the signal to the right channel output mixer is muted. Microphone Right Input Mixer Mute. When set to 1, the signal to the right channel input mixer is muted. D6 rbc D5 rbc D4 rbc D3 rbc D2 rbc D1 rbc D0 rbc MBST rbc Reserved, backwards compatible. RMOM D3 MG3 MIC Volume (X2) Default = 01011111 D7 D6 D5 D4 MG4 D2 MG2 D1 MG1 D0 MG0 LMIM LMOM MBST RMIM MG4-MG0 Microphone Gain. The least significant bit represents 1.5 dB, where 01111 = 0 dB and 11110 = -22.5 dB. When all bits are 1, the Mic is muted with one exception. If MBST = 1 when going from 11110 to 11111, the Mic volume does not change. The attenuation steps are shown in Table 9. Microphone 20 dB boost. When set to 1, the MIC input is gained by 20 dB. Microphone Left Output Mixer Mute. When set to 1, the signal to the left channel output mixer is muted. Microphone Left Input Mixer Mute. When set to 1, the signal to the left channel input mixer is muted. Synthesis and Input Mixer Control (X4) Default = e00exxxx D7 MIMR D6 LIS1 D5 LIS0 D4 IFM D3 rbc D2 rbc D1 res D0 res IFM MBST Internal FM enable. When set to 1, the internal FM synthesis engine is enabled. This bit can be set through the Hardware Configuration data in the EEPROM. Left Input Mixer Summer Attenuator. This attenuates the inputs to the left input mixer to enable overload protection when multiple input sources are utilized. 00 - 0 dB 01 - -6 dB 10 - -12 dB 11 - -18 dB LMOM LIS1-LIS0 LMIM 48 DS253PP2 CS4239 CrystalClear Portable ISA Audio System MIMR Mono Input Mute to the Right Output mixer. When set to 1, the MIN signal to the right output mixer is muted. The default state of this bit is set by MIM in the Hardware Configuration Data, Mono & DSP Port byte. TM Left DSP Serial Port Mute (X8) Default = exxxxxxx D7 LSPM D6 res D5 rbc D4 rbc D3 rbc D2 rbc D1 rbc D0 rbc Right Input Mixer Control (X5) Default = x00xxxxx D7 rbc LSPM D2 res D6 RIS1 D5 RIS0 D4 res D3 res D1 res D0 res Left DSP Serial Port Mute. When set to 1, the Left DSP Serial Port input (SDIN) is muted. The default state of this bit is the inverse of SPE in the Hardware Configuration Data, Mono & DSP Port byte. RIS1-RIS0 Right Input Mixer Summer Attenuator. This attenuates the inputs to the right input mixer to enable overload protection when multiple input sources are utilized. 00 - 0 dB 01 - -6 dB 10 - -12 dB 11 - -18 dB Right DSP Serial Port Mute (X9) Default = exxxxxxx D7 RSPM D6 res D5 rbc D4 rbc D3 rbc D2 rbc D1 rbc D0 rbc RSPM Left FM Synthesis Mute (X6) Default = exxxxxxx D7 LFMM Right DSP Serial Port Mute. When set to 1, the Right DSP Serial Port input (SDIN) is muted. The default state of this bit is the inverse of SPE in the Hardware Configuration Data, Mono & DSP Port byte. D6 res D5 rbc D4 rbc D3 rbc D2 rbc D1 rbc D0 rbc Reserved (X10) Default = xxxxxxxx D7 rbc LFMM Left FM mute. When set to 1, the left internal FM input to DAC2 is muted. The default state of this bit is the inverse of IFM in the Hardware Configuration Data, Global Configuration byte. D6 res D5 rbc D4 rbc D3 rbc D2 rbc D1 rbc D0 rbc rbc Reserved, backwards compatible. Right FM Synthesis Mute (X7) Default = exxxxxxx D7 RFMM DAC1 Mute and IFSE Enable (X11) Default = 110xxxxx D7 D2 rbc D6 RD1IM D5 IFSE D4 res D3 res D2 res D1 res D0 res D6 res D5 rbc D4 rbc D3 rbc D1 rbc D0 rbc LD1IM IFSE RFMM Right FM mute. When set to 1, the right internal FM input to DAC2 is muted. The default state of this bit is the inverse of IFM in the Hardware Configuration Data, Global Configuration byte. RD1IM Independent Sample Freq. Enable. When set to 1, the extended registers X12 and X13 are used to set the sample rate, and registers I8, I10 (OSM1,0), and I22 are ignored. X12 and X13 cannot be modified unless this bit is set to 1. Right DAC1 Input Mixer Mute. When set to 1, the output from the Right DAC1 is muted to the Right input mixer. See Figure 4. 49 DS253PP2 CS4239 CrystalClear Portable ISA Audio System LD1IM Left DAC1 Input Mixer Mute. When set to 1, the output from the Left DAC1 is muted to the Left input mixer. See Figure 4. TM Right Wavetable Serial Port Mute (X17) Default = exxxxxxx D7 D6 res D5 rbc D4 rbc D3 rbc D2 rbc D1 rbc D0 rbc Independent ADC Fs (X12) Default = xxxxxxxx D7 D6 D5 D4 D3 D2 D1 D0 SRAD7 SRAD6 SRAD5 SRAD4 SRAD3 SRAD2 SRAD1 SRAD0 RWM RWM SRAD7-SRAD0 Sample Rate frequency select for the A/D converter. See Table 10. Right Wavetable Serial Port Mute. When set, the Right Wavetable Serial Input to DAC2 is muted. The default state of this bit is the inverse of WTEN in the Hardware Configuration Data, Global Configuration byte. Independent DAC Fs (X13) Default = xxxxxxxx D7 D6 D5 D4 D3 D2 D1 D0 SRDA7 SRDA6 SRDA5 SRDA4 SRDA3 SRDA2 SRDA1 SRDA0 3D and RAM Port Enable (X18) Default = 0xeeeee0 D7 PAE D6 res D5 AUX1R D4 3DEN D3 D2 D1 D0 DLEN DSPD1 PSH ZVEN SRDA7-SRDA0 Sample Rate frequency select for the D/A converter. See Table 10. DLEN Reserved, backwards compatible (X14) Default = xxxxxxxx D7 rbc Digital Loopback Enable. When set, the input to DAC1 to comes from the ADCs. While DLEN is on, no other data is sent to DAC1. This provides a test path that is generally not used in normal operation. ZVPORT Enable. When set, the ZVPORT pins are enabled and selected as input to DAC2. While the ZVPORT is enabled, no other input to DAC2 is allowed (synthesizers or DSP). Playback Sample Hold. When set, the last sample is held in DAC1 when PEN is cleared. When clear, zero is sent to DAC1 when PEC is cleared. DSP port controls DAC1. When set, the serial DSP port controls DAC1 instead of the ISA playback FIFO. 3D Sound Enable. When set, 3D sound is enabled on L/ROUT. This bit is also controlled through C3. AUX1 Remap. When set, writes to I18/19 (DAC2 volume) also control the AUX1 volume. When clear, I18/19 control DAC2 volume and I2/3 control AUX1 volume. This bit provides some backwards compatibil- D6 rbc D5 rbc D4 rbc D3 rbc D2 rbc D1 rbc D0 rbc ZVEN rbc Reserved, backwards compatible. Reserved, backwards compatible (X15) Default = xxxxxxxx D7 rbc D6 rbc D5 rbc D4 rbc D3 rbc D2 rbc D1 rbc D0 rbc PSH rbc Reserved, backwards compatible. DSPD1 Left Wavetable Serial Port Mute (X16) Default = exxxxxx D7 LWM D6 res D5 rbc D4 rbc D3 rbc D2 rbc D1 rbc D0 rbc 3DEN LWM Left Wavetable Serial Port Mute. When set, the Left Wavetable Serial Input to DAC2 is muted. The default state of this bit is the inverse of WTEN in the Hardware Configuration Data, Global Configuration byte. AUX1R 50 DS253PP2 CS4239 CrystalClear Portable ISA Audio System ity when AUX1 analog inputs are substituted for LINE analog inputs which are no longer available. PAE Processor Access Enable. When set, I20/21 provide access to the Processor identically to CTRLbase+5/+6 respectively. TM 3D Space Control (X23) Default = 0000xxxx D7 SPC3 D6 SPC2 D5 SPC1 D4 SPC0 D3 res D2 D1 res res D0 res This register and C2 access the same data. SPC3-SPC0 Space control for 3D sound. Control’s the "width" of the sound expansion with increasing numbers giving decreasing space affects. The least sigificant bit represents 1.5 dB of attenuation, with 0000 = 0 dB (full space affect). FM Volume Scaling (X19) Default = xeeexxxx D7 res D6 FMS2 D5 D4 D3 res D2 res D1 res D0 res FMS1 FMS0 FMS2-FMS0 FM Volume Scaling relative to wavetable digital input. These bits are provided for backwards compatibility with previous chips. These bits are initialized through Hardware Configuration data. 010 - 0 dB 011 - +6 dB 100 - -12 dB 101 - -6 dB 110 - +12 dB 111 - +18 dB CS9236 Wavetable Control (X24) Default = 0exxee00 D7 VCIE D6 VCF1 D5 res D4 res D3 WTEN D2 D1 D0 VCEN DMCLK BRES This register and C8 access the same data. BRES Force BRESET low. When set, the BRESET pin is forced low. Typically used for power management of peripheral devices. Disable MCLK. When set, the MCLK pin of the CS9236 Wavetable Synthesizer serial interface is forced low providing a power savings mode. Volume Control Enable. When set, the UP, DOWN, and MUTE pins become active and provide hardware master volume control for the line outputs. Note that this bit can be initialized at power-up through Hardware Configuration data, Misc. Configuration Byte. Wavetable Serial Port Enable. When, set, the CS9236 Single-Chip Wavetable Music Synthesizer serial port pins are enabled. WTEN can be initialized in the E2PROM Hardware Configuration data, Global Configuration byte. Reserved (X20) Default = xxxxxxxx D7 res DMCLK D4 res D6 res D5 res D3 res D2 res D1 res D0 res res Reserved. Could read as 0 or 1. VCEN Reserved (X21) Default = xxxxxxxx D7 res D6 res D5 res D4 res D3 res D2 res D1 res D0 res res Reserved. Could read as 0 or 1. WTEN Reserved (X22) Default = xxxxxxxx D7 res D6 res D5 res D4 res D3 res D2 res D1 res D0 res res Reserved. Could read as 0 or 1. DS253PP2 51 CS4239 CrystalClear Portable ISA Audio System VCF1 Hardware Volume Control Format. This bit controls the format of the UP, DOWN, and MUTE pins. VCF1 is initialized in the E2PROM Hardware Configuration data, Global Configuration byte. 0 - MUTE is a momentary button. Pressing MUTE toggles between mute and un-mute. Pressing UP or DOWN will always un-mute. 1 - MUTE is not used. Pressing the up and down buttons simultaneously causes the volume to mute. Pressing up or down singularly will un-mute. VCIE Volume Control Interrupt Enable. When set, the hardware volume control pins cause interrupts, when pressed, on the WSSint pin. The status is available in CTRLbase+7, IMV bit. The IMV bit is cleared by reading CTRLbase+7. TM Joystick Control (X26) Default = xx0x0x01 D7 rbc D6 rbc D5 CONSW D4 rbc D3 ZERO D2 rbc D1 D0 JR1 JR0 X26 and CTRLbase+0 access the same data with the exception that the XTAL bit in CTRLbase is replaced with ZERO in this register. JR1,0 Joystick rate control. Selects operating speed of the joystick (changes the trigger threshold for the X/Y coordinates). 00 - slowest speed 01 - medium slow speed 10 - medium fast speed 11 - fastest speed ZERO This bit MUST be written to 0. Writing this bit to 1 will disable all accesses to the WSS register space. controls host interrupt generation when a context switch occurs 0 - no interrupt on context switch 1 - Control interrupt generated on context switch CONSW Chip Version and ID (X25) Default = 11011110 D7 V2 D6 V1 D5 V0 D4 CID4 D3 CID3 D2 CID2 D1 CID1 D0 CID0 CID5-CID0 Chip Identification. Distinguishes between this chip and other codec chips that support this register set. This register is identical to C1 and replaces the ID register in I25. 11110 - CS4239 E2PROM Interface (X27) CTRLbase+1, Default = 1xxxx000 D7 ICH D6 rbc D5 rbc D4 rbc D3 rbc D2 DIN/ EEN D1 DOUT D0 CLK X27 and CTRLbase+1 access the same data. CLK V2-V0 Version Number. As enhancements are made, the version number is changed so software can distinguish between the different versions of the same chip. DOUT 100 - Revision A 101 - Revision B 110 - Revision C This bit is used to generate the clock for the Plug and Play E2PROM. EEN must be set to 1 to make this bit operational. A 1 sets the SCL pin high and a 0 sets the SCL pin low. This bit is used to output serial data to the Plug and Play E2PROM. EEN must be set to 1 to make this bit operational. A 0 causes SDA to go low. A 1 releases SDA (open-drain). 52 DS253PP2 CS4239 CrystalClear Portable ISA Audio System DIN/EEN When read (DIN), this bit reflects the SDA pin, which should be serial data output from the Plug and Play E2PROM. EEN and DOUT must be 1 for this bit to function. When written (EEN), enables the E2PROM interface: CLK and DOUT onto the SCL/SDA pins. Writing: 0 - E2PROM interface disabled 1 - E2PROM interface enabled ICH Interrupt polarity - CDROM. When set, the CDINT pin is an active high signal. When low, CDINT is an active low signal. This bits can be initialized through the Hardware Configuration data. this chip will be lost, including this one, since the power-up state for PnP is all resources unassigned. TM Global Status (X30) CTRLbase+7, Default = 1000000 D7 CWSS D6 ICTRL D5 ISB D4 IWSS D3 IMPU D2 D1 D0 ZVA WDT IMV X30 and CTRLbase+7 access the same data. ZVA ZVPORT Active. When set, indicates that data is being received on the ZVPORT pins. Hardware Master Volume Control Interrupt Status. A hardware volume control interrupt is pending when set to 1. Master Volume Interrupts are enabled through VCIE in C8/X24. Watch-Dog Timer. If an error occurs on the ISA bus, the Processor will be reset and WDT will be set. MPU-401 Interrupt status. MPU interrupt pending when set to 1. Windows Sound System Interrupt Status. WSS interrupt pending when set to 1. Sound Blaster Interrupt status. Sound Blaster interrupt pending when set to 1. Control Logical Device 2 Interrupt status. A context switch interrupt is pending when set to 1. Context - WSS. Indicates the current context. 0 - Sound Blaster Emulation 1 - Windows Sound System IMV Block Power Down (X28) Default = 00000000 D7 PDWN D6 SRC D5 VREF D4 MIX D3 ADC1 D2 DAC1 D1 PROC D0 FM WDT This register and CTRLbase+2 access the same data. See CTRLbase+2 for a detailed description of each bit. IMPU IWSS Power Management (X29) Default = 0xxxx000 D7 RESET D6 res D5 res D4 res D3 res D2 MIXCD D1 DAC2 D0 SPORT ISB This register and C9 access the same data. ICTRL SPORT DAC2 Powers down the serial ports. Powers down DAC2 including FM and the CS9236 serial interface. Powers down the analog mixer - with the exception of MIN, AUX2, and the line outputs. When this bit goes from a 1 to a 0, a software RESDRV is initiated causing the entire chip to be reset and placed in its default power-up configuration. Access to all registers on CWSS MIXCD RESET Reserved (X31) Default = xxxxxxxx D7 res D6 res D5 res D4 res D3 res D2 res D1 res D0 res res DS253PP2 Reserved. Could read as 0 or 1. 53 CS4239 CrystalClear Portable ISA Audio System TM SOUND BLASTER INTERFACE The Sound Blaster Pro compatible interface is the third physical device in logical device 0. Since the WSS Codec and the Sound Blaster are mutually exclusive, the WSS Codec interrupt and playback DMA channel are shared with the Sound Blaster interface. Mode Switching To facilitate switching between different functional modes (i.e. Sound Blaster and Windows Sound System), logic is included to handle the switch transparently to the host. No special software is required on the host side to perform the mode switch. Sound Blaster Direct Register Interface The Sound Blaster software interface utilizes 10bit address decoding and is compatible with Sound Blaster and Sound Blaster Pro interfaces. 10-bit addressing requires that the upper address bits be 0 to decode a valid address, i.e. no aliasing occurs. This device requires 16 I/O locations Address SBbase+0 SBbase+0 SBbase+1 SBbase+2 SBbase+2 SBbase+3 SBbase+4 SBbase+5 SBbase+6 SBbase+8 SBbase+8 SBbase+9 SBbase+A SBbase+C SBbase+C SBbase+E located at the PnP address ’SBbase’. The following registers, shown in Table 14, are provided for Sound Blaster compatibility. Left/Right FM Registers, SBbase+0 - SBbase+3 These registers are mapped directly to the appropriate FM synthesizer registers. Mixer Address Register, SBbase+4, write only This register is used to specify the index address for the mixer. This register must be written before any data is accessed from the mixer registers. The mixer indirect register map is shown in Table 15. Mixer Data Register, SBbase+5 This register provides read/write access to a particular mixer register depending on the index address specified in the Mixer Address Register. Description Left FM Status Port Left FM Register Status Port Left FM Data Port Right FM Status Port Right FM Register Status Port Right FM Status Port Mixer Register Address Mixer Data Port Reset FM Status Port FM Register port FM Data Port Read Data Port Command/Write Data Write Buffer Status (Bit 7) Data Available Status (Bit 7) Type Read Write Write Only Read Write Write Only Write Only Read/Write Write Only Read Only Write Write Only Read Only Write Read Read Table 14. Sound Blaster Pro Compatible I/O Interface 54 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM Reset SBbase+6, write only When bit D[0] of this register is set to a one and then set to a zero, a reset of the Sound Blaster interface will occur. Read Data Port SBbase+A, read only When bit D[7] of the Data Available Register, SBbase+E, is set =1 then valid data is available in this register. The data may be the result of a Command that was previously written to the Command/Write Data Register or digital audio data. Command/Write Data SBbase+C, write only The Command/Write Data register is used to send Sound Blaster Pro commands. Write Buffer Status, SBbase+C, read only The Write Buffer Status register bit D[7] indicates when the SBPro interface is ready to accept another command to the Command/Write Data register. D[7]=1 indicates ready. D[7]=0 indicates not ready. Sound Blaster Mixer Registers The Sound Blaster mixer registers are shown in Table 15. Reset Register, Mixer Index 00H Writing any value to this register will reset the mixer to default values. Voice Volume Register, Mixer Index 04H, Default = 99H This register provides 8 steps of voice volume control each for the right and left channels. Microphone Mixing Register, Mixer Index 0AH, Default = 01H This register provides 4 steps of microphone volume control. Register 00H 02H 04H 06H 08H 0AH 0CH 0EH 20H 22H 24H 26H 28H 2AH 2CH 2EH D7 D6 D5 D4 D3 DATA RESET RESERVED RESERVED RESERVED X X X X X RESERVED RESERVED D2 D1 D0 VOICE VOLUME LEFT VOICE VOLUME RIGHT X X X X X X X X MIC MIXING INPUT SELECT X VSTC MASTER VOLUME RIGHT FM VOLUME RIGHT CD VOLUME RIGHT X X MASTER VOLUME LEFT FM VOLUME LEFT CD VOLUME LEFT RESERVED RESERVED LINE VOLUME LEFT LINE VOLUME RIGHT Table 15. SBPro Compatible Mixer Interface DS253PP2 55 CS4239 CrystalClear Portable ISA Audio System TM Input Control Register, Mixer Index 0CH This register selects the input source to the ADC. D2,D1 - 00 - Microphone 01 - CD Audio 10 - Microphone 11 - Line In Output Control Register, Mixer Index 0EH VSTC - 0 - Mono Mode 1 - Stereo Mode Master Volume Register, Mixer Index 22H, Default = 99H This register provides 8 steps of master volume control each for the right and left channels. FM Volume Register, Mixer Index 26H, Default = 99H This register provides 8 steps of FM volume control each for the right and left channels. CD Volume Register, Mixer Index 28H, Default = 01H This register provides 8 steps of CD volume control each for the right and left channels. Line-In Volume Register, Mixer Index 2EH, Default = 01H This register provides 8 steps of line-in volume control each for the right and left channels. GAME PORT INTERFACE The Game Port logical device software interface utilizes 10-bit address decoding and is located at PnP address ’GAMEbase’. 10-bit addressing requires that the upper address bits be 0 to decode a valid address, i.e. no aliasing occurs. For backwards compatibility, the Game Port consists of 8 I/O locations which alias to the same location, consisting of one read and one write register. Plug and Play configuration capability will allow the joystick I/O base address, GAMEbase, to be located anywhere within the host I/O address space. Currently most games software assume that the joystick I/O port is located at 200h. A write to the GAMEbase register triggers four timers. A read from the same register returns four status bits corresponding to the joystick fire buttons and four bits that correspond to the output from the four timers. A button value of 0 indicates the button is pressed or active. The button default state is 1. When GAMEbase is written, the X/Y timer bits go high. Once GAMEbase is written, each timer output remains high for a period of time determined by the current joystick position. The number in parenthesis below is the joystick connector pin number. GAMEbase+0 - GAMEbase+7 D7 JBB2 D6 JBB1 D5 JAB2 D4 JAB1 D3 JBCY D2 JBCX D1 JACY D0 JACX JACX JACY JBCX JBCY Joystick A, Coordinate X (pin 3) Joystick A, Coordinate Y (pin 6) Joystick B, Coordinate X (pin 11) Joystick B, Coordinate Y (pin 13) JAB1 JAB2 JBB1 JBB2 Joystick A, Button 1 (pin 2) Joystick A, Button 2 (pin 7) Joystick B, Button 1 (pin 10) Joystick B, Button 2 (pin 14) 56 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM Two bits, JR1 and JR0, are located in the Control register space (CTRLbase+0) for defining the speed of the Game Port Interface. Four different rates are software selectable for use with various joysticks and to support older software timing loops with aliasing (roll-over) problems. The Game Port hardware interface consists of 8 pins that connect directly to the standard game port connector. Buttons must have a 1000 pF capacitor to ground and have internal 20 kΩ pullups resistors. X/Y coordinates must have a 5.6 nF capacitor to ground and a 2.2 kΩ series resistor to the appropriate joystick connector pin. Figure 5 illustrates the schematic to the joystick connector. VDF CRYSTAL CODEC JAB1 JBB1 JACX JBCX 5.6 nF 2.2 k Ω 2.2 k Ω 5.6 nF 1 nF 1 nF 1 9 2 10 3 11 4 12 5 JBCY JACY JBB2 JAB2 5.6 nF 5.6 nF 1 nF 1 nF 2.2 k Ω 2.2 k Ω 13 6 14 7 15 MIDOUT MIDIN 8 Figure 5. Joystick Logic DS253PP2 57 CS4239 CrystalClear Portable ISA Audio System TM CONTROL INTERFACE The Control logical device includes registers for controlling various functions of the part that are not included in the other logical device blocks. These functions include game port rate control and programmable power management, as well as extra mixing functions. Control Register Interface The Control logical device software interface occupies 8 I/O locations, utilizes 12-bit address decoding, and is located at PnP address ’CTRLbase’. If the upper address bits, SA12SA15 are used, they must be 0 to decode a valid address. This device can also support an interrupt. Table 16 lists the eight Control registers. Address CTRLbase+0 CTRLbase+1 CTRLbase+2 CTRLbase+3 CTRLbase+4 CTRLbase+5 CTRLbase+6 CTRLbase+7 Register Joystick Control E2PROM Interface Block Power Down Control Indirect Address Reg. Control Indirect Data Register Control/RAM Access RAM Access End Global Status Table 16. Control Logical Device Registers E2PROM Interface CTRLbase+1, Default = 1xxxx000 D7 ICH D6 rbc D5 rbc D4 rbc D3 rbc D2 DIN/ EEN D1 DOUT D0 CLK Joystick Control CTRLbase + 0, Default = xx0x0x01 D7 rbc CLK D2 rbc D6 rbc D5 CONSW D4 rbc D3 XTAL D1 D0 JR1 JR0 This bit is used to generate the clock for the Plug and Play E2PROM. EEN must be set to 1 to make this bit operational. A 1 sets the SCL pin high and a 0 sets the SCL pin low. This bit is used to output serial data to the Plug and Play E2PROM. EEN must be set to 1 to make this bit operational. A 0 causes SDA to go low. A 1 releases SDA (open-drain). When read (DIN), this bit reflects the SDA pin, which should be serial data output from the Plug and Play E2PROM. EEN and DOUT must be 1 for this bit to function. When written (EEN), enables the E2PROM interface: CLK and DOUT onto the SCL/SDA pins. Writing: 0 - E2PROM interface disabled 1 - E2PROM interface enabled JR1,0 Joystick rate control. Selects operating speed of the joystick (changes the trigger threshold for the X/Y coordinates). 00 - slowest speed 01 - medium slow speed 10 - medium fast speed 11 - fastest speed DOUT DIN/EEN XTAL Crystal Oscillator disable. When set, all functions are disabled except access to this register. All registers retain their values in this power-down mode. controls host interrupt generation when a context switch occurs 0 - no interrupt on context switch 1 - Control interrupt generated on context switch ICH CONSW Interrupt polarity - CDROM. When set, the CDINT pin is an active high signal. When low, CDINT is an active low signal. This bits can be initialized through the Hardware Configuration data. 58 DS253PP2 CS4239 CrystalClear Portable ISA Audio System NOTE: Software should mute the DACs and Mixers and FM volume when asserting any power-down modes to prevent clicks and pops. D1 PROC TM Block Power Down CTRLbase+2, Default = 00000000 D7 PDWN D6 SRC D5 VREF D4 MIX D3 ADC1 D2 DAC1 D0 FM Control Indirect Address Register CTRLbase+3 D7 res FM Internal FM synthesizer powered down when set. Processor set to idle mode. When set, places the internal processor in an idle state. This effects the PnP interface, MPU401, and SBPro devices. Any command to any one of these interfaces will cause the processor to go active. DAC1 power down. When set, powers down DAC1. Playback is disabled. ADC1 power down. When set, powers down the ADC1. Capture is disabled. Mixer power down. All analog input and output channels are powered down. All outputs are centered around VREF if the VREF bit is set. A reset is not required to maintain the calibrated state if the mixer is powered down but the VREF bit is not set. VREF power down. When set, powers down the entire mixer. Since powering down VREF, powers down the entire analog section, some audible pops can occur. Internal Sample-Rate Converters are powered down. Only 44.1 kHz sample frequency is allowed when this bit is set. D6 res D5 res D4 res D3 CA3 D2 CA2 D1 CA1 D0 CA0 PROC CA3-CA0 Address bits to access the Control Indirect registers C0-C9 through CTRLbase+4 Control Indirect Data Register CTRLbase+4 D7 CD7 DAC1 D6 CD6 D5 CD5 D4 CD4 D3 CD3 D2 CD2 D1 CD1 D0 CD0 ADC1 CD7-CD0 MIX Control Indirect Data register. This register provides access to the indirect registers C0-C9, where CTRLbase+3 selects the actual register. See the Control Indirect Register section for more details. Control/RAM Access CTRLbase+5 D7 CR7 D6 CR6 D5 CR5 D4 CR4 D3 CR3 D2 CR2 D1 CR1 D0 CR0 VREF CR7-CR0 SRC This register controls the loading of the part’s internal RAM. RAM support includes hardware configuration and PnP default resource data, as well as program memory. See the Hostload Procedure section for more information. Commands are followed by address and data information. 0x55 - Disable PnP Key 0x56 - Disable Crystal Key 0x53 - Disable Crystal Key 2 0x5A - Update Hardware Configuration Data. 0xAA - Download RAM. Address followed by data. (Stopped by writing 0 to CTRLbase+6) Commands: PDWN Global Power Down with data retention. When set, the entire chip is powered down, except reads and writes to this register. When this bit is cleared, a full calibration is initiated. All registers retain their values; therefore, normal operation can resume after calibration is completed. DS253PP2 59 CS4239 CrystalClear Portable ISA Audio System TM RAM Access End CTRLbase+6 D7 RE7 D6 RE6 D5 RE5 D4 RE4 D3 RE3 D2 RE2 D1 RE1 D0 RE0 RE7-RE0 A 0 written to this location resets the previous location, CTRLbase+5, from data download mode to command mode. Control Indirect Registers T he Control Indirect registers are accessed through CTRLbase+3 and CTRLbase+4. CTRLbase+3 is the address register and CTRLbase+4 is the data register used to access C0 through C9 indirect registers. Reserved (C0) Default = xxxxxxxx D7 rbc Global Status CTRLbase+7, Default = 00000000 D7 CWSS D6 res D5 res D4 res D3 res D2 rbc D1 rbc D0 rbc D6 ICTRL D5 ISB D4 IWSS D3 IMPU D2 D1 D0 ZVA WDT IMV rbc Reserved, backwards compatible. ZVA ZVPORT Active. When set, indicates that data is being received on the ZVPORT pins. Hardware Master Volume Control Interrupt Status. When set, hardware volume has changed. IMV is cleared by reading this status register. Master Volume Interrupts are enabled through VCIE in C8. Watch-Dog Timer. If an error occurs on the ISA bus, the Processor will be reset and WDT will be set. MPU-401 Interrupt status. MPU interrupt pending when set to 1. Table 17. Control Indirect Access Registers Windows Sound System Interrupt Status. WSS interrupt pending when set to 1. Sound Blaster Interrupt status. Sound Blaster interrupt pending when set to 1. Control Logical Device 2 Interrupt status. A context switch interrupt is pending when set to 1. Context - WSS. Indicates the current context. 0 - Sound Blaster Emulation 1 - Windows Sound System Index C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 Register Name Reserved Version / Chip ID 3D Space Control 3D Enable Reserved Reserved Reserved Reserved Wavetable & Volume Control Power Management Address CTRLbase+3 CTRLbase+4 Register Name Control Indirect Address Control Indirect Data IMV WDT IMPU IWSS ISB ICTRL CWSS Table 18. Control Indirect Registers 60 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM Version / Chip ID (C1) Default = 11011110 D7 V2 3D Enable (C3) Default = xxxexxxx D3 CID3 D6 V1 D5 V0 D4 CID4 D2 CID2 D1 CID1 D0 CID0 D7 rbc D6 rbc D5 rbc D4 3DEN D3 res D2 res D1 res D0 res CID4-CID0 Chip Identification. Distinguishes between this chip and other codec chips that support this register set. This register is identical to the WSS X25 register. 11110 - CS4239 3DEN Enable 3D Sound. When set, 3D sound expansion is enabled on the analog outputs with the amount of 3D enhancement controlled through C2. V2-V0 Version number. As enhancements are made, the version number is changed so software can distinguish between the different versions of the same chip. 100 - Revision A 101 - Revision B 110 - Revision C Reserved (C4) Default = xxxxxxxx D7 rbc D6 rbc D5 rbc D4 rbc D3 res D2 res D1 res D0 res rbc Reserved, backwards compatible. Reserved (C5) Default = xxxxxxxx D7 D6 rbc D5 rbc D4 rbc D3 rbc D2 rbc D1 rbc D0 rbc 3D Space Control (C2) Default = 0000xxxx D7 SPC3 rbc D6 SPC2 D5 SPC1 D4 SPC0 D3 rbc D2 rbc D1 rbc D0 rbc rbc Reserved, backwards compatible. SPC3-SPC0 Space control for 3D sound. Control’s the "width" of the sound expansion with increasing numbers giving decreasing space affects. The least sigificant bit represents 1.5 dB of attenuation, with 0000 = 0 dB (full space affect). Reserved (C6) Default = xxxxxxxx D7 rbc D6 rbc D5 rbc D4 rbc D3 rbc D2 rbc D1 rbc D0 rbc rbc Reserved, backwards compatible. Reserved (C7) Default = xxxxxxxx D7 res D6 res D5 res D4 res D3 res D2 res D1 res D0 res res Reserved. Must write 0. Could read as 0 or 1. DS253PP2 61 CS4239 CrystalClear Portable ISA Audio System VCIE Volume Control Interrupt Enable. When set, the hardware volume control pins cause interrupts, when pressed, on the WSSint pin. The status is available in CTRLbase+7, IMV bit. TM Wavetable & Volume Control (C8) Default = 0exxee00 D7 D6 D5 D4 res res D3 WTEN D2 VCEN D1 DMCLK D0 BRES VCIE VCF1 BRES Force BRESET low. When set, the BRESET pin is forced low. Typically used for power management of peripheral devices. Disable MCLK. When set, the MCLK pin of the CS9236 Wavetable Synthesizer serial interface is forced low providing a power savings mode. Volume Control Enable. When set, the UP, DOWN, and MUTE pins become active and provide hardware master volume control for the line outputs. Note that this bit can be initialized at power-up through Hardware Configuration data, Misc. Configuration Byte. Wavetable Serial Port Enable. When, set, the CS9236 Single-Chip Wavetable Music Synthesizer serial port pins are enabled. WTEN can be initialized in the E2PROM Hardware Configuration data, Global Configuration byte. Hardware Volume Control Format. This bit controls the format of the UP, DOWN, and MUTE pins. VCF1 is initialized in the E2PROM Hardware Configuration data, Global Configuration byte. 0 - MUTE is a momentary button. Pressing MUTE toggles between mute and un-mute. Pressing UP or DOWN will always un-mute. 1 - MUTE is not used. Pressing the up and down buttons simultaneously causes the volume to mute. Pressing up or down singularly will un-mute. Power Management (C9) Default = 0xxxx000 D7 RESET D6 res D5 res D4 res D3 res D2 MIXCD D1 DAC2 D0 SPORT DMCLK SPORT DAC2 Powers down the serial ports. Powers down DAC2 including FM and the CS9236 serial interface. Powers down the analog mixer - with the exception of MIN, AUX2, and the line outputs. When this bit goes from a 1 to a 0, a software RESDRV is initiated causing the entire chip to be reset and placed in its default power-up configuration. Access to all registers on this chip will be lost, including this one, since the power-up state for PnP is all resources unassigned. VCEN MIXCD RESET WTEN VCF1 62 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM MPU-401 INTERFACE The MPU-401 is an intelligent MIDI interface that was introduced by Roland in 1984. Voyetra Technologies subsequently introduced an IBMPC plug in card that incorporated the MPU-401 functionality. The MPU-401 has become the defacto standard for controlling MIDI devices via IBM-PC compatible personal computers. Although the MPU-401 does have some intelligence, a non-intelligent mode is available in which the MPU-401 operates as a basic UART. By incorporating hardware to emulate the MPU401 in UART mode, MIDI capability is supported. MPU-401 Register Interface The MPU401 logical device software interface occupies 2 I/O locations, utilizes 10-bit address decoding, and is located at PnP address ’MPUbase’. 10-bit addressing requires that the upper address bits be 0 to decode a valid address, i.e. no aliasing occurs. The standard base address is 330h. This device also uses an interrupt, typically 9. MPUbase+0 is the MIDI Transmit/Receive port and MPUbase+1 is the Command/Status port. In addition to I/O decodes the only additional functionality required from an ISA bus viewpoint is the generation of a hardware interrupt whenever data has been received into the receive buffer. MIDI Transmit/Receive Port, MPUbase+0 D7 TR7 All MIDI transmit data is transferred through a 16-byte FIFO and receive data through a 16-byte FIFO. The FIFO gives the ISA interface time to respond to the asynchronous MIDI transfer rate of 31.25 k baud. The Command/Status Registers occupy the same address and are used to send instructions to and receive status information from the MPU-401. Command Register, write only MPUbase+1 D7 CS7 D6 CS6 D5 CS5 D4 CS4 D3 CS3 D2 CS2 D1 CS1 D0 CS0 CS7-CS0 Each write to the Command/Status Register produces an appropriate acknowledge byte in the receive register. Status Register, read only MPUbase+1 D7 RXS D6 TXS D5 CS5 D4 CS4 D3 CS3 D2 CS2 D1 CS1 D0 CS0 CS5-CS1 D0-D5 are the 6 LSBs of the last command written to this port. Transmit Buffer Status Flag. 0 - Transmit buffer not full 1 - Transmit buffer full TXS RXS Receive Buffer Status Flag 0 - Data in Receive buffer 1 - Receive buffer empty D6 TR6 D5 TR5 D4 TR4 D3 TR3 D2 TR2 D1 TR1 D0 TR0 TR7-TR0 The MIDI Transmit/Receive Port is used to send and receive MIDI data as well as status information that was returned from a previously sent command. When in "UART" mode, data is received into the receive buffer FIFO and a hardware interrupt is generated. Data can be received from two sources: MIDI data via the UART serial input or acknowledge data that is the result of a write to the Command Register (MPUbase+1). The interrupt is cleared by a read of the MIDI Receive Port (MPUbase+0). DS253PP2 63 CS4239 CrystalClear Portable ISA Audio System TM UART mode operation is defined as follows: MIDI UART The UART is used to convert parallel data to the serial data required by MIDI. The serial data rate is fixed at 31.25 k baud (±1%). The serial data format is RS-232 like: 1 start bit, 8 data bits, and 1 stop bit. In multimedia systems, the MIDI pins are typically connected to the joystick connector as illustrated in Figure 5. MPU-401 "UART" Mode Operation After power-up reset, the interface is in "nonUART" mode. Non-UART mode operation is defined as follows: 1. All writes to the Transmit Port, MPUbase+0, are ignored. 2. All reads of the Receive Port, MPUbase+0, return the last received buffer data. 3. All writes to the Command Port, MPUbase+1, are monitored and acknowledged as follows: a. A write of 3Fh sets the interface into UART operating mode. An acknowledge is generated by putting an FEh into the receive buffer FIFO which generates an interrupt. b. A write of A0-A7, ABh, ACh, ADh, AFh places an FEh into the receive buffer FIFO (which generates an interrupt) followed by a one byte write to the receive buffer FIFO of 00h for A0-A7, and ABh commands, 15h for ACh, 01h for ADh, and 64h for AFh commands. c. All other writes to the Command Port are ignored and an acknowledge is generated by putting an FEh into the receive buffer FIFO which generates an interrupt. 1. All writes to the Transmit Port, MPUbase+0, are placed in the transmit buffer FIFO. Whenever the transmit buffer FIFO is not empty, the next byte is read from the buffer and sent out the MIDOUT pin. The Status Register, MPUbase+1, bit 6, TXS is updated to reflect the transmit buffer FIFO status. 2. All reads of the Receive Port, MPUbase+0, return the next byte in the receive buffer FIFO. When serial data is received from the MIDIN pin, it is placed in the next receive buffer FIFO location. If the buffer is full, the last location is overwritten with the new data. The Status Register, MPUbase+1, bit 7, RXS is updated to reflect the new receive buffer FIFO state. 3. A write to the Command Register, MPUbase+1, of FFh will return the interface to non-UART mode. 4. All other writes to the Command Register, MPUbase+1, are ignored. FM SYNTHESIZER This part contains a games-compatible internal FM synthesizer. When enabled, this internal FM synthesis engine responds to both the SBPro FM synthesis addresses as well as the SYNbase addresses. To enable the internal FM synthesis engine, the IFM bit in the Hardware Configuration data, byte 8 (Global Configuration Byte) must be set. This bit is also available in WSS register X4. Volume control for the internal FM synthesizer is supported through I18 and I19 in the WSS extended register space. 64 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM The synthesizer interface is compatible with the Adlib and Sound Blaster standards. The typical Adlib I/O address is SYNbase = 388h. Standard Synthesizer I/O Map Address SYNbase+0 SYNbase+0 SYNbase+1 SYNbase+2 SYNbase+3 Name FM Status FM Address 0 FM Data 0 FM Address 1 FM Data 1 Type Read Only Write Only Read/Write Write Only Read/Write ACDCS. The range of addresses that ACDCS will respond to is programmable via the Hardware Configuration data, byte 5, from one to eight bytes (default = 1 byte). To make the CDROM interface more flexible, one global bit, located in the Hardware Configuration data section - byte 7, allow control over the polarity of the CDROM interrupt pin CDINT. IHC defaults to 1 indicating that CDINT is an active high interrupt. IHC is also controllable through CTRLbase+1. CS4610 DSP SERIAL DATA PORT The WSS Codec includes a CS4610 DSP serial audio interface for transferring digital audio data between the part and the CS4610 DC ’97 Audio Accelerator serial device. When SPE is set (MCE must be 1 to change SPE), the serial port pins are enabled; otherwise, they are high-impedance pins. The DSP audio serial port is software enabled via the SPE bit in the WSS Codec indirect register I16 or from the Hardware Configuration data in the EEPROM. The ISA interface is fully active in this mode. The serial port data format is always two’s complement 16-bit linear. FSYNC and SCLK are always output from the part when the serial port is enabled. The serial port can be configured in one of four serial port formats, shown in Figures 6-9. SF1 and SF0 in I16 select the particular format. MCE in R0 must be set to change SF1/0. Both left and right audio words are always 16 bit two’s complement. When the mono audio format is selected, the right channel output is set to zero and the left channel input is sent to both DAC channels. The first format - SPF0, shown in Figure 6, is called 64-bit enhanced. This format has 64 SCLKs per frame with a one bit period wide FSYNC that precedes the frame. The first 16 bits occupy the left word and the second 16 bits oc65 CDROM INTERFACE An IDE CDROM controller interface is provided that supports Enhanced as well as Legacy IDE CDROM drives. This interface includes two programmable chip selects and on-chip hardware to map DMA and interrupt signals to the ISA bus. Use of the CDROM interface requires an external 1k E2PROM to support PnP, Hardware Configuration, and firmware patch data. There are five pins that make up the CDROM interface which consist of: CDCS - chip select, COMbase address CDINT - interrupt, COMint CDRQ - DMA request, COMdma CDACK - DMA acknowledge, COMdma ACDCS - alternate chip select, ACDbase The four basic CDROM interface pins are multifunction pins that default to the upper address bits SA12 - SA15. To use the pins as a CDROM interface, a 10 kΩ pulldown resistor must be placed on MCLK. The fifth CDROM pin ACDCS is multiplexed with XCTL1/SINT/DOWN. This chip select supports the alternate CDROM chip select used for status. The volume control pin DOWN has the highest precedence; therefore, the VCEN bit must be zero to use this pin for the CDROM interface. Given that VCEN is zero, a 10 kΩ pulldown resistor on SDOUT converts this pin to DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM FSYNC SCLK SDOUT ... 0 ... ... 15 14 13 12 15 14 0 8 zeros INT 7 zeros CEN PEN OVR 13 zeros 16 Bits Left Data SDIN 15 14 13 12 ... 0 16 Bits Right Data 15 14 ... 0 32 Bits 16 Bits Left Data 16 Bits Right Data INT = Interrupt Bit CEN = Capture Enable PEN = Playback Enable OVR = Left Overrange or Right Overrange Figure 6. 64-bit Enhanced Mode (SF1,0 = 00) FSYNC SCLK SDOUT/ SDIN ... ... 15 14 13 ... 0 15 14 13 ... 0 15 16 Clocks Left Data 16 Clocks 16 Clocks 16 Clocks Right Data Figure 7. 64-bit Mode (SF1,0 = 01) FSYNC SCLK ... ... 32 No-Clock bit periods SDOUT/ SDIN 15 14 13 ... 0 15 14 13 ... 0 ... 15 14 16 Clocks Left Data 16 Clocks Right Data Left Data Figure 8. 32-bit Mode (SF1,0 = 10) 66 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM cupy the right word. The last 32 bits contain four status bits and 28 zeros. This is the only mode that contains status information. The second serial format - SPF1, shown in Figure 7, is called 64-bit mode. This format has 64 SCLKs per frame, with FSYNC high transitions at the start of the left data word and low transitions at the start of the right data word. Both the left and right data words are followed by 16 zeros. The third serial format - SPF2, shown in Figure 8, is called 32-bit mode. This format has 32 SCLKs per frame and FSYNC is high for the left channel and low for the right channel. The absolute time is similar to the other two modes but SCLK is stopped after the right channel is finished. SCLK is held stopped until the start of the next frame (stopped for 32 bit period times). This mode is useful for DSPs that do not want the interrupt overhead of the 32 unused bit periods. As an example, if a DSP serial word length is 16 bits, then four interrupts will occur in SPF0 and SPF1 modes. In mode SPF2 the DSP will only be interrupted twice. The fourth serial format - SPF3, shown in Figure 9, is called ADC/DAC mode. This format has 64 SCLKs per frame, with FSYNC high transitions at the start of the left ADC data word and low transitions at the start of the right ADC data word. For serial data in, SDIN, both the left and right 16-bit DAC data word should be followed by zeros. For serial data out, SDOUT, both the left and right ADC data words are followed by 16 bits of the DAC data words. The DAC data words are tapped off the data stream right before the data enters the Codec DACs. Having the ADC and DAC data on the SDOUT allows external modem DSPs to cancel the local audio source from the local microphone signal. CS9236 WAVETABLE SERIAL PORT A digital interface to the CS9236 Single-Chip Wavetable Music Synthesizer is provided that allows the CS9236 PCM audio data to be summed digitally into the output digital mixer. This serial port is enabled via the WTEN bit located in Control register C8/X24 or in the Global Configuration byte in the Hardware Configuration data. The hardware connections to the CS9236 are illustrated in Figure 11. FSYNC SCLK SDIN 15 14 13 ... ... ... 0 15 14 13 ... 0 15 DAC 16 Clocks SDOUT 15 14 13 ... DAC 16 Clocks 15 14 13 ... 0 0 15 14 13 ... 0 15 14 13 ... 0 15 ADC 16 Clocks DAC 16 Clocks ADC 16 Clocks DAC 16 Clocks Left Data Figure 9. ADC/DAC Mode (SF1,0 = 11) Right Data DS253PP2 67 CS4239 CrystalClear Portable ISA Audio System TM The CS9236 data is sent to DAC2 which can be summed into the input or output mixer. Volume control for the serial port is supported through I18 and I19 in the WSS register space. 100 Ω CS9236 MCLK5I MCLK LRCLK SDATA BRESET 100k Ω 100k Ω LRCLK SOUT RST PDN MIDI_IN The ZVPORT interface is enabled by setting ZVEN in X18. The initial state of ZVEN on power-up can be set from the Hardware Configuration, Global Configuration Byte 2. Once enabled, the ZVPORT interface is connected to DAC2. When DAC2 is being used for ZVPORT, it cannot be used for other devices such as CS9236 Wavetable serial interface, CS4610 DSP serial interface, or internal FM synthesizer. Volume control for the ZVPORT is supported through I18 and I19 in the WSS register space. An activity bit, ZVA, exists in the Global Status register, CTRLbase+7 (or X30 in WSS space) which is high when activity exists on the ZVPORT. When the ZVPORT is enabled (ZVEN = 1), the CS4239 automatically detects a clock on the ZLRCK pin and switches to the ZVPORT interface when the clock is present. When the ZLRCK is not present, the CS4239 automatically switches back to FM/Wavetable. WSS CODEC SOFTWARE DESCRIPTION The WSS Codec must be in Mode Change Enable Mode (MCE=1) before any changes to the Interface Configuration register (I9) or the Sample Frequency (lower four bits) in the Fs & Playback Data Format registers (I8) are allowed. The actual audio data formats, which are the upper four bits of I8 for playback and I28 for capture, can be changed by setting MCE (R0) or PMCE/CMCE (I16) high. The exceptions are CEN and PEN which can be changed "on-thefly" via programmed I/O writes. All outstanding DMA transfers must be completed before new values of CEN or PEN are recognized. MIDOUT MIDIN XTAL3I Midi In Midi Out Joystick Connector Figure 11. CS9236 Wavetable Serial Port Interface ZVPORT SERIAL INTERFACE The ZVPORT interface consists of three input pins: ZLRCK, ZSCLK, and ZSDATA. ZLRCK is the Left/Right clock indicating which channel is currently being received. ZSCLK is the serial bit clock where ZLRCK and ZSDATA change on the falling edge and serial data is internally latched on the rising edge. Note that the serial data starts one ZSCLK period after ZLRCK transitions. Figure 10 illustrates the clocking on the ZVPORT pins. ZLRCK ZSCLK Left Channel Right Channel ZSDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 10. ZVPORT Clocking Format 68 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM Calibration The WSS Codec has four different calibration modes. The selected calibration occurs whenever the Mode Change Enable (MCE, R0) bit goes form 1 to 0. The completion of calibration can be determined by polling the Auto-Calibrate In-Progress bit in the Error Status and Initialization register (ACI, I11). This bit will be high while the calibration is in progress and low once completed. Transfers enabled during calibration will not begin until the calibration cycle has completed. Since the part always operates at 44.1 kHz internally, all calibration times are based on 44.1 kHz sample periods. The Calibration procedure is as follows: 1) Place the WSS Codec in Mode Change Enable using the MCE bit of the Index Address register (R0). 2) Set the CAL1,0 bits in the Interface Configuration register (I9). 3) Return from Mode Change Enable by resetting the MCE bit of the Index Address register (R0). 4) Wait until 80h NOT returned 5) Wait until ACI (I11) cleared to proceed NO CALIBRATION (CAL1,0 = 00) This is the fastest mode since no calibration is performed. This mode is useful for games which require the sample frequency be changed quickly. This mode is also useful when the codec is operating full-duplex and an ADC data format change is desired. This is the only calibration mode that does not affect the DACs (i.e. mute the DACs). The No Calibration mode takes zero sample periods. DS253PP2 CONVERTER CALIBRATION (CAL1,0 = 01) This calibration mode calibrates the ADCs and the DACs, but does not calibrate any of the analog mixing channels. This is the second longest calibration mode, taking 321 sample periods at 44.1 kHz. Because the analog mixer is not calibrated in this mode, any signals fed through the mixer will be unaffected. The calibration sequence is as follows: The DACs are muted The ADCs are calibrated The DACs are calibrated The DACs are unmuted DAC CALIBRATION (CAL1,0 = 10) T his calibration mode only clears the DACs (playback) interpolation filters leaving the ADC unaffected. This is the second fastest calibration mode (no cal. is the fastest) taking 120 sample periods at 44.1 kHz to complete. The calibration sequence is as follows: The DACs are muted The DAC filters are cleared The DACs are unmuted FULL CALIBRATION (CAL1, 0 = 11) T his calibration mode calibrates all offsets, ADCs, DACs, and analog mixers. Full calibration will automatically be initiated on power up or anytime the WSS Codec exits from a full power down state. This is the longest calibration mode and takes 450 sample periods at 44.1 kHz to complete. The calibration sequence is as follows: All outputs are muted (DACs and mixer) The mixer is calibrated The ADCs are calibrated The DACs are calibrated All outputs are unmuted 69 CS4239 CrystalClear Portable ISA Audio System TM Changing Sampling Rate The internal states of the WSS Codec are synchronized by the selected sampling frequency. The sample frequency can be set in one of three fashions. The standard WSS Codec method uses the Fs & Playback Data Format register (I8) to set the sample frequency. The changing of either the clock source or the clock frequency divide requires a special sequence for proper WSS Codec operation: 1) Place the WSS Codec in Mode Change Enable using the MCE bit of the Index Address register (R0). 2) During a single write cycle, change the Clock Frequency Divide Select (CFS) and/or Clock 2 Base Select (C2SL) bits of the Fs & Playback Data Format register (I8) to the desired value. (The data format may also be changed.) 3) The WSS Codec resynchronizes its internal states to the new frequency. During this time the WSS Codec will be unable to respond. Writes to the WSS Codec will not be recognized and reads will always return the value 80 hex. 4) The host now polls the WSS Codec’s Index Address register (R0) until the value 80 hex is no longer returned. On slow processor systems, 80h may occur faster than software is able to read (80h may never occur). 5) Once the WSS Codec is no longer responding to reads with a value of 80 hex, normal operation can resume and the WSS Codec can be removed from MCE. A second method of changing the sample frequency is to disable the sample frequency bits in I8 (lower four bits) by setting SRE in I22. When this bit is set, OSM1 and OSM0 in I10, along 70 with the rest of the bits in I22, are used to set the sample frequency. Once enabled, these bits can be changed without doing an MCE cycle. The third method supports independent sample frequencies (Fs) for capture and playback. The independent sample frequency mode is enabled by setting IFSE in X11. Once enabled, the other two methods for setting Fs (I8, I10, and I22) are disabled. The capture (ADC) Fs is set in X12 and the playback (DAC) Fs is set in X13. Changing Audio Data Formats In MODE 1, MCE must be used to select the audio data format in I8. Since MCE causes a calibration cycle, it is not ideal for full-duplex operation. In MODE 2 and 3, individual Mode Change Enable bits for capture and playback are provided in register I16. MCE (R0) must still be used to select the sample frequency, but PMCE (playback) and CMCE (capture) allow changing the respective data formats without causing a calibration to occur. Setting PMCE (I16) clears the playback FIFO and allows the upper four bits of I8 to be changed. Setting CMCE (I16) clears the capture FIFO and allows the upper four bits of I28 to be changed. Audio Data Formats The sample frequency is always selected in the Fs & Playback Data Format register (I8). In MODE 1 the same register, I8, determines the audio data format for both playback and capture; however, in MODE 2 and 3, I8 only selects the playback data format and the capture data format is independently selectable in the Capture Data Format register (I28). The WSS Codec always orders the left channel data before the right channel. Note that these definitions apply regardless of the specific format of the data. For example, the left sample always comes first in the data stream regardless of whether the sample is 16-bit or 8-bit in size. DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM There are two data formats supported by the WSS Codec: 16-bit signed (little Endian) and 8bit unsigned. See Figures 13-16. 16-BIT SIGNED The 16-bit signed data format is "little endian". This format defines the byte ordering of a multibyte word as having the least significant byte occupying the lowest memory address. Likewise, the most significant byte of a little endian word occupies the highest memory address. The 16-bit signed format (also called 16-bit 2’s complement) is the standard method of representing 16-bit digital audio. This format gives 96 dB theoretical dynamic range and is the standard for compact disk audio players. This format uses the value -32768 (8000h) to represent maximum negative analog amplitude, 0 for center scale, and 32767 (7FFFh) to represent maximum positive analog amplitude. 8-BIT UNSIGNED The 8-bit unsigned format is commonly used in the personal computer industry. This format delivers a theoretical dynamic range of 48 dB. This format uses the value 0 (00h) to represent maximum negative analog amplitude, 128 for center scale, and 255 (FFh) to represent maximum positive analog amplitude. The 16-bit signed and 8-bit unsigned transfer functions are shown in Figure 12. DMA Registers The DMA registers allow easy integration of this part into ISA systems. Peculiarities of the ISA DMA controller require an external count mechanism to notify the host CPU of a full DMA buffer via interrupt. The programmable DMA Base registers provide this service. The act of writing a value to the Upper Base register causes both Base registers to load the Current Count register. DMA transfers are enabled by setting the PEN/CEN bit while DS253PP2 PPIO/CPIO is clear. (PPIO/CPIO can only be changed while the MCE bit is set.) Once transfers are enabled, each sample that is transferred by a DMA cycle will decrement the Current Count register until zero is reached. The next sample after zero generates an interrupt and reloads the Current Count registers with the values in the Base registers. For all data formats the DMA Base registers must be loaded with the number of samples, minus one, to be transferred between "DMA Interrupts". A sample is one to four bytes wide and is defined as all data taken at one instant in time. Stereo and mono data contain the same number of samples, and 8-bit data and 16-bit data contain the same number of samples. Symbolically: DMA Base register16 = NS - 1 Where NS is the number of samples transferred between interrupts and the "DMA Base register16" consists of the concatenation of the upper and lower DMA Base registers. Figure 12. Linear Transfer Functions 71 CS4239 CrystalClear Portable ISA Audio System 32-bit Word Time TM sample 6 sample 5 sample 4 sample 3 sample 2 sample 1 MONO 31 24 23 MONO 16 15 MONO 87 MONO 0 Figure 13. 8-bit Mono, Unsigned Audio Data 32-bit Word Time sample 3 sample 3 sample 2 sample 2 sample 1 sample 1 RIGHT 31 24 23 LEFT 16 15 RIGHT 87 LEFT 0 Figure 14. 8-bit Stereo, Unsigned Audio Data 32-bit Word Time sample 6 sample 5 sample 4 sample 3 sample 2 sample 1 MONO 31 24 23 16 15 MONO 87 0 Figure 15. 16-bit Mono, Signed Little Endian Audio Data 32-bit Word Time sample 3 sample 3 sample 2 sample 2 sample 1 sample 1 RIGHT 31 LEFT 16 15 24 23 87 0 Figure 16. 16-bit Stereo, Signed Little Endian Audio Data 72 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM PLAYBACK DMA REGISTERS The playback DMA registers (I14/15) are used for sending playback data to the DACs in MODE 2 and 3. In MODE 1, these registers (I14/15) are used for both playback and capture; therefore, full-duplex DMA operation is not possible. When the playback Current Count register rolls under, the Playback Interrupt bit, PI, (I24) is set causing the INT bit (R2) to be set. The interrupt is cleared by a write of any value to the Status register (R2), or writing a "0" to the Playback Interrupt bit, PI (I24). CAPTURE DMA REGISTERS The Capture DMA Base registers (I30/31) provide a second pair of Base registers that allow full-duplex DMA operation. With full-duplex operation capture and playback can occur simultaneously. These registers are provided in MODE 2 and 3 only. When the capture Current Count register rolls under, the Capture Interrupt bit, CI, (I24) is set causing the INT bit (R2) to be set. The interrupt is cleared by a write of any value to the Status register (R2), or writing a "0" to the Capture Interrupt bit, CI (I24). WSS Codec Interrupt The INT bit of the Status register (R2) always reflects the status of the WSS Codec’s internal interrupt state. A roll-over from any Current Count register (DMA playback, DMA capture, or Timer) sets the INT bit. This bit remains set until cleared by a write of ANY value to Status register (R2), or by clearing the appropriate bit or bits (PI, CI) in the Alternate Feature Status register (I24). The Interrupt Enable (IEN) bit in the Pin Control register (I10) determines whether the interrupt assigned to the WSS Codec responds to the inDS253PP2 terrupt event. When the IEN bit is low, the interrupt is masked and the IRQ pin assigned to the WSS Codec is held low. However, the INT bit in the Status register (R2) always responds to the counter. Error Conditions Data overrun or underrun could occur if data is not supplied to or read from the WSS Codec in an appropriate amount of time. The amount of time for such data transfers depends on the frequency selected within the WSS Codec. Should an overrun condition occur during data capture, the last whole sample (before the overrun condition) will be read by the DMA interface. A sample will not be overwritten while the DMA interface is in the process of transferring the sample. Should an underrun condition occur in a playback case the last valid sample will be output (assuming DACZ = 0) to the digital mixer. This will mask short duration error conditions. When the next complete sample arrives from the host computer the data stream will resume on the next sample clock. The overrun and underrun error bits in the Alternate Feature Status register, I24, are cleared by first clearing the condition that caused the overrun or underrun error, followed by writing the particular bit to a zero. As an example, to clear the playback underrun bit PU, first a sample must be sent to the WSS Codec, and then the PU bit must be written to a zero. DIGITAL HARDWARE DESCRIPTION The best example of hardware connection for the different sections of this part is the Reference Design Data Sheet. The Reference Design Data Sheet contains all the schematics, layout plots and a Bill of Materials; thereby providing a complete example. 73 CS4239 CrystalClear Portable ISA Audio System TM Bus Interface The ISA bus interface is capable of driving a 24 mA data bus load and therefore does not require any external data bus buffering. See the Reference Design Data Sheet for a typical connection diagram. Volume Control Interface Three hardware master volume control pins are supported: volume up, volume down, and mute. Hardware volume control is enabled by setting the VCEN bit in the Hardware Configuration data, byte 7 (Misc. Config. Byte). Once VCEN is set, the XTAL1/ACDCS/DOWN pin converts to the volume down function. The volume control pins affect the master volume control output after the analog output mixer. The UP and DOWN pins, when low, increment and decrement the master volume. These two pins would use SPST momentary switches. The MUTE pin can either be momentary or non-existent where pressing up and down simultaneously mutes the output volume. The circuit in Figure 17, contains optional resistors for EMI and ESD protection; however, the capacitors are required for switch debounce. The formats are selected using the VCF1 bit in the Hardware Configuration data, Global Config. byte. In the first format, where VCF1 = 0, the mute function is a momentary switch (similar to up and down). When MUTE goes low the master out volume mutes if it was un-muted and viseversa (the mute button alternates between mute and un-mute). If the master volume is muted and up or down is pressed, the volume automatically un-mutes. In the second format, where VCF1 = 1, the MUTE pin is not used. This is a two-button format where pressing up and down simultaneously mutes the master volume. If the master volume is muted and up or down is individually pressed, the volume automatically un-mutes. The two formats listed above as illustrated in Figure 18. Up Down Mute GND Up Down Mute GND VCF1 = 0 VCF1 = 1 Figure 18. Volume Control Formats UP DOW N MUTE 100 Ω 100 Ω 100 Ω Up Down Mute 10 nF 10 nF 10 nF GND Figure 17. Volume Control Circuit Pressing the up button, increments the volume. Pressing the down button, decrements the volume. Holding either of these buttons in the low state causes the volume to to continue changing. Crystal / Clock Two pins have been allocated to allow the interfacing of a crystal oscillator: XTALI and XTALO. The crystal should be designed as fundamental mode, parallel resonant, with a load capacitor of between 10 and 20 pF. The capacitors connected to each of the crystal pins should be twice the load capacitance specified to the crystal manufacturer. An external CMOS clock may be connected to the crystal input XTALI in lieu of the crystal. 74 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM W hen using an external CMOS clock, the XTALO pin must be left floating with no trace or external connection of any kind. General Purpose Output Pins Two general purpose outputs are provided to enable control of external circuitry (i.e. mute function). XCTL1 and XCTL0 in the WSS Codec register I10 are output directly to the appropriate pin when enabled. Pin XCTL1/ACDCS/DOWN is initially controlled by the VCEN bit in the Hardware Configuration data. If VCEN is zero, this pin becomes XCTL1 if the SDOUT pin is sampled high during a high-to-low transition of RESDRV. This pin can also output ACDCS if the SDOUT pin is sampled low during a high-to-low transition of the RESDRV pin. SDOUT has an internal pullup resistor. VCEN has the highest precedence and will cause this pin to convert to the DOWN function whenever VCEN is set. Reset and Power Down A RESDRV pin places the part into maximum power conservation mode. When RESDRV goes high, the PnP registers are reset - all logical devices are disabled, all analog outputs are muted, and the voltage reference then slowly decays to ground. When RESDRV is brought low, an initialization procedure begins which causes a full calibration cycle to occur. When initialization is completed, the registers will contain their reset value and the part will be isolated from the bus. RESDRV is required whenever the part is powered up. The initialization time varies based on whether an E2PROM is present or not and the size of the data in the E2PROM. After RESDRV goes low, the part should not be written to for approximately 200 ms to guarantee that the part is ready to respond to commands. The exact timing is specified in the Timing Section in the front of this data sheet. Software low-power states are available through bits in the Control or WSS logical device register space. See the CONTROL INTERFACE section for more information. Address Port Configuration The part provides a method for motherboards to hide the part from standard PnP (or traditional Crystal Key) software. BIOSes can use this method to set the part at a unique address, and report the device as a System Dev. Node to the operating system. On the high to low transition of the RESDRV pin, the part samples the state of the APSEL and SCL, which have internal 100 kΩ pullups to +5 V. APSEL selects the Address Port used to configure the part. When APSEL is left high, the Address Port is 0x279 and backwards compatible to previous chips and standard PnP software. When APSEL is externally tied to SGND, the Address Port is moved to one of two locations, selected by a strapping option on the SCL pin. If SCL is sampled high (default), then the Address Port is moved to 0x308. If SCL is strapped low with an external 10 kΩ resistor to SGND, the Address Port is moved to 0x388. If the Address Port is moved (APSEL = 0) then the device is no longer PnP compliant; however, it will still respond to all the standard PnP commands using the new Address Port. In addition, the new Address Port supports the traditional Crystal Key or the new Crystal Key 2. Multiplexed Pin Configuration On the high to low transition of the RESDRV pin, the part samples the state of the MCLK and SDOUT which have internal 100 kΩ pullups to +5 V. The state of MCLK at the time RESDRV is brought low determines the function of the CDROM interface pins. If MCLK is sampled high, then CDCS, CDACK, CDINT, CDRQ are 75 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM used to input SA12, SA13, SA14, SA15 respectively. If MCLK is sampled low (external pulldown) then CDCS, CDACK, CDINT, CDRQ become the standard CDROM interface pins. The XCTL1/ACDCS/DOWN pin state is first determined by VCEN. If VCEN is set this pin is forced to the DOWN volume control pin. If VCEN is zero, then a strapping option on SDOUT determines the pin function. If SDOUT is high (default) on powerup, the pin is forced to the XCTL1 general purpose output that tracks the bit by the same name in I10 in the WSS space. If SDOUT is externally pulled low through a 10 kΩ resistor, then the pin is forced to the alternate CDROM chip select function, ACDCS. ANALOG HARDWARE DESCRIPTION T he analog hardware consist of an MPC Level 3-compatible mixer. This section describes the analog hardware needed to interface with these pins. Line-Level Inputs The analog inputs consist of three stereo analog inputs, and one mono input. As shown in Figure 4, the input to the ADCs comes from the Input Mixer that selects any combination of the following: AUX1, AUX2, MIC, DAC1, DAC2, and the output from the analog output mixer. Unused analog inputs should be connected together and then connected through a capacitor to analog ground. The analog input interface is designed to accommodate two stereo inputs and two mono inputs. Three of these sources are mixed to the ADC. These inputs are: a mono microphone input (MIC), a stereo CD-ROM input (AUX2), and a stereo auxiliary line-level input (AUX1). The MIC, AUX1, and AUX2 inputs have paths after their volume controls, to the output mixer. The output mixer has the additional input of a mono input channel. All audio inputs should be capacitively coupled. Since some analog inputs can be as large as 2 VRMS, the circuit shown in Figure 19 can be used to attenuate the analog input to 1 VRMS which is the maximum voltage allowed for the line-level inputs. 6.8 kΩ 1.0 µF R 1.0 µF 6.8 kΩ 6.8 kΩ 6.8 kΩ L Figure 19. Line Inputs The AUX2 line-level inputs have an extra pin, CMAUX2, which provides a pseudo-differential input for both LAUX2 and RAUX2. This pin takes the common-mode noise out of the AUX2 inputs when connected to the ground coming from the AUX2 analog source. Connecting the AUX2 pins as shown in Figure 20 provides extra noise attenuation coming from the CDROM drive, thereby producing a higher quality signal. Since the better the resistors match, the better the common-mode attenuation, one percent resistors are recommended. If CMAUX2 is not used, it should be connected through an AC cap to analog ground. (All resistors 1%) 6.8 kΩ 3.4 kΩ 6.8 kΩ 6.8 kΩ 1.0 µF 2.0 µF 1.0 µF 6.8 kΩ RAUX2 CMAUX2 LAUX2 3.4 kΩ Figure 20. Differential CDROM In 76 DS253PP2 CS4239 CrystalClear Portable ISA Audio System +5VA (Low Noise) or AGND - if CMOS Source 4.7 kΩ 1 47 kΩ TM Microphone Level Input The microphone level input, MIC, include a selectable -22.5 dB to +22.5 dB gain stage for interfacing to an external microphone. An additional 20 dB gain block is also available. The 20 dB gain block can be switched off to provide another mono line-level input. Figure 21 illustrates a single-ended microphone input buffer circuit that will support lower gain mics. The circuit in Figure 21 supports dynamic mics and phantom-powered mics that use the ring portion of the jack for power. 2 kΩ 47 kΩ 0.1 µF MC33078 or MC33178 0.1 µF 2.7 nF MIN Figure 22. Mono Input 47 kΩ VREF + 1 µF 0.33 µF MIC 4.7 kΩ 2.7 nF NPO 10 µF X7R Line Level Outputs The analog output section provides a stereo linelevel output. The other output types (headphone and speaker) can be implemented with external circuitry. LOUT and ROUT outputs should be capacitively coupled to external circuitry. Both LOUT and ROUT need 1000 pF NPO capacitors between the pin and AGND. Miscellaneous Analog Signals The VREF pin is typically 2.2 V and provides a common mode signal for single-supply external circuits. VREF only supports light DC loads and should be buffered if AC loading is needed. For typical use, a 0.1 µF in parallel with a 10 µF capacitor should be connected to VREF. GROUNDING AND LAYOUT Figure 23 is a suggested layout for motherboard designs and Figure 24 is a suggested layout for add-inn cards. For optimum noise performance, the device should be located across a split analog/digital ground plane. The digital ground plane should extend across the ISA bus pins as well as the internal digital interface pins. DGND1 is ground for the data bus and should be electrically connected to the digital ground plane which will minimize the effects of the bus interface due to transient currents during bus switching. SGND1-4 should also be connected to the digital ground plane to minimize coupling into the analog section. Figure 25 shows the recommended positioning of the decoupling capacitors. The capacitors must be on the same layer as, and close to, the part. The vias shown 77 600 Ω + Figure 21. Microphone Input Mono Input The mono input, MIN, is useful for mixing the output of the "beeper" (timer chip), provided in all PCs, with the rest of the audio signals. The MIN pin can be mixed into the output mixer with at a 0 or -9 dB level. Also, the MIM and MIMR bits support muting the input to the left and right channels respectively. Figure 22 illustrates a typical input circuit for the Mono In. If MIN is driven from a CMOS gate, the 4.7 kΩ should be tied to AGND instead of VA+. Although this input is described for a low-quality beeper, the input is of the same high-quality as all other analog inputs and may be used for other purposes. DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM go through to the ground and power plane layers. Vias and power supply traces should be as large as possible to minimize the impedance. POWER SUPPLIES T he power supply providing analog power should be as clean as possible to minimize coupling into the analog section and degrading analog performance. The VD1 is isolated from the rest of the power supply pins and provide digital power for the asynchronous parallel ISA bus. The VD1 pin can be connected directly to the system digital power supply. VDF1 through VDF3 provide power to internal digital sections of the codec and should be quieter than VD1. This can be achieved by using a ferrite bead to the VD1 supply. VA provides power to the sensitive analog sections of the chip and should have a clean, regulated supply to minimize power supply coupled noise in the analog inputs and outputs. Di g it al Gr o Crystal Part Analog Ground 1 un d No ise Digital Ground Digital Ground Noise G tal igi D ro un ise No d Power Connector Figure 23. Suggested Motherboard Layout 78 DS253PP2 CS4239 CrystalClear Portable ISA Audio System Speaker Out CD-ROM TM Speaker In Analog Ground Crystal Part 1 Digital Ground Figure 24. Suggested Add-In Card Layout 1µ F + PIN 98 VDF3 PIN 1 .1µ F PIN 97 SGND3 PIN 80 AGND PIN 81 VA .1µ F PIN 79 .1µ F REFFLT Analog PIN 71 TEST PIN 66 SGND2 .1µ F Digital PIN 17 VDF1 PIN 65 VDF2 = vias through to power/ground plane .1µ F PIN 18 SGND1 PIN 53 SGND4 PIN 45 VD1 .1µ F PIN 46 DGND1 Figure 25. Recommended Decoupling Capacitor Positions DS253PP2 79 CS4239 CrystalClear Portable ISA Audio System TM ADC/DAC FILTER RESPONSE PLOTS Figures 26 through 31 show the overall frequency response, passband ripple, and transition band for the ADCs and DACs. Figure 32 shows the DACs’ deviation from linear phase. Since the filter response scales based on sample frequency selected, all frequency response plots x-axis are shown from 0 to 1, where 1 is equivalent to Fs. Therefore, for any given sample frequency, multiply the x-axis values by the sample frequency selected to get the actual frequency. 10 0 -10 -20 Magnitude (dB) -30 -40 -50 -60 -70 -80 -90 -100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Input Frequency ( x Fs) Figure 26. ADC Filter Response 0.2 0.1 0.0 0 - 10 - 20 Magnitude (dB) -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0.00 Magnitude (dB) 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 -0.1 - 30 - 40 - 50 - 60 - 70 - 80 - 90 -100 0.40 0.45 0.50 0.55 0.60 0.65 0.70 Input Frequency ( x Fs) Input Frequency ( x Fs) Figure 27. ADC Passband Ripple 80 Figure 28. ADC Transition Band DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM 10 0 -10 -20 0.2 0.1 0.0 Magnitude (dB) -30 -40 -50 -60 -70 -80 -90 Magnitude (dB) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0.00 -100 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency ( x Fs) Input Frequency ( x Fs) Figure 29. DAC Filter Response Figure 30. DAC Passband Ripple 0 -10 -20 2.0 1.5 1.0 ∆ P hase (degrees) Magnitude (dB) -30 -40 -50 -60 -70 -80 -90 -100 0.40 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0.00 0.45 0.50 0.55 0.60 0.65 0.70 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency ( x Fs) Input Frequency ( x Fs) Figure 31. DAC Transition Band Figure 32. Deviation from Linear Phase DS253PP2 81 CS4239 CrystalClear Portable ISA Audio System TM PIN DESCRIPTIONS XTALI XTALO VDF3 SGND3 CMAUX2 MUTE SA12*/CDCS SA13*/CDACK SA14*/CDINT SA15*/CDRQ RESDRV APSEL MIN FLT3D REFFLT VREF LAUX2 RAUX2 MIC AGND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 FLTO FLTI 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VA SDATA/SDIN LRCLK/FSYNC MCLK/SCLK ZLRCLK SDOUT ZSDATA ZSCLK SDA UP XCTL0 SCL BRESET XCTL1*/ACDCS/DOWN VDF1 SGND1 (INT15*) IRQF (INT12*) IRQE (INT11*) IRQD (INT9*) IRQC (INT7*) IRQB (INT5*) IRQA SA0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LAUX1 RAUX1 LOUT ROUT TEST JAB1 JBB1 JACX JBCX SGND2 VDF2 JBCY JACY JBB2 JAB2 MIDOUT MIDIN DACKA (DACK0*) DACKC (DACK3*) DACKB (DACK1*) DRQA (DRQ0*) IRQG (INT10) SGND4 DRQC (DRQ3*) DRQB (DRQ1*) C S4239 IOW AEN IOCHRDY SD0 SD1 SD2 SD3 VD1 DGND1 SD4 SD5 SD6 SD7 IOR (TOP VIEW ) * Defaults - See individual pin descriptions for more details 82 DS253PP2 SA6 SA7 SA8 SA9 SA10 SA11 SA1 SA2 SA3 SA4 SA5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100-PIN TQFP CS4239 CrystalClear Portable ISA Audio System TM ISA Bus Interface Pins SA - System Address Bus, Inputs These signals are decoded during I/O cycles to determine access to the various functional blocks within the part as defined by the configuration data written during a Plug and Play configuration sequence. SA - Upper System Address Bus, Inputs These signals are multi-function pins, shared with the CDROM, that default to the upper address bits SA12 through SA15. These pins are generally used for motherboard designs that want to eliminate address decode aliasing. Using these pins as upper address bits forces the part to only accept valid address decodes when A12-A15 = 0. If these pins are not used for address decodes or for CDROM support, they should be tied to SGND. These pins are forced to the CDROM interface when a 10 kΩ resistor is placed on pin MCLK/SCLK to SGND. SD - System Data Bus, Bi-directional, 24 mA drive These signals are used to transfer data to and from the part. AEN - Address Enable, Input This signal indicates whether the current bus cycle is an I/O cycle or a DMA cycle. This signal is low during an I/O cycle and high during a DMA cycle. IOR - Read Command Strobe, Input This active low signal defines a read cycle to the part. The cycle may be a register read or a read from the part’s DMA registers. IOW - Write Command Strobe, Input This active low signal indicates a write cycle to the part. The cycle may be a write to a control register or a DMA register. IOCHRDY - I/O Channel Ready, Open Drain Output, 8 mA drive This signal is driven low by the part during ISA bus cycles in which the part is not able to respond within a minimum cycle time. IOCHRDY is forced low to extend the current bus cycle. The bus cycle is extended until IOCHRDY is brought high. DRQ - DMA Requests, Outputs, 24 mA drive These active high outputs are generated when the part is requesting a DMA transfer. This signal remains high until all the bytes have been transferred as defined by the current transfer data type. The DRQ outputs must be connected to 8-bit DMA channel request signals only. The defaults on the ISA bus are DRQA = DRQ0, DRQB = DRQ1, and DRQC = DRQ3. The defaults can be changed by modifying the Hardware Resource data. DS253PP2 83 CS4239 CrystalClear Portable ISA Audio System TM DACK - DMA Acknowledge, Inputs The assertion of these active low signals indicate that the current DMA request is being acknowledged and the part will respond by either latching the data present on the data bus (write) or putting data on the bus (read). The DACK inputs must be connected to 8-bit DMA channel acknowledge lines only. The defaults on the ISA bus are DACKA = DACK0, DACKB = DACK1, and DACKC = DACK3. The defaults can be changed by modifying the Hardware Resource data. IRQ - Host Interrupt Pins, Outputs, 24 mA drive These signals are used to notify the host of events which need servicing. They are connected to specific interrupt lines on the ISA bus. The IRQ are individually enabled as per configuration data that is generated during a Plug and Play configuration sequence. The defaults on the ISA bus are IRQA = INT5, IRQB = INT7, IRQC = INT9, IRQD = INT11, IRQE = INT12, IRQF = INT15. IRQG is new to the CS4239 and defaults to unconnected for compatibility reasons. For new designs, IRQG is typically connected to IRQ10. The defaults can be changed by modifying the Hardware Configuration data loaded from the E2PROM. RESDRV - Reset Drive, Input Places the part in lowest power consumption mode. All sections of the part are shut down and consuming minimal power. The part is reset and in power down mode when this pin is logic high. The falling edge also latches the state of MCLK and SCLK to determine the functionality of dual mode pins, and SCL to determine the Address Port. This signal is typically connected to the ISA bus signal RESDRV. RESDRV must be asserted whenever the part is powered up to initialize the internal registers to a known state. This pin, when high, also drives the BRESET pin low. Analog Inputs MIC - Mic Input Microphone input centered around VREF. A programmable gain block provides volume control and is located in X2 with mutes located in X2 and X3. LAUX1 - Left Auxiliary #1 Input Nominally 1 VRMS max analog input for the Left AUX1 channel, centered around VREF. A programmable gain block provides volume control and is located in I2. Typically used for an external Left line-level input. RAUX1 - Right Auxiliary #1 Input Nominally 1 VRMS max analog input for the Right AUX1 channel, centered around VREF. A programmable gain block provides volume control and is located in I3. Typically used for an external Right line-level input. LAUX2 - Left Auxiliary #2 Input Nominally 1 VRMS max analog input for the Left AUX2 channel, centered around VREF. A programmable gain block provides volume control and is located in I4. Typically used for the Left channel CDROM input. 84 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM RAUX2 - Right Auxiliary #2 Input Nominally 1 VRMS max analog input for the Right AUX2 channel, centered around VREF. A programmable gain block provides volume control and is located in I5. Typically used for the Right channel CDROM input. CMAUX2 - Common Mode Auxiliary #2 Input Common mode ground input for the LAUX2 and RAUX2 inputs. Typically connected to the CDROM ground input to provide common-mode noise rejection. The impedance on this pin should be one half the impedance on the LAUX2 and RAUX2 inputs. MIN - Mono Input Nominally 1 VRMS m ax analog input, centered around VREF, that goes through a programmable gain stage (I26) into both channels of the output mixer. This is a general purpose mono analog input that is normally used to mix the typical "beeper" signal on most computers into the audio system. REFFLT - Reference Filter, Input Voltage reference used internal to the part. A 0.1 µF and a 1 µF capacitor with short fat traces must be connected between this pin and AGND. No other connections should be made to this pin. Analog Outputs LOUT - Left Line Level Output Analog output from the mixer for the left channel. Nominally 1 VRMS max centered around VREF. This pin needs a 1000 pF NPO capacitor attached and tied to analog ground. ROUT - Right Line Level Output Analog output from the mixer for the Right channel. Nominally 1 VRMS max centered around VREF. This pin needs a 1000 pF NPO capacitor attached and tied to analog ground. FLT3D - 3D Filter This pin needs a 0.01 µF capacitor attached and tied to analog ground. FLTO - Filter Output This pin needs a 1000 pF NPO capacitor attached and tied to FLTI. FLTI - Filter Input This pin needs a 1000 pF NPO capacitor attached and tied to FLTO. VREF - Voltage Reference, Output All analog inputs and outputs are centered around VREF which is nominally 2.1 Volts. This pin may be used to level shift external circuitry, although any AC loads should be buffered. DS253PP2 85 CS4239 CrystalClear Portable ISA Audio System TM MIDI Interface MIDOUT - MIDI Out Transmit Data, Output, 4 mA drive This output is used to send MIDI data serially out to a external MIDI device. Normally connected to pin 12 of the joystick connector for use with breakout boxes, as well as on-board synthesizers. MIDIN - MIDI In Receive Data, Input - Internal Pullup This input is used to receive serial MIDI data from an external MIDI device. This pin should be connected to pin 15 of the joystick connector for use with breakout boxes. External Peripheral Signals SDA - E2PROM Data Pin, Bi-directional, Open Drain, 4 mA sink This open-drain pin must have an external pullup (3.3 kΩ) and is used in conjunction with SCL to access an external serial E2PROM. When an E2PROM is used, the SDA pin should be connected to the data pin of the E2PROM device and provides a bi-directional data port. The E2PROM is used to set the Plug and Play resource data. XCTL0 - External Control, Output, 4 mA drive This pin is a general purpose output pin controlled by the XCTL0 bit in the WSS register I10. SCL - E2PROM Serial Clock, Output, 4 mA drive (Address Port Selection) When E2PROM access is enabled, via EEN in CTRLbase+1, then SCL is used as a clock output to the E2PROM. At power-up, this pin is an input (with an internal 100 kΩ pullup) that selects between two alternate addresses for the Address Port used to configure the chip. Assuming APSEL is strapped low, SCL high selects 308h as the Address Port, and when SCL is tied low (with a 10 kΩ resistor to ground), the Address Port is 388h. BRESET - Buffered Reset, Output, 4 mA drive This active low signal goes low whenever the RESDRV pin goes high. This pin is also software controllable through the BRES bit in register C8 in the Control Logical Device space. BRES provides a software power down and reset control over devices connected to the CS4239 such as the CS9236 Single-Chip Wavetable Music Synthesizer. 86 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM Joystick Interface JACX, JACY - Joystick A Coordinates, Input These pins are the X/Y coordinates for Joystick A. They should have a 5.6 nF capacitor to ground and a 2.2 kΩ resistor to the joystick connector pins 3 and 6, respectively. JAB1, JAB2 - Joystick A Buttons, Input - Internal Pullups These pins are the switch inputs for Joystick A. They should be connected to joystick connector pins 2 and 7, respectively; as well as have a 1 nF capacitor to ground. JBCX, JBCY - Joystick B Coordinates, Input These pins and are the X/Y coordinates for the second joystick, Joystick B. They should have a 5.6 nF capacitor to ground and a 2.2 kΩ resistor to the joystick connector pins 11 and 13, respectively. JBB1, JBB2 - Joystick B Buttons, Input - Internal Pullups These pins are the switch inputs for the second joystick, Joystick B. They should be connected to joystick connector pins 10 and 14, respectively; as well as have a 1 nF capacitor to ground. CS4610 DSP Serial Port Interface The CS4610 DSP serial port pins are shared with the CS9236 Wavetable serial port. When the serial port is enabled, SPE = 1 in I16, these pins are forced to the CS4610 DSP interface. FSYNC - Frame Sync, Output When the serial port is enabled, SPE = 1 in I16, this pin is the serial frame sync output. SCLK - Serial Clock, Output (CDROM Enable) When the serial port is enabled, SPE = 1 in I16, this pin is the serial clock output. At power-up, this pin is an input (with an internal 100 kΩ pullup) that, when pulled low with a 10 kΩ resistor to SGND, enables the CDROM interface (over the upper 4 ISA address pins). Loading must be limited to CMOS inputs if this pin has the 10 kΩ resistor attached. SDOUT - Serial Data Output, Output (Alternate CDROM Chip Select Enable) When the serial port is enabled, SPE = 1 in I16, this pin is the serial data output. At power-up, this pin is an input (with an internal 100 kΩ pullup) that, when pulled low with a 10 kΩ resistor to SGND, enables the alternate CDROM chip select pin ACDCS. Loading must be limited to CMOS inputs if this pin has the 10 kΩ resistor attached. SDIN - Serial Data Input, Input When the serial port is enabled, SPE = 1 in I16, this pin is the serial data input. DS253PP2 87 CS4239 CrystalClear Portable ISA Audio System TM CS9236 Wavetable Serial Port Interface A digital interface to the CS9236 Single-Chip Wavetable Music Synthesizer is provided that allows the CS9236 PCM audio data to be summed on the CS4239 without the need for an external DAC. This serial port is enabled via the WTEN bit which is located in the Global Configuration byte in the E2PROM Hardware Configuration data, or C8. The CS9236 Wavetable serial port pins are shared with the CS4610 DSP serial interface. If the CS4610 serial interface is enabled, the CS9236 interface is not available (SPE takes precedence over WTEN). SDATA - Wavetable Serial Audio Data, Input This input supplies the serial audio PCM data to be mixed on the CS4239. The data consists of left and right channel 16-bit data delineated by LRCLK. This pin should be connected to the SOUT output pin on the CS9236. This pin should also have a weak pull-down resistor of approx. 100 kΩ to minimize power-down currents and allow for stuffing options. LRCLK - Wavetable Serial Left/Right Clock, Input This input supplies the serial data alignment signal that delineates left from right data. This pin should be connected to the LRCLK output pin on the CS9236. This pin should also have a weak pull-down resistor of approx. 100 kΩ to minimize power-down currents and allow for stuffing options. MCLK - Wavetable Master Clock, Output (CDROM Enable) This output supplies the 16.9344 MHz master clock that controls all the timing on the CS9236. This pin should be connected to the MCLK5I input pin on the CS9236. MCLK can be disabled in software using the DMCLK bit in C8 in the Control logical device space. DMCLK provides a partial software power-down mode for the CS9236. At power-up, this pin is an input (with an internal 100 kΩ pullup) that, when pulled low with a 10 kΩ resistor to SGND, enables the CDROM interface (in lieu of the upper four ISA address pins). Loading must be limited to CMOS inputs if this pin has the 10 kΩ resistor attached. ZVPORT Serial Port Interface ZSDATA - ZV Port Serial Data, Input When the ZV port is enabled, ZVEN = 1 in X18, this pin is the serial data input. ZLRCLK - ZV Port Left/Right Clock, Input When the ZV port is enabled, ZVEN = 1 in X18, this pin is the Left/Right channel delineation clock input. ZSCLK - ZV Port Serial Clock, Input When the ZV port is enabled, ZVEN = 1 in X18, this pin is the serial data bit clock input. 88 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM CDROM Interface The four CDROM pins are multi-function and default to ISA upper address bits SA12-SA15. To enable the CDROM port, an external 10 kΩ resistor must be tied between MCLK/SCLK and SGND. MCLK/SCLK is sampled on the falling edge of RESDRV. The alternate CDROM chip select has its own strapping option to enable ACDCS. Use of the CDROM interface requires a 1 k E2PROM to support the Plug-and-Play data as well as firmware patch data. CDCS - CDROM Chip Select, Output, 4 mA drive This output goes low whenever an address is decoded that matches the value programmed into the CDROM base address register. ACDCS - Alternate CDROM Chip Select, Output, 4 mA drive This pin, XCTL1/ACDCS/DOWN, is multiplexed with two other functions, and defaults to the XCTL1 output which is controlled by the XCTL1 bit in the WSS I10. This pin can also be configured at a second CDROM Chip Select, ACDCS, to support the alternate IDE CDROM decode. To force this pin to the CDROM alternate chip select, an external 10 kΩ resistor must be tied between SDOUT and SGND. ACDCS output then goes low whenever an address is decoded that matches the value programmed into the CDROM alternate base address register, ACDbase. This pin can also be used as the volume up pin DOWN by setting VCEN in Control register C0 or the Hardware Configuration data. VCEN has the highest precedence over the other pin functions. CDINT - CDROM Interrupt, Input This pin is used to input an interrupt signal from the CDROM interface. The part can be programmed, through the plug-and-play resource data, to output this signal to the appropriate ISA bus interrupt line. The polarity if this input can be programmed through CTRLbase+1 register, bit ICH, or the Hardware Configuration data; the default is active high. CDRQ - CDROM DMA Request, Input This pin can be used to input the DMA request signal from the CDROM interface. The part can be programmed, through the plug-and-play resource data, to output this signal to the appropriate ISA bus DRQ line. CDACK- CDROM DMA Acknowledge, Output, 4 mA drive This pin can be used to output the ISA bus-generated DMA acknowledge signal to the CDROM interface. DS253PP2 89 CS4239 CrystalClear Portable ISA Audio System TM Volume Control The volume control pins are enabled by setting VCEN in the Hardware Configuration data, Misc. Hardware Config. byte. The VCF1 bit in the Hardware Configuration data, Global Configuration byte, set the format for the volume control pins. Typically a 100 Ω series resistor and a 10 nF capacitor (required) to ground, capacitor on the switch side of the series resistor, would be included on each pin for ESD protection and to help with EMI emissions. UP - Volume Up - Internal Pullup This pin is enabled when VCEN is set. When UP is low, the master volume output for left and right channels are incremented. A 10 nF capacitor to ground is required for switch debounce. DOWN - Volume Down - Internal Pullup The XCTL1/ACDCS/DOWN is a multiplexed pin that can be used as XCTL1, the alternate CDROM chip select, or the Volume Down pin. This pin is switched to the DOWN function when VCEN is set. When DOWN is low, the master volume output for left and right channels are decremented. A 10 nF capacitor to ground is required for switch debounce. MUTE - Volume Mute - Internal Pullup The MUTE pin function can be momentary, or non-existent based on the VCF1 bit. The MUTE function is enabled when VCEN is set. A 10 nF capacitor to ground is required for switch debounce. Miscellaneous XTALI - Crystal Input This pin will accept either a crystal, with the other pin attached to XTALO, or an external CMOS clock. XTAL must have a crystal or clock source attached for proper operation. The crystal frequency must be 16.9344 MHz and designed for fundamental mode, parallel resonance operation. XTALO - Crystal Output This pin is used for a crystal placed between this pin and XTALI. If an external clock is used on XTALI, this pin must be left floating with no traces or components connected to it. APSEL - Address Port Select, Input This pin has an internal pull-up of approximately 100 kΩ. Leaving this pin in its default condition, places the PnP/Crystal Key Address Port at the standard PnP address of 279h (hex). For Motherboard applications, APSEL can be tied to SGND, which will change the Address Port to one of two other addresses, chosen by a strapping option on pin SCL. When RESDRV goes inactive, pin SCL is forced to an input and sampled. When SCL is sampled high (default), the Address Port changes to address 308h. When SCL is sampled low, the Address Port changes to 388h. Add-in cards should leave APSEL unconnected. TEST - Test This pin must be tied to ground for proper operation. 90 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM Power Supplies VA - Analog Supply Voltage Supply to the analog section of the codec. AGND - Analog Ground Ground reference to the analog section of the codec. This pin should be placed on an analog ground pin separate from other chip grounds. VD1 - ISA Digital Supply Voltage Digital supply for the parallel data bus pins. This pin can be connected to either 3.3 V or 5 V power supply. When connected to a 3.3 V supply, all ISA bus pins must also be at 3.3 V. DGND1 - ISA Digital Ground Digital ground reference for the parallel data bus pins. These pins are isolated from the other grounds and should be connected to the digital ground section of the board (see Figure 25). VDF1, VDF2, VDF3 - Digital Filtered Supply Voltage Digital supply for the internal digital section of the codec (except for the parallel data bus). These pins should be filtered, using a ferrite bead, from VD1. SGND1, SGND2, SGND3, SGND4 - Internal Digital Ground Ground reference for the internal digital section of the codec. Optimum layout is achieved by placing SGND1/2/3/4 on the digital ground plane with the DGND pin as shown in Figure 25. DS253PP2 91 CS4239 CrystalClear Portable ISA Audio System TM PARAMETER DEFINITIONS Frequency Response Frequency Response is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The amplitude corner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The listed minimum and maximum frequencies are guaranteed to be within the Ac from minimum frequency to maximum frequency inclusive. Total Dynamic Range TDR is the ratio of the RMS sum of the lowest obtainable noise floor, in the presence of a signal, divided by the RMS full-scale signal level. The lowest obtainable noise floor is defined as the noise floor measured with the attenuation bits for the volume control at full attenuation without muting. Measured over a 20 Hz to 20 kHz bandwidth with units in dB FS A. (dB FS is defined as dB relative to full-scale. The "A" indicates an A weighting filter was used.) Instantaneous Dynamic Range or Dynamic Range IDR or DR is the ratio of the RMS sum of the noise floor, in the presence of a signal, divided by the RMS full-scale signal level, available at any instant in time (no change in gain settings between measurements). Measured over a 20 Hz to 20 kHz bandwidth with units in dB FS A. (dB FS is defined as dB relative to full-scale. The "A" indicates an A weighting filter was used.) Total Harmonic Distortion plus Noise THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMS full-scale signal level. Tested using a -3 dB FS input signal. Measured over a 20 Hz to 20 kHz bandwidth with units in dB FS A. (dB FS is defined as dB relative to full-scale. The "A" indicates an A weighting filter was used.) Interchannel Isolation The ratio of signal level on the tested channel divided by the stimulus channel level. For inputs, the tested input channel is terminated with 50 Ω. For outputs, the tested channel is fed digital zeros. Units in dB. Interchannel Gain Mismatch For the ADCs, the difference in input voltage to get an equal code on both channels. For the DACs, the difference in output voltages for each channel when both channels are fed the same code. Units in dB. PATHS: A-D-PC: Analog in, through ADC, onto PC bus PC-D-A: PC bus, through DAC, to analog out A-A: Analog in to Analog out (analog output mixer) Detailed information on audio testing and paths can be found in Personal Computer Audio Quality Measurements document by Dr. Steven Harris and Clif Sanchez, located at the following web address: http://www.cirrus.com/products/papers/meas/meas.html. 92 DS253PP2 CS4239 CrystalClear Portable ISA Audio System TM PACKAGE PARAMETERS D D1 100-pin TQFP - Package Code ’Q’ MIN Symbol Description N Lead Count A Overall Height A1 0.00 Stand Off 0.14 Lead Width b Lead Thickness 0.077 c Terminal Dimension 15.70 D Package Body D1 Terminal Dimension 15.70 E Package Body E1 0.40 Lead Pitch e1 0.30 Foot Length L1 0.0° Lead Angle T NOM 100 MAX 1.66 0.20 0.127 16.00 14.0 16.00 14.0 0.50 0.50 0.26 0.177 16.30 16.30 0.60 0.70 12.0° E E1 1 L1 e1 b T A1 A c Notes: 1) Dimensions in millimeters. 2) Package body dimensions do not include mold protrusion, which is 0.25 mm. 3) Coplanarity is 0.004 in. 4) Lead frame material is AL-42 or copper, and lead finish is solder plate. 5) Pin 1 identification may be either ink dot or dimple. 6) Package top dimensions can be smaller than bottom dimensions by 0.20 mm. 7) The "lead width with plating" dimension does not include a total allowable dambar protrusion of 0.08 mm (at maximum material condition). 8) Ejector pin marks in molding are present on every package. DS253PP2 100 93 CS4239 CrystalClear Portable ISA Audio System TM APPENDIX A: DEFAULT PnP DATA ; EEPROM Validation Bytes DB 055H, 0BBH DB DB ; Hardware DB DB DB DB DB DB DB DB DB DB DB DB ; Hardware DB DB DB DB DB DB DB 001H 014H Configuration Data 000H 003H 080H 080H 005H 020H 004H 008H 010H 080H 000H 000H Mapping Data 004H 048H 075H 0B9H 0FCH 010H 003H ; EEPROM Validation Bytes: CS4239 ; EEPROM data length upper byte ; lower byte, Listed Size = 276 ; ; ; ; ; ; ; ; ; ; ; ; ACDbase Addr. Mask Length = 1 bytes MCB: IHCD GCB1: IFM Code Base Byte FM Scaling 0 dB RESERVED RESERVED RESERVED M+DSP: MIM GCB2: No Bits Set ; ; ; ; ; ; ; CDbase Length = 4 RESERVED IRQ selection A & B IRQ selection C & D IRQ selection E & F DMA selection A & B DMA C,IRQ G select. - B= 7, D=11, F=15, B= 1, G= 0, A=5 C=9 E=12 A=0 C=3 ; PnP Resource Header - PnP ID for CS4236 IC, OEM ID = 42 DB 00EH, 063H, 042H, 036H, 0FFH,0FFH,0FFH,0FFH,0A9H ; CSC4236 FFFFFFFF DB 00AH, 010H, 005H ; PnP version 1.0, Vendor version 0.5 DB 082H, 00EH, 000H, ’Crystal Codec’, 000H ; ANSI ID ; LOGICAL DEVICE 0 (Windows Sound System & SBPro) DB 015H, 00EH, 063H, 000H, 000H, 000H ; EISA ID: CSC0000 DB DB DB DB DB DB DB DB DB DB DB DB 082H, 031H, 02AH, 02AH, 022H, 047H, 047H, 047H, 031H, 02AH, 02AH, 022H, 007H, 000H 002H, 009H, 020H, 001H, 001H, 001H, 000H, ’WSS/SB’, 000H ; ANSI ID ; DF Best Choice 028H ; DMA: 1 - WSS & SBPro 028H ; DMA: 0,3 - WSS & SBPro 000H ; IRQ: 5 Interrupt Select 034H, 005H, 034H, 005H, 004H, 004H ;16b 088H, 003H, 088H, 003H, 008H, 004H ;16b 020H, 002H, 020H, 002H, 020H, 010H ;16b capture 0 WSSbase: 534 SYNbase: 388 SBbase: 220 001H 00AH, 028H 00BH, 028H 0A0H, 09AH ; DF Acceptable Choice 1 ; DMA: 1,3 - WSS & SBPro ; DMA: 0,1,3 - WSS & SBPro capture ; IRQ: 5,7,9,11,12,15 Interrupt Select 0 94 DS253PP2 CS4239 CrystalClear Portable ISA Audio System DB DB DB DB DB DB DB DB DB DB 047H, 001H, 034H, 005H, 0FCH, 00FH, 004H, 004H ;16b WSSbase: 534-FFC 047H, 001H, 088H, 003H, 088H, 003H, 008H, 004H ;16b SYNbase: 388 047H, 001H, 020H, 002H, 060H, 002H, 020H, 010H ;16b SBbase: 220-260 031H, 02AH, 022H, 047H, 047H, 047H, 038H 002H 00BH, 0A0H, 001H, 001H, 001H, ; DF Suboptimal Choice 1 028H ; DMA: 0,1,3 - WSS & SBPro 09AH ; IRQ: 5,7,9,11,12,15 Interrupt Select 0 034H, 005H, 0FCH, 00FH, 004H, 004H ;16b WSSbase: 534-FFC 088H, 003H, 0F8H, 003H, 008H, 004H ;16b SYNbase: 388-3F8 020H, 002H, 000H, 003H, 020H, 010H ;16b SBbase: 220-300 ; End of DF for Logical Device 0 TM ; LOGICAL DEVICE 1 (Game Port) DB 015H, 00EH, 063H, 000H, 001H, 000H ; EISA ID: CSC0001 DB DB DB DB DB DB 082H, 005H, 000H, ’GAME’, 000H ; ANSI ID 031H, 000H ; DF Best Choice 047H, 001H, 000H, 002H, 000H, 002H, 008H, 008H ;16b GAMEbase: 200 031H, 001H ; DF Acceptable Choice 1 047H, 001H, 008H, 002H, 008H, 002H, 008H, 008H ;16b GAMEbase: 208 038H ; End of DF for Logical Device 1 ; LOGICAL DEVICE 2 (Control) DB 015H, 00EH, 063H, 000H, 010H, 000H ; EISA ID: CSC0010 DB DB 082H, 005H, 000H, ’CTRL’, 000H ; ANSI ID 047H, 001H, 020H, 001H, 0F8H, 00FH, 008H, 008H ;16b CTRLbase: 120-FF8 ; LOGICAL DEVICE 3 (MPU-401) DB 015H, 00EH, 063H, 000H, 003H, 000H ; EISA ID: CSC0003 DB DB DB DB DB DB DB DB DB DB 082H, 031H, 022H, 047H, 004H, 000H, ’MPU’, 000H ; ANSI ID 000H ; DF Best Choice 000H, 002H ; IRQ: 9 Interrupt Select 0 001H, 030H, 003H, 030H, 003H, 008H, 002H ;16b MPUbase: 330 031H, 001H ; DF Acceptable Choice 1 022H, 000H, 09AH ; IRQ: 9,11,12,15 Interrupt Select 0 047H, 001H, 030H, 003H, 060H, 003H, 008H, 002H ;16b MPUbase: 330-360 031H, 002H ; DF Suboptimal Choice 1 047H, 001H, 030H, 003H, 0E0H, 003H, 008H, 002H ;16b MPUbase: 330-3E0 038H ; End of DF for Logical Device 3 DB 079H, 09AH ; End of Resource Data, Resource Size = 280 DS253PP2 95 CS4239 CrystalClear Portable ISA Audio System TM APPENDIX B: DIFFERENCES BETWEEN THE CS423xB AND THE CS4239 This part is designed to be hardware backwards compatible with some CS423xB designs, primarily motherboard applications. New drivers will be needed to support this part. Hardware Pin Differences: 1. RFILT and LFILT capacitors are no longer needed and should be removed. On the CS4239, these pins are renamed FLTI and FLTO and should have a capacitor placed between them. They are used for the Crystal 3D Sound circuitry. Not populating this capacitor will not have any adverse affects on the part, but will result in non-optimum 3D Sound. 2. The external L/RLINE analog inputs are no longer supported. LLINE is now FLT3D and is used for the 3D Sound function. A 0.01 µF capacitor should be placed between this pin and analog ground. When external analog wavetable is desired, the AUX1 analog inputs should be used. 3. The analog microphone inputs are now mono. LMIC is changed to MIC, and RMIC has been removed. 4. Mono Out, MOUT, has been removed. The pin is redefined as APSEL and used to change the Address Port. APSEL has an internal pullup, setting the Address Port to 0x279 for backwards compatibility. 5. VDF4 has been changed to IRQG - a seventh interrupt (typically used for INT 10). The default is disabled to provide backwards compatibility. 6. The Modem Logical Device has been removed. This includes MCS and MINT. 7. Support for an external synthesizer has been removed. This includes SCS and SINT. 8. The peripheral port has been removed. This includes XD, XIOR, XIOW, XA. CDROM applications must now drive the ISA bus directly or through buffers. 9. The hardware strap enable for the CDROM has been moved. CS423xB designs have a pulldown on XIOR. To support the CDROM interface on the CS4239, the pulldown must be moved to the MCLK/SCLK pin. Also, to enable the alternate CDROM chip select pin ACDCS, a pulldown must be added to pin SDOUT. 10. The DSP serial port is no longer supported as an option on the 2nd Joystick connector or on pins 4 through 7. The DSP port has moved to pins 1, 2, 3, 5 and is multiplexed with the CS9236 wavetable pins. 11. The consumer IEC-958 (S/PDIF) output, supported on the CS4237B and CS4238B, has been removed. 12. Only two modes of Hardware Volume Control are supported: 2-button, and 3-button with momentary mute. In addition, a 10 nF capacitor to ground is required for switch debounce on the CS4239. 13. Pullup resistors for the Joystick buttons, Hardware Volume Control pins, and the MIDIN pin are no longer required as they are internal to the CS4239. 96 DS253PP2 • Notes •