CS42428-CQZ

CS42428 114 dB, 192 kHz 8-Ch Codec with PLL Features ! Eight 24-bit D/A, two 24-bit A/D Converters ! 114 dB DAC / 114 dB ADC Dynamic Range ! -100 dB THD+N ! System Sampling Rates up to 192 kHz ! Integrated Low-Jitter PLL for Increased System General Description The CS42428 codec provides two analog-to-digital and eight digital-to-analog delta-sigma converters, as well as an integrated PLL. The CS42428 integrated PLL provides a low-jitter system clock. The internal stereo ADC is capable of independent channel gain control for single-ended or differential analog inputs. All eight channels of DAC provide digital volume control and differential analog outputs. The general-purpose outputs may be driven high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators. The CS42428 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, digital speaker and automotive audio systems. The CS42428 is available in a 64-pin LQFP package in both Commercial (-10° to 70° C) and Automotive (-40° to 85° C) grades. The CDB42428 Customer Demonstration board is also available for device evaluation. Refer to “Ordering Information” on page 71. Jitter Tolerance ! PLL Clock or System Clock Selection ! 7 Configurable General-Purpose Outputs ! ADC High-Pass Filter for DC Offset Calibration ! Expandable ADC Channels and One-Line Mode Support ! Digital Output Volume Control with Soft Ramp ! Digital +/-15 dB Input Gain Adjust for ADC ! Differential Analog Architecture ! Supports Logic Levels between 1.8 V and 5 V VA AGND GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 MUTEC REFGND VQ FILT+ OMCK RMCK LPFLT VLC DGND VD INT Mult/Div GPO Mute Internal Voltage Reference Control Port PLL RST AD0/CS AD1/CDIN SDA/CDOUT SCL/CCLK AINL+ AINLAINR+ AINR- ADC#1 ADC#2 Digital Filter Gain & Clip Gain & Clip Digital Filter ADC Serial Audio Port Level Translator ADCIN1 ADCIN2 ADC_SDOUT ADC_LRCK ADC_SCLK VLS DAC_LRCK AOUTA1+ AOUTA1AOUTB1+ AOUTB1AOUTA2+ AOUTA2Analog Filter AOUTB2+ AOUTB2AOUTA3+ AOUTA3AOUTB3+ AOUTB3AOUTA4+ AOUTA4AOUTB4+ AOUTB4- DAC#1 DAC#2 DAC#3 Volume Control Digital Filter DAC#4 DAC#5 DAC#6 DAC#7 DAC#8 DAC Serial Audio Port Level Translator DAC_SCLK DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) NOVEMBER '05 DS605F1 CS42428 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 SPECIFIED OPERATING CONDITIONS ............................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 6 ANALOG INPUT CHARACTERISTICS .................................................................................................. 7 A/D DIGITAL FILTER CHARACTERISTICS .......................................................................................... 8 ANALOG OUTPUT CHARACTERISTICS .............................................................................................. 9 D/A DIGITAL FILTER CHARACTERISTICS ........................................................................................ 10 SWITCHING CHARACTERISTICS ...................................................................................................... 11 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT .............................................. 12 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT .......................................... 13 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 14 DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 15 2. PIN DESCRIPTIONS ............................................................................................................................ 16 3. TYPICAL CONNECTION DIAGRAMS .............................................................................................. 18 4. APPLICATIONS ................................................................................................................................... 20 4.1 Overview ......................................................................................................................................... 20 4.2 Analog Inputs .................................................................................................................................. 20 4.2.1 Line-Level Inputs ................................................................................................................... 20 4.2.2 High-Pass Filter and DC Offset Calibration ........................................................................... 21 4.3 Analog Outputs ............................................................................................................................... 21 4.3.1 Line-Level Outputs and Filtering ........................................................................................... 21 4.3.2 Interpolation Filter .................................................................................................................. 21 4.3.3 Digital Volume and Mute Control ........................................................................................... 22 4.3.4 ATAPI Specification ............................................................................................................... 22 4.4 Clock Generation ............................................................................................................................ 23 4.4.1 PLL and Jitter Attenuation ..................................................................................................... 23 4.4.2 OMCK System Clock Mode ................................................................................................... 24 4.4.3 Master Mode ......................................................................................................................... 24 4.4.4 Slave Mode ........................................................................................................................... 24 4.5 Digital Interfaces ............................................................................................................................. 25 4.5.1 Serial Audio Interface Signals ............................................................................................... 25 4.5.2 Serial Audio Interface Formats .............................................................................................. 27 4.5.3 ADCIN1/ADCIN2 Serial Data Format .................................................................................... 30 4.5.4 One-Line Mode (OLM) Configurations .................................................................................. 31 4.5.4.1 OLM Config #1 ........................................................................................................... 31 4.5.4.2 OLM Config #2 ........................................................................................................... 32 4.5.4.3 OLM Config #3 ........................................................................................................... 33 4.5.4.4 OLM Config #4 ........................................................................................................... 34 4.6 Control Port Description and Timing ............................................................................................... 35 4.6.1 SPI Mode ............................................................................................................................... 35 4.6.2 I²C Mode ................................................................................................................................ 36 4.7 Interrupts ........................................................................................................................................ 37 4.8 Reset and Power-Up ...................................................................................................................... 37 4.9 Power Supply, Grounding, and PCB Layout .................................................................................. 38 5. REGISTER QUICK REFERENCE ........................................................................................................ 39 6. REGISTER DESCRIPTION .................................................................................................................. 42 6.1 Memory Address Pointer (MAP) ..................................................................................................... 42 6.2 Chip I.D. and Revision Register (address 01h) (Read Only) .......................................................... 42 6.3 Power Control (address 02h) .......................................................................................................... 43 6.4 Functional Mode (address 03h) ...................................................................................................... 43 6.5 Interface Formats (address 04h) .................................................................................................... 45 6.6 Misc Control (address 05h) ............................................................................................................ 46 2 DS605F1 CS42428 6.7 Clock Control (address 06h) ........................................................................................................... 48 6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ....................................................................... 49 6.9 Clock Status (address 08h) (Read Only) ........................................................................................ 50 6.10 Volume Transition Control (address 0Dh) .................................................................................... 51 6.11 Channel Mute (address 0Eh) ........................................................................................................ 52 6.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h) ...................................... 53 6.13 Channel Invert (address 17h) ....................................................................................................... 53 6.14 Mixing Control Pair 1 (Channels A1 & B1)(address 18h) Mixing Control Pair 2 (Channels A2 & B2)(address 19h) Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah) Mixing Control Pair 4 (Channels A4 & B4)(address 1Bh) ............................................................ 53 6.15 ADC Left Channel Gain (address 1Ch) ........................................................................................ 55 6.16 ADC Right Channel Gain (address 1Dh) ...................................................................................... 55 6.17 Interrupt Control (address 1Eh) .................................................................................................... 55 6.18 Interrupt Status (address 20h) (Read Only) ................................................................................. 56 6.19 Interrupt Mask (address 21h) ....................................................................................................... 57 6.20 Interrupt Mode MSB (address 22h) Interrupt Mode LSB (address 23h) ............................................................................................... 57 6.21 Mutec Pin Control (address 28h) .................................................................................................. 57 6.22 General-Purpose Pin Control (addresses 29h to 2Fh) ................................................................. 58 7. PARAMETER DEFINITIONS ................................................................................................................ 60 8. APPENDIX A: EXTERNAL FILTERS ................................................................................................... 61 8.1 ADC Input Filter .............................................................................................................................. 61 8.2 DAC Output Filter ........................................................................................................................... 61 9. APPENDIX B: PLL FILTER .................................................................................................................. 62 9.1 External Filter Components ............................................................................................................ 62 9.1.1 General .................................................................................................................................. 62 9.1.2 Capacitor Selection ............................................................................................................... 62 9.1.3 Circuit Board Layout .............................................................................................................. 63 10. APPENDIX C: ADC FILTER PLOTS .................................................................................................. 64 11. APPENDIX D: DAC FILTER PLOTS .................................................................................................. 66 12. PACKAGE DIMENSIONS ............................................................................................................... 70 THERMAL CHARACTERISTICS .......................................................................................................... 70 13. ORDERING INFORMATION .............................................................................................................. 71 14. REFERENCES .................................................................................................................................... 71 15. REVISION HISTORY ......................................................................................................................... 72 LIST OF FIGURES Figure 1.Serial Audio Port Master Mode Timing ....................................................................................... 11 Figure 2.Serial Audio Port Slave Mode Timing ......................................................................................... 11 Figure 3.Control Port Timing - I²C Format ................................................................................................. 12 Figure 4.Control Port Timing - SPI Format ................................................................................................ 13 Figure 5.Typical Connection Diagram ....................................................................................................... 18 Figure 6.Typical Connection Diagram using the PLL ................................................................................ 19 Figure 7.Full-Scale Analog Input ............................................................................................................... 20 Figure 8.Full-Scale Output ........................................................................................................................ 21 Figure 9.ATAPI Block Diagram (x = channel pair 1, 2, 3, 4) ..................................................................... 22 Figure 10.Clock Generation ...................................................................................................................... 23 Figure 11.Right-Justified Serial Audio Formats ......................................................................................... 27 Figure 12.I²S Serial Audio Formats ........................................................................................................... 28 Figure 13.Left-Justified Serial Audio Formats ........................................................................................... 28 Figure 14.One Line Mode #1 Serial Audio Format .................................................................................... 29 Figure 15.One Line Mode #2 Serial Audio Format .................................................................................... 29 DS605F1 3 CS42428 Figure 16.ADCIN1/ADCIN2 Serial Audio Format ...................................................................................... 30 Figure 17.OLM Configuration #1 ............................................................................................................... 31 Figure 18.OLM Configuration #2 ............................................................................................................... 32 Figure 19.OLM Configuration #3 ............................................................................................................... 33 Figure 20.OLM Configuration #4 ............................................................................................................... 34 Figure 21.Control Port Timing in SPI Mode .............................................................................................. 35 Figure 22.Control Port Timing, I²C Write ................................................................................................... 36 Figure 23.Control Port Timing, I²C Read ................................................................................................... 36 Figure 24.Recommended Analog Input Buffer .......................................................................................... 61 Figure 25.Recommended Analog Output Buffer ....................................................................................... 61 Figure 26.Recommended Layout Example ............................................................................................... 63 Figure 27.Single-Speed Mode Stopband Rejection .................................................................................. 64 Figure 28.Single-Speed Mode Transition Band ........................................................................................ 64 Figure 29.Single-Speed Mode Transition Band (Detail) ............................................................................ 64 Figure 30.Single-Speed Mode Passband Ripple ...................................................................................... 64 Figure 31.Double-Speed Mode Stopband Rejection ................................................................................. 64 Figure 32.Double-Speed Mode Transition Band ....................................................................................... 64 Figure 33.Double-Speed Mode Transition Band (Detail) .......................................................................... 65 Figure 34.Double-Speed Mode Passband Ripple ..................................................................................... 65 Figure 35.Quad-Speed Mode Stopband Rejection ................................................................................... 65 Figure 36.Quad-Speed Mode Transition Band ......................................................................................... 65 Figure 37.Quad-Speed Mode Transition Band (Detail) ............................................................................. 65 Figure 38.Quad-Speed Mode Passband Ripple ....................................................................................... 65 Figure 39.Single-Speed (fast) Stopband Rejection ................................................................................... 66 Figure 40.Single-Speed (fast) Transition Band ......................................................................................... 66 Figure 41.Single-Speed (fast) Transition Band (detail) ............................................................................. 66 Figure 42.Single-Speed (fast) Passband Ripple ....................................................................................... 66 Figure 43.Single-Speed (slow) Stopband Rejection ................................................................................. 66 Figure 44.Single-Speed (slow) Transition Band ........................................................................................ 66 Figure 45.Single-Speed (slow) Transition Band (detail) ............................................................................ 67 Figure 46.Single-Speed (slow) Passband Ripple ...................................................................................... 67 Figure 47.Double-Speed (fast) Stopband Rejection ................................................................................. 67 Figure 48.Double-Speed (fast) Transition Band ........................................................................................ 67 Figure 49.Double-Speed (fast) Transition Band (detail) ............................................................................ 67 Figure 50.Double-Speed (fast) Passband Ripple ...................................................................................... 67 Figure 51.Double-Speed (slow) Stopband Rejection ................................................................................ 68 Figure 52.Double-Speed (slow) Transition Band ...................................................................................... 68 Figure 53.Double-Speed (slow) Transition Band (detail) .......................................................................... 68 Figure 54.Double-Speed (slow) Passband Ripple .................................................................................... 68 Figure 55.Quad-Speed (fast) Stopband Rejection .................................................................................... 68 Figure 56.Quad-Speed (fast) Transition Band .......................................................................................... 68 Figure 57.Quad-Speed (fast) Transition Band (detail) .............................................................................. 69 Figure 58.Quad-Speed (fast) Passband Ripple ........................................................................................ 69 Figure 59.Quad-Speed (slow) Stopband Rejection ................................................................................... 69 Figure 60.Quad-Speed (slow) Transition Band ......................................................................................... 69 Figure 61.Quad-Speed (slow) Transition Band (detail) ............................................................................. 69 Figure 62.Quad-Speed (slow) Passband Ripple ....................................................................................... 69 4 DS605F1 CS42428 LIST OF TABLES Table 1. Common OMCK Clock Frequencies ............................................................................................ 24 Table 2. Common PLL Output Clock Frequencies..................................................................................... 24 Table 3. Slave Mode Clock Ratios ............................................................................................................. 25 Table 4. Serial Audio Port Channel Allocations ......................................................................................... 26 Table 5. DAC De-Emphasis ....................................................................................................................... 44 Table 6. Digital Interface Formats .............................................................................................................. 45 Table 7. ADC One-Line Mode.................................................................................................................... 45 Table 8. DAC One-Line Mode.................................................................................................................... 45 Table 9. RMCK Divider Settings ................................................................................................................ 48 Table 10. OMCK Frequency Settings ........................................................................................................ 48 Table 11. Master Clock Source Select....................................................................................................... 49 Table 12. PLL Clock Frequency Detection................................................................................................. 50 Table 13. Example Digital Volume Settings ............................................................................................... 53 Table 14. ATAPI Decode ........................................................................................................................... 54 Table 15. Example ADC Input Gain Settings ............................................................................................. 55 Table 16. PLL External Component Values ............................................................................................... 62 DS605F1 5 CS42428 1. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode) Parameter DC Power Supply Analog Digital Serial Port Interface Control Port Interface CS42428-CQZ CS42428-DQZ Symbol VA VD VLS VLC TA Min 4.75 3.13 1.8 1.8 -10 -40 Typ 5.0 3.3 5.0 5.0 - Max 5.25 5.25 5.25 5.25 +70 +85 Units V V V V °C °C Ambient Operating Temperature (power applied) ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameters Analog Digital Serial Port Interface Control Port Interface Input Current (Note 1) Analog Input Voltage (Note 2) Digital Input Voltage Serial Port Interface (Note 2) Control Port Interface Ambient Operating Temperature(power applied) CS42428-CQZ CS42428-DQZ Storage Temperature DC Power Supply Symbol VA VD VLS VLC Iin Min -0.3 -0.3 -0.3 -0.3 - Max 6.0 6.0 6.0 6.0 ±10 Units V V V V mA VIN VIND-S VIND-C TA TA Tstg AGND-0.7 -0.3 -0.3 -20 -50 -65 VA+0.7 VLS+ 0.4 VLC+ 0.4 +85 +95 +150 V V V °C °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 2. The maximum over/under voltage is limited by the input current. 6 DS605F1 CS42428 ANALOG INPUT CHARACTERISTICS (TA = 25° C; VA = 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Full-scale input sine wave, 997 Hz.; PDN_PLL = 1; OMCK = 12.288 MHz; Single-Speed Mode DAC_SCLK = 3.072 MHz; Double-Speed Mode DAC_SCLK = 6.144 MHz; Quad-Speed Mode DAC_SCLK = 12.288 MHz.) CS42428-CQZ Typ Max 114 111 -100 -91 -51 114 111 108 -100 -91 -51 -97 114 111 108 -100 -91 -51 -97 110 0.0001 0.1 +/-100 0 100 1.10 VA 82 -94 -94 -94 1.16 VA - Parameter (Fs=48 kHz) A-weighted unweighted Total Harmonic Distortion + Noise (Note 3) -1 dB -20 dB -60 dB Double-Speed Mode (Fs=96 kHz) Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 3) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Quad-Speed Mode (Fs=192 kHz) Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion+ Noise (Note 3) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Single-Speed Mode Dynamic Range Symbol Min 108 105 Min 106 103 106 103 106 103 - CS42428-DQZ Typ Max 114 111 -100 -91 -51 114 111 108 -100 -91 -51 -97 114 111 108 -100 -91 -51 -97 110 0.0001 0.1 +/-100 0 100 1.10 VA 82 -92 -92 -92 1.21 VA - Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Degree dB ppm/°C LSB LSB Vpp kΩ dB THD+N 108 105 108 105 1.05 VA 17 - THD+N THD+N Dynamic Performance for All Modes Interchannel Isolation Interchannel Phase Deviation DC Accuracy Interchannel Gain Mismatch Gain Drift Offset Error HPF_FREEZE disabled HPF_FREEZE enabled Analog Input Full-scale Differential Input Voltage Input Impedance (Differential) (Note 4) Common Mode Rejection Ratio 0.99 VA 17 - CMRR Notes: 3. Referred to the typical full-scale voltage. 4. Measured between AIN+ and AIN- DS605F1 7 CS42428 A/D DIGITAL FILTER CHARACTERISTICS Parameter Single-Speed Mode (2 to 50 kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency tgd ∆tgd (Note 5) (Note 5) tgd ∆tgd (Note 5) (Note 5) tgd ∆tgd (Note 5) (-0.1 dB) (Note 5) 0 0.58 -95 0 0.68 -92 0 0.78 -97 (Note 6) (Note 6) 12/Fs 9/Fs 5/Fs 1 20 10 105/Fs 0.47 ±0.035 0.0 0.45 ±0.035 0.0 0.24 ±0.035 0.0 0 Fs dB Fs dB s µs Fs dB Fs dB s µs Fs dB Fs dB s µs Hz Hz Deg dB s Symbol Min Typ Max Unit Double-Speed Mode (50 to 100 kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency (-0.1 dB) Quad-Speed Mode (100 to 192 kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency (-0.1 dB) High-Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Setting Time -3.0 dB -0.13 dB @ 20 Hz Notes: 5. The filter frequency response scales precisely with Fs. 6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. 8 DS605F1 CS42428 ANALOG OUTPUT CHARACTERISTICS (TA = 25° C; VA = 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5V; Measurement Bandwidth 10 Hz to 20 kHz unless otherwise specified.; Full-scale output 997 Hz sine wave, Test load RL = 3 kΩ, CL = 30 pF; PDN_PLL = 1; OMCK = 12.288 MHz; Single-Speed Mode, DAC_SCLK = 3.072 MHz; Double-Speed Mode, DAC_SCLK = 6.144 MHz; Quad-Speed Mode, DAC_SCLK = 12.288 MHz.) CS42428-CQZ Typ Max CS42428-DQZ Typ Max Parameter Symbol Dynamic performance for all modes Dynamic Range (Note 7) 24-bit A-Weighted unweighted 16-bit A-Weighted (Note 8) unweighted Total Harmonic Distortion + Noise 24-bit 0 dB -20 dB -60 dB 16-bit 0 dB (Note 8) -20 dB -60 dB Idle Channel Noise/Signal-to-Noise Ratio (A-Weighted) Interchannel Isolation (1 kHz) Unloaded Full-Scale Differential Output Voltage Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance Load Capacitance Min Min Unit 108 105 - 114 111 97 94 -100 -91 -51 -94 -74 -34 114 90 -94 - 106 103 - 114 111 97 94 -100 -91 -51 -94 -74 -34 114 90 -92 - dB dB dB dB dB dB dB dB dB dB dB dB THD+N Analog Output Characteristics for all modes VFS .89 VA 3 .94 VA 0.1 300 150 .99 VA 30 .84 VA 3 .94 VA 0.1 300 150 1.04 VA 30 Vpp dB ppm/°C Ω kΩ pF ZOUT RL CL Notes: 7. One-half LSB of triangular PDF dither is added to data. 8. Performance limited by 16-bit quantization noise. DS605F1 9 CS42428 D/A DIGITAL FILTER CHARACTERISTICS Fast Roll-Off Slow Roll-Off Parameter Min Typ Max Min Typ Max Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz to -0.01 dB corner 0 to -3 dB corner 0 Frequency Response 10 Hz to 20 kHz -0.01 StopBand 0.5465 StopBand Attenuation (Note 10) 90 Group Delay Passband Group Delay Deviation 0 - 20 kHz De-emphasis Error (Note 11) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz to -0.01 dB corner 0 to -3 dB corner 0 Frequency Response 10 Hz to 20 kHz -0.01 StopBand 0.5834 StopBand Attenuation (Note 10) 80 Group Delay Passband Group Delay Deviation 0 - 20 kHz to -0.01 dB corner 0 to -3 dB corner 0 Frequency Response 10 Hz to 20 kHz -0.01 StopBand 0.6355 StopBand Attenuation (Note 10) 90 Group Delay Passband Group Delay Deviation 0 - 20 kHz Passband (Note 9) Passband (Note 9) Passband (Note 9) 12/Fs 4.6/Fs 4.7/Fs 0.4535 0.4998 +0.01 ±0.41/Fs ±0.23 ±0.14 ±0.09 0.4166 0.4998 0.01 ±0.03/Fs 0.1046 0.4897 0.01 ±0.01/Fs 0 0 -0.01 0.5834 64 0 0 -0.01 0.7917 70 6.5/Fs 3.9/Fs 4.2/Fs 0.4166 0.4998 +0.01 ±0.14/Fs ±0.23 ±0.14 ±0.09 0.2083 0.4998 0.01 ±0.01/Fs 0.1042 0.4813 0.01 ±0.01/Fs Unit Fs Fs dB Fs dB s s dB dB dB Fs Fs dB Fs dB s s Fs Fs dB Fs dB s s Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz 0 0 -0.01 0.8683 75 - Notes: 9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 39 to 62) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 10. Single- and Double-Speed Mode Measurement Bandwidth is from stopband to 3 Fs. Quad-Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs. 11. De-emphasis is available only in Single-Speed Mode. 10 DS605F1 CS42428 SWITCHING CHARACTERISTICS (For CQZ, TA = -10 to +70° C; For DQZ, TA = -40 to +85° C; VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, CL = 30 pF) Parameters RST Pin Low Pulse Width PLL Clock Recovery Sample Rate Range RMCK Output Jitter RMCK Output Duty Cycle OMCK Frequency OMCK Duty Cycle DAC_SCLK, ADC_SCLK Duty Cycle DAC_LRCK, ADC_LRCK Duty Cycle (Note 14) (Note 15) (Note 13) (Note 13) (Note 12) Symbol Min 1 30 45 1.024 40 45 45 Typ 200 50 50 50 50 - Max 200 55 25.600 60 55 55 15 15 Units ms kHz ps RMS % MHz % % % ns ns Master Mode RMCK to DAC_SCLK, ADC_SCLK active edge delay RMCK to DAC_LRCK, ADC_LRCK delay tsmd tlmd 0 0 Slave Mode DAC_SCLK, ADC_SCLK Falling Edge to ADC_SDOUT, ADC_SDOUT Output Valid DAC_LRCK, ADC_LRCK Edge to MSB Valid DAC_SDIN Setup Time Before DAC_SCLK Rising Edge DAC_SDIN Hold Time After DAC_SCLK Rising Edge DAC_SCLK, ADC_SCLK High Time DAC_SCLK, ADC_SCLK Low Time DAC_SCLK, ADC_SCLK falling to DAC_LRCK, SAI_LRCK Edge tdpd tlrpd tds tdh tsckh tsckl tlrck 10 30 20 20 -25 (Note 16) 26.5 +25 ns ns ns ns ns ns ns Notes: 12. After powering-up the CS42428, RST should be held low after the power supplies and clocks are settled. 13. See Table 1 on page 24 for suggested OMCK frequencies 14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz. 15. Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 48 is set to Multiply by 2. 16. 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode. DAC_SCLK ADC_SCLK (output) DAC_LRCK ADC_LRCK (output) DAC_LRCK ADC_LRCK (input) t lrckd t lrcks t sckh t sckl DAC_SCLK ADC_SCLK (input) t smd t lmd DAC_SDINx t lrpd t ds t dh M SB t dpd MSB-1 RMCK ADC_SDOUT Figure 1. Serial Audio Port Master Mode Timing Figure 2. Serial Audio Port Slave Mode Timing DS605F1 11 CS42428 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (For CQZ, TA = -10 to +70° C; For DQZ, TA = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CL = 30 pF) Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 18) (Note 17) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 - Max 100 1 300 (Note 19) Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns Notes: 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed. 19. 15 15 15 -------------------- for Single-Speed Mode, -------------------- for Double-Speed Mode, ----------------- for Quad-Speed Mode 256 × Fs 128 × Fs 64 × Fs RST t Stop irs Sta rt R e p e ate d Sta rt t rd t fd Stop SDA t buf t hdst t high t hdst t fc t susp SCL t t t sud t ack t sust t rc lo w hdd Figure 3. Control Port Timing - I²C Format 12 DS605F1 CS42428 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT (For CQZ, TA = -10 to +70° C; For DQZ, TA = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CL = 30 pF) Parameter CCLK Clock Frequency CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 21) (Note 21) (Note 20) Symbol fsck tcsh tcss tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2 Min 0 1.0 20 66 66 40 15 - Typ - Max 6.0 50 25 25 100 100 Units MHz µs ns ns ns ns ns ns ns ns ns ns Notes: 20. Data must be held for sufficient time to bridge the transition time of CCLK. 21. For fsck