CS42438-DMZ

CS42438 108 dB, 192 kHz 6-In, 8-Out TDM CODEC FEATURES Six 24-bit A/D, Eight 24-bit D/A Converters ADC Dynamic Range – 105 dB Differential – 102 dB Single-Ended DAC Dynamic Range – 108 dB Differential – 105 dB Single-Ended ADC/DAC THD+N – -98 dB Differential – -95 dB Single-Ended Compatible with Industry-Standard Time Division Multiplexed (TDM) Serial Interface DAC Sampling Rates up to 192 kHz ADC Sampling Rates up to 96 kHz Programmable ADC High-Pass Filter for DC Offset Calibration Logarithmic Digital Volume Control Hardware Mode or Software I²C® & SPI™ Supports Logic Levels Between 5 V and 1.8 V GENERAL DESCRIPTION The CS42438 CODEC provides six multi-bit analog-todigital and eight multi-bit digital-to-analog delta-sigma converters. The CODEC is capable of operation with either differential or single-ended inputs and outputs, in a 52-pin MQFP package. Six fully differential, or single-ended, inputs are available on stereo ADC1, ADC2, and ADC3. When operating in Single-ended Mode, an internal MUX before ADC3 allows selection from up to four single-ended inputs. Digital volume control is provided for each ADC channel, with selectable overflow detection. All eight DAC channels provide digital volume control and can operate with differential or single-ended outputs. An auxiliary serial input is available for an additional two channels of PCM data. The CS42438 is available in a 52-pin MQFP package in Commercial (-10° to +70°) and Automotive (-40° to +105°) grades. The CDB42438 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 61 for complete ordering information. The CS42438 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and automotive audio systems. Control Port & Serial Audio Port Supply = 1.8 V to 5 V Digital Supply = 3.3 V Analog Supply = 3.3 V to 5 V Level Translator Hardware Mode or I2C/SPI Software Mode Control Data Register Configuration Internal Voltage Reference Reset Level Translator TDM Serial Audio Input Auxilliary Serial Audio Input Input Master Clock TDM Serial Audio Output Volume Controls TDM Serial Interface Digital Filters ∆Σ Modulators Multibit DAC1-4 and Analog Filters 8 8 Differential or Single-Ended Outputs High Pass Filter High Pass Filter Digital Filters Digital Filters Multibit Oversampling ADC1&2 Multibit Oversampling ADC3 4:2* 4 4 Differential or Single-Ended Analog Inputs 2 2 *Optional MUX allows selection from up to 4 single-ended inputs. http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) AUGUST '06 DS646F1 CS42438 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE MODE ........................................................................................... 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. PIN DESCRIPTIONS - HARDWARE MODE .......................................................................................... 9 3. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 11 4. CHARACTERISTICS AND SPECIFICATIONS..................................................................................... 13 RECOMMENDED OPERATING CONDITIONS ................................................................................... 13 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 13 ANALOG INPUT CHARACTERISTICS (COMMERCIAL) .................................................................... 14 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE) ..................................................................... 15 ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 16 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL) ................................................................ 17 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE) ................................................................. 18 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 20 SWITCHING SPECIFICATIONS - ADC/DAC PORT ............................................................................ 21 SWITCHING CHARACTERISTICS - AUX PORT ................................................................................. 22 SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE ....................................................... 23 SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT ................................................. 24 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 25 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 25 5. APPLICATIONS .................................................................................................................................... 26 5.1 Overview ......................................................................................................................................... 26 5.2 Analog Inputs .................................................................................................................................. 27 5.2.1 Line-Level Inputs ................................................................................................................... 27 5.2.1.1 Hardware Mode ......................................................................................................... 27 5.2.1.2 Software Mode ........................................................................................................... 27 5.2.2 ADC3 Analog Input ................................................................................................................ 28 5.2.3 Hardware Mode ..................................................................................................................... 29 5.2.4 Software Mode ...................................................................................................................... 29 5.2.5 High-Pass Filter and DC Offset Calibration ........................................................................... 29 5.2.5.1 Hardware Mode ......................................................................................................... 29 5.2.5.2 Software Mode ........................................................................................................... 29 5.3 Analog Outputs ............................................................................................................................... 30 5.3.1 Initialization ............................................................................................................................ 30 5.3.2 Line-Level Outputs and Filtering ............................................................................................ 30 5.3.3 Digital Volume Control ........................................................................................................... 32 5.3.3.1 Hardware Mode ......................................................................................................... 32 5.3.3.2 Software Mode ........................................................................................................... 32 5.3.4 De-Emphasis Filter ................................................................................................................ 32 5.4 System Clocking ............................................................................................................................. 33 5.4.1 Hardware Mode ..................................................................................................................... 33 5.4.2 Software Mode ...................................................................................................................... 33 5.5 CODEC Digital Interface ................................................................................................................. 33 5.5.1 TDM ................................................................................................................................ 33 5.5.2 I/O Channel Allocation ........................................................................................................... 34 5.6 AUX Port Digital Interface Formats ................................................................................................. 34 5.6.1 Hardware Mode ..................................................................................................................... 34 5.6.2 Software Mode ...................................................................................................................... 34 5.6.3 I²S .......................................................................................................................................... 34 5.6.4 Left-Justified .......................................................................................................................... 35 5.7 Control Port Description and Timing ............................................................................................... 35 5.7.1 SPI Mode ............................................................................................................................... 35 5.7.2 I²C Mode ................................................................................................................................ 36 2 DS646F1 CS42438 5.8 Recommended Power-Up Sequence ............................................................................................. 37 5.8.1 Hardware Mode ..................................................................................................................... 37 5.8.2 Software Mode ...................................................................................................................... 38 5.9 Reset and Power-Up ...................................................................................................................... 38 5.10 Power Supply, Grounding, and PCB Layout ................................................................................. 38 6. REGISTER QUICK REFERENCE ......................................................................................................... 39 7. REGISTER DESCRIPTION ................................................................................................................... 41 7.1 Memory Address Pointer (MAP) ..................................................................................................... 41 7.1.1 Increment (INCR) .................................................................................................................. 41 7.1.2 Memory Address Pointer (MAP[6:0]) ..................................................................................... 41 7.2 Chip I.D. and Revision Register (Address 01h) (Read Only) .......................................................... 41 7.2.1 Chip I.D. (CHIP_ID[3:0]) ........................................................................................................ 41 7.2.2 Chip Revision (REV_ID[3:0]) ................................................................................................. 41 7.3 Power Control (Address 02h) ......................................................................................................... 42 7.3.1 Power Down ADC Pairs (PDN_ADCX) ................................................................................. 42 7.3.2 Power Down DAC Pairs (PDN_DACX) ................................................................................. 42 7.3.3 Power Down (PDN) ............................................................................................................... 42 7.4 Functional Mode (Address 03h) ...................................................................................................... 43 7.4.1 MCLK Frequency (MFREQ[2:0]) ........................................................................................... 43 7.5 Miscellaneous Control (Address 04h) ............................................................................................. 43 7.5.1 Freeze Controls (FREEZE) ................................................................................................... 43 7.5.2 Auxiliary Digital Interface Format (AUX_DIF) ........................................................................ 43 7.6 ADC Control & DAC De-Emphasis (Address 05h) ......................................................................... 44 7.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) .................................................. 44 7.6.2 ADC3 High Pass Filter Freeze (ADC3_HPF FREEZE) ......................................................... 44 7.6.3 DAC De-Emphasis Control (DAC_DEM) ............................................................................... 44 7.6.4 ADC1 Single-Ended Mode (ADC1 SINGLE) ......................................................................... 44 7.6.5 ADC2 Single-Ended Mode (ADC2 SINGLE) ......................................................................... 45 7.6.6 ADC3 Single-Ended Mode (ADC3 SINGLE) ......................................................................... 45 7.6.7 Analog Input Ch. 5 Multiplexer (AIN5_MUX) ......................................................................... 45 7.6.8 Analog Input Ch. 6 Multiplexer (AIN6_MUX) ......................................................................... 45 7.7 Transition Control (Address 06h) .................................................................................................... 46 7.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) .................................................... 46 7.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0]) .................................. 46 7.7.3 Auto-Mute (AMUTE) .............................................................................................................. 47 7.7.4 Mute ADC Serial Port (MUTE ADC_SP) ............................................................................... 47 7.8 DAC Channel Mute (Address 07h) ................................................................................................. 47 7.8.1 Independent Channel Mute (AOUTX_MUTE) ....................................................................... 47 7.9 AOUTX Volume Control (Addresses 08h- 0Fh) .......................................................................... 47 7.9.1 Volume Control (AOUTX_VOL[7:0]) ...................................................................................... 47 7.10 DAC Channel Invert (Address 10h) .............................................................................................. 48 7.10.1 Invert Signal Polarity (INV_AOUTX) .................................................................................... 48 7.11 AINX Volume Control (Address 11h-16h) ..................................................................................... 48 7.11.1 AINX Volume Control (AINX_VOL[7:0]) .............................................................................. 48 7.12 ADC Channel Invert (Address 17h) .............................................................................................. 49 7.12.1 Invert Signal Polarity (INV_AINX) ........................................................................................ 49 7.13 Status (Address 19h) (Read Only) ................................................................................................ 49 7.13.1 CLOCK ERROR (CLK ERROR) .......................................................................................... 49 7.13.2 ADC Overflow (ADCX_OVFL) ............................................................................................. 49 7.14 Status Mask (Address 1Ah) .......................................................................................................... 49 8. EXTERNAL FILTERS............................................................................................................................ 50 8.1 ADC Input Filter .............................................................................................................................. 50 8.1.1 Passive Input Filter ................................................................................................................ 51 8.1.2 Passive Input Filter w/Attenuation ......................................................................................... 51 DS646F1 3 CS42438 8.2 DAC Output Filter ........................................................................................................................... 53 9. ADC FILTER PLOTS............................................................................................................................. 54 10. DAC FILTER PLOTS........................................................................................................................... 56 11. PARAMETER DEFINITIONS............................................................................................................... 58 12. REFERENCES..................................................................................................................................... 59 13. PACKAGE INFORMATION................................................................................................................. 60 13.1 Thermal Characteristics ............................................................................................................. 60 14. ORDERING INFORMATION ............................................................................................................... 61 15. REVISION HISTORY ........................................................................................................................... 61 LIST OF FIGURES Figure 1.Typical Connection Diagram (Software Mode) ........................................................................... 11 Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 12 Figure 3.Output Test Circuit for Maximum Load ....................................................................................... 19 Figure 4.Maximum Loading ....................................................................................................................... 19 Figure 5.TDM Serial Audio Interface Timing ............................................................................................. 21 Figure 6.Serial Audio Interface Slave Mode Timing .................................................................................. 22 Figure 7.Control Port Timing - I²C Format ................................................................................................. 23 Figure 8.Control Port Timing - SPI Format ................................................................................................ 24 Figure 9.Full-Scale Input ........................................................................................................................... 28 Figure 10.ADC3 Input Topology ................................................................................................................ 28 Figure 11.Audio Output Initialization Flow Chart ....................................................................................... 31 Figure 12.Full-Scale Output ...................................................................................................................... 32 Figure 13.De-Emphasis Curve .................................................................................................................. 33 Figure 14.TDM Serial Audio Format ......................................................................................................... 34 Figure 15.AUX I²S Format ......................................................................................................................... 34 Figure 16.AUX Left-Justified Format ......................................................................................................... 35 Figure 17.Control Port Timing in SPI Mode .............................................................................................. 36 Figure 18.Control Port Timing, I²C Write ................................................................................................... 36 Figure 19.Control Port Timing, I²C Read ................................................................................................... 37 Figure 20.Single to Differential Active Input Filter ..................................................................................... 50 Figure 21.Single-Ended Active Input Filter ................................................................................................ 50 Figure 22.Passive Input Filter ................................................................................................................... 51 Figure 23.Passive Input Filter w/Attenuation ............................................................................................. 52 Figure 24.Active Analog Output Filter ....................................................................................................... 53 Figure 25.Passive Analog Output Filter .................................................................................................... 53 Figure 26.SSM Stopband Rejection .......................................................................................................... 54 Figure 27.SSM Transition Band ................................................................................................................ 54 Figure 28.SSM Transition Band (Detail) ................................................................................................... 54 Figure 29.SSM Passband Ripple .............................................................................................................. 54 Figure 30.DSM Stopband Rejection .......................................................................................................... 54 Figure 31.DSM Transition Band ................................................................................................................ 54 Figure 32.DSM Transition Band (Detail) ................................................................................................... 55 Figure 33.DSM Passband Ripple .............................................................................................................. 55 Figure 34.SSM Stopband Rejection .......................................................................................................... 56 Figure 35.SSM Transition Band ................................................................................................................ 56 Figure 36.SSM Transition Band (detail) .................................................................................................... 56 Figure 37.SSM Passband Ripple .............................................................................................................. 56 Figure 38.DSM Stopband Rejection .......................................................................................................... 56 Figure 39.DSM Transition Band ................................................................................................................ 56 Figure 40.DSM Transition Band (detail) .................................................................................................... 57 Figure 41.DSM Passband Ripple .............................................................................................................. 57 Figure 42.QSM Stopband Rejection ......................................................................................................... 57 4 DS646F1 CS42438 Figure 43.QSM Transition Band ................................................................................................................ 57 Figure 44.QSM Transition Band (detail) .................................................................................................... 57 Figure 45.QSM Passband Ripple .............................................................................................................. 57 LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Hardware Configurable Settings ................................................................................................. 26 Table 3. AIN5 Analog Input Selection ....................................................................................................... 29 Table 4. AIN6 Analog Input Selection ....................................................................................................... 29 Table 5. MCLK Frequency Settings .......................................................................................................... 33 Table 6. Serial Audio Interface Channel Allocations ................................................................................. 34 Table 7. MCLK Frequency Settings .......................................................................................................... 43 Table 8. Example AOUT Volume Settings ................................................................................................ 48 Table 9. Example AIN Volume Settings .................................................................................................... 48 DS646F1 5 CS42438 1. PIN DESCRIPTIONS - SOFTWARE MODE AIN6+/AIN6A AIN5+/AIN5A AIN6-/AIN6B AIN5-/AIN5B AGND AIN4+ AIN3+ AIN2+ AIN2FILT+ AIN4AIN3- 52 51 50 49 48 47 46 45 44 43 42 41 40 SCL/CCLK SDA/CDOUT AD0/CS AD1/CDIN RST VLC FS VD DGND VLS SCLK MCLK ADC_SDOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DAC_SDIN AUX_SDIN DGND AUX_LRCK AUX_SCLK AOUT4+ AOUT4AOUT1+ AOUT2+ AOUT3+ AOUT1AOUT2AOUT339 38 37 36 35 AIN1+ AIN1VA VQ AGND AOUT8AOUT8+ AOUT7+ AOUT7AOUT6AOUT6+ AOUT5+ AOUT5- VA 42438 34 33 32 31 30 29 28 27 Pin Name SCL/CCLK SDA/CDOUT AD0/CS AD1/CDIN RST VLC FS VD DGND VLS SCLK MCLK ADC_SDOUT DAC_SDIN AUX_LRCK # 1 2 3 4 5 6 7 8 9,18 10 11 12 13 14 15 Pin Description Serial Control Port Clock (Input) - Serial clock for the control port interface. Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Output for SPI data. Address Bit [0]/ Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select the chip in SPI Mode. Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I²C Mode. Input for SPI data. Reset (Input) - The device enters a low-power mode and all internal registers are reset to their default settings when low. Control Port Power (Input) - Determines the required signal level for the control port interface. See “Digital I/O Pin Characteristics” on page 8. Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. Digital Power (Input) - Positive power supply for the digital section. Digital Ground (Input) Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces. See “Digital I/O Pin Characteristics” on page 8. Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs. Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters. Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data. DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data. Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line. 6 DS646F1 CS42438 AUX_SCLK AUX_SDIN AOUT1 +,AOUT2 +,AOUT3 +,AOUT4 +,AOUT5 +,AOUT6 +,AOUT7 +,AOUT8 +,AGND VQ VA AIN1 +,AIN2 +,AIN3 +,AIN4 +,AIN5 +,AIN6 +,AIN5 A,B AIN6 A,B 16 17 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. Auxiliary Serial Input (Input) - The 42438 provides an additional serial input for two’s complement serial audio data. 20,19 21,22 24,23 Differential Analog Output (Output) - The full-scale differential analog output level is specified in 25,26 the Analog Characteristics specification table. Each positive leg of the differential outputs may 28,27 also be used single-ended. 29,30 31,32 33,34 35,48 Analog Ground (Input) - Ground reference for the analog section. 36 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. 37,46 Analog Power (Input) - Positive power supply for the analog section. 39,38 41,40 43,42 45,44 50,49 52,51 Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators. The full-scale input level is specified in the Analog Characteristics specification table. Singleended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled. Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to common mode. See below for a description of AIN5-AIN6 in Single-Ended Mode. Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allows 50,49 selection between two channels for both analog inputs AIN5 and AIN6 (see Sections 7.6.6-7.6.8 52,51 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table. 47 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. FILT+ DS646F1 7 CS42438 1.1 Digital I/O Pin Characteristics Various pins on the CS42438 are powered from separate power supply rails. The logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings. Power Rail VLC Pin Name SW/(HW) RST SCL/CCLK (AIN5_MUX) SDA/CDOUT (AIN6_MUX) AD0/CS (MFREQ) AD1/CDIN (ADC3_HPF) I/O Input Input Input/ Output Input Input Input Input Input Driver 1.8 V - 5.0 V, CMOS/Open Drain - Receiver 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS, with Hysteresis 1.8 V - 5.0 V, CMOS, with Hysteresis 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS VLS MCLK LRCK SCLK 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS - ADC_SDOUT3 Input/ (ADC3_SINGLE) Output DAC_SDIN AUX_LRCK AUX_SCLK AUX_SDIN Input Output Output Input Table 1. I/O Power Rails 8 DS646F1 CS42438 2. PIN DESCRIPTIONS - HARDWARE MODE AIN6+/AIN6A AIN5+/AIN5A AIN6-/AIN6B AIN5-/AIN5B AGND AIN4+ AIN3+ AIN2+ AIN2FILT+ AIN4AIN3- 52 51 50 49 48 47 46 45 44 43 42 41 40 AIN5_MUX AIN6_MUX MFREQ ADC3_HPF RST VLC FS VD DGND VLS SCLK MCLK ADC_SDOUT/ ADC3_SINGLE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 AUX_SDIN DAC_SDIN DGND AOUT3+ AOUT1+ AOUT2+ AUX_LRCK AUX_SCLK AOUT4+ AOUT4AOUT1AOUT2AOUT339 38 37 36 35 AIN1+ AIN1VA VQ AGND AOUT8AOUT8+ AOUT7+ AOUT7AOUT6AOUT6+ AOUT5+ AOUT5- VA 42438 34 33 32 31 30 29 28 27 Pin Name AIN5_MUX AIN6_MUX MFREQ # 1 2 3 Pin Description Analog Input Multiplexer (Input) - Allows selection between the A and B single-ended inputs of ADC3. See Section 7.6.7 and 7.6.8 for details. MCLK Frequency (Input) - Sets the required frequency range of the input Master Clock. See Section 5.4 for the appropriate settings. ADC3 High-Pass Filter Freeze (Input) - When this pin is driven high, the internal high-pass filter will be disabled for ADC3. The current DC offset value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter Characteristics” on page 16. Reset (Input) - The device enters a low-power mode and all internal registers are reset to their default settings when low. Control Port Power (Input) - Determines the required signal level for the control port interface. See “Digital I/O Pin Characteristics” on page 8. Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. Digital Power (Input) - Positive power supply for the digital section. Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces. Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs. Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data. Startup Option for Hardware Mode: Pull-up to VLS enables Single-Ended Mode for AIN5-AIN6. DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line. ADC3_HPF 4 RST VLC FS VD VLS SCLK ADC_SDOUT/ ADC3_SINGLE DAC_SDIN AUX_LRCK 5 6 7 8 10 11 13 14 15 DS646F1 9 CS42438 AUX_SCLK AUX_SDIN AOUT1 +,AOUT2 +,AOUT3 +,AOUT4 +,AOUT5 +,AOUT6 +,AOUT7 +,AOUT8 +,AGND VQ VA AIN1 +,AIN2 +,AIN3 +,AIN4 +,AIN5 +,AIN6 +,AIN7 +,AIN8 +,AIN5 A,B AIN6 A,B 16 17 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. Auxiliary Serial Input (Input) - The 42438 provides an additional serial input for two’s complement serial audio data. 20,19 21,22 24,23 Differential Analog Output (Output) - The full-scale differential analog output level is specified in 25,26 the Analog Characteristics specification table. Each positive leg of the differential outputs may 28,27 also be used single-ended. 29,30 31,32 33,34 35,48 Analog Ground (Input) - Ground reference for the analog section. 36 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. 37,46 Analog Power (Input) - Positive power supply for the analog section. 39,38 41,40 43,42 45,44 50,49 52,51 52,53 Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators. The full-scale input level is specified in the Analog Characteristics specification table. Single-ended inputs may be applied to the positive terminals when the ADCx SINGLE pin is enabled. Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to common mode. See below for a description of AIN5-AIN6 in Single-Ended Mode. Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allows 50,49 selection between 2 channels for both analog inputs AIN5 and AIN6 (see Sections 7.6.6-7.6.8 for 52,51 details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table. 47 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. FILT+ 10 DS646F1 CS42438 3. TYPICAL CONNECTION DIAGRAMS +3.3 V 10 µF + 0.01 µF 0.01 µF + +3.3 V to +5 V 10 µF 0.01 µF 8 37 46 VD 10 VA VA VLS AOUT1+ AOUT1AOUT2+ AOUT220 19 21 22 24 23 25 26 28 27 29 30 32 31 33 34 0.01 µF Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 16 CS5341 A/D Converter 15 17 AUX_SCLK AUX_LRCK AUX_SDIN AOUT3+ AOUT3AOUT4+ AOUT4AOUT5+ AOUT5AOUT6+ AOUT6AOUT7+ AOUT7AOUT8+ AOUT8- Analog Output Filter 2 Analog Output Filter 2 AIN1+ AIN1AIN2+ 12 11 39 38 41 40 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Analog Input 1 AIN2MCLK SCLK FS DAC_SDIN AIN3+ AIN3AIN4+ AIN4- Analog Input 2 43 42 45 44 Analog Input 3 +1.8 V to +5.0 V 7 Digital Audio Processor 14 Analog Input 4 13 ADC_SDOUT AIN5+/AIN5A AIN5-/AIN5B AIN6+/AIN6A 50 49 52 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Analog Input 5 5 MicroController RST SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS AIN6-/AIN6B 51 Analog Input 6 1 2 4 3 Analog Input 5A Analog Input 5B Analog Input 6A Analog Input 6B ** 2 kΩ +1.8 V to +5 V ** Resistors are required for I2C control port operation ** 2 kΩ 6 VLC VQ FILT+ 37 47 Input Filter 1 0.1 µF + DGND DGND 9 18 + 100 µF 0.1 µF 4.7 µF AGND 35 AGND 48 0.1 µF Connect DGND and AGND at Codec 1. See the ADC Input Filter section in the Appendix. 2. See the DAC Output Filter section in the Appendix. Figure 1. Typical Connection Diagram (Software Mode) DS646F1 11 CS42438 +3.3 V 10 µF + 0.01 µF 0.01 µF + +3.3 V to +5 V 10 µF 0.01 µF 8 37 46 VD 10 VA VA VLS AOUT1+ AOUT1AOUT2+ AOUT220 19 21 22 24 23 25 26 28 27 29 30 32 31 33 34 0.01 µF Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 16 CS5341 A/D Converter 15 17 AUX_SCLK AUX_LRCK AUX_SDIN AOUT3+ AOUT3AOUT4+ AOUT4AOUT5+ AOUT5AOUT6+ AOUT6AOUT7+ AOUT7AOUT8+ AOUT8- Analog Output Filter 2 Analog Output Filter 2 AIN1+ AIN1AIN2+ 12 11 39 38 41 40 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Analog Input 1 AIN2MCLK SCLK FS DAC_SDIN AIN3+ AIN3AIN4+ AIN4ADC_SDOUT/ ADC3_SINGLE AIN5+/AIN5A AIN5-/AIN5B AIN6+/AIN6A Analog Input 2 43 42 45 44 Analog Input 3 +1.8 V to +5.0 V VLS 7 14 Analog Input 4 * 13 Digital Audio Processor * 50 49 52 51 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Analog Input 5 Analog Input 6 5 1 2 4 3 RST AIN5_MUX AIN6_MUX ADC3_HPF MFREQ AIN6-/AIN6B Analog Input 5A Analog Input 5B Analog Input 6A Analog Input 6B 6 VLC 0.1 µF VQ FILT+ 37 47 + * MUX configuration settings for AIN5-AIN6. See the ADC Input MUX section. + 100 µF 0.1 µF 4.7 µF DGND DGND 9 18 AGND 35 AGND 48 0.1 µF Connect DGND and AGND at Codec 1. See the ADC Input Filter section in the Appendix. 2. See the DAC Output Filter section in the Appendix. Figure 2. Typical Connection Diagram (Hardware Mode) 12 DS646F1 CS42438 4. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) Parameters DC Power Supply Analog Digital Serial Audio Interface Control Port Interface Ambient Temperature Commercial Automotive (Note 1) (Note 2) Symbol VA VD VLS VLC TA Min 3.14 3.14 1.71 1.71 -10 -40 Max 5.25 3.47 5.25 5.25 +70 +105 Units V V V V °C °C -CMZ -DMZ ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Analog Digital Serial Port Interface Control Port Interface (Note 3) (Note 4) Serial Port Interface Control Port Interface Symbol VA VD VLS VLC Iin VIN VIND-S VIND-C TA Tstg Min -0.3 -0.3 -0.3 -0.3 AGND-0.7 -0.3 -0.3 -50 -65 Max 6.0 6.0 6.0 6.0 ±10 VA+0.7 VLS+ 0.4 VLC+ 0.4 +125 +150 Units V V V V mA V V V °C °C Input Current Analog Input Voltage Digital Input Voltage (Note 4) Ambient Operating Temperature (power applied) Storage Temperature WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Typical Analog input/output performance will slightly degrade at VA = 3.3 V. 2. The ADC_SDOUT may not meet timing requirements in Double-Speed Mode. 3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 4. The maximum over/under voltage is limited by the input current. DS646F1 13 CS42438 ANALOG INPUT CHARACTERISTICS (COMMERCIAL) (Test Conditions (unless otherwise specified): TA = -10 to +70°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%; Full-scale input sine wave: 1 kHz through the active input filter in Figure 20 on page 50 and Figure 21 on page 50; Measurement Bandwidth is 10 Hz to 20 kHz.) Differential Parameter Fs=48 kHz, 96 kHz Dynamic Range Min Typ Max Min Single-Ended Typ Max Unit A-weighted 99 105 96 102 dB unweighted 96 102 93 99 dB 40 kHz bandwidth unweighted 99 96 dB dB -89 -95 -92 -98 Total Harmonic Distortion + Noise -1 dB dB -79 -82 (Note 5) -20 dB dB -39 -42 -60 dB dB -90 -90 40 kHz bandwidth -1 dB ADC1-3 Interchannel Isolation 90 90 dB ADC3 MUX Interchannel Isolation 90 90 dB DC Accuracy Interchannel Gain Mismatch 0.1 0.1 dB Gain Drift ±100 ±100 ppm/°C Analog Input Full-Scale Input Voltage 1.06*VA 1.12*VA 1.18*VA 0.53*VA 0.56*VA 0.59*VA Vpp Differential Input Impedance (Note 6) 18 kΩ Single-Ended Input Impedance (Note 7) 18 kΩ Common Mode Rejection Ratio (CMRR) 82 dB 14 DS646F1 CS42438 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE) (Test Conditions (unless otherwise specified): TA = -40 to +85°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%; Full-scale input sine wave: 1 kHz through the active input filter in Figure 20 on page 50 and Figure 21 on page 50; Measurement Bandwidth is 10 Hz to 20 kHz.) Differential Parameter Fs=48 kHz, 96 kHz Dynamic Range Min Typ Max Min Single-Ended Typ Max Unit A-weighted 97 105 94 102 dB unweighted 94 102 91 99 dB 40 kHz bandwidth unweighted 99 96 dB dB -87 -95 -90 -98 Total Harmonic Distortion + Noise -1 dB dB -79 -82 (Note 5) -20 dB dB -39 -42 -60 dB dB -87 -87 40 kHz bandwidth -1 dB ADC1-3 Interchannel Isolation 90 90 dB ADC3 MUX Interchannel Isolation 85 85 dB DC Accuracy Interchannel Gain Mismatch 0.1 0.1 dB Gain Drift ±100 ±100 ppm/°C Analog Input Full-Scale Input Voltage 1.04*VA 1.12*VA 1.20*VA 0.52*VA 0.56*VA 0.60*VA Vpp Differential Input Impedance (Note 6) 18 kΩ Single-Ended Input Impedance (Note 7) 18 kΩ Common Mode Rejection Ratio (CMRR) 82 dB Notes: 5. Referred to the typical full-scale voltage. 6. Measured between AINx+ and AINx-. 7. Measured between AINxx and AGND. DS646F1 15 CS42438 ADC DIGITAL FILTER CHARACTERISTICS Parameter (Notes 8, 9) Single-Speed Mode (Note 9) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay Double-Speed Mode (Note 9) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay High-Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time Notes: 8. Filter response is guaranteed by design. 9. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 26 to 33) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. -3.0 dB -0.13 dB @ 20 Hz 1 20 10 10 /Fs 5 Min to -0.1 dB corner 0 0.5688 70 to -0.1 dB corner 0 0.5604 69 - Typ 12/Fs 9/Fs Max 0.4896 0.08 0.4896 0.16 0 0 Unit Fs dB Fs dB s Fs dB Fs dB s Hz Hz Deg dB s 16 DS646F1 CS42438 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL) (Test Conditions (unless otherwise specified): TA = -10 to +70°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%; Full-scale 997 Hz output sine wave (see Note 11) into passive filter in Figure 26 on page 54 and active filter in Figure 26 on page 54; Measurement Bandwidth is 10 Hz to 20 kHz.) Differential Typ Single-Ended Typ Max Parameter Min Fs = 48 kHz, 96 kHz, 192 kHz Dynamic Range 102 18 to 24-Bit A-weighted 99 unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) Analog Output Full-Scale Output 1.235•VA Interchannel Gain Mismatch Gain Drift Output Impedance DC Current draw from an AOUT pin (Note 10) AC-Load Resistance (RL) (Note 12) 3 Load Capacitance (CL) (Note 12) - Max Min Unit 108 105 99 96 -98 -85 -45 -93 -76 -36 100 -92 - 99 96 - 105 102 96 93 -95 -82 -42 -90 -73 -33 100 -89 - dB dB dB dB dB dB dB dB dB dB dB 1.300•VA 1.365•VA 0.618•VA 0.650•VA 0.683•VA Vpp 0.1 0.25 0.1 0.25 dB ±100 ±100 ppm/°C 100 100 Ω 10 10 µA 100 3 100 kΩ pF DS646F1 17 CS42438 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE) (Test Conditions (unless otherwise specified): TA = -40 to +85°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%; Full-scale 997 Hz output sine wave (see Note 11) in Figure 26 on page 54 and Figure 26 on page 54; Measurement Bandwidth is 10 Hz to 20 kHz.) Differential Typ Single-Ended Typ Max Parameter Min Fs = 48 kHz, 96 kHz, 192 kHz Dynamic Range 100 18 to 24-Bit A-weighted 97 unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) Analog Output Full-Scale Output 1.210•VA Interchannel Gain Mismatch Gain Drift Output Impedance DC Current draw from an AOUT pin (Note 10) AC-Load Resistance (RL) (Note 12) 3 Load Capacitance (CL) Notes: (Note 12) - Max Min Unit 108 105 99 96 -98 -85 -45 -93 -76 -36 100 -90 - 97 94 - 105 102 96 93 -95 -82 -42 -90 -73 -33 100 -87 - dB dB dB dB dB dB dB dB dB dB dB 1.300•VA 1.392•VA 0.605•VA 0.650•VA 0.696•VA Vpp 0.1 0.25 0.1 0.25 dB ±100 ±100 ppm/°C 100 100 Ω 10 10 µA 100 3 100 kΩ pF 10. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC-blocking capacitors. 11. One-half LSB of triangular PDF dither is added to data. 12. Guaranteed by design. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively move the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. See “External Filters” on page 50 for a recommended output filter. 18 DS646F1 CS42438 125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region DAC1-4 AOUTxx 3.3 µF + Analog Output RL CL AGND 2.5 3 5 10 15 20 Resistive Load -- RL (kΩ ) Figure 3. Output Test Circuit for Maximum Load Figure 4. Maximum Loading DS646F1 19 CS42438 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter (Notes 8, 13) Single-Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 15) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz (Note 14) to -0.05 dB corner to -3 dB corner 0 0 -0.2 0.5465 50 10/Fs 0.4780 0.4996 +0.08 Fs Fs dB Fs dB s Min Typ Max Unit +1.5/+0 dB +0.05/-0.25 dB -0.2/-0.4 dB Double-Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Quad-Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Notes: 13. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 34 to 45) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 14. Single- and Double-Speed Mode Measurement Bandwidth is from Stopband to 3 Fs. Quad-Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs. 15. De-emphasis is only available in Single-Speed Mode. (Note 14) to -0.1 dB corner to -3 dB corner 0 0 -0.2 0.7 51 2.5/Fs 0.397 0.476 +0.05 Fs Fs dB Fs dB s (Note 14) to -0.1 dB corner to -3 dB corner 0 0 -0.2 0.5770 55 5/Fs 0.4650 0.4982 +0.7 Fs Fs dB Fs dB s 20 DS646F1 CS42438 SWITCHING SPECIFICATIONS - ADC/DAC PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT CLOAD = 15 pF.) Parameters Slave Mode RST pin Low Pulse Width MCLK Frequency MCLK Duty Cycle Input Sample Rate (FS pin) (Note 16) (Note 17) Single-Speed Mode Double-Speed Mode (Note 18) Quad-Speed Mode (Note 19) 1 0.512 45 4 50 100 45 8 8 5 16 3 5 5 10 15 50 55 50 100 200 55 ms MHz % kHz kHz kHz % ns ns ns ns ns ns ns ns ns Symbol Min Max Units Fs Fs Fs tsckh tsckl tfss tfsh tds tdh tdh1 tdh2 tdval SCLK Duty Cycle SCLK High Time SCLK Low Time FS Rising Edge to SCLK Rising Edge SCLK Rising Edge to FS Falling Edge DAC_SDIN Setup Time Before SCLK Rising Edge DAC_SDIN Hold Time After SCLK Rising Edge DAC_SDIN Hold Time After SCLK Rising Edge ADC_SDOUT Hold Time After SCLK Rising Edge ADC_SDOUT Valid Before SCLK Rising Edge Notes: 16. After powering up the CS42438, RST should be held low after the power supplies and clocks are settled. 17. See Table 7 on page 43 for suggested MCLK frequencies. 18. VLS is limited to nominal 2.5 V to 5.0 V operation only. 19. ADC does not meet timing specification for Quad-Speed Mode. FS (input) tfss SCLK (input) tfsh tsckh tsckl tds DAC_SDIN tdh1 MSB MSB-1 tdh2 ADC_SDOUT MSB tdval MSB-1 Figure 5. TDM Serial Audio Interface Timing DS646F1 21 CS42438 SWITCHING CHARACTERISTICS - AUX PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS.) Parameters Master Mode Output Sample Rate (AUX_LRCK) AUX_SCLK Frequency AUX_SCLK Duty Cycle AUX_LRCK Edge to SCLK Rising Edge AUX_SDIN Setup Time Before SCLK Rising Edge AUX_SDIN Hold Time After SCLK Rising Edge tlcks tds tdh All Speed Modes Fs 45 3 5 LRCK 64·LRCK 55 5 kHz kHz % ns ns ns Symbol Min Max Units AUX_LRCK tlcks tsckh tsckl AUX_SCLK tds AUX_SDIN tdh MSB MSB-1 Figure 6. Serial Audio Interface Slave Mode Timing 22 DS646F1 CS42438 SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE (VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF) Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling Notes: 20. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 21. Guaranteed by design. (Note 21) (Note 21) (Note 20) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 1000 Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns RST t Stop irs Start R e p e a te d Sta rt t rd t fd Stop SDA t buf t hdst t high t hdst t fc t susp SCL t t t sud t ack t sust t rc lo w hdd Figure 7. Control Port Timing - I²C Format DS646F1 23 CS42438 SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT (VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL = 30 pF) Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN Notes: 22. Data must be held for sufficient time to bridge the transition time of CCLK. 23. For fsck