DRAFTv1
5/13/08
CS42L52
Low-power, Stereo CODEC w/ Headphone & Speaker Amps
Stereo CODEC
Class D Stereo/Mono Speaker Amplifier
High Performance Stereo ADC & DAC
– 99 dB (ADC), 98 dB (DAC) Dyn. Range (A-wtd)
– -88 dB THD+N
No External Filter Required
High-power Stereo Output at 10% THD+N
– 2 x 1.00 W into 8 Ω @ 5.0 V
– 2 x 550 mW into 8 Ω @ 3.7 V
– 2 x 230 mW into 8 Ω @ 2.5 V
Flexible Stereo Analog Input Architecture
– 4:1 Analog Input MUX
– Analog Input Mixing
– Analog Passthrough with Volume Control
– Analog Programmable Gain Amplifier (PGA)
High-power Mono Output at 10% THD+N
– 1 x 1.90 W into 4 Ω @ 5.0 V
– 1 x 1.00 W into 4 Ω @ 3.7 V
– 1 x 350 mW into 4 Ω @ 2.5 V
Programmable Automatic Level Control (ALC)
– Noise Gate for Noise Suppression
– Programmable Threshold & Attack/Release
Rates
Direct Battery-powered Operation
– Battery Level Monitoring & Compensation
81% Efficiency at 800 mW
Phase-aligned PWM Output Reduces Idle
Dual MIC Inputs
– Differential or Single-ended
– +16 dB to +32 dB w/ 1dB step MIC PreAmplifiers
– Programmable, Low-noise MIC Bias Levels
Channel Current
Spread Spectrum Modulation
Low Quiescent Current
Stereo Headphone Amplifier
Digital Signal Processing Engine
– Bass & Treble Tone Control, De-emphasis
–
Ground-centered Outputs
– No DC-Blocking Capacitors Required
– Integrated Negative Voltage Regulator
–
–
Master Vol. and Independent PCM SDIN + ADC
SDOUT Mix Volume Control
Soft-ramp & Zero-Cross Transitions
Programmable Peak-detect and Limiter
High-power Output at -75 dB THD+N
– 2 x 23 mW Into 16 Ω @ 1.8 V
– 2 x 44 mW Into 16 Ω @ 2.5 V
–
Beep Generator w/Full Tone Control
(Features continued on page 2)
+1.65 V to +2.63 V
Analog Supply
+1.65 V to +2.63 V
Digital Supply
Summing
Programmable
Gain Amps
Battery Level Monitoring & Compensation
+
-
Σ
Left
Inputs
1
2
3
4
Right
Inputs
1
2
3
4
+1.60 V to +5.25 V
Battery
Pulse-Width
Modulator
(PWM)
ALC
+
-
Beep
Stereo/Mono
Full-Bridge
Speaker
Outputs
Class D Amps
Multi-bit
∆Σ ADC
Volume, Mono
Swap, Mix
Left HP/Line
Output
Mono mix,
Limiter, Bass,
Treble Adjust
Multi-bit
∆Σ DAC
Σ
ALC
+16 to +32 dB Diff./
S.E. MIC Pre-Amps
MIC Bias
Selectable
Bias Voltage
http://www.cirrus.com
Ground-Centered
Amps
Right HP/Line
Output
HPF
Control Port
Serial Audio Port
Level Shifter
+1.65 V to +3.47 V 2
I C Control
Interface Supply
Reset
-VHP
+VHP
Charge Pump
Serial Audio
Input/Output
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
Speaker/HP
Switch
+1.65 V to +2.63 V
Headphone Supply
+1.65 V to +2.63 V
Analog Supply
MAY '08
DS680F1
5/13/08
CS42L52
System Features
General Description
12, 24, and 27 MHz Master Clock Support in
The CS42L52 is a highly integrated, low-power stereo CODEC with headphone and Class D speaker amplifiers. The
CS42L52 offers many features suitable for low-power, portable system applications.
Addition to Typical Audio Clock Rates
High-performance 24-bit Converters
–
–
Multi-bit Delta-Sigma Architecture
Very Low 64Fs Oversampling Clock Reduces
Power Consumption
Low-power Operation
– Stereo Analog Passthrough: 10 mW @ 1.8 V
– Stereo Playback: 14 mW @ 1.8 V
– Stereo Rec. and Playback: 23 mW @ 1.8 V
Variable Power Supplies
– 1.8 V to 2.5 V Digital & Analog
– 1.6 V to 5 V Class D Amplifier
– 1.8 V to 2.5 V Headphone Amplifier
– 1.8 V to 3.3 V Interface Logic
Power-down Management
– ADC, DAC, CODEC, MIC Pre-Amplifier, PGA,
Headphone Amplifier, Speaker Amplifier
Analog & Digital Routing/Mixes:
– Line/Headphone Out = Analog In (ADC
Bypassed)
– Line/Headphone/Speaker
Out = ADC + Digital In
– Digital Out = ADC + Digital In
– Internal Digital Loopback
– Mono Mixes
Flexible Clocking Options
– Master or Slave Operation
– High-impedance Digital Output Option (for easy
MUXing between CODEC & other data
sources)
– Quarter-speed Mode - (i.e. allows 8 kHz Fs
while maintaining a flat noise floor up to 16 kHz)
– 4 kHz to 96 kHz Sample Rates
I²C® Control Port Operation
Headphone/Speaker Detection Input
Pop and Click Suppression
Applications
Digital Voice Recorders, Digital Cameras, &
Camcorders
PDA’s
Personal Media Players
Portable Game Consoles
2
The ADC input path allows independent channel control of a
number of features. Input summing amplifiers mix and select
line-level and/or microphone-level inputs for each channel.
The microphone input path includes a selectable programmable-gain pre-amplifier stage and a low-noise MIC bias voltage
supply. A PGA is available for line or microphone inputs and
provides analog gain with soft-ramp and zero-cross transitions. The ADC also features a digital volume control with soft
ramp transitions. A programmable ALC and Noise Gate monitor the input signals and adjust the volume levels
appropriately. To conserve power, the ADC may be bypassed
while still allowing full analog volume control.
The DAC output path includes a digital signal processing engine with various fixed-function controls. Tone Control
provides bass and treble adjustment of four selectable corner
frequencies. The Digital Mixer provides independent volume
control for both the ADC output and PCM input signal paths,
as well as a master volume control. Digital Volume controls
may be configured to change on soft-ramp transitions while
the analog controls can be configured to occur on every zero
crossing. The DAC also includes de-emphasis, limiting functions and a BEEP generator, delivering tones selectable
across a range of two full octaves.
The stereo headphone amplifier is powered from a separate
positive supply and the integrated charge pump provides a
negative supply. This allows a ground-centered, analog output
with a wide signal swing and eliminates external DC-blocking
capacitors.
The Class D stereo speaker amplifier does not require an
external filter and provides the high-efficiency amplification required by power-sensitive portable applications. The speaker
amplifier may be powered directly from a battery while the internal DC supply monitoring and compensation provides a
constant gain level as the battery’s voltage decays.
In addition to its many features, the CS42L52 operates from a
low-voltage analog and digital core making it ideal for portable
systems that require extremely low power consumption in a
minimal amount of space.
The CS42L52 is available in a 40-pin QFN package in both
Commercial (-40 to +85 °C) and Automotive (-40 to +105 °C)
grades. The CS42L52 Customer Demonstration board is also
available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 81 for
complete ordering information.
DS680F1
5/13/08
CS42L52
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 8
1.1 I/O Pin Characteristics ...................................................................................................................... 9
2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 10
3. CHARACTERISTIC AND SPECIFICATIONS ...................................................................................... 11
RECOMMENDED OPERATING CONDITIONS ................................................................................... 11
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 11
ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ) .......................................................... 12
ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) .......................................................... 13
ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 14
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ...................................................... 15
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ...................................................... 16
ANALOG PASSTHROUGH CHARACTERISTICS ............................................................................... 17
PWM OUTPUT CHARACTERISTICS .................................................................................................. 17
HEADPHONE OUTPUT POWER CHARACTERISTICS ...................................................................... 19
LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS ..................................................................... 20
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 20
SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 21
SWITCHING SPECIFICATIONS - I²C CONTROL PORT ..................................................................... 22
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 23
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 23
POWER CONSUMPTION .................................................................................................................... 24
4. APPLICATIONS ................................................................................................................................... 25
4.1 Overview ......................................................................................................................................... 25
4.1.1 Basic Architecture ................................................................................................................. 25
4.1.2 Line & MIC Inputs .................................................................................................................. 25
4.1.3 Line & Headphone Outputs ................................................................................................... 25
4.1.4 Speaker Driver Outputs ......................................................................................................... 25
4.1.5 Fixed Function DSP Engine .................................................................................................. 25
4.1.6 Beep Generator ..................................................................................................................... 25
4.1.7 Power Management .............................................................................................................. 25
4.2 Analog Inputs ................................................................................................................................. 26
4.2.1 MIC Inputs ............................................................................................................................. 27
4.2.2 Automatic Level Control (ALC) .............................................................................................. 27
4.2.3 Noise Gate ............................................................................................................................ 28
4.3 Analog Outputs .............................................................................................................................. 29
4.3.1 Beep Generator ..................................................................................................................... 30
4.3.2 Limiter .................................................................................................................................... 31
4.4 Analog In to Analog Out Passthrough ............................................................................................ 32
4.4.1 Overriding the ADC Power Down .......................................................................................... 32
4.4.2 Overriding the PGA Power Down .......................................................................................... 33
4.5 PWM Outputs ................................................................................................................................. 33
4.5.1 Mono Speaker Output Configuration ..................................................................................... 33
4.5.2 VP Battery Compensation ..................................................................................................... 33
4.5.2.1 Maintaining a Desired Output Level ........................................................................... 34
4.6 Serial Port Clocking ........................................................................................................................ 34
4.7 Digital Interface Formats ................................................................................................................ 36
4.7.1 DSP Mode ............................................................................................................................. 36
4.8 Initialization ..................................................................................................................................... 37
4.9 Recommended Power-up Sequence .............................................................................................. 37
4.10 Recommended Power-down Sequence ....................................................................................... 37
4.11 Required Initialization Settings ..................................................................................................... 37
4.12 Control Port Operation .................................................................................................................. 38
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CS42L52
4.12.1 I²C Control ........................................................................................................................... 38
4.12.2 Memory Address Pointer (MAP) .......................................................................................... 39
4.12.2.1 Map Increment (INCR) ............................................................................................. 39
5. REGISTER QUICK REFERENCE ........................................................................................................ 40
6. REGISTER DESCRIPTION .................................................................................................................. 42
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 42
6.1.1 Chip I.D. (Read Only) ............................................................................................................ 42
6.1.2 Chip Revision (Read Only) .................................................................................................... 42
6.2 Power Control 1 (Address 02h) ...................................................................................................... 42
6.2.1 Power Down ADC Charge Pump .......................................................................................... 42
6.2.2 Power Down PGAx ................................................................................................................ 42
6.2.3 Power Down ADCx ................................................................................................................ 43
6.2.4 Power Down .......................................................................................................................... 43
6.3 Power Control 2 (Address 03h) ...................................................................................................... 43
6.3.1 Power Down ADC Override ................................................................................................... 43
6.3.2 Power Down MICx ................................................................................................................. 43
6.3.3 Power Down MIC Bias .......................................................................................................... 43
6.4 Power Control 3 (Address 04h) ...................................................................................................... 44
6.4.1 Headphone Power Control .................................................................................................... 44
6.4.2 Speaker Power Control ......................................................................................................... 44
6.5 Clocking Control (Address 05h) ...................................................................................................... 44
6.5.1 Auto-Detect ........................................................................................................................... 44
6.5.2 Speed Mode .......................................................................................................................... 45
6.5.3 32kHz Sample Rate Group ................................................................................................... 45
6.5.4 27 MHz Video Clock .............................................................................................................. 45
6.5.5 Internal MCLK/LRCK Ratio ................................................................................................... 45
6.5.6 MCLK Divide By 2 ................................................................................................................. 46
6.6 Interface Control 1 (Address 06h) .................................................................................................. 46
6.6.1 Master/Slave Mode ............................................................................................................... 46
6.6.2 SCLK Polarity ........................................................................................................................ 46
6.6.3 ADC Interface Format ........................................................................................................... 46
6.6.4 DSP Mode ............................................................................................................................. 46
6.6.5 DAC Interface Format ........................................................................................................... 47
6.6.6 Audio Word Length ................................................................................................................ 47
6.7 Interface Control 2 (Address 07h) .................................................................................................. 47
6.7.1 SCLK equals MCLK .............................................................................................................. 47
6.7.2 SDOUT to SDIN Digital Loopback ......................................................................................... 47
6.7.3 Tri-State Serial Port Interface ................................................................................................ 48
6.7.4 Speaker/Headphone Switch Invert ........................................................................................ 48
6.7.5 MIC Bias Level ...................................................................................................................... 48
6.8 Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h) ....................... 48
6.8.1 ADC Input Select ................................................................................................................... 48
6.8.2 PGA Input Mapping ............................................................................................................... 49
6.9 Analog & HPF Control (Address 0Ah) ............................................................................................ 49
6.9.1 ADCx High-Pass Filter .......................................................................................................... 49
6.9.2 ADCx High-Pass Filter Freeze .............................................................................................. 49
6.9.3 Ch. x Analog Soft Ramp ........................................................................................................ 49
6.9.4 Ch. x Analog Zero Cross ....................................................................................................... 49
6.10 ADC HPF Corner Frequency (Address 0Bh) ................................................................................ 50
6.10.1 HPF x Corner Frequency .................................................................................................... 50
6.11 Misc. ADC Control (Address 0Ch) ................................................................................................ 50
6.11.1 Analog Front-End Volume Setting B=A ............................................................................... 50
6.11.2 Digital MUX ......................................................................................................................... 50
6.11.3 Digital Sum .......................................................................................................................... 50
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CS42L52
6.11.4 Invert ADC Signal Polarity ................................................................................................... 51
6.11.5 ADC Mute ............................................................................................................................ 51
6.12 Playback Control 1 (Address 0Dh) ............................................................................................... 51
6.12.1 Headphone Analog Gain ..................................................................................................... 51
6.12.2 Playback Volume Setting B=A ............................................................................................ 51
6.12.3 Invert PCM Signal Polarity .................................................................................................. 52
6.12.4 Master Playback Mute ......................................................................................................... 52
6.13 Miscellaneous Controls (Address 0Eh) ........................................................................................ 52
6.13.1 Passthrough Analog ............................................................................................................ 52
6.13.2 Passthrough Mute ............................................................................................................... 52
6.13.3 Freeze Registers ................................................................................................................. 52
6.13.4 HP/Speaker De-emphasis ................................................................................................... 53
6.13.5 Digital Soft Ramp ................................................................................................................ 53
6.13.6 Digital Zero Cross ................................................................................................................ 53
6.14 Playback Control 2 (Address 0Fh) ................................................................................................ 54
6.14.1 Headphone Mute ................................................................................................................. 54
6.14.2 Speaker Mute ...................................................................................................................... 54
6.14.3 Speaker Volume Setting B=A .............................................................................................. 54
6.14.4 Speaker Channel Swap ....................................................................................................... 54
6.14.5 Speaker MONO Control ...................................................................................................... 54
6.14.6 Speaker Mute 50/50 Control ............................................................................................... 54
6.15 MICx Amp Control:MIC A (Address 10h) & MIC B (Address 11h) ................................................ 55
6.15.1 MIC x Select ........................................................................................................................ 55
6.15.2 MICx Configuration .............................................................................................................. 55
6.15.3 MICx Gain ........................................................................................................................... 55
6.16 PGAx Vol. & ALCx Transition Ctl.:
ALC, PGA A (Address 12h) & ALC, PGA B (Address 13h) .................................................................. 55
6.16.1 ALCx Soft Ramp Disable ..................................................................................................... 55
6.16.2 ALCx Zero Cross Disable .................................................................................................... 56
6.16.3 PGAx Volume ...................................................................................................................... 56
6.17 Passthrough x Volume: PASSAVOL (Address 14h) & PASSBVOL (Address 15h) .................... 57
6.17.1 Passthrough x Volume ........................................................................................................ 57
6.18 ADCx Volume Control: ADCAVOL (Address 16h) & ADCBVOL (Address 17h) .......................... 57
6.18.1 ADCx Volume ...................................................................................................................... 57
6.19 ADCx Mixer Volume: ADCA (Address 18h) & ADCB (Address 19h) ............................................ 58
6.19.1 ADC Mixer Channel x Mute ................................................................................................. 58
6.19.2 ADC Mixer Channel x Volume ............................................................................................. 58
6.20 PCMx Mixer Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh) .......................................... 58
6.20.1 PCM Mixer Channel x Mute ................................................................................................ 58
6.20.2 PCM Mixer Channel x Volume ............................................................................................ 58
6.21 Beep Frequency & On Time (Address 1Ch) ................................................................................. 59
6.21.1 Beep Frequency .................................................................................................................. 59
6.21.2 Beep On Time ..................................................................................................................... 60
6.22 Beep Volume & Off Time (Address 1Dh) ...................................................................................... 60
6.22.1 Beep Off Time ..................................................................................................................... 60
6.22.2 Beep Volume ....................................................................................................................... 61
6.23 Beep & Tone Configuration (Address 1Eh) .................................................................................. 61
6.23.1 Beep Configuration .............................................................................................................. 61
6.23.2 Beep Mix Disable ................................................................................................................ 61
6.23.3 Treble Corner Frequency .................................................................................................... 62
6.23.4 Bass Corner Frequency ...................................................................................................... 62
6.23.5 Tone Control Enable ........................................................................................................... 62
6.24 Tone Control (Address 1Fh) ......................................................................................................... 62
6.24.1 Treble Gain .......................................................................................................................... 62
DS680F1
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CS42L52
6.24.2 Bass Gain ............................................................................................................................ 63
6.25 Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h) ....................................... 63
6.25.1 Master Volume Control ........................................................................................................ 63
6.26 Headphone Volume Control: HPA (Address 22h) & HPB (Address 23h) ..................................... 63
6.26.1 Headphone Volume Control ................................................................................................ 63
6.27 Speaker Volume Control: SPKA (Address 24h) & SPKB (Address 25h) ...................................... 64
6.27.1 Speaker Volume Control ..................................................................................................... 64
6.28 ADC & PCM Channel Mixer (Address 26h) .................................................................................. 64
6.28.1 PCM Mix Channel Swap ..................................................................................................... 64
6.28.2 ADC Mix Channel Swap ...................................................................................................... 64
6.29 Limiter Control 1, Min/Max Thresholds (Address 27h) ................................................................. 65
6.29.1 Limiter Maximum Threshold ................................................................................................ 65
6.29.2 Limiter Cushion Threshold .................................................................................................. 65
6.29.3 Limiter Soft Ramp Disable ................................................................................................... 65
6.29.4 Limiter Zero Cross Disable .................................................................................................. 66
6.30 Limiter Control 2, Release Rate (Address 28h) ............................................................................ 66
6.30.1 Peak Detect and Limiter ...................................................................................................... 66
6.30.2 Peak Signal Limit All Channels ........................................................................................... 66
6.30.3 Limiter Release Rate ........................................................................................................... 66
6.31 Limiter Attack Rate (Address 29h) ................................................................................................ 67
6.31.1 Limiter Attack Rate .............................................................................................................. 67
6.32 ALC Enable & Attack Rate (Address 2Ah) ................................................................................... 67
6.32.1 ALCx Enable ....................................................................................................................... 67
6.32.2 ALC Attack Rate .................................................................................................................. 67
6.33 ALC Release Rate (Address 2Bh) ................................................................................................ 68
6.33.1 ALC Release Rate ............................................................................................................... 68
6.34 ALC Threshold (Address 2Ch) ..................................................................................................... 68
6.34.1 ALC Maximum Threshold .................................................................................................... 68
6.34.2 ALC Minimum Threshold ..................................................................................................... 69
6.35 Noise Gate Control (Address 2Dh) ............................................................................................... 69
6.35.1 Noise Gate All Channels ..................................................................................................... 69
6.35.2 Noise Gate Enable .............................................................................................................. 69
6.35.3 Noise Gate Threshold and Boost ........................................................................................ 70
6.35.4 Noise Gate Delay Timing .................................................................................................... 70
6.36 Status (Address 2Eh) (Read Only) ............................................................................................... 70
6.36.1 Serial Port Clock Error (Read Only) .................................................................................... 70
6.36.2 DSP Engine Overflow (Read Only) ..................................................................................... 71
6.36.3 PCMx Overflow (Read Only) ............................................................................................... 71
6.36.4 ADCx Overflow (Read Only) ............................................................................................... 71
6.37 Battery Compensation (Address 2Fh) .......................................................................................... 71
6.37.1 Battery Compensation ......................................................................................................... 71
6.37.2 VP Monitor ........................................................................................................................... 71
6.37.3 VP Reference ...................................................................................................................... 72
6.38 VP Battery Level (Address 30h) (Read Only) ............................................................................... 72
6.38.1 VP Voltage Level (Read Only) ............................................................................................ 72
6.39 Speaker Status (Address 31h) (Read Only) ................................................................................. 72
6.39.1 Speaker Current Load Status (Read Only) ......................................................................... 72
6.39.2 SPKR/HP Pin Status (Read Only) ....................................................................................... 73
6.40 Charge Pump Frequency (Address 34h) ...................................................................................... 73
6.40.1 Charge Pump Frequency .................................................................................................... 73
7. ANALOG PERFORMANCE PLOTS .................................................................................................... 74
7.1 Headphone THD+N versus Output Power Plots ............................................................................ 74
8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 76
8.1 Auto Detect Enabled ....................................................................................................................... 76
6
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CS42L52
8.2 Auto Detect Disabled ...................................................................................................................... 76
9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 77
9.1 Power Supply, Grounding ............................................................................................................... 77
9.2 QFN Thermal Pad .......................................................................................................................... 77
10. ADC & DAC DIGITAL FILTERS ........................................................................................................ 78
11. PARAMETER DEFINITIONS .............................................................................................................. 79
12. PACKAGE DIMENSIONS .................................................................................................................. 80
THERMAL CHARACTERISTICS .......................................................................................................... 80
13. ORDERING INFORMATION .............................................................................................................. 81
14. REFERENCES .................................................................................................................................... 81
15. REVISION HISTORY .......................................................................................................................... 81
LIST OF FIGURES
Figure 1. Typical Connection Diagram ...................................................................................................... 10
Figure 2. Headphone Output Test Load .................................................................................................... 19
Figure 3. Serial Audio Interface Timing ..................................................................................................... 21
Figure 4. Control Port Timing - I²C ............................................................................................................ 22
Figure 5. Analog Input Signal Flow ........................................................................................................... 26
Figure 6. Single-Ended MIC Configuration ............................................................................................... 27
Figure 7. Differential MIC Configuration .................................................................................................... 27
Figure 8. ALC ............................................................................................................................................ 28
Figure 9. Noise Gate Attenuation .............................................................................................................. 28
Figure 10. DSP Engine Signal Flow .......................................................................................................... 29
Figure 11. PWM Output Stage .................................................................................................................. 30
Figure 12. Analog Output Stage ................................................................................................................ 30
Figure 13. Beep Configuration Options ..................................................................................................... 31
Figure 14. Peak Detect & Limiter .............................................................................................................. 32
Figure 15. Battery Compensation ............................................................................................................. 34
Figure 16. I²S Format ................................................................................................................................ 36
Figure 17. Left-Justified Format ................................................................................................................ 36
Figure 18. Right-Justified Format (DAC only) ........................................................................................... 36
Figure 19. DSP Mode Format) .................................................................................................................. 36
Figure 20. Control Port Timing, I²C Write .................................................................................................. 38
Figure 21. Control Port Timing, I²C Read .................................................................................................. 38
Figure 22. THD+N vs. Output Power per Channel at 1.8 V (16 Ω load) ................................................... 74
Figure 23. THD+N vs. Output Power per Channel at 2.5 V (16 Ω load) ................................................... 74
Figure 24. THD+N vs. Output Power per Channel at 1.8 V (32 Ω load) ................................................... 75
Figure 25. THD+N vs. Output Power per Channel at 2.5 V (32 Ω load) ................................................... 75
Figure 26. ADC Passband Ripple ............................................................................................................. 78
Figure 27. ADC Stopband Rejection ......................................................................................................... 78
Figure 28. ADC Transition Band ............................................................................................................... 78
Figure 29. ADC Transition Band (Detail) ................................................................................................... 78
Figure 30. DAC Passband Ripple ............................................................................................................. 78
Figure 31. DAC Stopband ......................................................................................................................... 78
Figure 32. DAC Transition Band ............................................................................................................... 78
Figure 33. DAC Transition Band (Detail) ................................................................................................... 78
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CS42L52
SDOUT
DGND
VD
VL
RESET
SPKR/HP
36
35
34
33
32
31
MCLK
37
SDIN
SCLK
39
38
LRCK
SDA
1
30
AIN1B
SCL
2
29
AIN1A
AD0
3
28
AFILTB
SPKR_OUTA+
4
27
AFILTA
VP
5
26
AIN2B
SPKR_OUTA-
6
25
AIN2A
SPKR_OUTB+
7
24
AIN3B/MIC2-/MIC1B
VP
8
23
AIN3A/MIC1-/MIC1A
SPKR_OUTB-
9
22
AIN4B/MIC2+/MIC2B
-VHPFILT
10
21
AIN4A/MIC1+/MIC2A
Pin Name
SDA
SCL
AD0
SPKR_OUTA+
SPKR_OUTASPKR_OUTB+
SPKR_OUTBVP
-VHPFILT
FLYN
FLYP
+VHP
HP/LINE_OUTB, A
VA
8
40
1. PIN DESCRIPTIONS
#
1
2
3
4
6
7
9
5
8
GND/Thermal Pad
11
12
13
14
15
16
17
18
19
20
FLYN
FLYP
+VHP
HP/LINE_OUTB
HP/LINE_OUTA
VA
AGND
FILT+
VQ
MICBIAS
Top-Down (Through-Package) View
40-Pin QFN Package
Pin Description
Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode.
Serial Control Port Clock (Input) - Serial clock for the serial control port.
Address Bit 0 (Input) - Chip address bit 0.
PWM Speaker Output (Output) - Full-bridge amplified PWM speaker outputs.
Power for PWM Drivers (Input) - Power supply for the PWM output driver stages.
Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge
pump that provides the negative rail for the headphone/line amplifiers.
Charge Pump Cap Negative Node (Output) - Negative node for the inverting charge pump’s fly11
ing capacitor.
Charge Pump Cap Positive Node (Output) - Positive node for the inverting charge pump’s flying
12
capacitor.
Positive Analog Power for Headphone (Input) - Positive voltage rail and power for the internal
13
headphone amplifiers and inverting charge pump.
14,15 Headphone/Line Audio Output (Output) - Stereo headphone or line level analog outputs.
16 Analog Power (Input) - Positive power for the internal analog section.
10
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CS42L52
AGND
17
FILT+
18
VQ
19
MICBIAS
20
AIN4A,B
AIN3A,B
MIC1+,MIC2+,MIC2A,B
MIC1A,B
AIN2A,B
AIN1A,B
AFILTA,B
21,22
23,24
21,23
22,24
21,22
23,24
25,26
29,30
27,28
SPKR/HP
31
RESET
32
VL
33
VD
DGND
SDOUT
MCLK
SCLK
SDIN
34
35
36
37
38
39
LRCK
40
GND/Thermal Pad
1.1
-
Analog Ground (Input) - Ground reference for the internal analog section.
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.
Microphone Bias (Output) - Low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.
Line-Level Analog Inputs (Input) - Single-ended stereo line-level analog inputs.
Differential Microphone Inputs (Input) - Differential stereo microphone inputs.
Single-Ended Microphone Inputs (Input) - Single-ended stereo microphone inputs.
Line-Level Analog Inputs (Input) - Single-ended stereo line-level analog inputs.
Anti-alias Filter Connection (Output) - Anti-alias filter connection for the ADC inputs.
Speaker/Headphone Switch (Input) - Powers down the left and/or right channel of the speaker
and/or headphone outputs.
Reset (Input) - The device enters a low power mode when this pin is driven low.
Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port.
Digital Power (Input) - Positive power for the internal digital section.
Digital Ground (Input) - Ground reference for the internal digital section.
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
Master Clock (Input) - Clock source for the delta-sigma modulators.
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on
the serial audio data line.
Ground reference for PWM power FETs and charge pump; thermal relief pad for optimized heat
dissipation.
I/O Pin Characteristics
Input and output levels and associated power supply voltage are shown in the table below. Logic levels
should not exceed the corresponding power supply voltage.
Power
Supply
VL
Pin Name
I/O
Internal
Connections
Driver
Receiver
RESET
SCL
SDA
-
1.65 V - 3.47 V, CMOS/Open
Drain
1.65 V - 3.47 V, CMOS
1.65 V - 3.47 V, with Hysteresis
1.65 V - 3.47 V, with Hysteresis
1.65 V - 3.47 V, with Hysteresis
1.65 V - 3.47 V, CMOS
1.65 V - 3.47 V
SDOUT
Input
Input
Input/
Output
Input
Input/
Output
Input/
Output
Output
SDIN
SPKR/HP
SPKR_OUTA+
SPKR_OUTASPKR_OUTB+
SPKR_OUTB-
Input
Input
Output
Output
Output
Output
MCLK
LRCK
SCLK
VA
VP
DS680F1
Weak Pullup
(~1 MΩ)
Weak Pullup
(~1 MΩ)
Weak Pullup
(~1 MΩ)
-
1.65 V - 3.47 V
1.65 V - 3.47 V
1.65 V - 3.47 V, CMOS
1.6 V - 5.25 V Power MOSFET
1.6 V - 5.25 V Power MOSFET
1.6 V - 5.25 V Power MOSFET
1.6 V - 5.25 V Power MOSFET
1.65 V - 3.47 V
1.65 V - 2.63 V
-
9
5/13/08
CS42L52
2. TYPICAL CONNECTION DIAGRAM
+1.8 V to +2.5 V
+1.8 V to +2.5 V
1 µF
0.1 µF
0.1 µF
0.1 µF
1 µF
See Note 5
VD
VA
+VHP
Line Level Out
Left & Right
47 kΩ
0.022 µF
Note 1
1 µF
**
FLYP
HP/LINE_OUTB
FLYN
HP/LINE_OUTA
Headphone Out
Left & Right
51.1 Ω
0.022 µF
Note 2
-VHPFILT
1 µF
51.1 Ω
SPKR/HP
**
CS42L52
VP
0.1 µF
10 µF
+1.6 V to
Stereo Speakers
+5 V
SPKR_OUTA+
SPKR_OUTA-
* *Use low ESR ceramic capacitors.
VP
0.1 µF
SPKR_OUTB+
SPKR_OUTB-
MCLK
SCLK
Note 4
AIN1A
LRCK
100 Ω
1800 pF *
SDIN
Digital Audio
Processor
SDOUT
1800 pF
*
Left 1
100 kΩ
Analog
Input 1
100 kΩ
100 Ω
AIN1B
RESET
1 µF
Right 1
1 µF
SCL
SDA
AIN2A
100 Ω
1800 pF *
1800 pF
*
Note 7
MIC1-
VL
Analog
Input 2
Right 2
1 µF
2 kΩ
+1.8 V to +3.3 V
Left 2
100 kΩ
100 kΩ
100 Ω
AIN2B
2 kΩ
1 µF
AIN3A/MIC1A
1 µF
0.1 µF
Microphone 1
MIC1+
AIN4A/MIC2A
Notes:
1. Recommended values for the default charge pump switching
frequency. The required capacitance follows an inverse
relationship with the charge pump’s switching frequency. When
increasing the switching frequency, the capacitance may
decrease; when lowering the switching frequency, the
capacitance must increase.
2. Larger capacitance reduces the ripple on the internal
amplifier’s supply. This may reduce the distortion at higher
output power levels.
3. Additional bulk capacitance may be added to improve PSRR
at low frequencies.
4. These capacitors serve as a charge reservoir for the internal
switched capacitor ADC modulators. They are only needed
when the PGA (Programmable Gain Amplifier) is bypassed.
5. Series resistance in the path of the power supplies must be
avoided. Any voltage drop on VHP will directly impact the
negative charge pump supply (-VHPFILT) and clip the audio
output.
6. The value of RL, a current-limiting resistor used with electret
condenser microphones, is dictated by the microphone
cartridge.
7. The negative terminal of the MICx inputs connects to the
ground pin of the microphone cartridge. Gain is applied only to
the positive terminal.
1 µF
100 kΩ
Mic-Level
Inputs
MICBIAS
RL
0.1 µF
Note 6
RL
MIC2+
AIN4B/MIC2B
1 µF
100 kΩ
Microphone 2
MIC2AIN3B/MIC1B
Note 7
1 µF
Note 3
AGND
*
150 pF
*
150 pF
1 µF
10 µF
AFILTA
AFILTB
VQ
FILT+
DGND
* Capacitors must be C0G or equivalent
Figure 1. Typical Connection Diagram
10
DS680F1
5/13/08
CS42L52
3. CHARACTERISTIC AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
AGND=DGND=0 V, All voltages with respect to ground.
Parameters
DC Power Supply
Analog
Headphone Amplifier
Speaker Amplifier
Digital
Serial/Control Port Interface
Ambient Temperature
Commercial - CNZ
Automotive - DNZ
Symbol
Min
Max
Units
VA
+VHP
VP
VD
VL
1.65
1.65
1.60
1.65
1.65
-40
-40
2.63
2.63
5.25
2.63
3.47
+85
+105
V
V
V
V
V
°C
°C
TA
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V; All voltages with respect to ground.
Parameters
Symbol
Min
Max
Units
Analog
Speaker
Digital
Serial/Control Port Interface
Input Current
(Note 1)
External Voltage Applied to Analog Input
(Note 2)
VA, VHP
VP
VD
VL
Iin
VIN
-0.3
-0.3
-0.3
-0.3
AGND-0.3
3.0
6.0
3.0
4.0
±10
VA+0.3
V
V
V
V
mA
V
VIN
-VHP - 0.3
+VHP + 0.3
V
VIND
TA
Tstg
-0.3
-50
-65
VL+ 0.3
+115
+150
V
°C
°C
DC Power Supply
External Voltage Applied to Analog Output
External Voltage Applied to Digital Input
Ambient Operating Temperature
Storage Temperature
(Note 2)
(power applied)
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
Notes:
1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
2. The maximum over/under voltage is limited by the input current.
DS680F1
11
5/13/08
CS42L52
ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ)
Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive input filter; All
Supplies = VA; TA = +25°C; Sample Frequency = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified; “Required Initialization Settings” on page 37 written on power up.
Min
VA = 2.5V
Typ
Max
Min
VA = 1.8V
Typ
Max
Unit
A-weighted
unweighted
-1 dBFS
-20 dBFS
-60 dBFS
93
90
-
99
96
-86
-76
-36
-80
-30
90
87
-
96
93
-84
-73
-33
-78
-27
dB
dB
dB
dB
dB
A-weighted
unweighted
A-weighted
unweighted
92
89
85
82
96
93
91
88
-
89
86
82
79
95
92
88
85
-
dB
dB
dB
dB
-88
-33
-85
-82
-27
-79
-
-86
-32
-83
-80
-26
-77
dB
dB
dB
86
83
-
-
83
80
-
dB
dB
-76
-
-
-74
-
dB
76
73
-
-
74
71
-
dB
dB
-74
-
-
-71
-
dB
0.2
±100
352
-
-
0.2
±100
352
-
dB
ppm/°C
LSB
90
100
70
-
-
90
100
70
-
dB
dB
dB
0.73•VA
0.73•VA
60
0.769•VA
0.770•VA
0.194•VA
0.115•VA
0.019•VA
20
39
50
0.83•VA
0.83•VA
dB
Vpp
Vpp
Vpp
Vpp
Vpp
kΩ
kΩ
kΩ
Parameters
Analog In to ADC (PGA bypassed)
Dynamic Range
Total Harmonic Distortion + Noise
Analog In to PGA to ADC
Dynamic Range
PGA Setting: 0 dB
PGA Setting: +12 dB
Total Harmonic Distortion + Noise
PGA Setting: 0 dB
-1 dBFS
-60 dBFS
PGA Setting: +12 dB
-1 dBFS
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB
-1 dBFS
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB
-2 dBFS
Other Characteristics
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Offset Error
SDOUT Code with HPF On
Input
Interchannel Isolation
HP Amp to Analog Input Isolation
RL = 10 kΩ
(Note 3)
RL = 16 Ω
Speaker Amp to Analog Input Isolation
Full-scale Input Voltage
ADC 0.73•VA
PGA (0 dB) 0.73•VA
PGA (+12 dB)
MIC (+16 dB)
MIC (+32 dB)
Input Impedance (Note 4)
ADC
PGA
MIC
-
60
0.769•VA 0.83•VA
0.770•VA 0.83•VA
0.194•VA
0.115•VA
0.019•VA
20
39
50
-
-
-
3. Measured with DAC delivering full-scale output into specified load.
4. Measured between analog input and AGND.
12
DS680F1
5/13/08
CS42L52
ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) Test Conditions (unless
otherwise specified): Input sine wave (relative to full-scale): 1 kHz through passive input filter; All Supplies = VA; TA = -40 to
+85°C; Sample Frequency = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified; “Required Initialization Settings” on page 37 written on power up.
VA = 2.37 - 2.63 V
Min
Typ
Max
Parameters
Analog In to ADC
Dynamic Range
Total Harmonic Distortion + Noise
Analog In to PGA to ADC
Dynamic Range
PGA Setting: 0 dB
PGA Setting: +12 dB
Total Harmonic Distortion + Noise
PGA Setting: 0 dB
Input Impedance (Note 4)
DS680F1
Unit
A-weighted
unweighted
-1 dBFS
-20 dBFS
-60 dBFS
91
88
-
99
96
-86
-76
-36
-78
-28
88
85
-
96
93
-84
-73
-33
-76
-25
dB
dB
dB
dB
dB
A-weighted
unweighted
A-weighted
unweighted
90
87
83
80
96
93
91
88
-
87
84
80
77
95
92
88
85
-
dB
dB
dB
dB
-
-88
-33
-85
-80
-25
-77
-
-86
-32
-83
-78
-24
-75
dB
dB
dB
-
86
83
-
-
83
80
-
dB
dB
-
-76
-
-
-74
-
dB
-
76
73
-
-
74
71
-
dB
dB
-
-74
-
-
-71
-
dB
-
0.1
±100
352
-
-
0.1
±100
352
-
dB
ppm/°C
LSB
-
90
100
70
-
-
90
100
70
-
dB
dB
dB
60
0.769•VA
0.770•VA
0.194•VA
0.115•VA
0.019•VA
-
0.83•VA
0.83•VA
-
0.73•VA
0.73•VA
18
40
50
60
0.769•VA
0.770•VA
0.194•VA
0.115•VA
0.019•VA
-
0.83•VA
0.83•VA
-
dB
Vpp
Vpp
Vpp
Vpp
Vpp
kΩ
kΩ
kΩ
-1 dBFS
-60 dBFS
PGA Setting: +12 dB
-1 dBFS
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB
-1 dBFS
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB
-2 dBFS
Other Characteristics
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Offset Error
SDOUT Code with HPF On
Input
Interchannel Isolation
HP Amp to Analog Input Isolation
RL = 10 kΩ
(Note 3)
RL = 16 Ω
Speaker Amp to Analog Input Isolation
Full-scale Input Voltage
VA = 1.65 - 1.89 V
Min
Typ
Max
ADC 0.73•VA
PGA (0 dB) 0.73•VA
PGA (+12 dB)
MIC (+16 dB)
MIC (+32 dB)
ADC
18
PGA
40
MIC
50
13
5/13/08
CS42L52
ADC DIGITAL FILTER CHARACTERISTICS
Parameters (Note 5)
Passband (Frequency Response)
to -0.1 dB corner
Passband Ripple
Min
Typ
Max
Unit
0
-
0.4948
Fs
-0.09
-
0.17
dB
Stopband
0.6
-
-
Fs
Stopband Attenuation
33
-
-
dB
-
7.6/Fs
-
s
-
3.6
24.2
-
Hz
Hz
Total Group Delay
High-Pass Filter Characteristics (48 kHz Fs)
Frequency Response
Phase Deviation
-3.0 dB
-0.13 dB
-
10
-
Deg
Passband Ripple
@ 20 Hz
-
-
0.17
dB
Filter Settling Time
-
105/Fs
0
s
5. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 26 to 29 on
page 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
HPF parameters are for Fs = 48 kHz.
14
DS680F1
5/13/08
CS42L52
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA; TA = +25°C;
Sample Frequency = 48 kHz; Measurement bandwidth is 20 Hz to 20 kHz; Test load RL = 10 kΩ, CL = 10 pF for the line output
(see Figure 2); Test load RL = 16 Ω, CL = 10 pF (see Figure 2) for the headphone output; HP_GAIN[2:0] = 011; “Required Initialization Settings” on page 37 written on power up.
VA = 2.5 V
Min
Typ
Max
Parameters (Note 6)
VA = 1.8 V
Min
Typ
Max
Unit
RL = 10 kΩ
Dynamic Range
18- to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Total Harmonic Distortion + Noise
18- to 24-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
16-Bit
92
89
-
98
95
96
93
-
89
86
-
95
92
93
90
-
dB
dB
dB
dB
-
-86
-75
-35
-86
-73
-33
-80
-29
-
-
-88
-72
-32
-88
-70
-30
-82
-26
-
dB
dB
dB
dB
dB
dB
92
89
-
98
95
96
93
-
89
86
-
95
92
93
90
-
dB
dB
dB
dB
-
-75
-75
-35
-75
-73
-33
-69
-29
-
-
-75
-72
-32
-75
-70
-30
-69
-26
-
dB
dB
dB
dB
dB
dB
RL = 16 Ω
Dynamic Range
18- to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Total Harmonic Distortion + Noise
18- to 24-Bit
16-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Other Characteristics for RL = 16 Ω or 10 kΩ
Output Parameters
Modulation Index (MI)
0.6787
0.6787
(Note 7)
Analog Gain Multiplier (G)
0.6047
0.6047
Full-scale Output Voltage (2•G•MI•VA) (Note 7)
Refer to Table “Line Output Voltage Level CharacterisVpp
tics” on page 20
Full-scale Output Power (Note 7)
Refer to Table “Headphone Output Power Characteristics” on
page 19
Interchannel Isolation (1 kHz)
16 Ω
80
80
dB
10 kΩ
95
93
dB
Speaker Amp to HP Amp Isolation
80
80
dB
Interchannel Gain Mismatch
0.1
0.25
0.1
0.25
dB
Gain Drift
±100
±100
ppm/°C
AC Load Resistance (RL)
(Note 8)
16
16
Ω
Load Capacitance (CL)
(Note 8)
-
-
150
-
-
150
pF
6. One-half LSB of triangular PDF dither is added to data.
7. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog
Gain” on page 51. High gain settings at certain VA and VHP supply levels may cause clipping when the
audio signal approaches full-scale, maximum power output, as shown in Figures 22 - 25 on page 75.
DS680F1
15
5/13/08
CS42L52
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA; TA = -40 to
+85°C; Sample Frequency = 48 kHz and 96 kHz; Measurement bandwidth is 20 Hz to 20 kHz; Test load RL = 10 kΩ, CL = 10 pF
for the line output (see Figure 2); Test load RL = 16 Ω, CL = 10 pF (see Figure 2) for the headphone output;
HPGAIN[2:0] = 011. “Required Initialization Settings” on page 37 written on power up.
VA = 2.37 - 2.63 V
Min
Typ
Max
Parameters (Note 6)
VA = 1.65 - 1.89 V
Min
Typ
Max
Unit
RL = 10 kΩ
Dynamic Range
18- to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Total Harmonic Distortion + Noise
18- to 24-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
16-Bit
90
87
-
98
95
96
93
-
87
84
-
95
92
93
90
-
dB
dB
dB
dB
-
-86
-75
-35
-86
-73
-33
-78
-27
-
-
-88
-72
-32
-88
-70
-30
-80
-24
-
dB
dB
dB
dB
dB
dB
90
87
-
98
95
96
93
-
87
84
-
95
92
93
90
-
dB
dB
dB
dB
-
-75
-75
-35
-75
-73
-33
-67
-27
-
-
-75
-72
-32
-75
-70
-30
-67
-24
-
dB
dB
dB
dB
dB
dB
RL = 16 Ω
Dynamic Range
18- to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Total Harmonic Distortion + Noise
18- to 24-Bit
16-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Other Characteristics for RL = 16 Ω or 10 kΩ
Output Parameters
Modulation Index (MI)
0.6787
0.6787
(Note 7)
Analog Gain Multiplier (G)
0.6047
0.6047
Full-scale Output Voltage (2•G•MI•VA)
(Note 7) Refer to the table in “Line Output Voltage Level CharacVpp
teristics” on page 20
Full-scale Output Power
(Note 7) Refer to the table in “Headphone Output Power Characteristics” on
page 19
Interchannel Isolation (1 kHz)
16 Ω
80
80
dB
10 kΩ
95
93
dB
Speaker Amp to HP Amp Isolation
80
80
dB
Interchannel Gain Mismatch
0.1
0.25
0.1
0.25
dB
Gain Drift
±100
±100
ppm/°C
AC Load Resistance (RL)
(Note 8)
16
16
Ω
Load Capacitance (CL)
(Note 8)
-
-
150
-
-
150
pF
8. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively
move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recommended 150 pF can cause the internal op-amp to become unstable.
16
DS680F1
5/13/08
CS42L52
ANALOG PASSTHROUGH CHARACTERISTICS
Test Conditions (unless otherwise specified): Input sine wave (relative to full-scale): 1 kHz through passive input filter; PGA and
HP/Line Gain = 0 dB; All Supplies = VA; TA = +25°C; Sample Frequency = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz;
“Required Initialization Settings” on page 37 written on power up.
Min
VA = 2.5 V
Typ
Max
A-weighted
unweighted
-1 dBFS
-20 dBFS
-60 dBFS
-
-96
-93
-70
-73
-33
0.91•VA
0.84•VA
0/-0.3
A-weighted
unweighted
-1 dBFS
-20 dBFS
-60 dBFS
-
-96
-93
-70
-73
-33
0.91•VA
0.84•VA
32
0/-0.3
Parameters
Min
VA = 1.8 V
Typ
Max
Unit
-
-
-94
-91
-70
-71
-31
0.91•VA
0.84•VA
0/-0.3
-
dB
dB
dB
dB
dB
Vpp
Vpp
dB
-
-
-94
-91
-70
-71
-31
0.91•VA
0.84•VA
17
0/-0.3
-
dB
dB
dB
dB
dB
Vpp
Vpp
mW
dB
Analog In to HP/Line Amp (ADC is powered down)
RL = 10 kΩ
Dynamic Range
Total Harmonic Distortion + Noise
Full-scale Input Voltage
Full-scale Output Voltage
Passband Ripple
RL = 16 Ω
Dynamic Range
Total Harmonic Distortion + Noise
Full-scale Input Voltage
Full-scale Output Voltage
Output Power
Passband Ripple
PWM OUTPUT CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full scale 997 Hz signal; MCLK = 12.2880 MHz; Measurement
Bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 8 Ω for stereo full-bridge, RL = 4 Ω for mono parallel
full-bridge; VD = VL = VA = VHP = 1.8V; PWM Modulation Index of 0.85; PWM Switch Rate = 384 kHz; “Required Initialization
Settings” on page 37 written on power up. (Note 9)
Parameters (Note 10)
Symbol
VP = 5.0 V
Power Output per Channel
Stereo Full-Bridge
PO
Mono Parallel Full-Bridge
Total Harmonic Distortion + Noise
THD+N
Stereo Full-Bridge
Mono Parallel Full-Bridge
Dynamic Range
Min
Typ
Max Units
THD+N < 10%
THD+N < 1%
THD+N < 10%
THD+N < 1%
-
1.00
0.80
1.90
1.50
-
Wrms
Wrms
Wrms
Wrms
PO = 0 dBFS = 0.8W
PO = -3 dBFS = 0.75 W
PO = 0 dBFS = 1.5 W
-
0.52
0.10
0.50
-
%
%
%
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
-
91
88
91
88
-
dB
dB
dB
dB
DR
Stereo Full-Bridge
Mono Parallel Full-Bridge
DS680F1
Conditions
17
5/13/08
CS42L52
Parameters (Note 10)
Symbol
VP = 3.7 V
Power Output per Channel
Stereo Full-Bridge
PO
Mono Parallel Full-Bridge
Total Harmonic Distortion + Noise
THD+N
Stereo Full-Bridge
Mono Parallel Full-Bridge
Dynamic Range
Conditions
Min
Typ
Max Units
THD+N < 10%
THD+N < 1%
THD+N < 10%
THD+N < 1%
-
0.55
0.45
1.00
0.84
-
Wrms
Wrms
Wrms
Wrms
PO = 0 dBFS = 0.43 W
PO = -3 dBFS = 0.41 W
PO = 0 dBFS = 0.81 W
-
0.54
0.09
0.45
-
%
%
%
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
-
91
88
95
92
-
dB
dB
dB
dB
THD+N < 10%
THD+N < 1%
THD+N < 10%
THD+N < 1%
-
0.23
0.19
0.44
0.35
-
Wrms
Wrms
Wrms
Wrms
PO = 0 dBFS = 0.18 W
PO = -3 dBFS = 0.17 W
PO = 0 dBFS = 0.35 W
-
0.50
0.08
0.43
-
%
%
%
-
91
88
94
91
600
640
760
81
0.8
1.5
5.0
dB
dB
dB
dB
mΩ
mΩ
mΩ
%
A
µA
DR
Stereo Full-Bridge
Mono Parallel Full-Bridge
VP =2.5 V
Power Output per Channel
Stereo Full-Bridge
PO
Mono Parallel Full-Bridge
Total Harmonic Distortion + Noise
THD+N
Stereo Full-Bridge
Mono Parallel Full-Bridge
Dynamic Range
DR
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
Mono Parallel Full-Bridge
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
VP = 5.0V, Id = 0.5 A
MOSFET On Resistance
RDS(ON)
VP = 3.7V, Id = 0.5 A
MOSFET On Resistance
RDS(ON)
VP = 2.5V, Id = 0.5 A
MOSFET On Resistance
RDS(ON)
Efficiency
η
VP = 5.0 V, PO = 2 x 0.8 W, RL = 8 Ω
Output Operating Peak Current
IPC
VP Input Current During Reset
IVP
RESET, pin 32, is held low
Stereo Full-Bridge
9. The PWM driver should be used in captive speaker systems only.
10. Optimal PWM performance is achieved when MCLK > 12 MHz.
18
DS680F1
5/13/08
CS42L52
HEADPHONE OUTPUT POWER CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; Sample Frequency = 48 kHz;
Measurement Bandwidth is 20 Hz to 20 kHz; Test load RL = 16 Ω, CL = 10 pF (see Figure 2); “Required Initialization Settings”
on page 37 written on power up.
Parameters
Min
VA = 2.5V
Typ
Max
Min
VA = 1.8V
Typ
Unit
Max
AOUTx Power Into RL = 16 Ω
HP_GAIN[2:0]
000
Analog
Gain (G)
0.3959
001
0.4571
010
0.5111
011 (default)
0.6047
100
0.7099
101
0.8399
110
1.0000
111
1.1430
VHP
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
-
14
14
19
19
23
23
(Note 11)
32
(Note 11)
44
7
7
10
10
12
12
17
17
23
23
(Note 7), Figure 22 on page 74
32
(Note 7, 11) See Figures 22 and 23 on page 74
-
-
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
11. VHP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC
may not achieve the full THD+N performance at full-scale output voltage and power.
AOUTx
51 Ω
0.022 µF
C
L
R
L
AGND
Figure 2. Headphone Output Test Load
DS680F1
19
5/13/08
CS42L52
LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 20 Hz
to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 10 kΩ, CL = 10 pF (see Figure 2); “Required Initialization Settings” on
page 37 written on power up.
Parameters
Min
VA = 2.5V
Typ
Max
Min
2.15
-
1.41
-
VA = 1.8V
Typ
Unit
Max
AOUTx Voltage Into RL = 10 kΩ
HP_GAIN[2:0]
000
Analog
Gain (G)
0.3959
001
0.4571
010
0.5111
011 (default)
0.6047
100
0.7099
101
0.8399
110
1.0000
111
1.1430
VHP
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.95
-
1.34
1.34
1.55
1.55
1.73
1.73
2.05
2.05
2.41
2.41
2.85
2.85
3.39
3.39
(See (Note 11)
3.88
-
-
0.97
0.97
1.12
1.12
1.25
1.25
1.48
1.48
1.73
1.73
2.05
2.05
2.44
2.44
2.79
2.79
1.55
-
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
-
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameters (Note 12)
Frequency Response 10 Hz to 20 kHz
Passband
to -0.05 dB corner
to -3 dB corner
StopBand
StopBand Attenuation (Note 13)
Group Delay
De-emphasis Error
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Min
Typ
Max
Unit
-0.01
-
+0.08
dB
0
0
-
0.4780
0.4996
Fs
Fs
0.5465
-
-
Fs
50
-
-
dB
-
9/Fs
-
s
-
-
+1.5/+0
+0.05/-0.25
-0.2/-0.4
dB
dB
dB
12. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 30 and 33 on
page 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
13. Measurement Bandwidth is from Stopband to 3 Fs.
20
DS680F1
5/13/08
CS42L52
SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.
Parameters
Symbol
RESET pin Low Pulse Width
(Note 14)
MCLK Frequency (Note 15)
MCLK Duty Cycle
Min
Max
1
-
Units
ms
(See “Serial Port Clocking” on page 34)
45
55
MHz
(See “Serial Port Clocking” on page 34)
45
55
64•Fs
45
55
40
52
20
30
20
20
-
kHz
(See “Serial Port Clocking” on page 34)
45
55
12.0000
68•Fs
64•Fs
45
55
52
20
30
20
20
-
Hz
%
Slave Mode
Fs
Input Sample Rate (LRCK)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
1/tP
ts(LK-SK)
td(MSB)
ts(SDO-SK)
th(SK-SDO)
ts(SD-SK)
th
%
Hz
%
ns
ns
ns
ns
ns
ns
Master Mode
Output Sample Rate (LRCK)
All Speed Modes
LRCK Duty Cycle
SCLK Frequency
SCLK=MCLK mode
MCLK=12.0000 MHz
all other modes
SCLK Duty Cycle
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Fs
1/tP
1/tP
1/tP
td(MSB)
ts(SDO-SK)
th(SK-SDO)
ts(SD-SK)
th
%
MHz
Hz
Hz
%
ns
ns
ns
ns
ns
14. After powering up the CS42L52, RESET should be held low after the power supplies and clocks are
settled.
15. See “Example System Clock Frequencies” on page 76 for typical MCLK frequencies.
//
LRCK
ts(LK-SK)
//
tP
//
SCLK
//
td(MSB)
SDOUT
ts(SD-SK)
SDIN
th(SK-SDO)
//
MSB
//
th
//
MSB
//
ts(SDO-SK)
MSB-1
MSB-1
Figure 3. Serial Audio Interface Timing
DS680F1
21
5/13/08
CS42L52
SWITCHING SPECIFICATIONS - I²C CONTROL PORT
Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF.
Parameters
SCL Clock Frequency
RESET Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
(Note 16)
Symbol
Min
Max
Unit
fscl
tirs
550
100
-
kHz
ns
tbuf
thdst
tlow
thigh
tsust
thdd
tsud
trc
tfc
tsusp
tack
4.7
4.0
4.7
4.0
4.7
0
250
4.7
300
1
300
1000
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
16. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Stop
Repeated
Start
Start
Stop
SDA
t buf
t
t high
t hdst
tf
hdst
t susp
SCL
t
low
t
hdd
t sud
t sust
tr
Figure 4. Control Port Timing - I²C
22
DS680F1
5/13/08
CS42L52
DC ELECTRICAL CHARACTERISTICS
AGND = 0 V; All voltages with respect to ground.
Parameters
Min
Typ
Max
Units
-
0.5•VA
23
-
1
V
kΩ
µA
1 kHz
-
0.5•VA
0.6•VA
0.7•VA
0.8•VA
0.83•VA
0.91•VA
50
1
-
V
V
V
V
V
V
mA
dB
PSRR @1 kHz (Note 17)
PGA to ADC
ADC
DAC (HP & Line Amps)
-
44
60
60
-
dB
dB
dB
PSRR @60 Hz (Note 17)
PGA to ADC(Note 18)
ADC
DAC (HP & Line Amps)
-
22
42
60
-
dB
dB
dB
Full-Bridge PWM Outputs
-
56
-
dB
VQ Characteristics
Nominal Voltage
Output Impedance
DC Current Source/Sink
MIC BIAS Characteristics
Nominal Voltage
BIASLVL[2:0] = 000
BIASLVL[2:0] = 001
BIASLVL[2:0] = 010
BIASLVL[2:0] = 011
BIASLVL[2:0] = 100
BIASLVL[2:0] = 101
DC Output Current
Power Supply Rejection Ratio (PSRR)
Power Supply Rejection Ratio Characteristics
PSRR @217 Hz
17. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also
increase the PSRR.
18. The PGA is biased with VQ, created from a resistor divider from the VA supply. Increasing the capacitance on VQ will also increase the PSRR at low frequencies. A 10 µF capacitor on VQ improves the
PSRR to 42 dB.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 19)
Input Leakage Current
Symbol
Min
Max
Units
Iin
-
±10
µA
-
10
pF
Input Capacitance
1.8 V - 3.3 V Logic
High-Level Output Voltage (IOH = -100 µA)
VOH
VL - 0.2
-
V
Low-Level Output Voltage (IOL = 100 µA)
VOL
-
0.2
V
VIH
0.85•VL
0.76•VL
0.68•VL
0.65•VL
-
V
V
V
V
VIL
-
0.30•VL
V
High-Level Input Voltage
Low-Level Input Voltage
VL = 1.65 V
VL = 1.8 V
VL = 2.0 V
VL > 2.0 V
19. See “I/O Pin Characteristics” on page 9 for serial and control port power rails.
DS680F1
23
5/13/08
CS42L52
POWER CONSUMPTION See (Note 20).
Operation
PDN_SPKB[1:0]
PDN_SPKA[1:0]
Typical Current (mA)
PDN_HPA[1:0]
Power Ctl. Registers
03h
04h
PDN_PGAB
PDN_PGAA
PDN_ADCB
PDN_ADCA
PDN
PDN_MICB
PDN_MICA
PDN_MICBIAS
PDN_HPB[1:0]
02h
1
Off (Note 21)
x x x x x x x x x
x
x
x
2
Standby (Note 22)
x x x x 1 x x x x
x
x
x
3
Mono Record
ADC 1 1 1 0 0 1 1 1 11 11 11 11
PGA to ADC 1 0 1 0 0 1 1 1 11 11 11 11
MIC to PGA to ADC 1 0 1 0 0 1 0 0 11 11 11 11
(with Bias)
MIC to PGA to ADC 1 0 1 0 0 1 0 1 11 11 11 11
(no Bias)
4
Stereo Record
ADC 1 1 0 0 0 1 1 1 11 11 11 11
PGA to ADC 0 0 0 0 0 1 1 1 11 11 11 11
MIC to PGA to ADC 0 0 0 0 0 0 0 1 11 11 11 11
(no Bias)
5
Mono Playback to Headphone
1 1 1 1 0 1 1 1 10 11 11 11
6
Mono Playback to Speaker
1 1 1 1 0 1 1 1 11 11 10 10
7
Stereo Playback to Headphone
1 1 1 1 0 1 1 1 10 10 11 11
8
Stereo Playback to Speaker
1 1 1 1 0 1 1 1 11 11 10 10
9
Stereo Passthrough to Headphone
1 1 1 1 0 1 1 1 10 10 11 11
10 Mono Record & Playback
1 0 1 0 0 1 1 1 11 10 11 11
PGA in (no MIC) to Mono HP
11 Phone Monitor
1 0 1 0 0 1 0 0 11 10 11 11
MIC (w/bias) in to Mono Out
12 Stereo Record & Playback
0 0 0 0 0 1 1 1 10 10 11 11
PGA in (no MIC) to St. HP Out
13 Stereo Rec. & Full Playback
0 0 0 0 0 1 1 1 10 10 10 10
PGA (no MIC) to St. HP & SPK
iVHP
iVA
iVD
iVL
iVP
VL=3.3V
(Note 23)
VP=3.7V
0.00
0.00
0.00
0.00
0.03
0.00
0.03
0.00
0.03
0.00
0.03
0.00
0.03
0.00
0.03
0.00
0.03
0.00
0.01
0.00
0.01
1.00
0.01
0.00
0.01
1.00
0.01
0.00
0.03
0.00
0.03
0.00
0.03
0.00
0.03
1.00
Total
Power
(mWrms)
V
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
1.59
2.07
0.00
0.00
2.77
3.27
0.00
0.00
2.79
3.18
1.77
2.13
1.76
2.15
2.76
3.21
3.49
3.95
0.00
0.00
0.00
0.00
1.67
1.87
2.1
2.3
3.48
3.71
3.15
3.37
2.31
2.53
3.18
3.42
5.32
5.57
1.99
2.62
0.20
0.22
2.00
2.63
0.20
0.22
1.91
2.14
3.95
4.77
5.33
6.19
5.05
5.90
5.24
6.10
0.00
0.00
0.01
0.02
2.32
3.72
2.31
3.72
2.32
3.72
2.32
3.73
2.37
3.82
2.37
3.81
2.37
3.81
2.72
4.27
4.42
6.77
2.91
4.28
4.38
6.80
1.06
1.81
4.28
6.63
4.28
6.69
4.64
7.17
7.20
10.46
0.00
0.00
0.02
0.05
7.24
14.05
7.99
15.13
10.49
18.65
9.90
17.83
8.48
15.95
10.04
18.15
13.90
23.53
11.36
22.43
12.05
21.21
13.84
25.48
11.98
21.28
10.39
17.85
18.05
33.90
20.52
37.65
22.46
40.78
32.47
55.07
20. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample
rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode
and master/slave operation. “Required Initialization Settings” on page 37 written on power up.
21. RESET pin 25 held LO, all clocks and data lines are held LO.
22. RESET pin 25 held HI, all clocks and data lines are held HI.
23. VL current will slightly increase in master mode.
24
DS680F1
5/13/08
CS42L52
4. APPLICATIONS
4.1
Overview
4.1.1
Basic Architecture
The CS42L52 is a highly integrated, low-power, 24-bit audio CODEC comprised of a stereo analog-todigital converter (ADC), a stereo digital-to-analog converter (DAC), a digital PWM modulator and two fullbridge power back-ends. The ADC and DAC are designed using multi-bit delta-sigma techniques - the
DAC operates at an oversampling ratio of 128Fs and the ADC operates at 64Fs, where Fs is equal to the
system sample rate.
The different clock rates maximize power savings while maintaining high performance. The PWM modulator operates at a fixed frequency of 384 kHz. The power FETs are configured for either stereo full-bridge
or mono parallel full-bridge output. The CODEC operates in one of four sample rate speed modes: Quarter, Half, Single, and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input Master Clock (MCLK).
4.1.2
Line & MIC Inputs
The analog input portion of the CODEC allows selection from and configuration of multiple combinations
of stereo and microphone (MIC) sources. Eight line inputs with an option for two balanced MIC inputs, a
MIC bias output, and a Programmable Gain Amplifier (PGA) comprise the analog front-end.
4.1.3
Line & Headphone Outputs
The analog output portion of the CODEC includes a headphone amplifier capable of driving headphone
and line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale
output swing centered around ground. This eliminates the need for large DC-Blocking capacitors and allows the amplifier to deliver more power to headphone loads at lower supply voltages.
4.1.4
Speaker Driver Outputs
The Class D power amplifiers drive 8 ohm (stereo) and 4 ohm (mono) speakers directly, without the need
for an external filter. The power MOSFETS are powered directly from a battery eliminating the efficiency
loss associated with an external regulator. Battery level monitoring and compensation maintains a steady
output as battery levels fall. NOTE: The CS42L52 should only be used in captive speaker systems where
the outputs are permanently tied to the speaker terminals.
4.1.5
Fixed Function DSP Engine
The fixed-function digital signal processing engine processes both the PCM serial input data and ADC
output data, allowing a mix between the two. Independent volume control, left/right channel swaps, mono
mixes, tone control, and limiting functions also comprise the DSP engine.
4.1.6
Beep Generator
The beep generator delivers tones at select frequencies across approximately two octave major scales.
With independent volume control, beeps may be configured to occur continuously, periodically, or at single time intervals.
4.1.7
Power Management
Three control registers provide independent power-down control of the ADC, DAC, PGA, MIC pre-amp,
MIC bias, Headphone, and Speaker outputs, allowing operation in select applications with minimal power
consumption.
DS680F1
25
5/13/08
CS42L52
4.2
Analog Inputs
HPFRZA
HPFA
HPFA_CF[1:0]
ADCAMUTE
DIGSFT
DIGZC
ADCAVOL[7:0]
+24/-96dB
1dB steps
= PGAASEL[5:1]
PDN_ADCA
INV_ADCA
PDN_CHRG
AIN1A
AIN2A
Gain Adjust
ADC
Σ
ADCASEL[2:0]
PCM Serial Interface
DIGSUM [1:0]
Swap/
Mix
DIGM IX
AIN4A/ MIC1+/
MIC2A
ALCA
ALCASRDIS
ALCAZCDIS
ALCARATE[5:0]
ALCRRATE[5:0]
AIN3A/MIC1-/
MIC1A
Noise Gate
ALC
`
MAX[2:0]
M IN[2:0]
PDN_PGAA
PGAAVOL[5:0]
ADCB=A
ANLGSFTA
ANLGZCA
NGALL
NG
THRESH[3:0]
NGDELAY[1:0]
PDN_PGAB
PGABVOL[5:0]
ADCB=A
ANLGSFTB
ANLGZCB
ALCB
ALCBSRDIS
ALCBZCDIS
ADCBSEL[2:0]
Gain Adjust
ADCBM UTE
DIGSFT
DIGZC
ADCBVOL[7:0]
+24/-96dB
1dB steps
ADC
Refer to
“M IC Inputs”
BIASLVL[2:0]
PDN_BIAS
MICBIAS
Refer to
“M IC Inputs”
AIN4B/ MIC2+/
MIC2B
Σ
AIN3B/MIC2-/
MIC1B
AIN2B
HPFRZB
HPB
HPFB_CF[1:0]
PDN_ADCB
INV_ADCB
PDN_CHRG
AIN1B
= PGABSEL[5:1]
TO DSP Engine
ANALOG PASS THRU TO
HEADPHONE AM PLIFIER M UX
FROM DSP ENGINE
Figure 5. Analog Input Signal Flow
Referenced Control
Analog Front End
PDN_PGAx .........................
PGAxVOL[5:0].....................
ADCB=A ..............................
ANLGSFTx ..........................
ANLGZCx ............................
ADCxSEL[2:0] .....................
PGAxSEL5,4,3,2,1 ..............
BIASLVL[2:0] .......................
PDN_BIAS...........................
PDN_ADCx .........................
PDN_CHRG ........................
INV_ADCx ...........................
HPFRZx...............................
HPFx ...................................
HPFx_CF[1:0]......................
ADCxOVFL..........................
Digital Volume
ADCxMUTE.........................
ADCxVOL............................
ALCx....................................
ALCxSRDIS.........................
ALCxZCDIS.........................
ALCARATE[5:0]...................
ALCRRATE[5:0] ..................
MAX[2:0]..............................
MIN[2:0]...............................
NGALL.................................
NG .......................................
THRESH[3:0].......................
NGDELAY[1:0] ....................
Miscellaneous
DIGSUM[1:0] .......................
DIGMUX ..............................
26
Register Location
“Power Down PGAx” on page 42
“PGAx Volume” on page 56
“Analog Front-End Volume Setting B=A” on page 50
“Ch. x Analog Soft Ramp” on page 49
“Ch. x Analog Zero Cross” on page 49
“ADC Input Select” on page 48
“PGA Input Mapping” on page 49
“MIC Bias Level” on page 48
“Power Down MIC Bias” on page 43
“Power Down ADCx” on page 43
“Power Down ADC Charge Pump” on page 42
“Invert ADC Signal Polarity” on page 51
“ADCx High-Pass Filter Freeze” on page 49
“ADCx High-Pass Filter” on page 49
“HPF x Corner Frequency” on page 50
“ADCx Overflow (Read Only)” on page 71
“ADC Mute” on page 51
“ADCx Volume” on page 57
“ALCx Enable” on page 67
“ALCx Soft Ramp Disable” on page 55
“ALCx Zero Cross Disable” on page 56
“ALC Attack Rate” on page 67
“ALC Release Rate” on page 68
“ALC Maximum Threshold” on page 68
“ALC Minimum Threshold” on page 69
“Noise Gate All Channels” on page 69
“Noise Gate Enable” on page 69
“Noise Gate Threshold and Boost” on page 70
“Noise Gate Delay Timing” on page 70
“Digital Sum” on page 50
“Digital MUX” on page 50
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4.2.1
MIC Inputs
The input pins 21, 22, 23, and 24 accept stereo line-level or microphone signals. For microphone inputs,
either single-ended or differential configuration is allowed, providing programmable pre-amplification of
low-level signals. In the single-ended configuration, an internal MUX chooses one of two stereo sets (selection is made independently on channels A and B). In the differential configuration, an internal voltage
follower cascaded with the pre-amplifier maintains high input impedance and provides noise rejection
above the MICxGAIN setting. The pre-amps are biased to VQ in both configurations.
MICAGAIN[4:0]
MICAGAIN[4:0]
MIC1A
23
MIC2A
21
VQ
+
16..32 dB/
1 dB steps
to summing
PGA A
MIC1-
23
MIC1+
21
+
+
16..32 dB/
1 dB steps
to summing
PGA A
MICASEL
MICBGAIN[4:0]
MICBGAIN[4:0]
MIC1B
MIC2B
24
VQ
22
+
16..32 dB/
1 dB steps
to summing
PGA B
MIC2-
24
MIC2+
22
+
+
16..32 dB/
1 dB steps
to summing
PGA B
MICBSEL
MICACFG=’0'b
MICBCFG=’0'b
PDN_MICA=’0'b
PDN_MICB=’0'b
MICACFG=’1'b
MICBCFG=’1'b
PDN_MICA=’0'b
PDN_MICB=’0'b
Note: Output to PGA = (MIC + - MIC -)*gain + MIC -
Figure 6. Single-Ended MIC Configuration
4.2.2
Referenced Control
Register Location
MICxCFG ............................
PDN_MICx ..........................
MICxGAIN ...........................
“MICx Configuration” on page 55
“Power Down MICx” on page 43
“MICx Gain” on page 55
Figure 7. Differential MIC Configuration
Automatic Level Control (ALC)
When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak
levels exceed the maximum (MAX) threshold settings, and responds by applying attenuation as necessary to maintain the resulting level below the MAX threshold. To apply this attenuation, the ALC first lowers the PGA gain settings and then increases the digital attenuation levels. All attenuation is applied at a
programmable attack rate.
When input signal levels fall below the minimum (MIN) threshold, the ALC responds by removing any attenuation that it has previously applied until all ALC-applied attenuation has been removed or until the
MAX threshold is again crossed. To remove this attenuation, the ALC first decreases the digital attenuation levels and then increases the PGA gain. All attenuation is removed at a programmable release rate.
It should be noted that the ALC is applied independently to channels A and B with one exception: the input
signals on both channels A and B must be below the MIN threshold in order for the ALC attenuation to be
released on channel B.
Attack and release rates are affected by the ADC soft-ramp/zero-cross settings and sample rate, Fs. ALC
soft-ramp and zero-cross dependency may be independently enabled/disabled.
Recommended settings: Best level control may be realized with the fastest attack and slowest release
setting with soft ramp enabled in the control registers.
Notes:
1. When ALC x is enabled and the PGAxVOL[5:0] is set above 12 dB, the ADCxVOL[7:0] should not be
set below 0 dB.
2. The maximum realized gain must be set in the PGAxVOL register. The ALC will only apply the gain
set in the PGAxVOL.
3. The ALC maintains the output signal between the MIN and MAX thresholds. As the input signal level
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CS42L52
changes, the level-controlled output may not always be the same but will always fall within the
thresholds.
Referenced Control Register Location
PGAxVOL[5:0
MAX[2:0], MIN[2:0]
“PGAx Vol. & ALCx Transition Ctl.: ALC, PGA A (Address 12h) & ALC, PGA B (Address 13h)” on page 55
“ALC Threshold (Address 2Ch)” on page 68
In p u t (b e fo re A L C )
M A X [2 :0 ]
M IN [2 :0 ]
b e lo w fu ll s ca le
b e lo w fu ll s ca le
A LC
R e sp o n s e
P G A G a in a n d /o r
A tte n u a to r
O u tp u t
(a fte r A L C )
M A X [2 :0 ]
M IN [2 :0 ]
b e lo w fu ll sca le
b e lo w fu ll sc a le
A R A T E [5 :0
]
R R A T E [5 :0 ]
Figure 8. ALC
4.2.3
Noise Gate
The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents
the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before
the noise gate attacks the signal.
Note: Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC
pre-amplifier. For example: If both +32 dB pre-amplification and +12 dB programmable gain is applied,
the maximum attenuation that the noise gate achieves will be 52 dB (-96 + 32 + 12) below full-scale.
Referenced Control
Register Location
Noise Gate Controls............ “Noise Gate Control (Address 2Dh)” on page 69
Output
(dB)
N
EN
G
=1
N
EN
G
=0
-96
Maximum Attenuation*
-52 dB
-64 dB
-80 dB
-40
Input (dB)
THRESH[2:0]
Figure 9. Noise Gate Attenuation
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4.3
Analog Outputs
INPUTS FROM ADCA
and ADCB
Fixed Function DSP
AMIXAMUTE
AMIXBMUTE
AMIXAVOL[6:0]
AMIXBVOL[6:0]
+12dB/-51.5dB
0.5dB steps
PCM Serial Interface
VOL
PMIXAMUTE
PMIXBMUTE
PMIXAVOL[6:0]
PMIXBVOL[6:0]
Channel
Swap
DEEMPH
VOL
Channel
Swap
Σ
INV_PCMA
INV_PCMB
Limiter
ADCASWAP[1:0]
ADCBSWAP[1:0]
Peak
Detect
PWM
Modulator
0dB/-50dB
2.0dB steps
Beep
Generator
Σ
VOL
MSTAMUTE
MSTBMUTE
DIGSFT
DIGZC
PLYBCKB=A
BPVOL[4:0]
OFFTIME[2:0]
ONTIME[3:0]
FREQ[3:0]
BEEP[1:0]
BEEPMIXDIS
Chnl Vol.
Settings
PCMASWAP[1:0]
PCMBSWAP[1:0]
+12dB/-51.5dB
0.5dB steps
Demph
LIMARATE[7:0]
LIMRRATE[7:0]
LMAX[2:0]
CUSH[2:0]
LIMSRDIS
LIMZCDIS
LIMIT
MSTAVOL[7:0]
MSTBVOL[7:0]
+12dB/-102dB
0.5dB steps
VOL
Bass/
Treble/
Control
TC_EN
BASS_CF[1:0]
TREB_CF[1:0]
BASS[3:0]
TREB[3:0]
+12.0dB/-10.5dB
1.5dB steps
DAC
Digital Mix to ADC
Serial Interface
Figure 10. DSP Engine Signal Flow
Referenced Control
Register Location
DSP
DEEMPH .............................
PMIXxMUTE........................
PMIXxVOL[6:0]....................
INV_PCMx...........................
PCMxSWAP[1:0] .................
AMIXxMUTE........................
AMIXxVOL[6:0]....................
ADCxSWAP[1:0]..................
MSTxVOL[7:0].....................
MSTxMUTE.........................
DIGSFT ...............................
DIGZC .................................
PLYBCKB=A........................
TC_EN.................................
BASS_CF[1:0] .....................
TREB_CF[1:0] .....................
BASS[3:0]............................
TREB[3:0]............................
LIMIT ...................................
LIMSRDIS ...........................
LIMZCDIS............................
LMAX[2:0]............................
CUSH[2:0] ...........................
LIMARATE[7:0]....................
LIMRRATE[7:0] ...................
“HP/Speaker De-emphasis” on page 53
“PCM Mixer Channel x Mute” on page 58
“PCM Mixer Channel x Volume” on page 58
“Invert PCM Signal Polarity” on page 52
“PCM Mix Channel Swap” on page 64
“ADC Mixer Channel x Mute” on page 58
“ADC Mixer Channel x Volume” on page 58
“ADC Mix Channel Swap” on page 64
“Master Volume Control” on page 63
“Master Playback Mute” on page 52
“Digital Soft Ramp” on page 53
“Digital Zero Cross” on page 53
“Playback Volume Setting B=A” on page 51
“Tone Control Enable” on page 62
“Bass Corner Frequency” on page 62
“Treble Corner Frequency” on page 62
“Bass Gain” on page 63
“Treble Gain” on page 62
“Peak Detect and Limiter” on page 66
“Limiter Soft Ramp Disable” on page 65
“Limiter Zero Cross Disable” on page 66
“Limiter Maximum Threshold” on page 65
“Limiter Cushion Threshold” on page 65
“Limiter Attack Rate” on page 67
“Limiter Release Rate” on page 66
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CS42L52
BATTCMP
VPREF[3:0]
VPLVL[7:0]
SPKAMUTE
SPKBMUTE
MUTE50/50
SPKMONO
SPKSWAP
SPKB=A
SPKAVOL[7:0]
SPKBVOL[7:0]
+0dB/-102dB
0.5dB steps
from DSP
Engine
from DSP
Engine
VOL
PWM
Modulator
+ A
+ B
-
Gate
Drive
Short
Circuit
SPKASHRT
SPKBSHRT
Figure 11. PWM Output Stage
Referenced Control
Register Location
PWM Control
SPKxMUTE .........................
MUTE50/50 .........................
SPKMONO ..........................
SPKxVOL[7:0] .....................
SPKSWAP...........................
SPKB=A ..............................
BATTCMP ...........................
VPREF[3:0] .........................
VPLVL[7:0] ..........................
PDN_SPKx[1:0]...................
SPKxSHRT..........................
“Speaker Mute” on page 54
“Speaker Mute 50/50 Control” on page 54
“Speaker MONO Control” on page 54
“Speaker Volume Control” on page 64
“Speaker Channel Swap” on page 54
“Speaker Volume Setting B=A” on page 54
“Battery Compensation” on page 71
“VP Reference” on page 72
“VP Voltage Level (Read Only)” on page 72
“Speaker Power Control” on page 44
“Speaker Current Load Status (Read Only)” on page 72
Referenced Control
Register Location
Analog Output
HPxMUTE ...........................
HPxVOL[7:0] .......................
PDN_HPx[1:0] .....................
HPGAIN[2:0]........................
PASSTHRUx .......................
PASSxMUTE .......................
PASSxVOL[7:0] ...................
CHGFREQ ..........................
“Headphone Mute” on page 54
“Headphone Volume Control” on page 63
“Headphone Power Control” on page 44
“Headphone Analog Gain” on page 51
“Passthrough Analog” on page 52
“Passthrough Mute” on page 52
“Passthrough x Volume” on page 57
“Charge Pump Frequency” on page 73
HPGAIN[2:0]
A
VOL
Analog Passthru
from PGA
Speaker
Outputs
PDN_SPKA[1:0]
PDN_SPKB[1:0]
4.3.1
PDN_HPA[1:0]
PDN_HPB[1:0]
HPAMUTE
HPBMUTE
HPA_VOL[7:0]
HPB_VOL[7:0]
+0dB/-102dB
0.5dB steps
Battery
Compensation
DAC
HP/Line
Outputs
B
VOL
PASSTHRUA
PASSTHRUB
PASSAMUTE
PASSBMUTE
PASSAVOL[7:0]
PASSBVOL[70]
+12dB/-60dB
0.5dB steps
(uses PGA)
Charge
Pump
CHGFREQ[3:0]
Figure 12. Analog Output Stage
Beep Generator
The Beep Generator generates audio frequencies across approximately two octave major scales. It offers
three modes of operation: Continuous, multiple, and single (one-shot) beeps. Sixteen on and eight off
times are available.
Note: The Beep is generated before the limiter and may affect desired limiting performance. If the limiter function is used, it may be required to set the beep volume sufficiently below the threshold to prevent
the peak detect from triggering. Since the master volume control, MSTxVOL[7:0], will affect the beep volume, DAC volume may alternatively be controlled using the PMIXxVOL[6:0] bits.
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CS42L52
BEEP[1:0] =
'11'
CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains on
until BEEP is cleared.
BEEP[1:0] =
'10'
MULTI-BEEP: Beep turns on at a configurable frequency (FREQ)
and volume (BPVOL) for the duration of ONTIME and turns off for
the duration of OFFTIME. On and off cycles are repeated until
BEEP is cleared.
BEEP[1:0] =
'01'
SINGLE-BEEP: Beep turns on at a
configurable frequency (FREQ) and
volume (BPVOL) for the duration of
ONTIME. BEEP must be cleared
and set for additional beeps.
...
BPVOL[4:0]
FREQ[3:0]
ONTIME[3:0]
OFFTIME[2:0]
Figure 13. Beep Configuration Options
4.3.2
Referenced Control
Register Location
MSTxVOL[7:0].....................
PMIXxVOL[6:0] ...................
OFFTIME[2:0] .....................
ONTIME[3:0] .......................
FREQ[3:0] ...........................
BEEP[1:0]............................
BEEPMIXDIS ......................
BPVOL[4:0] .........................
“Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)” on page 63
“PCMx Mixer Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh)” on page 58
“Beep Off Time” on page 60
“Beep On Time” on page 60
“Beep Frequency” on page 59
“Beep Configuration” on page 61
“Beep Mix Disable” on page 61
“Beep Volume” on page 61
Limiter
When enabled, the limiter monitors the digital input signal before the DAC and PWM modulators, detects
when levels exceed the maximum threshold settings, and lowers the master volume at a programmable
attack rate below the maximum threshold. When the input signal level falls below the maximum threshold,
the AOUT volume returns to its original level set in the Master Volume Control register at a programmable
release rate. Attack and release rates are affected by the DAC soft-ramp/zero-cross settings and sample
rate, Fs. Limiter soft-ramp and zero-cross dependency may be independently enabled/disabled.
Notes:
1. Recommended settings: Best limiting performance may be realized with the fastest attack and
slowest release setting with soft ramp enabled in the control registers. The MIN bits allow the user to
set a threshold slightly below the maximum threshold for hysteresis control - this cushions the sound
as the limiter attacks and releases.
2. The Limiter maintains the output signal between the MIN and MAX thresholds. As the digital input
signal level changes, the level-controlled output may not always be the same but will always fall within
the thresholds.
Referenced Control
Register Location
Limiter Controls ................... “Limiter Control 2, Release Rate (Address 28h)” on page 66, “Limiter Attack Rate (Address 29h)” on page 67
Master Volume Control........ “Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)” on page 63
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CS42L52
In p u t
M A X [2 :0 ]
L im ite r
A T T A C K /R E L E A S E S O U N D
C U S H IO N
V o lu m e
O u tp u t
(a fte r L im ite r)
C U S H [2 :0 ]
M A X [2 :0 ]
A R A T E [5 :0 ]
R R A T E [5 :0 ]
Figure 14. Peak Detect & Limiter
4.4
Analog In to Analog Out Passthrough
The CS42L52 accommodates analog routing of the analog input signal directly to the headphone amplifiers.
This feature is useful in applications that utilize an FM tuner where audio recovered over-the-air must be
transmitted to the headphone amplifier without digital conversion in the ADC and DAC. This analog
passthrough path reduces power consumption and is immune to modulator switching noise that could
interfere with some tuners.
4.4.1
Overriding the ADC Power Down
To accommodate automatic activation of the speaker amplifier when the SPK/HP_SW switch pin changes, the CS42L52 provides the option to automatically power up the ADC whenever the analog signal must
route to the digital PWM modulator, regardless of the PDN_ADC bit. Refer to the table below for details
on how this ADC power-down override functions in accordance with the state of the speaker channels.
The shaded cells represent normal ADC operation when passthrough is disabled.
PDN_ADC
0
1
PASSTHRU
x
0
1
PDN_OVRD
x
x
0
1
Speaker Channel
x
x
x
OFF
ON
ADC Status
Powered UP
Powered DOWN
Powered DOWN
Powered DOWN
Powered UP
When PASSTHRU and PDN_OVRD are enabled, turning the speaker channel ON (by writing ‘11’b to
SPKx_PDN[1:0] or by automatic activation of the headphone detect switch, SPK/HP_SW) will automatically disable the ADCx_PDN in order to convert the analog input to a digital signal for the PWM modulator.
This allows automatic analog input routing to the speaker amplifiers.
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CS42L52
4.4.2
Referenced Control
Register Location
PDN_ADCx .........................
PASSTHRU .........................
PDN_OVRD ........................
SPKx_PDN[1:0]...................
“Power Down ADCx” on page 43
“Passthrough Analog” on page 52
“Power Down ADC Override” on page 43
“Speaker Power Control” on page 44
Overriding the PGA Power Down
To accommodate automatic activation of the headphone amplifier when the SPK/HP_SW switch pin
changes, the CS42L52 will automatically power up the PGA whenever passthrough is enabled, regardless of the PDN_PGA setting. Refer to the table below for details on how this PGA power-down override
functions in accordance with the state of the headphone channels. The shaded cells represent normal
PGA operation when passthrough is disabled.
PDN_PGA
0
PASSTHRU
x
0
1
1
HP Channel
x
x
OFF
ON
PGA Status
Powered UP
Powered DOWN
Powered DOWN
Powered UP
When passthrough is enabled, turning the headphone channel ON (by writing ‘11’b to HPx_PDN[1:0] or
by automatic activation of the headphone detect switch, SPK/HP_SW) will automatically disable the
PGAx_PDN in order to transmit the analog signal to the headphone.
Referenced Control
Register Location
PDN_PGAx ......................... “Power Down PGAx” on page 42
PASSTHRU ......................... “Passthrough Analog” on page 52
HPx_PDN[1:0]..................... “Headphone Power Control” on page 44
4.5
PWM Outputs
4.5.1
Mono Speaker Output Configuration
The CS42L52 accommodates a stereo as well as a mono speaker output configuration. In mono mode
the output drivers of each channel are connected in parallel to deliver maximum power to a 4 ohm speaker. Refer to the table below for pin mapping in mono configuration.
Pin
4
6
7
9
Referenced Control
Speaker Output
SPKMONO=0
SPKMONO=1
SPKSWAP=0
SPKSWAP=1
SPKSWAP=0
SPKSWAP=1
SPKOUTA+
SPKOUTB+
SPKOUTA+
SPKOUTB+
SPKOUTASPKOUTBSPKOUTA+
SPKOUTB+
SPKOUTB+
SPKOUTA+
SPKOUTASPKOUTBSPKOUTBSPKOUTASPKOUTASPKOUTBRegister Location
SPKMONO.......................... “Speaker MONO Control” on page 54
SPKSWAP........................... “Speaker Channel Swap” on page 54
4.5.2
VP Battery Compensation
The CS42L52 provides the option to maintain a desired power output level, independent of the VP supply.
When enabled, this feature works by monitoring the voltage on the VP supply and reducing the attenuation on the speaker outputs when VP voltage levels fall.
Note: The internal ADC that monitors the VP supply operates from the VA supply. Calculations are
based on typical VA levels of 1.8 V and 2.5 V using the VPREF bits.
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4.5.2.1
Maintaining a Desired Output Level
Using SPKxVOL, the speaker output level must first be attenuated by the decibel equivalent of the expected VP supply range (MAX relative to MIN). The CS42L52 then gradually reduces the attenuation as the
VP supply drops from its maximum level, maintaining a nearly constant power output.
Compensation Example 1 (VP Battery supply ranges from 4.5 V to 3.0 V)
1. Set speaker attenuation (SPKxVOL) to -3.5 dB. The VP supply changes ~3.5 dB.
2. Set the reference VP supply (VPREF) to 4.5 V.
3. Enable battery compensation (BATTCMP).
The CS42L52 automatically adjusts the output level as the battery discharges.
Compensation Example 2 (VP Battery supply ranges from 5.0 V to 1.6 V)
1. Set speaker attenuation (SPKxVOL) to -10 dB. The VP supply changes ~9.9 dB.
2. Set the reference VP supply (VPREF) to 5.0 V.
3. Enable battery compensation (BATTCMP).
The CS42L52 automatically adjusts the output level as the battery discharges. Refer to Figure 15 on page
34. In this example, the VP supply changes over a wide range, illustrating the accuracy of the CS42L52’s
battery compensation.
-6
Battery Compensated
PWM Output Level
PWM Output Level (dB)
-8
-10
-12
Uncompensated
PWM Output
Level
-14
-16
-18
-20
-22
-24
4.9
4.6
4.3
4
3.7
3.4
3.1
2.8
2.5
2.2
1.9
1.6
VP Supply (V)
Figure 15. Battery Compensation
4.6
Referenced Control
Register Location
VPREF ................................
SPKxVOL ............................
“VP Reference” on page 72
“Speaker Volume Control” on page 64
Serial Port Clocking
The CODEC serial audio interface port operates either as a slave or master, determined by the M/S bit. It
accepts externally generated clocks in Slave Mode and will generate synchronous clocks derived from an
input master clock (MCLK) in Master Mode. Refer to the tables below for the required setting in register 05h
and 06h associated with a given MCLK and sample rate.
34
Referenced Control
Register Location
M/S
Register 05h
Register 06h
“Master/Slave Mode” on page 46
“Clocking Control (Address 05h)” on page 44
“Interface Control 1 (Address 06h)” on page 46
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5/13/08
CS42L52
MCLK
(MHz)
12.2880
11.2896
18.4320
(Slave
Mode
ONLY)
16.9344
(Slave
Mode
ONLY)
12.0000
24.0000
27.0000
Sample Rate,
Fs (kHz)
8.0000
12.0000
16.0000
24.0000
32.0000
48.0000
96.0000
11.0250
22.0500
44.1000
88.2000
8.0000
12.0000
16.0000
24.0000
32.0000
48.0000
96.0000
8.0182
11.0250
22.0500
44.1000
88.2000
8.0000
11.0294
12.0000
16.0000
22.0588
24.0000
32.0000
44.1176
48.0000
88.2353
96.0000
8.0000
11.0294
12.0000
16.0000
22.0588
24.0000
32.0000
44.1176
48.0000
88.2353
96.0000
8.0000
12.0000
24.0000
32.0000
44.1176
48.0000
11.0294
22.0588
16.0000
SPEED[1:0]
(AUTO=’0’b)
11
11
10
10
01
01
00
11
10
01
00
11
11
10
10
01
01
00
11
11
10
01
00
11
11
11
10
10
10
01
01
01
00
00
11
11
11
10
10
10
01
01
01
00
00
11
11
10
01
01
01
11
10
10
32kGROUP
VIDEOCLK
RATIO[1:0]
MCLKDIV2
1
0
1
0
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
10
00
00
00
00
01
11
01
01
11
01
01
11
01
11
01
01
11
01
01
11
01
01
11
01
11
01
01
01
01
01
11
01
11
11
01
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
Table 1. MCLK, LRCK Quick Decode
DS680F1
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CS42L52
4.7
Digital Interface Formats
The serial port operates in standard I²S, Left-justified, Right-justified (DAC only), or DSP Mode digital interface formats with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the
rising edge of SCLK.
LRCK
L eft C h a n n el
R ig ht C h a n n el
SCLK
SDIN
SDOUT
MSB
M SB
LS B
AOUTA / AINxA
MSB
LS B
AOUTB / AINxB
Figure 16. I²S Format
LRCK
L eft C h a n n el
R ig ht C h a n n el
SCLK
SDIN
SDOUT
MSB
LS B
M SB
LS B
MSB
AOUTB / AINxB
AOUTA / AINxA
Figure 17. Left-Justified Format
LRCK
L e ft C h a n n e l
R ig h t C h a n n e l
SCLK
MSB
SDIN
MSB
LSB
AO UTL
LS B
AO UTR
Audio W ord Length (AW L)
Figure 18. Right-Justified Format (DAC only)
4.7.1
DSP Mode
In DSP Mode, the LRCK acts as a frame sync for 2 data-packed words (left and right channel) input on
SDIN and output on SDOUT. The MSB is input/output on the first SCLK rising edge after the frame sync
rising edge. The right channel immediately follows the left channel.
1/fs
LRCK
SCLK
SDIN
L SB MSB
L eft C h a n n el
LS B M SB
HP/LINE OUTA
R ig ht C h a n n el
LSB M SB
HP/LINE OUTB
Audio Word Length (AWL)
Figure 19. DSP Mode Format)
36
DS680F1
5/13/08
CS42L52
4.8
Initialization
The CODEC enters a Power-down state upon initial power-up. The interpolation and decimation filters, delta-sigma and PWM modulators, and control port registers are reset. The internal voltage reference, and
switched-capacitor low-pass filters are powered down.
The device will remain in the Power-down state until the RESET pin is brought high. The control port is accessible once RESET is high and the desired register settings can be loaded per the interface descriptions
in the “Register Description” on page 42.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+, will begin powering up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then
applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the
MCLK/LRCK frequency ratio and normal operation begins.
4.9
Recommended Power-up Sequence
1. Hold RESET low until the power supplies are stable.
2. Bring RESET high.
3. The default state of the PDN bit is ‘1’b. Load the desired register settings while keeping the PDN bit set
to ‘1’b.
4. Load the required initialization settings listed in Section 4.11.
5. Start MCLK to the appropriate frequency, as discussed in Section 4.6.
6. Set the PDN bit to ‘0’b.
7. Apply LRCK, SCLK, and SDIN for normal operation to begin.
8. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
4.10
Recommended Power-down Sequence
To minimize audible pops when turning off or placing the CODEC in standby:
1. Mute the DAC’s and ADC’s.
2. Set the PDN bit in the power control register to ‘1’b. The CODEC will not power down until it reaches a
fully muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary
to disable the soft-ramp and/or zero-cross volume transitions to achieve faster muting/power down.
3. Bring RESET low.
4.11
Required Initialization Settings
The current and thresholds required for various sections in the CODEC must be adjusted by implementing
the initialization settings shown below after power-up sequence step 3. All performance and power consumption measurements were taken with the following settings:
1. Write 0x99 to register 0x00.
2. Write 0xBA to register 0x3E.
3. Write 0x80 to register 0x47.
4. Write ‘1’b to bit 7 in register 0x32.
5. Write ‘0’b to bit 7 in register 0x32.
6. Write 0x00 to register 0x00.
DS680F1
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5/13/08
CS42L52
4.12
Control Port Operation
The control port is used to access the registers, allowing the CODEC to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates using an I²C interface with the CODEC acting as a slave device.
4.12.1 I²C Control
SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. The signal timings for a read and write cycle are shown in Figure 20 and Figure 21. A Start condition is defined as a
falling transition of SDA while the clock is high. A Stop condition is defined as a rising transition of SDA
while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS42L52 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low
for a write).
The upper 7 bits of the address field are fixed at 1001010. To communicate with the CS42L52, the chip
address field, which is the first byte sent to the CS42L52, should match 1001010. The eighth bit of the
address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP),
which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows successive reads or writes
of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the
CS42L52 after each input byte is read and is input to the CS42L52 from the microcontroller after each
transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
24 25 26 27 28
19
SCL
CHIP ADDRESS (WRITE)
1
SDA
0
0
1
0
1
0
MAP BYTE
0
INCR
6
5
4
3
DATA +1
DATA
2
1
0
7
ACK
6
1
ACK
0
7
6
1
DATA +n
0
7
6
1
0
ACK
ACK
STOP
START
Figure 20. Control Port Timing, I²C Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
1
0
0
1
0 1 0 0
INCR
ACK
START
STOP
MAP BYTE
6
5
4
3
2
1
CHIP ADDRESS (READ)
1
0
ACK
0
0
1
0
DATA
1 0 1
7
ACK
START
DATA +1
0
7
ACK
0
DATA + n
7
0
NO
ACK
STOP
Figure 21. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 21, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
38
DS680F1
5/13/08
CS42L52
Send start condition.
Send 10010100 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto-increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10010101 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
4.12.2 Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudo code above for implementation details.
4.12.2.1 Map Increment (INCR)
The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads. If INCR is set to 1, MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.
DS680F1
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5/13/08
CS42L52
5. REGISTER QUICK REFERENCE
(Default values are shown below the bit names)
I²C Address: 1001010[R/W] - 10010100 = 0x94(Write); 10010101 = 0x95(Read)
Adr. Function
7
6
5
4
01h ID
CHIPID4
CHIPID3
CHIPID2
CHIPID1
p 42
1
1
1
0
02h Power Ctl 1
PDN_CHRG
Reserved
Reserved
PDN_PGAB
p 42
0
0
0
0
03h Power Ctl 2
Reserved
Reserved
Reserved
OVRDB
p 43
0
0
0
0
04h Power Ctl 3
PDN_HPB1 PDN_HPB0 PDN_HPA1
PDN_HPA0
p 44
0
0
0
0
05h Clocking Ctl
AUTO
SPEED1
SPEED0
32kGROUP
p 44
1
0
1
0
06h Interface Ctl 1
M/S
INV_SCLK
ADCDIF
DSP
p 46
0
0
0
0
07h Interface Ctl 2
Reserved SCLK=MCLK DIGLOOP
3ST_SP
p 47
0
0
0
0
08h Input A Select
ADCASEL2 ADCASEL1 ADCASEL0 PGAASEL5
p 48
1
0
0
0
09h Input B Select
ADCBSEL2 ADCBSEL1 ADCBSEL0 PGABSEL5
p 48
1
0
0
0
0Ah Analog,
HPFB
HPFRZB
HPFA
HPFRZA
p 49 HPF Ctl
1
0
1
0
0Bh ADC HPF CorReserved
Reserved
Reserved
Reserved
p 50 ner Freq.
0
0
0
0
0Ch Misc. ADC Ctl
ADCB=A
DIGMIX
DIGSUM1
DIGSUM0
p 50
0
0
0
0
0Dh Playback Ctl 1
HPGAIN2
HPGAIN1
HPGAIN0
PLYBCKB=A
p 51
0
1
1
0
0Eh Misc. Ctl
PASSTHRUB PASSTHRUA PASSBMUTE PASSAMUTE
p 52
0
0
0
0
0Fh Playback Ctl 2
HPBMUTE
HPAMUTE SPKBMUTE SPKAMUTE
p 54
0
0
0
0
10h MICA Amp Ctl
Reserved
MICASEL
MICACFG
MICAGAIN4
p 55
0
0
0
0
11h MICB Amp Ctl
Reserved
MICBSEL
MICBCFG
MICBGAIN4
p 55
0
0
0
0
12h PGAA Vol, Misc ALCASRDIS ALCAZCDIS PGAAVOL5 PGAAVOL4
p 55
0
0
0
0
13h PGAB Vol, Misc ALCBSRDIS ALCBZCDIS PGABVOL5 PGABVOL4
p 55
0
0
0
0
14h Passthru A Vol PASSAVOL7 PASSAVOL6 PASSAVOL5 PASSAVOL4
p 57
0
0
0
0
15h Passthru B Vol PASSBVOL7 PASSBVOL6 PASSBVOL5 PASSBVOL4
p 57
0
0
0
0
16h ADCA Vol
ADCAVOL7 ADCAVOL6 ADCAVOL5 ADCAVOL4
p 57
0
0
0
0
17h ADCB Vol
ADCBVOL7 ADCBVOL6 ADCBVOL5 ADCBVOL4
p 57
0
0
0
0
18h ADCMIXA Vol AMIXAMUTE AMIXAVOL6 AMIXAVOL5 AMIXAVOL4
p 58
1
0
0
0
19h ADCMIXB Vol AMIXBMUTE AMIXBVOL6 AMIXBVOL5 AMIXBVOL4
p 58
1
0
0
0
1Ah PCMMIXA Vol PMIXAMUTE PMIXAVOL6 PMIXAVOL5 PMIXAVOL4
p 58
0
0
0
0
40
3
CHIPID0
0
PDN_PGAA
0
OVRDA
0
PDN_SPKB1
0
VIDEOCLK
0
DACDIF1
0
INV_SWCH
0
PGAASEL4
0
PGABSEL4
0
ANLGSFTB
0
HPFB_CF1
0
INV_ADCB
0
INV_PCMB
0
FREEZE
0
SPKB=A
0
MICAGAIN3
0
MICBGAIN3
0
PGAAVOL3
0
PGABVOL3
0
PASSAVOL3
0
PASSBVOL3
0
ADCAVOL3
0
ADCBVOL3
0
AMIXAVOL3
0
AMIXBVOL3
0
PMIXAVOL3
0
2
REVID2
x
PDN_ADCB
0
PDN_MICB
1
PDN_SPKB0
1
RATIO1
0
DACDIF0
0
BIASLVL2
0
PGAASEL3
0
PGABSEL3
0
ANLGZCB
1
HPFB_CF0
0
INV_ADCA
0
INV_PCMA
0
DEEMPH
0
SPKSWAP
MICAGAIN2
0
MICBGAIN2
0
PGAAVOL2
0
PGABVOL2
0
PASSAVOL2
0
PASSBVOL2
0
ADCAVOL2
0
ADCBVOL2
0
AMIXAVOL2
0
AMIXBVOL2
0
PMIXAVOL2
0
1
REVID1
x
PDN_ADCA
0
PDN_MICA
1
PDN_SPKA1
0
RATIO0
0
AWL1
0
BIASLVL1
0
PGAASEL2
0
PGABSEL2
0
ANLGSFTA
0
HPFA_CF1
0
ADCBMUTE
0
MSTBMUTE
0
DIGSFT
1
SPKMONO
0
MICAGAIN1
0
MICBGAIN1
0
PGAAVOL1
0
PGABVOL1
0
PASSAVOL1
0
PASSBVOL1
0
ADCAVOL1
0
ADCBVOL1
0
AMIXAVOL1
0
AMIXBVOL1
0
PMIXAVOL1
0
0
REVID0
x
PDN
1
PDN_BIAS
1
PDN_SPKA0
1
MCLKDIV2
0
AWL0
0
BIASLVL0
0
PGAASEL1
1
PGABSEL1
1
ANLGZCA
1
HPFA_CF0
0
ADCAMUTE
0
MSTAMUTE
0
DIGZC
0
MUTE50/50
0
MICAGAIN0
0
MICBGAIN0
0
PGAAVOL0
0
PGABVOL0
0
PASSAVOL0
0
PASSBVOL0
0
ADCAVOL0
0
ADCBVOL0
0
AMIXAVOL0
0
AMIXBVOL0
0
PMIXAVOL0
0
DS680F1
5/13/08
CS42L52
I²C Address: 1001010[R/W] - 10010100 = 0x94(Write); 10010101 = 0x95(Read)
Adr. Function
7
6
5
4
1Bh PCMMIXB Vol PMIXBMUTE PMIXBVOL6 PMIXBVOL5 PMIXBVOL4
p 58
0
0
0
0
1Ch BEEP Freq,
FREQ3
FREQ2
FREQ1
FREQ0
p 59 On Time
0
0
0
0
1Dh BEEP Vol,
OFFTIME2
OFFTIME1
OFFTIME0
BPVOL4
p 60 Off Time
0
0
0
0
1Eh BEEP,
BEEP1
BEEP0
BEEPMIXDIS TREB_CF1
p 61 Tone Cfg.
0
0
0
0
1Fh Tone Ctl
TREB3
TREB2
TREB1
TREB0
p 62
1
0
0
0
20h Master A Vol
MSTAVOL7 MSTAVOL6 MSTAVOL5
MSTAVOL4
p 63
0
0
0
0
21h Master B Vol
MSTBVOL7 MSTBVOL6 MSTBVOL5 MSTBVOL4
p 63
0
0
0
0
22h Headphone A
HPAVOL7
HPAVOL6
HPAVOL5
HPAVOL4
p 63 Volume
0
0
0
0
23h Headphone B
HPBVOL7
HPBVOL6
HPBVOL5
HPBVOL4
p 63 Volume
0
0
0
0
24h Speaker A
SPKAVOL7 SPKAVOL6 SPKAVOL5
SPKAVOL4
p 64 Volume
0
0
0
0
25h Speaker B
SPKBVOL7 SPKBVOL6 SPKBVOL5 SPKBVOL4
p 64 Volume
0
0
0
0
26h Channel Mixer PCMASWP1 PCMASWP0 PCMBSWP1 PCMBSWP0
p 64 & Swap
0
0
0
0
27h Limit Ctl 1,
LMAX2
LMAX1
LMAX0
CUSH2
p 65 Thresholds
0
0
0
0
28h Limit Ctl 2,
LIMIT
LIMIT_ALL LIMRRATE5 LIMRRATE4
p 66 Release Rate
0
1
1
1
29h Limiter Attack
Reserved
Reserved
LIMARATE5 LIMARATE4
p 67 Rate
1
1
0
0
2Ah ALC Ctl 1,
ALCB
ALCA
ALCARATE5 AALCRATE4
p 67 Attack Rate
0
0
0
0
2Bh ALC Release
Reserved
Reserved
ALCRRATE5 ALCRRATE4
p 68 Rate
0
0
1
1
2Ch ALC ThreshALCMAX2
ALCMAX1
ALCMAX0
ALCMIN2
p 68 olds
0
0
0
0
2Dh Noise Gate Ctl
NGALL
NG
NGBOOST
THRESH2
p 69
0
0
0
0
2Eh Overflow &
Reserved
SPCLKERR DSPBOVFL DSPAOVFL
p 70 Clock Status
0
0
0
0
2Fh Battery ComBATTCMP VPMONITOR Reserved
Reserved
p 71 pensation
0
0
0
0
30h VP Battery
VPLVL7
VPLVL6
VPLVL5
VPLVL4
p 72 Level
0
0
0
0
31h Speaker Status
Reserved
Reserved
SPKASHRT SPKBSHRT
p 72
0
0
0
0
32h Reserved
Reserved
Reserved
Reserved
Reserved
0
0
1
1
33h Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
34h Charge Pump
CHGFREQ3 CHGFREQ2 CHGFREQ1 CHGFREQ0
p 73 Frequency
0
1
0
1
DS680F1
3
PMIXBVOL3
0
ONTIME3
0
BPVOL3
0
TREB_CF0
0
BASS3
1
MSTAVOL3
0
MSTBVOL3
0
HPAVOL3
0
HPBVOL3
0
SPKAVOL3
0
SPKBVOL3
0
ADCASWP1
0
CUSH1
0
LIMRRATE3
1
LIMARATE3
0
ALCARATE3
0
ALCRRATE3
1
ALCMIN1
0
THRESH1
0
PCMAOVFL
0
VPREF3
0
VPLVL3
0
SPKR/HP
0
Reserved
1
Reserved
0
Reserved
1
2
PMIXBVOL2
0
ONTIME2
0
BPVOL2
0
BASS_CF1
0
BASS2
0
MSTAVOL2
0
MSTBVOL2
0
HPAVOL2
0
HPBVOL2
0
SPKAVOL2
0
SPKBVOL2
0
ADCASWP0
0
CUSH0
0
LIMRRATE2
1
LIMARATE2
0
ALCARATE2
0
ALCRRATE2
1
ALCMIN0
0
THRESH0
0
PCMBOVFL
0
VPREF2
0
VPLVL2
0
Reserved
0
Reserved
0
Reserved
0
Reserved
1
1
PMIXBVOL1
0
ONTIME1
0
BPVOL1
0
BASS_CF0
0
BASS1
0
MSTAVOL1
0
MSTBVOL1
0
HPAVOL1
0
HPBVOL1
0
SPKAVOL1
0
SPKBVOL1
0
ADCBSWP1
0
LIMSRDIS
0
LIMRRATE1
1
LIMARATE1
0
ALCARATE1
0
ALCRRATE1
1
Reserved
0
NGDELAY1
0
ADCAOVFL
0
VPREF1
0
VPLVL1
0
Reserved
0
Reserved
1
Reserved
0
Reserved
1
0
PMIXBVOL0
0
ONTIME0
0
BPVOL0
0
TC_EN
0
BASS0
0
MSTAVOL0
0
MSTBVOL0
0
HPAVOL0
0
HPBVOL0
0
SPKAVOL0
0
SPKBVOL0
0
ADCBSWP0
0
LIMZCDIS
0
LIMRRATE0
1
LIMARATE0
0
ALCARATE0
0
ALCRRATE0
1
Reserved
0
NGDELAY0
0
ADCBOVFL
0
VPREF0
0
VPLVL0
0
Reserved
0
Reserved
1
Reserved
0
Reserved
1
41
5/13/08
CS42L52
6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are
read only. See the following bit definition tables for bit assignment information. The default state of each bit after a
power-up sequence or reset is listed in each bit description. Unless otherwise specified, all “Reserved” bits must
maintain their default value.
6.1
Chip I.D. and Revision Register (Address 01h) (Read Only)
7
CHIPID4
6.1.1
6
CHIPID3
5
CHIPID2
4
CHIPID1
3
CHIPID0
2
REVID2
1
REVID1
0
REVID0
3
PDN_PGAA
2
PDN_ADCB
1
PDN_ADCA
0
PDN
Chip I.D. (Read Only)
I.D. code for the CS42L52.
6.1.2
CHIPID[4:0]
Device
11100
CS42L52
Chip Revision (Read Only)
CS42L52 revision level.
6.2
REVID[2:0]
Revision Level
000
A0
001
A1
010
B0
011
B1
Power Control 1 (Address 02h)
7
PDN_CHRG
6.2.1
6
Reserved
5
Reserved
4
PDN_PGAB
Power Down ADC Charge Pump
Configures the power state of the ADC charge pump.
6.2.2
PDN_CHRG
ADC Charge Pump Status
0
Powered Up
1
Powered Down
Power Down PGAx
Configures the power state of PGA channel x.
PDN_PGAx
PGA Status
0
Powered Up (ONLY when the ADC or the analog passthru is used)
1
Powered Down
Application
“Analog In to Analog Out Passthrough” on page 32
Notes:
1. The CS42L52 employs a clever scheme for controlling the power to the PGA when PASSTHRU
(“Passthrough Analog” on page 52) is enabled. Refer to the referenced application for more information.
2. This bit should be used in conjunction with ADCxSEL and PGAxSEL bits to determine the analog
42
DS680F1
5/13/08
CS42L52
input path. The PGAxSEL bits may be used to isolate the input signal(s) from the PGA outputs. When
the PGA is powered down, no input should be selected. Refer to “ADC Input Select” on page 48 and
“PGA Input Mapping” on page 49 for the required settings.
6.2.3
Power Down ADCx
Configures the power state of ADC channel x.
PDN_ADCx
ADC Status
0
Powered Up
1
Powered Down
Application
“Analog In to Analog Out Passthrough” on page 32
Notes:
1. The CS42L52 employs a clever scheme for controlling the power to the ADC when PASSTHRU
(“Passthrough Analog” on page 52) and PDN_OVRD (“Power Down ADC Override” on page 43) are
enabled. Refer to the referenced application.
6.2.4
Power Down
Configures the power state of the entire CODEC.
6.3
PDN
CODEC Status
0
Powered Up
1
Powered Down
Power Control 2 (Address 03h)
7
Reserved
6.3.1
6
Reserved
5
Reserved
4
OVRDB
3
OVRDA
2
PDN_MICB
1
PDN_MICA
0
PDN_BIAS
Power Down ADC Override
Configures an override of the power down control for ADCx.
OVRDx
6.3.2
PDN_ADC Override
0
Disable
1
Enable
Application
“Analog In to Analog Out Passthrough” on page 32
Power Down MICx
Configures the power state of the microphone pre-amplifier for channel x.
6.3.3
PDN_MICx
MIC Pre-Amp Status
0
Powered Up
1
Powered Down
Application
“MIC Inputs” on page 27
Power Down MIC Bias
Configures the power state of the microphone bias circuit.
DS680F1
PDN_BIAS
MIC Bias Status
0
Powered Up
1
Powered Down
43
5/13/08
CS42L52
6.4
Power Control 3 (Address 04h)
7
PDN_HPB1
6.4.1
6
PDN_HPB0
5
PDN_HPA1
4
PDN_HPA0
3
PDN_SPKB1
2
PDN_SPKB0
1
PDN_SPKA1
0
PDN_SPKA0
Headphone Power Control
Configures how the SPKR/HP pin, 31, controls the power for the headphone amplifier.
6.4.2
PDN_HPx[1:0]
Headphone Status
00
Headphone channel is ON when the SPKR/HP pin, 31, is LO.
Headphone channel is OFF when the SPKR/HP pin, 31, is HI.
01
Headphone channel is ON when the SPKR/HP pin, 31, is HI.
Headphone channel is OFF when the SPKR/HP pin, 31, is LO.
10
Headphone channel is always ON.
11
Headphone channel is always OFF.
Speaker Power Control
Configures how the SPKR/HP pin, 31, controls the power for the speaker amplifier.
6.5
PDN_SPKx[1:0]
Speaker Status
00
Speaker channel is ON when the SPKR/HP pin, 31, is LO.
Speaker channel is OFF when the SPKR/HP pin, 31, is HI.
01
Speaker channel is ON when the SPKR/HP pin, 31, is HI.
Speaker channel is OFF when the SPKR/HP pin, 31, is LO.
10
Speaker channel is always ON.
11
Speaker channel is always OFF.
Clocking Control (Address 05h)
7
AUTO
6.5.1
6
SPEED1
5
SPEED0
4
32k_GROUP
3
VIDEOCLK
2
RATIO1
1
RATIO0
0
MCLKDIV2
Auto-Detect
Configures the auto-detect circuitry for detecting the speed mode of the CODEC when operating as a
slave.
AUTO
Auto-detection of Speed Mode
0
Disabled
1
Enabled
Application:
“Serial Port Clocking” on page 34
Notes:
1. The SPEED[1:0] bits are ignored and speed is determined by the MCLK/LRCK ratio.
2. When AUTO is disabled and the CODEC operates in master mode, the MCLKDIV2 bit is ignored.
3. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
(“32kHz Sample Rate Group” on page 45) and/or the VIDEOCLK bit (“27 MHz Video Clock” on
page 45) and RATIO[1:0] bits (“Internal MCLK/LRCK Ratio” on page 45). Low sample rates may also
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
44
DS680F1
5/13/08
CS42L52
6.5.2
Speed Mode
Configures the speed mode of the CODEC in slave mode and sets the appropriate MCLK divide ratio for
LRCK and SCLK in master mode.
SPEED[1:0]
Slave Mode
Master Mode
Serial Port Speed
MCLK/LRCK Ratio
SCLK/LRCK Ratio
00
Double-Speed Mode (DSM - 50 kHz -100 kHz Fs)
512
64
01
Single-Speed Mode (SSM - 4 kHz -50 kHz Fs)
256
64
10
Half-Speed Mode (HSM - 12.5kHz -25 kHz Fs)
128
64
11
Quarter-Speed Mode (QSM - 4 kHz -12.5 kHz Fs)
128
64
Application:
“Serial Port Clocking” on page 34
Notes:
1. Slave/Master Mode is determined by the M/S bit in “Master/Slave Mode” on page 46.
2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
(“32kHz Sample Rate Group” on page 45) and/or the VIDEOCLK bit (“27 MHz Video Clock” on
page 45) and RATIO[1:0] bits (“Internal MCLK/LRCK Ratio” on page 45). Low sample rates may also
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
3. These bits are ignored when the AUTO bit (“Auto-Detect” on page 44) is enabled.
6.5.3
32kHz Sample Rate Group
Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.
32kGROUP
6.5.4
8 kHz, 16 kHz or 32 kHz sample rate?
0
No
1
Yes
Application:
“Serial Port Clocking” on page 34
27 MHz Video Clock
Specifies whether or not the external MCLK frequency is 27 MHz
VIDEOCLK
6.5.5
27 MHz MCLK?
0
No
1
Yes
Application:
“Serial Port Clocking” on page 34
Internal MCLK/LRCK Ratio
Configures the internal MCLK/LRCK ratio.
RATIO[1:0]
DS680F1
Internal MCLK Cycles per LRCK
SCLK/LRCK Ratio in Master Mode
00
128
64
01
125
62
10
132
66
11
136
68
Application:
“Serial Port Clocking” on page 34
45
5/13/08
CS42L52
6.5.6
MCLK Divide By 2
Divides the input MCLK by 2 prior to all internal circuitry.
MCLKDIV2
No divide
1
Divided by 2
Application:
“Serial Port Clocking” on page 34
Note:
6.6
MCLK signal into CODEC
0
In slave mode, this bit is ignored when the AUTO bit (“Auto-Detect” on page 44) is disabled.
Interface Control 1 (Address 06h)
7
M/S
6.6.1
6
INV_SCLK
5
ADCDIF
4
DSP
3
DACDIF1
2
DACDIF0
1
AWL1
0
AWL0
Master/Slave Mode
Configures the serial port I/O clocking.
M/S
6.6.2
Serial Port Clocks
0
Slave (input ONLY)
1
Master (output ONLY)
SCLK Polarity
Configures the polarity of the SCLK signal.
INV_SCLK
6.6.3
SCLK Polarity
0
Not Inverted
1
Inverted
ADC Interface Format
Configures the digital interface format for data on SDOUT.
6.6.4
ADCDIF
ADC Interface Format
0
Left Justified
1
I²S
Application:
“Digital Interface Formats” on page 36
DSP Mode
Configures a data-packed interface format for both the ADC and DAC.
DSP
DSP Mode
0
Disabled
1
Enabled
Application:
“DSP Mode” on page 36
Notes:
1. Select the audio word length using the AWL[1:0] bits (“Audio Word Length” on page 47).
2. The interface format for both the ADC and the DAC must be set to “Left-Justified” when DSP Mode
is enabled.
46
DS680F1
5/13/08
CS42L52
6.6.5
DAC Interface Format
Configures the digital interface format for data on SDIN.
DACDIF[1:0]
DAC Interface Format
00
Left Justified, up to 24-bit data
01
I²S, up to 24-bit data
10
Right Justified
11
Reserved
Application:
“Digital Interface Formats” on page 36
Note: Select the audio word length for Right Justified using the AWL[1:0] bits (“Audio Word Length” on
page 47).
6.6.6
Audio Word Length
Configures the audio sample word length used for the data into SDIN and out of SDOUT.
Audio Word Length
AWL[1:0]
DSP Mode
Right Justified (DAC ONLY)
00
32-bit data
24-bit data
01
24-bit data
20-bit data
10
20-bit data
18-bit data
11
16-bit data
16-bit data
Application:
“DSP Mode” on page 36
Note: When the internal MCLK/LRCK ratio is set to 125 in master mode, the 32-bit data width option
for DSP Mode is not valid unless SCLK=MCLK.
6.7
Interface Control 2 (Address 07h)
7
Reserved
6.7.1
6
SCLK=MCLK
5
DIGLOOP
4
3ST_SP
3
INV_SWCH
2
BIASLVL2
1
BIASLVL1
0
BIASLVL0
SCLK equals MCLK
Configures the SCLK signal source for master mode.
SCLK=MCLK
Re-timed signal, synchronously derived from MCLK
1
Non-retimed, MCLK signal
Note:
6.7.2
Output SCLK
0
This bit is only valid for MCLK = 12.0000 MHz.
SDOUT to SDIN Digital Loopback
Configures an internal loops the signal on the SDOUT pin to SDIN.
DS680F1
DIGLOOP
Internal Loopback
0
Disabled; SDOUT internally disconnected from SDIN
1
Enabled; SDOUT internally connected to SDIN
47
5/13/08
CS42L52
6.7.3
Tri-State Serial Port Interface
Determines the state of the serial port drivers.
3ST_SP
Serial Port Status
Slave Mode
Master Mode
0
Serial Port clocks are inputs and SDOUT is output
Serial Port clocks and SDOUT are outputs
1
Serial Port clocks are inputs and SDOUT is HI-Z
Serial Port clocks and SDOUT are HI-Z
Notes:
1. Slave/Master Mode is determined by the M/S bit in “Master/Slave Mode” on page 46.
2. When the serial port is tri-stated in master mode, the ADC and DAC serial ports are clocked internally.
6.7.4
Speaker/Headphone Switch Invert
Determines the control signal polarity of the SPK/HP_SW pin.
6.7.5
INV_SWCH
SPK/HP_SW pin 6 Control
0
Not inverted
1
Inverted
MIC Bias Level
Sets the output voltage level on the MICBIAS output pin.
6.8
BIASLVL[2:0]
Output Bias Level
000
0.5 x VA
001
0.6 x VA
010
0.7 x VA
011
0.8 x VA
100
0.83 x VA
101
0.91 x VA
110
Reserved
111
Reserved
Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h)
7
ADCASEL2
6.8.1
6
ADCASEL1
5
ADCASEL0
4
PGAASEL5
3
PGAASEL4
2
PGAASEL3
1
PGAASEL2
0
PGAASEL1
ADC Input Select
Selects the specified analog input signal into ADCx.
ADCxSEL[2:0]
48
Selected Input to ADCx
000
AIN1x
001
AIN2x
010
AIN3x
011
AIN4x
100
PGAx - Use PGAxSEL bits (“PGA Input Mapping” on page 49) to select input channels
101
Reserved
110
Reserved
111
Reserved
Application:
“Analog Inputs” on page 26
DS680F1
5/13/08
CS42L52
6.8.2
PGA Input Mapping
Selects one or sums/mixes the analog input signal into the PGA. Each bit of the PGAx_SEL[5:1] word
corresponds to individual channels (i.e. PGAx_SEL1 selects AIN1x, PGAx_SEL2 selects AIN2x, etc.).
PGAxSEL[5:1]
Selected Input to PGAx (Examples)
00000
No inputs selected
00001
AIN1x
00010
AIN2x
00100
AIN3x
01000
AIN4x
10000
MICx; for single-ended MIC inputs, use MICxSEL (“MIC x Select” on page 55) to select MIC 1 or MIC 2; for
differential MIC inputs, enable MICxCFG (“MICx Configuration” on page 55)
10001
MICx + AIN1x
10011
MICx + AIN1x + AIN2x
Application:
“Analog Inputs” on page 26
Note: Table does not show all possible combinations.
6.9
Analog & HPF Control (Address 0Ah)
7
HPFB
6.9.1
6
HPFRZB
5
HPFA
4
HPFRZA
3
ANLGSFTB
2
ANLGZCB
1
ANLGSFTA
0
ANLGZCA
ADCx High-Pass Filter
Configures the internal high-pass filter after ADCx.
6.9.2
HPFx
High Pass Filter Status
0
Disabled
1
Enabled
ADCx High-Pass Filter Freeze
Configures the high pass filter’s digital DC subtraction and/or calibration after ADCx.
6.9.3
HPFRZx
High Pass Filter Digital Subtraction
0
Continuous DC Subtraction
1
Frozen DC Subtraction
Ch. x Analog Soft Ramp
Configures an incremental volume ramp from the current level to the new level at the specified rate.
ANLGSFTx
6.9.4
Volume Changes
Affected Analog Volume Controls
0
Do not occur with a soft ramp
1
Occur with a soft ramp
MICxGAIN[4:0] (“MICx Gain” on page 55), PGAxVOL[5:0] (“PGAx Volume”
on page 56), and PASSxVOL[7:0] (“Passthrough x Volume” on page 57)
Ramp Rate:
1/2 dB every 16 LRCK cycles
Ch. x Analog Zero Cross
Configures when the signal level changes occur for the analog volume controls.
ANLGZCx
Volume Changes
0
Do not occur on a zero crossing
1
Occur on a zero crossing
Affected Analog Volume Controls
MICxGAIN[4:0] (“MICx Gain” on page 55), PGAxVOL[5:0] (“PGAx Volume”
on page 56), and PASSxVOL[7:0] (“Passthrough x Volume” on page 57)
Note: If the signal does not encounter a zero crossing, the requested volume change will occur after a
timeout period of 1024 sample periods (approximately 10.7 ms at 48 kHz sample rate).
DS680F1
49
5/13/08
CS42L52
6.10
ADC HPF Corner Frequency (Address 0Bh)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
HPFB_CF1
2
HPFB_CF0
1
HPFA_CF1
0
HPFA_CF0
6.10.1 HPF x Corner Frequency
Sets the corner frequency (-3 dB point) for the internal High-Pass Filter (HPF).
6.11
HPFx_CF[1:0]
HPF Corner Frequency Setting (Fs=48 kHz)
00
Normal setting as specified in “ADC Digital Filter Characteristics” on page 14
01
119 Hz
10
236 Hz
11
464 Hz
Misc. ADC Control (Address 0Ch)
7
ADCB=A
6.11.1
6
DIGMUX
5
DIGSUM1
4
DIGSUM0
3
INV_ADCB
2
INV_ADCA
1
ADCBMUTE
0
ADCAMUTE
Analog Front-End Volume Setting B=A
Configures independent or ganged volume control and muting of the analog front end.
6.11.2
ADCB=A
Single Volume Control
Affected Volume Controls
0
Disabled
1
Enabled
ADCxVOL[7:0] (“ADCx Volume” on page 57),
ADCxMUTE (“ADC Mute” on page 51),
ALC and Limiter Attack/Release (page 66 to page 68)
MICxGAIN[4:0] (“MICx Gain” on page 55),
PGAxVOL[5:0] (“PGAx Volume” on page 56),
PASSxVOL[7:0] (“Passthrough x Volume” on page 57)
Digital MUX
Selects the signal source for the ADC serial port
DIGMUX
6.11.3
SDOUT Signal Source
0
ADC
1
DSP
Digital Sum
Configures a mix/swap of ADCA and ADCB.
DIGSUM[1:0]
50
Serial Output Signal
Left Channel
Right Channel
00
ADCA
ADCB
01
(ADCA + ADCB)/2
(ADCA + ADCB)/2
10
(ADCA - ADCB)/2
(ADCA - ADCB)/2
11
ADCB
ADCA
DS680F1
5/13/08
CS42L52
6.11.4
Invert ADC Signal Polarity
Configures the polarity of the ADC signal.
6.11.5
INV_ADCx
ADC Signal Polarity
0
Not Inverted
1
Inverted
ADC Mute
Configures a digital mute on ADC channel x.
ADCxMUTE
0
Disabled
1
Enabled
Note:
6.12
ADC Mute
When the ADCxMUTE bit is enabled, the PGA will automatically apply 6 dB of attenuation.
Playback Control 1 (Address 0Dh)
7
HPGAIN2
6
HPGAIN1
5
HPGAIN0
4
PLYBCKB=A
3
INV_PCMB
2
INV_PCMA
1
MSTBMUTE
0
MSTAMUTE
6.12.1 Headphone Analog Gain
Selects the gain multiplier for the headphone/line outputs.
HPGAIN[2:0]
Headphone/Line Gain Setting (G)
000
0.3959
001
0.4571
010
0.5111
011
0.6047
100
0.7099
101
0.8399
110
1.000
111
1.1430
Note: Refer to “Line Output Voltage Level Characteristics” on page 20 and “Headphone Output Power
Characteristics” on page 19.
6.12.2 Playback Volume Setting B=A
Configures independent or ganged volume control of all playback channels.
DS680F1
PLYBCKB=A
Single Volume Control
Affected Volume Controls
0
Disabled
1
Enabled
HPxMUTE (“Playback Control 2 (Address 0Fh)” on page 54),
AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),
PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),
MSTxVOL[7:0] (“Master Volume Control” on page 63),
HPxVOL[7:0] (“Headphone Volume Control” on page 63)
51
5/13/08
CS42L52
6.12.3 Invert PCM Signal Polarity
Configures the polarity of the digital input signal.
INV_PCMx
PCM Signal Polarity
0
Not Inverted
1
Inverted
6.12.4 Master Playback Mute
Configures a digital mute on the master volume control for channel x.
MSTxMUTE
Master Mute
0
Not Inverted
1
Inverted
Note: The muting function is affected by the DIGSFT (“Digital Soft Ramp” on page 53) and DIGZC
(“Digital Zero Cross” on page 53) bits.
6.13
Miscellaneous Controls (Address 0Eh)
7
6
5
4
PASSTHRUB PASSTHRUA PASSBMUTE PASSAMUTE
3
FREEZE
2
DEEMPH
1
DIGSFT
0
DIGZC
6.13.1 Passthrough Analog
Configures an analog passthrough from the PGA inputs to the headphone/line outputs.
PASSTHRUx
Analog In Routed to HP/Line Output
0
Disabled
1
Enabled
Notes:
1. The Passthrough volume control is realized using a combination of the PGA volume control settings
(“PGAx Volume” on page 56) and the headphone amplifier volume control settings (hidden). When
passthrough is enabled and the PGA to ADC path is selected, the signal seen by the ADC will change
depending on the passthrough volume setting.
6.13.2 Passthrough Mute
Configures an analog mute on the channel x analog in to analog out passthrough.
PASSxMUTE
Passthrough Mute
0
Disabled
1
Enabled
6.13.3 Freeze Registers
Configures a hold on all register settings.
52
FREEZE
Control Port Status
0
Register changes take effect immediately
1
Modifications may be made to all control port registers without the changes taking effect until after the
FREEZE is disabled.
DS680F1
5/13/08
CS42L52
6.13.4 HP/Speaker De-emphasis
Configures a 15µs/50µs digital de-emphasis filter response on the headphone/line and speaker outputs.
DEEMPHASIS
Control Port Status
0
Disabled
1
Enabled
6.13.5 Digital Soft Ramp
Configures an incremental volume ramp from the current level to the new level at the specified rate.
DIGSFT
Volume Changes
Affected Digital Volume Controls
0
Do not occur with a soft ramp
1
Occur with a soft ramp
MSTxMUTE (“Master Playback Mute” on page 52),
HPxMUTE, SPKxMUTE (“Playback Control 2 (Address 0Fh)” on page 54),
ADCxVOL[7:0] (“ADCx Volume” on page 57),
AMIXxMUTE, AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),
PMIXxMUTE, PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),
MSTxVOL[7:0] (“Master Volume Control” on page 63),
HPxVOL[7:0] (“Headphone Volume Control” on page 63),
SPKxVOL[7:0] (“Speaker Volume Control” on page 64),
ALC and Limiter Attack/Release (page 66 to page 68)
Beep Volume (“Beep Volume” on page 61)
Ramp Rate:
1/8 dB every LRCK cycle
Notes:
1. When the DIGSFT bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed to
occur with a soft ramp only when bits 7 and 6 in register 29h are set to ‘00’b.
6.13.6 Digital Zero Cross
Configures when the signal level changes occur for the digital volume controls.
DIGZC
Volume Changes
Affected Digital Volume Controls
0
Do not occur on a zero crossing
1
Occur on a zero crossing
MSTxMUTE (“Master Playback Mute” on page 52),
AMIXxMUTE, AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),
PMIXxMUTE, PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),
MSTxVOL[7:0] (“Master Volume Control” on page 63),
ALC and Limiter Attack/Release (page 66 to page 68)
Beep Volume (“Beep Volume” on page 61)
Notes:
1. If the signal does not encounter a zero crossing, the requested volume change will occur after a
timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate).
2. The zero cross function is independently monitored and implemented for each channel.
3. The DIS_LIMSFT bit (“Limiter Soft Ramp Disable” on page 65) is ignored when zero cross is enabled.
4. When the DIGSFT bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed to
occur on a zero crossing only when bits 7 and 6 in register 29h are set to ‘00’b.
DS680F1
53
5/13/08
CS42L52
6.14
Playback Control 2 (Address 0Fh)
7
HPBMUTE
6
HPAMUTE
5
SPKBMUTE
4
SPKAMUTE
3
SPKB=A
2
SPKSWAP
1
SPKMONO
0
MUTE50/50
6.14.1 Headphone Mute
Configures a digital mute on headphone channel x.
HPxMUTE
Headphone Mute
0
Disabled
1
Enabled
6.14.2 Speaker Mute
Configures a digital mute on speaker channel x.
SPKxMUTE
Speaker Mute
0
Disabled
1
Enabled
6.14.3 Speaker Volume Setting B=A
Configures independent or ganged volume control of the speaker output.
SPKB=A
Single Volume Control
Affected Volume Controls
0
Disabled
1
Enabled
SPKxMUTE (“Speaker Mute” on page 54),
SPKxVOL[7:0] (“Speaker Volume Control” on page 64)
6.14.4 Speaker Channel Swap
Configures a channel swap on the speaker channels.
SPKSWAP
Speaker Output
0
Channel A
1
Channel B
Application:
“Mono Speaker Output Configuration” on page 33
6.14.5 Speaker MONO Control
Configures a parallel full-bridge output for the speaker channels.
SPKMONO
Parallel Full Bridge Output
0
Disabled
1
Enabled
Application:
“Mono Speaker Output Configuration” on page 33
6.14.6 Speaker Mute 50/50 Control
Configures how the speaker channels mute.
54
MUTE50/50
Speaker Mute 50/50
0
Disabled; The PWM amplifiers outputs modulated silence when SPKxMUTE is enabled.
1
Enabled; The PWM amplifiers switch at an exact 50%-duty-cycle signal (not modulated) when SPKxMUTE is
enabled.
DS680F1
5/13/08
CS42L52
6.15
MICx Amp Control:MIC A (Address 10h) & MIC B (Address 11h)
7
Reserved
6
MICxSEL
5
MICxCFG
4
MICxGAIN4
3
MICxGAIN3
2
MICxGAIN2
1
MICxGAIN1
0
MICxGAIN0
1
PGAxVOL1
0
PGAxVOL0
6.15.1 MIC x Select
Selects one of two single-ended MIC inputs on channel x.
MICxSEL
MIC x Selection
0
MIC 1x
1
MIC 2x
Application:
“MIC Inputs” on page 27
6.15.2 MICx Configuration
Configures the input topology for MICx.
MICxCFG
MIC Input Topology
0
Single-Ended
1
Differential
Application:
“MIC Inputs” on page 27
6.15.3 MICx Gain
Sets the gain of the microphone pre-amplifier.
6.16
MICxGAIN[4:0]
Gain
1 1111
32 dB
...
...
1 0000
32 dB
0 1111
30.5 dB
0 1110
30 dB
...
...
0 0000
16 dB
Step Size:
1 dB (unless otherwise noted)
Application:
“MIC Inputs” on page 27
PGAx Vol. & ALCx Transition Ctl.:
ALC, PGA A (Address 12h) & ALC, PGA B (Address 13h)
7
ALCxSRDIS
6
ALCxZCDIS
5
PGAxVOL5
4
PGAxVOL4
3
PGAxVOL3
2
PGAxVOL2
6.16.1 ALCx Soft Ramp Disable
Configures an override of the analog soft ramp setting.
ALCxSRDIS
DS680F1
ALC Soft Ramp Disable
0
OFF; ALC Attack Rate is dictated by the ANLGSFT (“Ch. x Analog Soft Ramp” on page 49) setting
1
ON; ALC volume changes take effect in one step, regardless of the ANLGSFT setting.
Application:
“Automatic Level Control (ALC)” on page 27
55
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CS42L52
6.16.2 ALCx Zero Cross Disable
Configures an override of the analog zero cross setting.
ALCxZCDIS
ALC Zero Cross Disable
0
OFF; ALC Attack Rate is dictated by the ANLGZC (“Ch. x Analog Zero Cross” on page 49) setting
1
ON; ALC volume changes take effect at any time, regardless of the ANLGZC setting.
Application:
“Automatic Level Control (ALC)” on page 27
6.16.3 PGAx Volume
Sets the volume/gain of the Programmable Gain Amplifier (PGA).
PGAxVOL[5:0]
Volume
01 1111
12 dB
...
...
01 1000
12 dB
...
...
00 0001
+0.5 dB
00 0000
0 dB
11 1111
-0.5 dB
...
...
10 1000
-6.0 dB
...
...
10 0000
-6.0 dB
Step Size:
0.5 dB
Note: The PGAxVOL bits are ignored when the PASSTHRUx bit (“Passthrough Analog” on page 52) is
enabled.
56
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6.17
Passthrough x Volume: PASSAVOL (Address 14h) & PASSBVOL (Address 15h)
7
PASSxVOL7
6
PASSxVOL6
5
PASSxVOL5
4
PASSxVOL4
3
PASSxVOL3
2
PASSxVOL2
1
PASSxVOL1
0
PASSxVOL0
6.17.1 Passthrough x Volume
Sets the volume/gain of the signal routed from the PGA to the headphone/line output.
PASSxVOL[7:0]
Gain
0111 1111
12 dB
...
...
0001 1000
12 dB
...
...
0000 0001
+0.5 dB
0000 0000
0 dB
11111 1111
-0.5 dB
...
...
1000 1000
-60.0 dB
...
...
1000 0000
-60.0 dB
Step Size:
0.5 dB (approximate)
Application:
“Analog In to Analog Out Passthrough” on page 32
Notes:
1. This register is ignored when the PASSTHRUx bit (“Passthrough Analog” on page 52) is disabled.
2. The step size may deviate from 0.5 dB at settings below -40 dB. Code settings 0x95, 0xA1, 0xAD,
and 0xB9 are not guaranteed to be monotonic.
6.18
ADCx Volume Control: ADCAVOL (Address 16h) & ADCBVOL (Address 17h)
7
ADCAVOL7
6
ADCAVOL6
5
ADCAVOL5
4
ADCAVOL4
3
ADCAVOL3
2
ADCAVOL2
1
ADCAVOL1
0
ADCAVOL0
6.18.1 ADCx Volume
Sets the volume of the ADC signal out the serial data output (SDOUT).
DS680F1
ADCxVOL[7:0]
Volume
0111 1111
24 dB
...
...
0001 1000
24 dB
...
...
0000 0000
0 dB
1111 1111
-1.0 dB
1111 1110
-2.0 dB
...
...
1010 0000
-96.0 dB
...
...
1000 0000
-96.0 dB
Step Size:
1.0 dB
57
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6.19
ADCx Mixer Volume: ADCA (Address 18h) & ADCB (Address 19h)
7
AMIXxMUTE
6
AMIXxVOL6
5
AMIXxVOL5
4
AMIXxVOL4
3
AMIXxVOL3
2
AMIXxVOL2
1
AMIXxVOL1
0
AMIXxVOL0
6.19.1 ADC Mixer Channel x Mute
Configures a digital mute on the ADC mix in the DSP.
AMIXxMUTE
ADC Mixer Mute
0
Disabled
1
Enabled
6.19.2 ADC Mixer Channel x Volume
Sets the volume/gain of the ADC mix in the DSP.
6.20
AMIXxVOL[6:0]
Volume
001 1000
+12.0 dB
...
...
000 0001
+0.5 dB
000 0000
0 dB
111 1111
-0.5 dB
...
...
001 1001
-51.5 dB
Step Size:
0.5 dB
PCMx Mixer Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh)
7
PMIXxMUTE
6
PMIXxVOL6
5
PMIXxVOL5
4
PMIXxVOL4
3
PMIXxVOL3
2
PMIXxVOL2
1
PMIXxVOL1
0
PMIXxVOL0
6.20.1 PCM Mixer Channel x Mute
Configures a digital mute on the PCM mix from the serial data input (SDIN) to the DSP.
PMIXxMUTE
PCM Mixer Mute
0
Disabled
1
Enabled
6.20.2 PCM Mixer Channel x Volume
Sets the volume/gain of the PCM mix from the serial data input (SDIN) to the DSP.
58
PMIXxVOL[6:0]
Volume
001 1000
+12.0 dB
...
...
000 0001
+0.5 dB
000 0000
0 dB
111 1111
-0.5 dB
...
...
001 1001
-51.5 dB
Step Size:
0.5 dB
DS680F1
5/13/08
CS42L52
6.21
Beep Frequency & On Time (Address 1Ch)
7
FREQ3
6
FREQ2
5
FREQ1
4
FREQ0
3
ONTIME3
2
ONTIME2
1
ONTIME1
0
ONTIME0
6.21.1 Beep Frequency
Sets the frequency of the beep signal.
FREQ[3:0]
Frequency (Fs = 12, 24, 48 or 96 kHz)
Pitch
0000
260.87 Hz
C4
0001
521.74 Hz
C5
0010
585.37 Hz
D5
0011
666.67 Hz
E5
0100
705.88 Hz
F5
0101
774.19 Hz
G5
0110
888.89 Hz
A5
0111
1000.00 Hz
B5
1000
1043.48 Hz
C6
1001
1200.00 Hz
D6
1010
1333.33 Hz
E6
1011
1411.76 Hz
F6
1100
1600.00 Hz
G6
1101
1714.29 Hz
A6
1110
2000.00 Hz
B6
1111
2181.82 Hz
C7
Application:
“Beep Generator” on page 30
Notes:
1. This setting must not change when BEEP is enabled.
2. Beep frequency will scale directly with sample rate, Fs, but is fixed at the nominal Fs within each
speed mode.
DS680F1
59
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CS42L52
6.21.2 Beep On Time
Sets the on duration of the beep signal.
ONTIME[3:0]
On Time (Fs = 12, 24, 48 or 96 kHz)
0000
~86 ms
0001
~430 ms
0010
~780 ms
0011
~1.20 s
0100
~1.50 s
0101
~1.80 s
0110
~2.20 s
0111
~2.50 s
1000
~2.80 s
1001
~3.20 s
1010
~3.50 s
1011
~3.80 s
1100
~4.20 s
1101
~4.50 s
1110
~4.80 s
1111
~5.20 s
Application:
“Beep Generator” on page 30
Notes:
1. This setting must not change when BEEP is enabled.
2. Beep on time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed
mode.
6.22
Beep Volume & Off Time (Address 1Dh)
7
OFFTIME2
6
OFFTIME1
5
OFFTIME0
4
BPVOL4
3
BPVOL3
2
BPVOL2
1
BPVOL1
0
BPVOL0
6.22.1 Beep Off Time
Sets the off duration of the beep signal.
OFFTIME[2:0]
Off Time (Fs = 48 or 96 kHz)
000
~1.23 s
001
~2.58 s
010
~3.90 s
011
~5.20 s
100
~6.60 s
101
~8.05 s
110
~9.35 s
111
~10.80 s
Application:
“Beep Generator” on page 30
Notes:
1. This setting must not change when BEEP is enabled.
2. Beep off time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed
mode.
60
DS680F1
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CS42L52
6.22.2 Beep Volume
Sets the volume of the beep signal.
BEEPVOL[4:0]
Gain
00110
+6.0 dB
···
···
00000
-6 dB
11111
-8 dB
11110
-10 dB
···
···
00111
-56 dB
Step Size:
2 dB
Application:
“Beep Generator” on page 30
Note:
6.23
This setting must not change when BEEP is enabled.
Beep & Tone Configuration (Address 1Eh)
7
BEEP1
6
BEEP0
5
BEEPMIXDIS
4
TREBCF1
3
TREBCF0
2
BASSCF1
1
BASSCF0
0
TCEN
6.23.1 Beep Configuration
Configures a beep mixed with the HP/Line and SPK output.
BEEP[1:0]
Beep Occurrence
00
Off
01
Single
10
Multiple
11
Continuous
Application:
“Beep Generator” on page 30
Notes:
1. When used in analog pass-through mode, the output alternates between the signal from the PGA and
the beep signal. The beep signal does not mix with the analog signal from the PGA.
2. Re-engaging the beep before it has completed its initial cycle will cause the beep signal to remain ON
for the maximum ONTIME duration.
6.23.2 Beep Mix Disable
Configures how the beep mixes with the serial data input.
BEEPMIXDIS
Beep Output to HP/Line and Speaker
0
Mix Enabled; The beep signal mixes with the digital signal from the serial data input.
1
Mix Disabled; The output alternates between the signal from the serial data input and the beep signal. The
beep signal does not mix with the digital signal from the serial data input.
Application:
“Beep Generator” on page 30
Note:
DS680F1
This setting must not change when BEEP is enabled.
61
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6.23.3 Treble Corner Frequency
Sets the corner frequency (-3 dB point) for the treble shelving filter.
TREBCF[1:0]
Treble Corner Frequency Setting
00
5 kHz
01
7 kHz
10
10 kHz
11
15 kHz
6.23.4 Bass Corner Frequency
Sets the corner frequency (-3 dB point) for the bass shelving filter.
BASSCF[1:0]
Bass Corner Frequency Setting
00
50 Hz
01
100 Hz
10
200 Hz
11
250 Hz
6.23.5 Tone Control Enable
Configures the treble and bass activation.
6.24
TCEN
Bass and Treble Control
0
Disabled
1
Enabled
Application:
“Beep Generator” on page 30
Tone Control (Address 1Fh)
7
TREB3
6
TREB2
5
TREB1
4
TREB0
3
BASS3
2
BASS2
1
BASS1
0
BASS0
6.24.1 Treble Gain
Sets the gain of the treble shelving filter.
62
TREB[3:0]
Gain Setting
0000
+12.0 dB
···
···
0111
+1.5 dB
1000
0 dB
1001
-1.5 dB
···
···
1111
-10.5 dB
Step Size:
1.5 dB
DS680F1
5/13/08
CS42L52
6.24.2 Bass Gain
Sets the gain of the bass shelving filter.
6.25
TREB[3:0]
Gain Setting
0000
+12.0 dB
···
···
0111
+1.5 dB
1000
0 dB
1001
-1.5 dB
···
···
1111
-10.5 dB
Step Size:
1.5 dB
Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)
7
MSTxVOL7
6
MSTxVOL6
5
MSTxVOL5
4
MSTxVOL4
3
MSTxVOL3
2
MSTxVOL2
1
MSTxVOL1
0
MSTxVOL0
6.25.1 Master Volume Control
Sets the volume of the signal out the DSP.
6.26
MSTxVOL[7:0]
Master Volume
0001 1000
+12.0 dB
···
···
0000 0000
0 dB
1111 1111
-0.5 dB
1111 1110
-1.0 dB
···
···
0011 0100
-102 dB
···
···
0001 1001
-102 dB
Step Size:
0.5 dB
Headphone Volume Control: HPA (Address 22h) & HPB (Address 23h)
7
HPxVOL7
6
HPxVOL6
5
HPxVOL5
4
HPxVOL4
3
HPxVOL3
2
HPxVOL2
1
HPxVOL1
0
HPxVOL0
6.26.1 Headphone Volume Control
Sets the volume of the signal out the DAC.
HPxVOL[7:0]
DS680F1
Headphone Volume
0000 0000
0 dB
1111 1111
-0.5 dB
1111 1110
-1.0 dB
···
···
0011 0100
-96.0 dB
···
···
0000 0001
Muted
Step Size:
0.5 dB
63
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6.27
Speaker Volume Control: SPKA (Address 24h) & SPKB (Address 25h)
7
SPKxVOL7
6
SPKxVOL6
5
SPKxVOL5
4
SPKxVOL4
3
SPKxVOL3
2
SPKxVOL2
1
SPKxVOL1
0
SPKxVOL0
2
ADCASWP0
1
ADCBSWP1
0
ADCBSWP0
6.27.1 Speaker Volume Control
Sets the volume of the signal out the PWM modulator.
SPKxVOL[7:0]
0 dB
1111 1111
-0.5 dB
1111 1110
-1.0 dB
···
···
0100 0000
-96.0 dB
···
···
0000 0001
Muted
Step Size:
0.5 dB
Note:
6.28
Speaker Volume
0000 0000
The maximum step size error is ±0.15 dB.
ADC & PCM Channel Mixer (Address 26h)
7
PCMASWP1
6
PCMASWP0
5
PCMBSWP1
4
PCMBSWP0
3
ADCASWP1
6.28.1 PCM Mix Channel Swap
Configures a mix/swap of the PCM Mix to the headphone/line or speaker outputs.
PCMxSWP[1:0]
PCM Mix to HP/LINEOUTA
PCM Mix to HP/LINEOUTB
00
Left
Right
(Left + Right)/2
(Left + Right)/2
Right
Left
01
10
11
6.28.2 ADC Mix Channel Swap
Configures a mix/swap of the ADC Mix to the headphone/line or speaker outputs.
ADCxSWP[1:0]
ADC Mix to HP/LINEOUTA Channel
ADC Mix to HP/LINEOUTB Channel
00
Left
Right
(Left + Right)/2
(Left + Right)/2
Right
Left
01
10
11
64
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6.29
Limiter Control 1, Min/Max Thresholds (Address 27h)
7
LMAX2
6
LMAX1
5
LMAX0
4
CUSH2
3
CUSH1
2
CUSH0
1
LIMSRDIS
0
LIMZCDIS
6.29.1 Limiter Maximum Threshold
Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack
rate (LIMARATE - “Limiter Release Rate” on page 66).
LMAX[2:0]
Threshold Setting
000
0 dB
001
-3 dB
010
-6 dB
011
-9 dB
100
-12 dB
101
-18 dB
110
-24 dB
111
-30 dB
Application:
“Limiter” on page 31
Note: Bass, Treble, and digital gain settings that boost the signal beyond the maximum threshold may
trigger an attack.
6.29.2 Limiter Cushion Threshold
Sets the minimum level at which to disengage the Limiter’s attenuation at the release rate (LIMRRATE “Limiter Release Rate” on page 66) until levels lie between the LMAX and CUSH thresholds.
CUSH[2:0]
Threshold Setting
000
0 dB
001
-3 dB
010
-6 dB
011
-9 dB
100
-12 dB
101
-18 dB
110
-24 dB
111
-30 dB
Application:
“Limiter” on page 31
Note:
This setting is usually set slightly below the LMAX threshold.
6.29.3 Limiter Soft Ramp Disable
Configures an override of the digital soft ramp setting.
LIMSRDIS
OFF; Limiter Attack Rate is dictated by the DIGSFT (“Digital Soft Ramp” on page 53) setting
1
ON; Limiter volume changes take effect in one step, regardless of the DIGSFT setting.
Application:
“Limiter” on page 31
Note:
DS680F1
Limiter Soft Ramp Disable
0
This bit is ignored when the DIGZC (“Digital Zero Cross” on page 53) is enabled.
65
5/13/08
CS42L52
6.29.4 Limiter Zero Cross Disable
Configures an override of the digital zero-cross setting.
6.30
LIMZCDIS
Limiter Zero Cross Disable
0
OFF; Limiter Attack Rate is dictated by the DIGZC (“Digital Zero Cross” on page 53) setting
1
ON; Limiter volume changes take effect in one step, regardless of the DIGZC setting.
Application:
“Limiter” on page 31
Limiter Control 2, Release Rate (Address 28h)
7
LIMIT
6
LIMIT_ALL
5
LIMRRATE5
4
LIMRRATE4
3
LIMRRATE3
2
LIMRRATE2
1
LIMRRATE1
0
LIMRRATE0
6.30.1 Peak Detect and Limiter
Configures the peak-detect and limiter circuitry.
LIMIT
Limiter Status
0
Disabled
1
Enabled
Application:
“Limiter” on page 31
6.30.2 Peak Signal Limit All Channels
Sets how channels are attenuated when the limiter is enabled.
LIMIT_ALL
Limiter action:
0
Apply the necessary attenuation on a specific channel only when the signal amplitude on that specific channel rises above LMAX.
Remove attenuation on a specific channel only when the signal amplitude on that specific channel falls below
CUSH.
1
Apply the necessary attenuation on BOTH channels when the signal amplitude on any ONE channel rises
above LMAX.
Remove attenuation on BOTH channels only when the signal amplitude on BOTH channels fall below CUSH.
Application:
“Limiter” on page 31
6.30.3 Limiter Release Rate
Sets the rate at which the limiter releases the digital attenuation from levels below the CUSH[2:0] threshold (“Limiter Cushion Threshold” on page 65) and returns the analog output level to the MSTxVOL[7:0]
(“Master Volume Control” on page 63) setting.
LIMRRATE[5:0]
Release Time
00 0000
Fastest Release
···
···
11 1111
Slowest Release
Application:
“Limiter” on page 31
Note: The limiter release rate is user-selectable but is also a function of the sampling frequency, Fs,
and the DIGSFT (“Digital Soft Ramp” on page 53) and DIGZC (“Digital Zero Cross” on page 53) setting.
66
DS680F1
5/13/08
CS42L52
6.31
Limiter Attack Rate (Address 29h)
7
Reserved
6
Reserved
5
LIMARATE5
4
LIMARATE4
3
LIMARATE3
2
LIMARATE2
1
LIMARATE1
0
LIMARATE0
6.31.1 Limiter Attack Rate
Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold
(“Limiter Maximum Threshold” on page 65).
LIMARATE[5:0]
Attack Time
00 0000
Fastest Attack
···
···
11 1111
Slowest Attack
Application:
“Limiter” on page 31
Note: The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and
the DIGSFT (“Digital Soft Ramp” on page 53) and DIGZC (“Digital Zero Cross” on page 53) setting unless
the respective disable bit (“Limiter Soft Ramp Disable” on page 65 or “Limiter Zero Cross Disable” on
page 66) is enabled.
6.32
ALC Enable & Attack Rate (Address 2Ah)
7
ALCB
6
ALCA
5
ALCARATE5
4
AALCRATE4
3
ALCARATE3
2
ALCARATE2
1
ALCARATE1
0
ALCARATE0
6.32.1 ALCx Enable
Configures the automatic level controller.
ALC
ALC Status
0
Disabled
1
Enabled
Application:
“Automatic Level Control (ALC)” on page 27
Note:
The ALC is not available in passthrough mode.
6.32.2 ALC Attack Rate
Sets the rate at which the ALC applies analog and/or digital attenuation from levels above the AMAX[2:0]
threshold (“ALC Maximum Threshold” on page 68).
LIMARATE[5:0]
Attack Time
00 0000
Fastest Attack
···
···
11 1111
Slowest Attack
Application:
“Automatic Level Control (ALC)” on page 27
Note: The ALC attack rate is user-selectable but is also a function of the sampling frequency, Fs, and
the ANLGSFTx (“Ch. x Analog Soft Ramp” on page 49) and ANLGZCx (“Ch. x Analog Zero Cross” on
page 49) setting unless the respective disable bit (“ALCx Soft Ramp Disable” on page 55 or “ALCx Zero
Cross Disable” on page 56) is enabled.
DS680F1
67
5/13/08
CS42L52
6.33
ALC Release Rate (Address 2Bh)
7
Reserved
6
Reserved
5
ALCRRATE5
4
ALCRRATE4
3
ALCRRATE3
2
ALCRRATE2
1
ALCRRATE1
0
ALCRRATE0
6.33.1 ALC Release Rate
Sets the rate at which the ALC releases the analog and/or digital attenuation from levels below the
MIN[2:0] threshold (“ALC Minimum Threshold” on page 69) and returns the signal level to the PGAxVOL[5:0] (“PGAx Volume” on page 56) and ADCxVOL[7:0] (“ADCx Volume” on page 57) setting.
ALCRRATE[5:0]
Release Time
00 0000
Fastest Release
···
···
11 1111
Slowest Release
Application:
“Automatic Level Control (ALC)” on page 27
Notes:
1. The ALC release rate is user-selectable but is also a function of the sampling frequency, Fs, and the
ANLGSFTx (“Ch. x Analog Soft Ramp” on page 49) and ANLGZCx (“Ch. x Analog Zero Cross” on
page 49) setting.
2. The Release Rate setting must always be slower than the Attack Rate.
6.34
ALC Threshold (Address 2Ch)
7
ALCMAX2
6
ALCMAX1
5
ALCMAX0
4
ALCMIN2
3
ALCMIN1
2
ALCMIN0
1
Reserved
0
Reserved
6.34.1 ALC Maximum Threshold
Sets the maximum level, below full scale, at which to limit and attenuate the input signal at the attack rate
(ALCARATE - “ALC Attack Rate” on page 67).
MAX[2:0]
68
Threshold Setting
000
0 dB
001
-3 dB
010
-6 dB
011
-9 dB
100
-12 dB
101
-18 dB
110
-24 dB
111
-30 dB
Application:
“Automatic Level Control (ALC)” on page 27
DS680F1
5/13/08
CS42L52
6.34.2 ALC Minimum Threshold
Sets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at the release rate (ALCRRATE - “ALC Release Rate” on page 68) until levels lie between the ALCMAX and ALCMIN thresholds.
ALCMIN[2:0]
Threshold Setting
000
0 dB
001
-3 dB
010
-6 dB
011
-9 dB
100
-12 dB
101
-18 dB
110
-24 dB
111
-30 dB
Application:
“Automatic Level Control (ALC)” on page 27
Notes:
1. This setting is usually set slightly below the ALCMAX threshold.
6.35
Noise Gate Control (Address 2Dh)
7
NGALL
6
NG
5
NG_BOOST
4
THRESH2
3
THRESH1
2
THRESH0
1
NGDELAY1
0
NGDELAY0
6.35.1 Noise Gate All Channels
Sets which channels are attenuated when clipping on any single channel occurs.
NGALL
Noise Gate triggered by:
0
Individual channel; Any channel that falls below the threshold setting triggers the noise gate attenuation for
both channels.
1
Both channels A & B; Both channels must fall below the threshold setting for the noise gate attenuation to
take effect.
Application:
“Noise Gate” on page 28
6.35.2 Noise Gate Enable
Configures the noise gate.
DS680F1
NG
Noise Gate Status
0
Disabled
1
Enabled
Application:
“Noise Gate” on page 28
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6.35.3 Noise Gate Threshold and Boost
THRESH sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96 dB. NG_BOOST configures a +30 dB boost to the threshold settings.
THRESH[2:0]
Minimum Setting (NG_BOOST = ‘0’b)
000
-64 dB
Minimum Setting (NG_BOOST = ‘1’b)
-34 dB
001
-67 dB
-37 dB
010
-70 dB
-40 dB
011
-73 dB
-43 dB
100
-76 dB
-46 dB
101
-82 dB
-52 dB
110
Reserved
-58 dB
111
Reserved
-64 dB
Application:
“Noise Gate” on page 28
6.35.4 Noise Gate Delay Timing
Sets the delay time before the noise gate attacks.
NGDELAY[1:0]
Delay Setting
00
50 ms
01
100 ms
10
150 ms
11
200 ms
Application:
“Noise Gate” on page 28
Note: The Noise Gate attack rate is a function of the sampling frequency, Fs, and the ANLGSFTx (“Ch.
x Analog Soft Ramp” on page 49) and ANLGZCx (“Ch. x Analog Zero Cross” on page 49) setting unless
the respective disable bit (“ALCx Soft Ramp Disable” on page 55 or “ALCx Zero Cross Disable” on
page 56) is enabled.
6.36
Status (Address 2Eh) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
7
Reserved
6
SPCLKERR
5
DSPAOVFL
4
DSPBOVFL
3
PCMAOVFL
2
PCMBOVFL
1
ADCAOVFL
0
ADCBOVFL
6.36.1 Serial Port Clock Error (Read Only)
Indicates the status of the MCLK to LRCK ratio.
SPCLKERR
Serial Port Clock Status:
0
MCLK/LRCK ratio is valid.
1
MCLK/LRCK ratio is not valid.
Application:
“Serial Port Clocking” on page 34
Note:
nizes.
70
On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-
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6.36.2 DSP Engine Overflow (Read Only)
Indicates the over-range status in the DSP data path.
DSPxOVFL
DSP Overflow Status:
0
No digital clipping has occurred in the data path after the DSP.
1
Digital clipping has occurred in the data path after the DSP.
Application:
“Analog Outputs” on page 29
6.36.3 PCMx Overflow (Read Only)
Indicates the over-range status in the PCM mix data path.
PCMxOVFL
PCM Overflow Status:
0
No digital clipping has occurred in the data path of the PCM mix (“PCM Mixer Channel x Volume” on page 58)
of the DSP.
1
Digital clipping has occurred in the data path of the PCM mix of the DSP.
Application:
“Analog Outputs” on page 29
6.36.4 ADCx Overflow (Read Only)
Indicates the over-range status in the ADC signal path.
6.37
ADCxOVFL
ADC Overflow Status:
0
No clipping has occurred anywhere in the ADC signal path.
1
Clipping has occurred in the ADC signal path.
Application:
“Analog Inputs” on page 26
Battery Compensation (Address 2Fh)
7
BATTCMP
6
VPMONITOR
5
Reserved
4
Reserved
3
VPREF3
2
VPREF2
1
VPREF1
0
VPREF0
6.37.1 Battery Compensation
Configures automatic adjustment of the speaker volume when VP deviates from VPREF[3:0].
BATTCMP
Automatic Battery Compensation
0
Disabled
1
Enabled
Application:
“Maintaining a Desired Output Level” on page 34
6.37.2 VP Monitor
Configures the internal ADC that monitors the VP voltage level.
VPMONITOR
VP ADC Status
0
Disabled
1
Enabled
Notes:
1. The internal ADC that monitors the VP supply is enabled automatically when BATTCMP is enabled,
regardless of the VPMONITOR setting. Conversely, when BATTCMP is disabled, the ADC may be
enabled by enabling VPMONITOR; this provides a convenient battery monitor without enabling
battery compensation.
2. When enabled, VPMONITOR remains enabled regardless of the PDN bit setting.
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6.37.3 VP Reference
Sets the desired VP reference used for battery compensation.
VPREF[3:0]
Desired VP used to calculate the required attenuation on the speaker output:
0000
1.5 V
0001
2.0 V
0010
2.5 V
(for VA = 1.8 V)
0011
3.0 V
0100
3.5 V
0101
4.0 V
0110
4.5 V
0111
5.0 V
1000
1.5 V
1001
2.0 V
1010
2.5 V
(for VA = 2.5 V)
6.38
1011
3.0 V
1100
3.5 V
1101
4.0 V
1110
4.5 V
1111
5.0 V
Application:
“VP Battery Compensation” on page 33
VP Battery Level (Address 30h) (Read Only)
7
VPLVL7
6
VPLVL6
5
VPLVL5
4
VPLVL4
3
VPLVL3
2
VPLVL2
1
VPLVL1
0
VPLVL0
6.38.1 VP Voltage Level (Read Only)
Indicates the unsigned VP voltage level.
VPLVL[7:0]
VP Voltage
...
0101 1110
3.0 V (for VA = 2.0 V); apply formula using actual VA voltage to calculate VP voltage.
...
0111 0010
3.7 V (for VA = 2.0 V); apply formula using actual VA voltage to calculate VP voltage.
...
Formula:
6.39
VP Voltage = (Binary representation of VPLVL[7:0]) * VA / 63.3
Speaker Status (Address 31h) (Read Only)
7
Reserved
6
Reserved
5
SPKASHRT
4
SPKBSHRT
3
SPKR/HP
2
Reserved
1
Reserved
0
Reserved
6.39.1 Speaker Current Load Status (Read Only)
Indicates whether or not any of the speaker outputs is shorted to ground.
72
SPKxSHRT
Speaker Output Load
0
No overload detected
1
Overload detected
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6.39.2 SPKR/HP Pin Status (Read Only)
Indicates the status of the SPKR/HP pin.
6.40
SPKR/HP
Pin State
0
Pulled Low
1
Pulled High
Charge Pump Frequency (Address 34h)
7
CHGFREQ3
6
CHGFREQ2
5
CHGFREQ1
4
CHGFREQ0
3
Reserved
2
Reserved
1
Reserved
0
Reserved
6.40.1 Charge Pump Frequency
Sets the charge pump frequency on FLYN and FLYP.
CHGFREQ[3:0]
N
0000
0
...
0101
5
...
1111
15
Formula:
Frequency = (64xFs)/(N+2)
Note:
DS680F1
The headphone output THD+N performance may be affected.
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CS42L52
7. ANALOG PERFORMANCE PLOTS
7.1
Headphone THD+N versus Output Power Plots
Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48 kHz.
-10
G = 0.6047
-15
VHP = VA = 1.8 V
G = 0.7099
-20
G = 0.8399
-25
-30
G = 1.0000
-35
G = 1.1430
-40
Legend
-45
d
B
r
A
-50
NOTE: Graph shows the output power per channel (i.e.
Output Power = 23 mW
into
single 16 Ω and 46 mW into
stereo 16 Ω with THD+N = 75 dB).
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
0
10m
20m
30m
40m
50m
60m
70m
80m
W
Figure 22. THD+N vs. Output Power per Channel at 1.8 V (16 Ω load)
-10
-15
G = 0.6047
VHP = VA = 2.5 V
G = 0.7099
-20
-25
G = 0.8399
-30
G = 1.0000
-35
G = 1.1430
-40
Legend
-45
d
B
r
A
NOTE: Graph shows the output power per channel (i.e.
Output Power = 44 mW
into
single 16 Ω and 88 mW into
stereo 16 Ω with THD+N = 75 dB).
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
0
10m
20m
30m
40m
50m
60m
70m
80m
W
Figure 23. THD+N vs. Output Power per Channel at 2.5 V (16 Ω load)
74
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CS42L52
G = 0.6047
VHP = VA = 1.8 V
G = 0.7099
-20
-30
G = 0.8399
-35
G = 1.0000
-40
G = 1.1430
-45
Legend
-50
NOTE: Graph shows the output power per channel (i.e.
Output Power = 22 mW
into
single 32 Ω and 44 mW into
stereo 32 Ω with THD+N = 75 dB).
-55
d
B
r
-60
A
-65
-70
-75
-80
-85
-90
-95
-100
0
6m
12m
18m
24m
30m
36m
42m
48m
54m
60m
W
Figure 24. THD+N vs. Output Power per Channel at 1.8 V (32 Ω load)
G = 0.6047
-20
VHP = VA = 2.5 V
-25
G = 0.7099
-30
G = 0.8399
-35
G = 1.0000
-40
G = 1.1430
-45
Legend
-50
-55
d
B
r
NOTE: Graph shows the output power per channel (i.e.
Output Power = 42 mW
into
single 32 Ω and 84 mW into
stereo 32 Ω with THD+N = 75 dB).
-60
A
-65
-70
-75
-80
-85
-90
-95
-100
0
5m
10m
15m
20m
25m
30m
35m
40m
45m
50m
55m
60m
W
Figure 25. THD+N vs. Output Power per Channel at 2.5 V (32 Ω load)
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8. EXAMPLE SYSTEM CLOCK FREQUENCIES
8.1
8.2
76
*The”MCLKDIV2” bit must be enabled.
Auto Detect Enabled
Sample Rate
LRCK (kHz)
1024x
MCLK (MHz)
1536x
2048x*
8
11.025
12
3072x*
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
24.5760
33.8688
36.8640
Sample Rate
LRCK (kHz)
512x
MCLK (MHz)
768x
1024x*
16
22.05
24
8.1920
11.2896
12.2880
Sample Rate
LRCK (kHz)
256x
32
44.1
48
8.1920
11.2896
12.2880
Sample Rate
LRCK (kHz)
128x
64
88.2
96
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
MCLK (MHz)
384x
512x*
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
MCLK (MHz)
192x
256x*
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
1536x*
24.5760
33.8688
36.8640
768x*
24.5760
33.8688
36.8640
384x*
24.5760
33.8688
36.8640
Auto Detect Disabled
Sample Rate
LRCK (kHz)
512x
8
11.025
12
6.1440
768x
MCLK (MHz)
1024x
1536x
2048x
3072x
6.1440
8.4672
9.2160
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
Sample Rate
LRCK (kHz)
256x
384x
512x
16
22.05
24
6.1440
6.1440
8.4672
9.2160
8.1920
11.2896
12.2880
Sample Rate
LRCK (kHz)
256x
32
44.1
48
8.1920
11.2896
12.2880
Sample Rate
LRCK (kHz)
128x
64
88.2
96
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
MCLK (MHz)
768x
12.2880
16.9344
18.4320
1024x
1536x
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
MCLK (MHz)
384x
512x
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
MCLK (MHz)
192x
256x
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
768x
24.5760
33.8688
36.8640
384x
24.5760
33.8688
36.8640
DS680F1
5/13/08
CS42L52
9. PCB LAYOUT CONSIDERATIONS
9.1
Power Supply, Grounding
As with any high-resolution converter, the CS42L52 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 10 shows the recommended power arrangements, with VA and VHP connected to clean supplies VD, which powers the digital
circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply
via a ferrite bead. In this case, no additional devices should be powered from VD.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS42L52 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same
side of the board as the CS42L52 to minimize inductance effects.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and AGND. The CDB42L52 evaluation board demonstrates the optimum layout and power supply arrangements.
9.2
QFN Thermal Pad
The CS42L52 is available in a compact QFN package. The underside of the QFN package reveals a large
metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS42L52 evaluation board demonstrates the optimum thermal pad and via configuration.
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CS42L52
10.ADC & DAC DIGITAL FILTERS
78
Figure 26. ADC Passband Ripple
Figure 27. ADC Stopband Rejection
Figure 28. ADC Transition Band
Figure 29. ADC Transition Band (Detail)
Figure 30. DAC Passband Ripple
Figure 31. DAC Stopband
Figure 32. DAC Transition Band
Figure 33. DAC Transition Band (Detail)
DS680F1
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CS42L52
11.PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channel pairs. Units in decibels.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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CS42L52
12.PACKAGE DIMENSIONS
40L QFN (6 X 6 mm BODY) PACKAGE DRAWING
D
b
2.00REF
e
PIN #1CORNER
2.00REF
PIN #1IDENTIFIER
∅0.50±0.10
LASER MARKING
E2
E
A1
L
D2
A
DIM
A
A1
b
D
D2
E
E2
e
L
MIN
-0.0000
0.0071
0.1594
0.1594
0.0118
INCHES
NOM
--0.0091
0.2362 BSC
0.1614
0.2362 BSC
0.1614
0.0197 BSC
0.0157
MAX
0.0394
0.0020
0.0110
MIN
-0.00
0.18
0.1634
4.05
0.1634
4.05
0.0197
0.30
MILLIMETERS
NOM
--0.23
6.00 BSC
4.10
6.00 BSC
4.10
0.50 BSC
0.40
NOTE
MAX
1.00
0.05
0.28
4.15
4.15
0.50
1
1
1,2
1
1
1
1
1
1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm
from the terminal tip.
THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance
80
2 Layer Board
4 Layer Board
Symbol
Min
Typ
Max
Units
θJA
-
44
19
-
°C/Watt
DS680F1
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CS42L52
13.ORDERING INFORMATION
Product
CS42L52
CDB42L52
CRD42L52
Description
Low-Power Stereo
CODEC w/HP and
Speaker Amps for
Portable Apps
CS42L52 Evaluation
Board
CS42L52 Reference
Design
Package Pb-Free
Grade
Temp Range
Commercial -40 to +85° C
40L-QFN
Yes
Automotive -40 to +105° C
Container
Order #
Rail
CS42L52-CNZ
Tape & Reel CS42L52-CNZR
Rail
CS42L52-DNZ
Tape & Reel CS42L52-DNZR
-
No
-
-
-
CDB42L52
-
No
-
-
-
CRD42L52
14.REFERENCES
1. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000.
http://www.semiconductors.philips.com.
15.REVISION HISTORY
Revision
Changes
F1
Removed the Thermal Error Detection and Thermal Foldback Feature
Added “Internal Connections” to table in “I/O Pin Characteristics” on page 9.
Added and updated absolute maximum parameters in “Absolute Maximum Ratings” on page 11
Lowered the VP Current Consumption in “Power Consumption” on page 24.
Updated the expected ALC behavior when signals cross the MIN threshold in “Automatic Level Control (ALC)” on
page 27.
Added the Thermal Error Disable control port initialization setting in “Required Initialization Settings” on page 37.
Updated note 2 in “Power Down PGAx” on page 42.
Added note in “ADC Mute” on page 51.
Added note in “Digital Soft Ramp” on page 53.
Added notes in “Digital Zero Cross” on page 53.
Updated the ADCB=A, PLYBCKB=A and SPKRB=A descriptions in “Analog Front-End Volume Setting B=A” on
page 50, “Playback Volume Setting B=A” on page 51, and “Speaker Volume Setting B=A” on page 54.
Corrected the MICxGAIN decode settings in “MICx Gain” on page 55.
Corrected BEEP volume settings to reflect level relative to DAC’s full scale in “Beep Volume” on page 61.
Added note 2 in “VP Monitor” on page 71.
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CS42L52
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY
INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
82
DS680F1
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