CS42L92-CWZR

CS42L92 32-Bit 384-kHz Hi-Fi Audio Codec • Multichannel asynchronous sample-rate conversion Features • Multiline SLIMbus® audio and control interface • Integrated multichannel 32-bit hi-fi audio hub codec — 99-dB signal-to-noise ratio (SNR) mic input (48 kHz) — 127-dB SNR headphone playback (48 kHz) — –100-dB total harmonic distortion + noise (THD+N) — Ultrasonic input- and output-path support • Three multichannel digital-audio interfaces — Standard data formats up to 384 kHz, 32 bits • Flexible clocking, derived from MCLKn, AIFn, or SLIMbus — Low-power frequency-locked loops (FLLs) support reference clocks down to 32 kHz. • Up to eight analog or digital microphone (DMIC) inputs • Advanced accessory detection functions • Multipurpose headphone/earpiece/line output drivers — Support for balanced headphone output loads • Configurable functions on up to 16 general-purpose input/output (GPIO) pins — 33 mW into 32- load at 0.1% THD+N • Integrated regulators and charge pumps — Hi-fi filters for audiophile-quality playback • Small W-CSP package, 0.4-mm staggered ball array MICBIAS1A MICBIAS1B MICBIAS1C MICBIAS1D MICBIAS2A MICBIAS2B SUBGND CP2VOUT AVDD AGND VREFC CS42L92 Charge Pumps LDO and MICBIAS Generators DCVDD DBVDD FLLGND DGND • Smartphones, tablets, and multimedia handsets FLLVDD CPVDD1 CPVDD2 CPGND • Digital pulse-density modulation (PDM) output interface CP2CA CP2CB CP1C1A CP1C1B CP1VOUT1P CP1VOUT1N CP1C2A CP1C2B CP1VOUT2P CP1VOUT2N Applications MICVDD • Native audio playback up to 384 kHz sample rate, concurrent with voice and ultrasonic input signal paths Reference Generator DAC HPOUTnL DAC HPOUTnR Digital Mixing Core http://www.cirrus.com SYSCLK ASYNCCLK Accessory Detect SLIMbus Interface Control Interface (SPI/I2C) Copyright  Cirrus Logic, Inc. 2017 (All Rights Reserved) GPIO x4 SPKCLK SPKDAT JACKDET1 JACKDET2 JACKDET3 HPDET1 HPDET2 MICDET1/HPOUTFB1 MICDET2/HPOUTFB2 MICDET3/HPOUTFB3 MICDET4/HPOUTFB4 MICDET5/HPOUTFB5 GPSW1P GPSW1N GPSW2P GPSW2N Digital Audio Interfaces AIF1, AIF2, AIF3 GPIO1 GPIO2 Clocking Control CIFMISO CIFMOSI/SDA CIFSCLK CIFSS CIFMODE AIFnBCLK AIFnLRCLK SLIMCLK AIF1TXDAT AIF1RXDAT AIF1BCLK AIF1LRCLK IRQ PDM Driver AEC (Echo Cancelation) Loop-Back SLIMCLK SLIMDAT1 SLIMDAT2 RESET 4 x ADC 4 x Stereo Digital Mic Interface AIF3TXDAT AIF3RXDAT AIF3BCLK AIF3LRCLK MCLK1 MCLK2 MCLK3 Programmable DSP Five-band equalizer (EQ) Dynamic range control (DRC) Low-pass/high-pass filter (LHPF) Asynchronous sample -rate conversion Automatic sample -rate detection Data format conversion Ultrasonic demodulator PWM signal generator Haptic control signal generator Input Select AIF2TXDAT AIF2RXDAT AIF2BCLK AIF2LRCLK IN1ALN/DMICCLK1, IN1BLN IN1ALP/DMICDAT1, IN1BLP IN1ARN/DMICCLK3 IN1ARP/DMICDAT3, IN1BR IN2ALN/DMICCLK2 IN2ALP/DMICDAT2, IN2BL IN2ARN/DMICCLK4 IN2ARP/DMICDAT4, IN2BR DS1162F1 NOV '17 CS42L92 Description The CS42L92 is a highly integrated low-power audio system for smartphones, tablets, and other portable audio devices. Multiple input/output paths are supported by a fully flexible all-digital mixing and routing engine, incorporating sample rate converters and other signal-processing functions for wide use-case flexibility. The integrated DSP provides a general-purpose signal processing capability; this is supported by general-purpose timer and event-logger functions. The digital audio interfaces and hi-fi DACs enable 32-bit playback through the entire signal chain. Native audio playback at sample rates up to 384 kHz is possible, concurrent with voice and ultrasonic input paths. The CS42L92 supports up to eight analog inputs and up to eight PDM digital inputs. Low-power input modes are available for always-on (e.g., voice-trigger) functionality using either analog or digital input. A smart accessory interface, with multipurpose impedance sensing and measurement capability, supports detection of external headsets and push buttons. Dual headphone connections (e.g., 3.5-mm and USB-C™) can be detected simultaneously. Four hi-fi quality stereo headphone drivers are provided, each supporting stereo ground-referenced or mono bridge-tied load (BTL) configurations. Multiple headphone/earpiece outputs can be supported, including balanced stereo headphone configurations. The output drivers offer noise levels as low as 0.63 VRMS into line or headphone loads. Selectable hi-fi filters support playback modes at sample rates up to 384 kHz. Two channels of PDM output (one stereo interface) are available, and also an IEC-60958-3–compatible S/PDIF transmitter. A signal generator for controlling haptics devices is included; vibe actuators can connect directly to the PDM output interface. All inputs, outputs, and system interfaces can function concurrently. A SLIMbus interface supports multichannel audio paths and host control register access. Three further digital audio interfaces are provided, each supporting a wide range of standard audio sample rates and serial interface formats. Automatic sample-rate detection enables seamless wideband/narrowband voice-call handover. Two FLLs are integrated, providing support for a wide range of system-clock frequencies. The CS42L92 is configured using the SLIMbus, SPI™, or IC interfaces. The device is powered from 1.8- and 1.2-V supplies. The power, clocking, and output driver architectures are designed to maximize battery life in voice, music, and standby modes. Low-power (10 A) Sleep Mode is supported, with configurable wake-up events. 2 DS1162F1 CS42L92 Table of Contents 1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 WLCSP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . 10 Table 3-1. Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3-2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3-3. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3-4. Analog Input Signal Level—IN1xx, IN2xx . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3-5. Analog Input Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3-6. Analog Input Gain—Programmable Gain Amplifiers (PGAs) . . . . . . . . . . . . 11 Table 3-7. Digital Input Signal Level—DMICDATn . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3-8. Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3-9. Input/Output Path Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3-10. Digital Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3-11. Miscellaneous Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3-12. Device Reset Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3-13. System Clock and Frequency-Locked Loop (FLL) . . . . . . . . . . . . . . . . . . . 17 Table 3-14. Digital Microphone (DMIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 3-15. Digital Speaker (PDM) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3-16. Digital Audio Interface—Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 3-17. Digital Audio Interface—Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 3-18. Digital Audio Interface Timing—TDM Mode . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 3-19. Control Interface Timing—Two-Wire (I2C) Mode . . . . . . . . . . . . . . . . . . . . 22 Table 3-20. Control Interface Timing—Four-Wire (SPI) Mode . . . . . . . . . . . . . . . . . . . . 23 Table 3-21. SLIMbus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 3-22. JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 3-23. Typical Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 3-24. Typical Signal Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 Input Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3 Digital Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3 4.4 DSP Firmware Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.5 DSP Peripheral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.6 Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.7 Digital Audio Interface Control . . . . . . . . . . . . . . . . . . . . . . 130 4.8 SLIMbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 4.9 SLIMbus Control Sequences . . . . . . . . . . . . . . . . . . . . . . . 142 4.10 SLIMbus Interface Control . . . . . . . . . . . . . . . . . . . . . . . . 144 4.11 Output Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.12 External Accessory Detection . . . . . . . . . . . . . . . . . . . . . 169 4.13 Low Power Sleep Configuration . . . . . . . . . . . . . . . . . . . . 189 4.14 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 4.15 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 4.16 Clocking and Sample Rates . . . . . . . . . . . . . . . . . . . . . . . 219 4.17 Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 4.18 Control-Write Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . 249 4.19 Charge Pumps, Regulators, and Voltage Reference . . . . 257 4.20 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 4.21 Short-Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 263 4.22 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . 264 4.23 Hardware Reset, Software Reset, Wake-Up, and Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 5.1 Recommended External Components . . . . . . . . . . . . . . . . 267 5.2 Resets Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 5.3 Output-Signal Drive-Strength Control . . . . . . . . . . . . . . . . . 274 5.4 Digital Audio Interface Clocking Configurations . . . . . . . . . 276 5.5 PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . 280 6 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 7 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 8 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 10 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 DS1162F1 CS42L92 1 Pin Descriptions 1 Pin Descriptions 1.1 WLCSP Pinout A1 A3 A5 A2 B2 B4 CPVDD1 B3 CP2CA C2 D1 B5 CPGND C4 CP1C2A D3 CP1VOUT2P CP2CB E2 CPVDD2 E4 F1 CP1C1A F3 CP1VOUT1N CP2VOUT G2 CP1C1B G4 H1 MICBIAS1B H3 MICBIAS1C MICVDD J2 MICBIAS1D J4 K1 IN1BLN K3 IN1BLP L2 M1 B8 MICDET4/ HPOUTFB4 HPDET2 D11 MICDET3/ HPOUTFB3 D13 JACKDET1 E10 HPDET1 E12 GPSW1N GPSW2N F9 MICDET2/ HPOUTFB2 F11 GPSW1P F13 TDO G8 GPSW2P G10 MICDET1/ HPOUTFB1 G12 JACKDET2 MICBIAS2B H7 CIFMODE H9 JACKDET3 H11 AGND2 H13 IN1ALN/ DMICCLK1 J6 GPIO2 J8 GPIO1 J10 IRQ J12 AVDD2 C10 D5 HPOUT4R D7 MICDET5/ HPOUTFB5 D9 E6 TRST E8 MICBIAS2A F7 MICBIAS1A G6 H5 IN1ALP/ DMICDAT1 K5 AIF3LRCLK/ GPIO16 K7 AIF3TXDAT/ GPIO13 K9 SPKCLK/ GPIO3 K11 RESET K13 IN1ARN/ DMICCLK3 L4 AIF1TXDAT/ GPIO5 CIFSS L10 SPKDAT/ GPIO4 L12 SUBGND IN1ARP/ DMICDAT3 M3 IN2BR M5 CIFMISO M9 MCLK3 M11 FLLGND M13 IN1BR N2 IN2ARN/ DMICCLK4 N4 SLIMCLK N10 MCLK2 N12 FLLVDD P1 IN2ARP/ DMICDAT4 P3 SLIMDAT1 P11 DGND P13 IN2BL R2 R10 MCLK1 R12 DCVDD T1 AGND1 T11 DGND D8 J3 G7 J5 J7 L3 L5 L7 L6 M4 L8 M6 M8 VREFC N6 AIF2BCLK/ GPIO10 N8 IN2ALN/ DMICCLK2 P5 AIF1BCLK/ GPIO6 P7 AIF3BCLK/ GPIO14 P9 IN2ALP/ DMICDAT2 R4 DGND R6 AIF2RXDAT/ GPIO11 R8 CIFSCLK T3 SUBGND P2 N5 N7 P4 R3 T2 P6 R5 T4 AVDD1 P8 R7 T6 T8 Digital I/O M14 N13 P12 R11 T10 AIF1LRCLK/ AIF3RXDAT/ SLIMDAT2 T7 T9 GPIO8 GPIO15 DCVDD AIF2TXDAT/ CIFMOSI/SDA GPIO9 Analog I/O L13 N11 R9 K14 M12 P10 T5 J13 L11 N9 H14 K12 M10 M7 N3 H12 K10 AIF1RXDAT/ GPIO7 F14 G13 J11 L9 AIF2LRCLK/ GPIO12 F12 H10 K8 D14 E13 G11 J9 K6 D12 F10 H8 C13 E11 G9 H6 K4 D10 F8 G5 C11 E9 F6 F5 H4 M2 C9 E7 CP1VOUT1P F4 K2 NC C8 C7 D6 G3 R1 HPOUT3R E5 H2 S1 HPOUT2R E3 N1 C6 D4 F2 O1 B11 C5 D2 L1 B9 B14 C12 J1 HPOUT3L B12 HPOUT1R G1 CP1C2B B10 B13 E1 B7 A13 A12 HPOUT2L C3 HPOUT4L A11 A10 HPOUT1L C1 Q1 A9 A8 B6 CP1VOUT2N B1 I1 A7 A6 A4 P14 R13 T12 DBVDD T14 T13 DGND Power Figure 1-1. Top-Down (Through-Package) View—104-Ball WLCSP Package 4 DS1162F1 CS42L92 1.2 Pin Descriptions 1.2 Pin Descriptions Table 1-1 describes each pin on the CS42L92. Note that pins that share a common name should be tied together on the printed circuit board (PCB). Table 1-1. Pin Descriptions PU = Pull-up, PD = Pull-down, K = Bus keeper, H = Hysteresis on CMOS input, Z = Hi-Z (High impedance), C = CMOS, OD = Open drain. Pin Name Pin # Power Supply I/O Pin Description Digital Pad State at Reset 1 Attributes Analog I/O CP1C1A E2 — O Charge Pump 1 fly-back capacitor 1 pin — — CP1C1B F3 — O Charge Pump 1 fly-back capacitor 1 pin — — CP1C2A C2 — O Charge Pump 1 fly-back capacitor 2 pin — — CP1C2B B5 — O Charge Pump 1 fly-back capacitor 2 pin — — CP1VOUT1N E4 — O Charge Pump 1 negative output 1 decoupling pin — Output CP1VOUT1P D5 — O Charge Pump 1 positive output 1 decoupling pin — Output CP1VOUT2N A4 — O Charge Pump 1 negative output 2 decoupling pin — Output CP1VOUT2P C4 — O Charge Pump 1 positive output 2 decoupling pin — Output CP2CA B1 — O Charge Pump 2 fly-back capacitor pin — Output CP2CB D1 — O Charge Pump 2 fly-back capacitor pin — Output CP2VOUT F1 — O Charge Pump 2 output decoupling pin/supply for LDO2 — Output GPSW1N D13 — I/O General-purpose bidirectional switch 1 contact — — GPSW1P E12 — I/O General-purpose bidirectional switch 1 contact — — GPSW2N E8 — I/O General-purpose bidirectional switch 2 contact — — GPSW2P F9 — I/O General-purpose bidirectional switch 2 contact — — HPDET1 D11 — I/O Headphone sense 1 input — Input HPDET2 C10 — I/O Headphone sense 2 input — Input HPOUT1L A12 — O Left headphone 1 output — Output HPOUT1R B11 — O Right headphone 1 output — Output HPOUT2L A10 — O Left headphone 2 output — Output HPOUT2R B9 — O Right headphone 2 output — Output HPOUT3L A8 — O Left headphone 3 output — Output HPOUT3R B7 — O Right headphone 3 output — Output HPOUT4L A6 — O Left headphone 4 output — Output HPOUT4R C6 — O Right headphone 4 output — Output IN1ALN/ DMICCLK1 H5 MICVDD or MICBIASn [2] I Left/right-channel negative differential mic/line input/ DMIC Clock Output 1. Also suitable for connection to external accessory interfaces. — IN1ALN input IN1ALP/ DMICDAT1 J4 MICVDD or MICBIASn [2] I Left-channel single-ended mic/line input/positive differential mic/line input/DMIC Data Input 1. Also suitable for connection to external accessory interfaces. PD/H IN1ALP input IN1ARN/ DMICCLK3 K3 MICVDD or MICBIASn [2] I Right-channel negative differential mic/line input/DMIC Clock Output 3. Also suitable for connection to external accessory interfaces. — IN1ARN input IN1ARP/ DMICDAT3 L2 MICVDD or MICBIASn [2] I/O PD/H IN1ARP input IN1BLN J2 MICVDD I Negative differential mic/line input. Also suitable for connection to external accessory interfaces. — Input IN1BLP K1 MICVDD I Single-ended mic/line input/positive differential mic/line input. Also suitable for connection to external accessory interfaces. — Input 5 Right-channel single-ended mic/line input/positive differential mic/line input/DMIC Data Input 3. Also suitable for connection to external accessory interfaces. DS1162F1 CS42L92 1.2 Pin Descriptions Table 1-1. Pin Descriptions (Cont.) PU = Pull-up, PD = Pull-down, K = Bus keeper, H = Hysteresis on CMOS input, Z = Hi-Z (High impedance), C = CMOS, OD = Open drain. Pin # Power Supply I/O IN1BR M1 MICVDD I Right-channel single-ended mic/line input/positive differential mic/line input. — Input IN2ALN/ DMICCLK2 N4 MICVDD or MICBIASn [2] I Left-channel negative differential mic/line input/DMIC Clock Output 2. Also suitable for connection to external accessory interfaces. — IN2ALN input IN2ALP/ DMICDAT2 P3 MICVDD or MICBIASn [2] I/O PD/H IN2ALP input IN2ARN/ DMICCLK4 M3 MICVDD or MICBIASn [2] I — IN2ARN input IN2ARP/ DMICDAT4 N2 MICVDD or MICBIASn [2] I/O PD/H IN2ARP input IN2BL P1 MICVDD I Left-channel single-ended mic/line input — Input IN2BR L4 MICVDD I Right-channel single-ended mic/line input. Also suitable for connection to external accessory interfaces. — Input Pin Name Pin Description Left-channel single-ended mic/line input/positive differential mic/line input/DMIC Data Input 2. Also suitable for connection to external accessory interfaces. Right-channel negative differential mic/line input/DMIC Clock Output 4. Also suitable for connection to external accessory interfaces. Right-channel single-ended mic/line input/positive differential mic/line input/DMIC Data Input 4. Also suitable for connection to external accessory interfaces. Digital Pad State at Reset 1 Attributes JACKDET1 D9 AVDD I Jack detect input 1 — Input JACKDET2 F13 AVDD I Jack detect input 2 — Input JACKDET3 G10 AVDD I Jack detect input 3 — Input MICBIAS1A F5 MICVDD O Microphone bias 1A — Output MICBIAS1B G2 MICVDD O Microphone bias 1B — Output MICBIAS1C G4 MICVDD O Microphone bias 1C — Output MICBIAS1D H3 MICVDD O Microphone bias 1D — Output MICBIAS2A E6 MICVDD O Microphone bias 2A — Output MICBIAS2B G6 MICVDD O Microphone bias 2B — Output MICDET1/ HPOUTFB1 F11 — I/O Mic/accessory sense input 1/HPOUT ground feedback pin 1 — Input MICDET2/ HPOUTFB2 E10 — I/O Mic/accessory sense input 2/HPOUT ground feedback pin 2 — Input MICDET3/ HPOUTFB3 C12 — I/O Mic/accessory sense input 3/HPOUT ground feedback pin 3 — Input MICDET4/ HPOUTFB4 B13 — I/O Mic/accessory sense input 4/HPOUT ground feedback pin 4 — Input MICDET5/ HPOUTFB5 C8 — I/O Mic/accessory sense input 5/HPOUT ground feedback pin 5 — Input MICVDD H1 — O LDO2 output decoupling pin (generated internally by CS42L92). (Can also be used as reference/supply for external microphones.) — Output VREFC M5 — O Band-gap reference external capacitor connection — Output AIF1BCLK/ GPIO6 N6 DBVDD I/O Audio interface 1 bit clock/GPIO6 PU/PD/K/H/ GPIO6 input with Z/C/OD bus-keeper AIF1LRCLK/ GPIO8 R6 DBVDD I/O Audio interface 1 left/right clock/GPIO8 PU/PD/K/H/ GPIO8 input with Z/C/OD bus-keeper AIF1RXDAT/ GPIO7 L6 DBVDD I/O Audio interface 1 RX digital audio data/GPIO7 PU/PD/K/H/ GPIO7 input with C/OD bus-keeper AIF1TXDAT/ GPIO5 K5 DBVDD I/O Audio interface 1 TX digital audio data/GPIO5 PU/PD/K/H/ GPIO5 input with Z/C/OD bus-keeper Digital I/O 6 DS1162F1 CS42L92 1.2 Pin Descriptions Table 1-1. Pin Descriptions (Cont.) PU = Pull-up, PD = Pull-down, K = Bus keeper, H = Hysteresis on CMOS input, Z = Hi-Z (High impedance), C = CMOS, OD = Open drain. Pin # Power Supply I/O AIF2BCLK/ GPIO10 M7 DBVDD I/O Audio interface 2 bit clock/GPIO10 PU/PD/K/H/ Z/C/OD GPIO10 input with bus-keeper AIF2LRCLK/ GPIO12 K7 DBVDD I/O Audio interface 2 left/right clock/GPIO12 PU/PD/K/H/ Z/C/OD GPIO12 input with bus-keeper AIF2RXDAT/ GPIO11 P7 DBVDD I/O Audio interface 2 RX digital audio data/GPIO11 PU/PD/K/H/ C/OD GPIO11 input with bus-keeper AIF2TXDAT/ GPIO9 T7 DBVDD I/O Audio interface 2 TX digital audio data/GPIO9 PU/PD/K/H/ GPIO9 input with Z/C/OD bus-keeper AIF3BCLK/ GPIO14 N8 DBVDD I/O Audio interface 3 bit clock/GPIO14. If the JTAG interface is configured, this pin provides the TCK input connection. PU/PD/K/H/ Z/C/OD GPIO14 input with bus-keeper AIF3LRCLK/ GPIO16 J6 DBVDD I/O Audio interface 3 left/right clock/GPIO16 PU/PD/K/H/ Z/C/OD GPIO16 input with bus-keeper AIF3RXDAT/ GPIO15 R8 DBVDD I/O Audio interface 3 RX digital audio data/GPIO15. If the JTAG interface is configured, this pin provides the TDI input connection. PU/PD/K/H/ C/OD GPIO15 input with bus-keeper AIF3TXDAT/ GPIO13 J8 DBVDD I/O Audio interface 3 TX digital audio data/GPIO13. If the JTAG interface is configured, this pin provides the TMS input connection. PU/PD/K/H/ Z/C/OD GPIO13 input with bus-keeper CIFMISO L8 DBVDD O Control interface (SPI) Master In Slave Out data. The CIFMISO is high impedance if CIF1SS is not asserted. Z/C Output CIFMOSI/SDA T9 DBVDD I/O Control interface (SPI) Master Out Slave In data/ Control interface (I2C) data input/output. H/OD Input CIFSCLK P9 DBVDD I Control interface clock input H Input CIFSS K9 DBVDD I Control interface (SPI) slave select (SS) H Input CIFMODE G8 DBVDD I Control interface mode select H Input GPIO1 H9 DBVDD I/O GPIO1 PU/PD/K/H/ GPIO1 input with C/OD bus-keeper GPIO2 H7 DBVDD I/O GPIO2 PU/PD/K/H/ GPIO2 input with C/OD bus-keeper IRQ H11 DBVDD O Interrupt request (IRQ) output (default is active low) MCLK1 P11 DBVDD I Master clock 1 MCLK2 M11 DBVDD I Master clock 2 H Input MCLK3 L10 DBVDD I Master clock 3 H Input RESET J12 DBVDD I Digital reset input (active low) Pin Name Pin Description Digital Pad State at Reset 1 Attributes C/OD Output H Input PU/PD/K/H Input with pull-up SLIMCLK M9 DBVDD I/O SLIMbus clock I/O H/C Input SLIMDAT1 N10 DBVDD I/O SLIMbus data I/O H/C Input SLIMDAT2 R10 DBVDD I/O SLIMbus data I/O H/C Input SPKCLK/ GPIO3 J10 DBVDD I/O Digital speaker (PDM) clock output/GPIO3 PU/PD/K/H/ GPIO3 input with C/OD bus-keeper SPKDAT/ GPIO4 K11 DBVDD I/O Digital speaker (PDM) data output/GPIO4 PU/PD/K/H/ GPIO4 input with C/OD bus-keeper TDO F7 DBVDD O JTAG data output TRST D7 DBVDD I JTAG test access port reset (active low) AGND1 R2 — — Analog ground (return path for AVDD1) AGND2 G12 — — Analog ground (return path for AVDD2) — — AVDD1 T3 — — Analog supply — — AVDD2 H13 — — Analog supply — — C Output PD/H Input with pull-down — — Supply 7 DS1162F1 CS42L92 1.2 Pin Descriptions Table 1-1. Pin Descriptions (Cont.) PU = Pull-up, PD = Pull-down, K = Bus keeper, H = Hysteresis on CMOS input, Z = Hi-Z (High impedance), C = CMOS, OD = Open drain. Pin Name CPGND Pin # Power Supply I/O B3 — — Pin Description Digital Pad State at Reset 1 Attributes Charge pump ground (return path for CPVDD1, CPVDD2) — — CPVDD1 A2 — — Supply for Charge Pump 1 and Charge Pump 2 — — CPVDD2 D3 — — Secondary supply for Charge Pump 1 — — DBVDD T11 — — Digital buffer (I/O) supply — — DCVDD P13, T5 — — Digital core supply — — N12, P5, R12, T13 — — Digital ground (return path for DCVDD and DBVDD) — — FLLGND L12 — — Analog ground (return path for FLLVDD) — — FLLVDD M13 — — Analog FLL supply — — SUBGND K13, R4 — — Substrate ground — — — — DGND No Connect NC T1 — — — 1.Note that the default conditions described are not valid if modified by the boot sequence or by a wake-up control sequence. 2.The analog input functions on these pins are referenced to the MICVDD power domain. The digital input/output functions are referenced to the MICVDD or MICBIASn power domain, as selected by the applicable INx_DMIC_SUP field. 8 DS1162F1 CS42L92 2 Typical Connection Diagram 2 Typical Connection Diagram 1.2 V AGND1 AGND2 DGND CPGND FLLGND SUBGND 1.8 V CPVDD2 120  2.2 F VREFC CIF1SS FLLVDD DCVDD (pin P13) DCVDD (pin T5) CIF1SCLK Control Interface CIF1MOSI/SDA CIF1MISO CIFMODE 4.7 F 2 x 1.0 F 4.7 F MCLK1 MCLK2 MCLK3 CPVDD1 AVDD1 AVDD2 DBVDD CS42L92 Master Clocks RESET Reset Control Interrupt Output IRQ 4.7 F 0.1 F 2 x 1.0 F GPIO1 GPIO2 SLIMCLK SLIMDAT1 SLIMbus Interface SLIMDAT2 GPSW1P GPSW1N GPSW2P GPSW2N AIF1BCLK AIF1LRCLK Audio Interface 1 AIF1RXDAT CP1C1A AIF1TXDAT 4.7 F CP1VOUT1P AIF2LRCLK 4.7 F CP1VOUT1N AIF2RXDAT CP1C2A AIF2TXDAT 2.2 F CP1C2B AIF3BCLK 4.7 F CP1VOUT2P AIF3LRCLK Audio Interface 3 2.2 F CP1C1B AIF2BCLK Audio Interface 2 GPIO 4.7 F CP1VOUT2N AIF3RXDAT CP2CA AIF3TXDAT 470 nF CP2CB CP2VOUT MICBIAS1A Pseudodifferential Microphone Connection 4.7 F MICDET1/HPOUTFB1 2.2 k 1 F 1 F IN1BLP IN1ALP/DMICDAT1 IN1BLN IN1ALN/DMICCLK1 MICDET2/HPOUTFB2 JACKDET1 JACKDET2 JACKDET3 Jack-Detect Inputs HPOUT1L Headphone HPOUT1R MICDET2/HPOUTFB2 MICBIAS2A VDD CHAN GND Stereo Digital Microphone Connection VDD CHAN GND DAT CLK DMIC IN1BR IN1ARP/DMICDAT3 IN1ARN/DMICCLK3 (Note: HPOUT1 ground connection close to headset jack ) HPDET1 HPDET2 HPOUT2L Line Output HPOUT2R DAT CLK DMIC MICDET3/HPOUTFB3 (Note: HPOUT2 ground connection close to headset jack ) MICDET4/HPOUTFB4 HPOUT3L Line Output HPOUT3R 1 F IN2BL IN2ALP/DMICDAT2 IN2ALN/DMICCLK2 Stereo Single-Ended Line Connection HPOUT4L HPOUT4R IN2BR MICDET5/HPOUTFB5 IN2ARP/DMICDAT4 IN2ARN/DMICCLK4 1 F Analog and Digital Inputs MICBIAS1A MICBIAS1B MICBIAS1C MICBIAS1D MICBIAS2A MICBIAS2B Bias/Supplies for Microphones and External Accessory Detection SPKCLK SPKDAT Earpiece Speaker Outputs HPOUT1–HPOUT4 can be configured as stereo pairs or differential mono. Digital Speaker (PDM) interface MICVDD 4.7 F TRST Figure 2-1. Typical Connection Diagram 9 DS1162F1 CS42L92 3 Characteristics and Specifications 3 Characteristics and Specifications Table 3-1 defines parameters as they are characterized in this section. Table 3-1. Parameter Definitions Parameter Channel separation Common-mode rejection ratio (CMRR) Dynamic range (DR) Power-supply rejection ratio (PSRR) Signal-to-noise ratio (SNR) Total harmonic distortion (THD) Total harmonic distortion plus noise (THD+N) Definition Left-to-right and right-to-left channel separation is the difference in level between the active channel (driven to maximum full scale output) and the measured signal level in the idle channel at the test signal frequency. The active channel is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the associated idle channel. The ratio of a specified input signal (applied to both sides of a differential input), relative to the output signal that results from it. A measure of the difference between the maximum full scale output signal and the sum of all harmonic distortion products plus noise, with a low-level input signal applied. Typically, an input signal level 60 dB below full scale is used. The ratio of a specified power supply variation relative to the output signal that results from it. PSRR is measured under quiescent signal path conditions. A measure of the difference in level between the maximum full scale output signal and the output with no input signal applied. The ratio of the RMS sum of the harmonic distortion products in the specified bandwidth 1 relative to the RMS amplitude of the fundamental (i.e., test frequency) output. The ratio of the RMS sum of the harmonic distortion products plus noise in the specified bandwidth 1 relative to the RMS amplitude of the fundamental (i.e., test frequency) output. 1.All performance measurements are specified with a 20-kHz, low-pass brick-wall filter and, where noted, an A-weighted filter. The low-pass filter removes out-of-band noise. Table 3-2. Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. Parameter Symbol Minimum Maximum DCVDD [1], FLLVDD [1] –0.3 V 1.6 V AVDD [2], CPVDD1, CPVDD2 –0.3 V 2.5 V DBVDD, MICVDD –0.3 V 5.0 V Voltage range digital inputs DBVDD domain — SUBGND – 0.3 V DBVDD + 0.3 V DMICDAT1–DMICDAT2 — SUBGND – 0.3 V MICVDD + 0.3 V SUBGND – 0.3 V MICVDD + 0.3 V Voltage range analog inputs IN1ARx, IN2Axx, IN2Bx SUBGND – 0.9 V MICVDD + 0.3 V IN1ALx, IN1BLx, IN1BR SUBGND – 0.3 V MICVDD + 0.3 V MICDETn 3 HPOUTFBn 3 SUBGND – 0.3 V SUBGND + 0.3 V JACKDET1, HPDET1, HPDET2 CP1VOUT2N – 0.3 V [5] AVDD + 0.3 V SUBGND – 0.3 V JACKDET2 [4], JACKDET3 [4] MICVDD + 0.3 V GPSWnP, GPSWnN SUBGND – 0.3 V MICVDD + 0.3 V SUBGND – 0.3V SUBGND + 0.3V Ground AGND 6, DGND, CPGND, FLLGND Operating temperature range TA –40ºC +85ºC –40ºC +125ºC Operating junction temperature TJ Storage temperature after soldering — –65ºC +150ºC ESD-sensitive device. The CS42L92 is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. This device is qualified to current JEDEC ESD standards. Supply voltages 1.The DCVDD and FLLVDD pins should be tied to a common supply rail. The associated power domain is referred to as DCVDD. 2.The AVDD1 and AVDD2 pins should be tied together. The associated power domain is referred to as AVDD. 3.The MICDETn and HPOUTFBn functions share common pins. The absolute maximum rating varies according to the applicable function of each pin. The HPOUTFBn ratings are applicable if any of the HPn_GND_SEL bits select the respective pin for HPOUT ground feedback. 4.If AVDD > MICVDD (e.g., if LDO2 is disabled), the maximum JACKDET2/JACKDET3 voltage is AVDD + 0.3 V. 5.CP1VOUT2N is an internal supply, generated by the CS42L92 charge pump (CP1). Its voltage can vary between CPGND and –CPVDD1. 6.The AGND1 and AGND2 pins should be tied together. The associated ground domain is referred to as AGND. 10 DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-3. Recommended Operating Conditions Parameter Digital supply range 1 Digital supply range Charge pump supply range Symbol Minimum Typical DCVDD [2], FLLVDD [3] 1.14 1.2 DBVDD 1.71 — CPVDD1 1.71 1.8 CPVDD2 1.14 1.2 AVDD 1.71 1.8 Analog supply range 5,6 Mic bias supply 7 MICVDD 0.9 2.5 Ground 8 DGND, AGND, CPGND, FLLGND, SUBGND — 0 Power supply rise time 9,10 DCVDD 10 — All other supplies 10 — –40 — Operating temperature range TA Note: There are no power sequencing requirements; the supplies may be enabled and disabled in any order. Core and FLL I/O CPVDD1 CPVDD2 Maximum 1.26 3.6 [4] 1.89 1.26 1.89 3.78 — 2000 — 85 Units V V V V V V V s s ºC 1.The DCVDD and FLLVDD pins should be tied to a common supply rail. The associated power domain is referred to as DCVDD. 2.Sleep mode is supported for when DCVDD is below the limits noted, provided that AVDD and DBVDD are present. 3.It is recommended to connect a 120- resistor in series with the FLLVDD pin connection. Note that the minimum voltage limit applies at the supply end of the 120- resistor in this case. 4.If the SLIMbus interface is enabled, the maximum DBVDD voltage is 1.98 V. 5.The AVDD1 and AVDD2 pins should be tied together. The associated power domain is referred to as AVDD. 6.The AGND1 and AGND2 pins should be tied together. The associated ground domain is referred to as AGND. 7.An internal charge pump and LDO (powered by CPVDD1) provide the mic bias supply; the MICVDD pin must not be connected to an external supply. 8.The impedance between DGND, AGND, CPGND, FLLGND, and SUBGND must not exceed 0.1 . 9.If the DCVDD rise time exceeds 2 ms, RESET must be asserted during the rise and held asserted until after DCVDD is within the recommended operating limits. 10.The specified minimum power supply rise times assume a minimum decoupling capacitance of 100 nF per pin. However, Cirrus Logic strongly advises that the recommended decoupling capacitors are present on the PCB and that appropriate layout guidelines are observed. The specified minimum power supply rise times also assume a maximum PCB inductance of 10 nH between decoupling capacitor and pin. Table 3-4. Analog Input Signal Level—IN1xx, IN2xx Test conditions (unless specified otherwise): AVDD = 1.8V; with the exception of the condition noted, the following electrical characteristics are valid across the full range of recommended operating conditions. Parameter Minimum Typical Maximum Units Full-scale input signal level (0 dBFS output) Single-ended PGA input, 0 dB PGA gain — 0.5 — VRMS dBV — –6 — Differential PGA input, 0 dB PGA gain — 1 — VRMS dBV — 0 — Notes: • The full-scale input signal level is also the maximum analog input level, before clipping occurs. • The maximum input signal level is reduced by 6 dB if mid-power operation is selected (INn_OSR = 100); the maximum signal level corresponds to –6 dBFS at the respective ADC outputs in this case. • The full-scale input signal level changes in proportion with AVDD. For differential input, it is calculated as AVDD / 1.8. • A 1.0VRMS differential signal equates to 0.5VRMS/–6dBV per input. • A sinusoidal input signal is assumed. Table 3-5. Analog Input Pin Characteristics Test conditions (unless specified otherwise): TA = +25ºC; with the exception of the condition noted, the following electrical characteristics are valid across the full range of recommended operating conditions. Input resistance Input capacitance Parameter Minimum Single-ended PGA input, All PGA gain settings 9 Differential PGA input, All PGA gain settings 17 — Typical 11 22 — Maximum — — 5 Units k k pF Typical 0 31 1 Maximum — — — Units dB dB dB Table 3-6. Analog Input Gain—Programmable Gain Amplifiers (PGAs) The following electrical characteristics are valid across the full range of recommended operating conditions. Parameter Minimum programmable gain Maximum programmable gain Programmable gain step size 11 Minimum — — Guaranteed monotonic — DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-7. Digital Input Signal Level—DMICDATn The following electrical characteristics are valid across the full range of recommended operating conditions. Parameter Full-scale input level 1 0 dBFS digital core input, 0 dB gain Minimum — Typical –6 Maximum — Units dBFS 1. The digital input signal level is measured in dBFS, where 0 dBFS is a signal level equal to the full-scale range (FSR) of the PDM input. The FSR is defined as the amplitude of a 1-kHz sine wave whose positive and negative peaks are represented by the maximum and minimum digital codes respectively—this is the largest 1-kHz sine wave that can fit in the digital output range without clipping. Table 3-8. Output Characteristics The following electrical characteristics are valid across the full range of recommended operating conditions. Parameter Minimum Line/headphone/earpiece Load resistance Normal operation, Single-Ended Mode 6 output driver (HPOUTnL, Normal operation, Differential (BTL) Mode 15 HPOUTnR) Device survival with load applied indefinitely 0 Load capacitance Single-Ended Mode — Differential (BTL) Mode — 0 dBFS digital core output, 0 dB gain — Digital speaker output Full-scale output level 1 (SPKDAT) Typical — — — — — –6 Maximum — — — 500 200 — Units    pF pF dBFS 1.The digital output signal level is measured in dBFS, where 0 dBFS is a signal level equal to the full-scale range (FSR) of the PDM output. The FSR is defined as the amplitude of a 1-kHz sine wave whose positive and negative peaks are represented by the maximum and minimum digital codes respectively—this is the largest 1-kHz sine wave that can fit in the digital output range without clipping. Table 3-9. Input/Output Path Characteristics Test conditions (unless specified otherwise): DBVDD = CPVDD1 = AVDD = 1.8 V, DCVDD = FLLVDD = CPVDD2 = 1.2 V; MICVDD = 3.1 V (powered from internal LDO); TA = +25ºC; 1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data. Parameter Line/headphone/earpiece output DC offset at Load Single-ended mode driver (HPOUTnL, HPOUTnR) Differential (BTL) mode Analog input paths (IN1xx, SNR (A-weighted), defined in Table 3-1 20 Hz to 20 kHz, 48 kHz sample rate IN2xx) to ADC (Differential Input 20 Hz to 8 kHz, 16 kHz sample rate Mode) THD, defined in Table 3-1 –1 dBV input THD+N, defined in Table 3-1 –1 dBV input Channel separation (L/R), defined in Table 3-1 100 Hz to 10 kHz Input-referred noise floor A-weighted, PGA gain = +20 dB CMRR, defined in Table 3-1 PGA gain = +30 dB PGA gain = 0 dB PSRR (DBVDD, CPVDD1, AVDD), defined 100 mV (peak-peak) 217 Hz in Table 3-1 100 mV (peak-peak) 10 kHz PSRR (DCVDD, FLLVDD, CPVDD2), 100 mV (peak-peak) 217 Hz defined in Table 3-1 100 mV (peak-peak) 10 kHz Analog input paths (IN1xx, SNR (A-weighted), defined in Table 3-1 20 Hz to 20 kHz, 48 kHz sample rate IN2xx) to ADC (Single-Ended 20 Hz to 8 kHz, 16 kHz sample rate Input Mode) THD, defined in Table 3-1 –7dB V input THD+N, defined in Table 3-1 –7dB V input Channel separation (L/R), defined in Table 3-1 100 Hz to 10 kHz Input-referred noise floor A-weighted, PGA gain = +20 dB PSRR (DBVDD, CPVDD1, AVDD), defined 100 mV (peak-peak) 217 Hz in Table 3-1 100 mV (peak-peak) 10 kHz PSRR (DCVDD, FLLVDD, CPVDD2), 100 mV (peak-peak) 217 Hz defined in Table 3-1 100 mV (peak-peak) 10 kHz 12 Min — — 91 — — — — — — — — — — — 87 — — — — — — — — — Typ Max Units 50 — V 75 — V 99 — dB 104 — dB –87 — dB –88 –79 dB 109 — dB 2.6 — VRMS 83 — dB 72 — dB 99 — dB 84 — dB 100 — dB 82 — dB 98 — dB 108 — dB –84 — dB –83 –78 dB 107 — dB 4 — VRMS 76 — dB 52 — dB 96 — dB 87 — dB DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-9. Input/Output Path Characteristics (Cont.) Test conditions (unless specified otherwise): DBVDD = CPVDD1 = AVDD = 1.8 V, DCVDD = FLLVDD = CPVDD2 = 1.2 V; MICVDD = 3.1 V (powered from internal LDO); TA = +25ºC; 1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data. Analog input paths (IN1xx, IN2xx) to ADC (Differential Input, Mid Power Mode) DAC to line output (HPOUT1x, HPOUT2x; Load = 10 k, 50 pF) DAC to headphone output (HPOUT1x, HPOUT2x; RL = 32 ) DAC to headphone output (HPOUT1x, HPOUT2x; RL = 16 ) DAC to headphone output (HPOUT1L+HPOUT1R, HPOUT2L+HPOUT2R; Stereo differential output, RL = 32  BTL) 13 Parameter SNR, defined in Table 3-1 THD, defined in Table 3-1 THD+N, defined in Table 3-1 Channel separation (L/R), defined in Table 3-1 Input-referred noise floor CMRR, defined in Table 3-1 PSRR (DBVDD, CPVDD1, AVDD), defined in Table 3-1 PSRR (DCVDD, FLLVDD, CPVDD2), defined in Table 3-1 Full-scale output signal level A-weighted –7 dBV input –7 dBV input 100 Hz to 10 kHz A-weighted, PGA gain = +20 dB PGA gain = +30 dB PGA gain = 0 dB 100 mV (peak-peak) 217 Hz 100 mV (peak-peak) 10 kHz 100 mV (peak-peak) 217 Hz 100 mV (peak-peak) 10 kHz 0 dBFS input SNR, defined in Table 3-1 A-weighted, output signal = 1 VRMS Dynamic range, defined in Table 3-1 A-weighted, –60 dBFS input THD+N, defined in Table 3-1 0 dBFS input Channel separation (L/R), defined in Table 3-1 100 Hz to 10 kHz Output noise floor A-weighted PSRR (DBVDD, CPVDD1, AVDD), 100 mV (peak-peak) 217 Hz defined in Table 3-1 100 mV (peak-peak) 10 kHz PSRR (DCVDD, FLLVDD, CPVDD2), 100 mV (peak-peak) 217 Hz defined in Table 3-1 100 mV (peak-peak) 10 kHz Maximum output power 0.1% THD+N SNR, defined in Table 3-1 A-weighted, output signal = 1 VRMS Dynamic range, defined in Table 3-1 A-weighted, –60 dBFS input THD+N, defined in Table 3-1 PO = 20 mW THD+N, defined in Table 3-1 PO = 2 mW Channel separation (L/R), defined in Table 3-1 100 Hz to 10 kHz Output noise floor A-weighted PSRR (DBVDD, CPVDD1, AVDD), 100 mV (peak-peak) 217 Hz defined in Table 3-1 100 mV (peak-peak) 10 kHz PSRR (DCVDD, FLLVDD, CPVDD2), 100 mV (peak-peak) 217 Hz defined in Table 3-1 100 mV (peak-peak) 10 kHz Maximum output power 0.1% THD+N SNR, defined in Table 3-1 A-weighted, output signal = 1 VRMS Dynamic range, defined in Table 3-1 A-weighted, –60 dBFS input THD+N, defined in Table 3-1 PO = 20 mW THD+N, defined in Table 3-1 PO = 2 mW Channel separation (L/R), defined in Table 3-1 100 Hz to 10 kHz Output noise floor A-weighted PSRR (DBVDD, CPVDD1, AVDD), 100 mV (peak-peak) 217 Hz defined in Table 3-1 100 mV (peak-peak) 10 kHz PSRR (DCVDD, FLLVDD, CPVDD2), 100 mV (peak-peak) 217 Hz defined in Table 3-1 100 mV (peak-peak) 10 kHz Maximum output power 0.1% THD+N SNR, defined in Table 3-1 A-weighted, output signal = 2 VRMS Dynamic range, defined in Table 3-1 A-weighted, –60 dBFS input THD+N, defined in Table 3-1 PO = 75 mW THD+N, defined in Table 3-1 PO = 5 mW Output noise floor A-weighted PSRR (DBVDD, CPVDD1, AVDD), 100 mV (peak-peak) 217 Hz defined in Table 3-1 100 mV (peak-peak) 10 kHz PSRR (DCVDD, FLLVDD, CPVDD2), 100 mV (peak-peak) 217 Hz defined in Table 3-1 100 mV (peak-peak) 10 kHz Min — — — — — — — — — — — — — — 108 — — — — — — — — — 108 — — — — — — — — — — 108 — — — — — — — — — — — — — — — — — — Typ 88 –81 –80 96 4.79 73 81 93 75 97 81 1 0 125 117 –100 95 0.7 105 81 108 81 33 125 117 –100 –96 105 0.6 126 103 128 105 46 125 117 –97 –95 97 0.6 127 107 127 108 109 127 115 –100 –97 0.36 120 90 120 90 Max — — — — — — — — — — — — — — — –90 — — — — — — — — — –90 — — — — — — — — — — –90 — — — — — — — — — — — — — — — — — Units dB dB dB dB VRMS dB dB dB dB dB dB VRMS dBV dB dB dB dB VRMS dB dB dB dB mW dB dB dB dB dB VRMS dB dB dB dB mW dB dB dB dB dB VRMS dB dB dB dB mW dB dB dB dB VRMS dB dB dB dB DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-9. Input/Output Path Characteristics (Cont.) Test conditions (unless specified otherwise): DBVDD = CPVDD1 = AVDD = 1.8 V, DCVDD = FLLVDD = CPVDD2 = 1.2 V; MICVDD = 3.1 V (powered from internal LDO); TA = +25ºC; 1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data. DAC to line output (HPOUT3x, HPOUT4x; Load = 10 k, 50 pF) DAC to headphone output (HPOUT3x, HPOUT4x; RL = 32 ) DAC to headphone output (HPOUT3x, HPOUT4x; RL = 16 ) DAC to earpiece output (HPOUT3L+HPOUT3R, HPOUT4L+HPOUT4R, Mono Mode, RL = 32  BTL) 14 Parameter Full-scale output signal level Min 0 dBFS input — — SNR, defined in Table 3-1 A-weighted, output signal = 1 VRMS 115 Dynamic range, defined in Table 3-1 A-weighted, –60 dBFS input 107 THD, defined in Table 3-1 0 dBFS input — THD+N, defined in Table 3-1 0 dBFS input — Channel separation (L/R), defined in Table 3-1 100 Hz to 10 kHz — Output noise floor A-weighted — PSRR (DBVDD, CPVDD1, AVDD), 100 mV (peak-peak) 217 Hz — defined in Table 3-1 100 mV (peak-peak) 10 kHz — PSRR (DCVDD, FLLVDD, CPVDD2), 100 mV (peak-peak) 217 Hz — defined in Table 3-1 100 mV (peak-peak) 10 kHz — Maximum output power 0.1% THD+N — SNR, defined in Table 3-1 A-weighted, output signal = 1 VRMS — Dynamic range, defined in Table 3-1 A-weighted, –60 dBFS input 107 THD, defined in Table 3-1 PO = 20 mW — THD+N, defined in Table 3-1 PO = 20 mW — THD, defined in Table 3-1 PO = 2 mW — THD+N, defined in Table 3-1 PO = 2 mW — Channel separation (L/R), defined in Table 3-1 100 Hz to 10 kHz — Output noise floor A-weighted — PSRR (DBVDD, CPVDD1, AVDD), 100 mV (peak-peak) 217 Hz — defined in Table 3-1 100 mV (peak-peak) 10 kHz — PSRR (DCVDD, FLLVDD, CPVDD2), 100 mV (peak-peak) 217 Hz — defined in Table 3-1 100 mV (peak-peak) 10 kHz — Maximum output power 0.1% THD+N — SNR, defined in Table 3-1 A-weighted, output signal = 1 VRMS — Dynamic range, defined in Table 3-1 A-weighted, –60 dBFS input 107 THD, defined in Table 3-1 PO = 20 mW — THD+N, defined in Table 3-1 PO = 20 mW — THD, defined in Table 3-1 PO = 2 mW — THD+N, defined in Table 3-1 PO = 2 mW — Channel separation (L/R), defined in Table 3-1 100 Hz to 10 kHz — Output noise floor A-weighted — PSRR (DBVDD, CPVDD1, AVDD), 100 mV (peak-peak) 217 Hz — defined in Table 3-1 100 mV (peak-peak) 10 kHz — PSRR (DCVDD, FLLVDD, CPVDD2), 100 mV (peak-peak) 217 Hz — defined in Table 3-1 100 mV (peak-peak) 10 kHz — Maximum output power 0.1% THD+N — SNR, defined in Table 3-1 A-weighted, output signal = 2 VRMS — Dynamic range, defined in Table 3-1 A-weighted, –60 dBFS input 110 THD, defined in Table 3-1 PO = 75 mW — THD+N, defined in Table 3-1 PO = 75 mW — THD, defined in Table 3-1 PO = 5 mW — THD+N, defined in Table 3-1 PO = 5 mW — Output noise floor A-weighted — PSRR (DBVDD, CPVDD1, AVDD), 100 mV (peak-peak) 217 Hz — defined in Table 3-1 100 mV (peak-peak) 10 kHz — PSRR (DCVDD, FLLVDD, CPVDD2), 100 mV (peak-peak) 217 Hz — defined in Table 3-1 100 mV (peak-peak) 10 kHz — Typ 1 0 125 115 –92 –91 90 0.63 110 78 99 69 33 124 115 –93 –90 –94 –92 102 0.63 127 100 120 95 46 124 115 –94 –89 –91 –89 100 0.63 128 104 125 97 115 129 120 –99 –97 –98 –94 0.36 127 106 125 101 Max — — — — — –85 — — — — — — — — — — –85 — — — — — — — — — — — — –80 — — — — — — — — — — — — — — — — — — — — Units VRMS dBV dB dB dB dB dB VRMS dB dB dB dB mW dB dB dB dB dB dB dB VRMS dB dB dB dB mW dB dB dB dB dB dB dB VRMS dB dB dB dB mW dB dB dB dB dB dB VRMS dB dB dB dB DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-9. Input/Output Path Characteristics (Cont.) Test conditions (unless specified otherwise): DBVDD = CPVDD1 = AVDD = 1.8 V, DCVDD = FLLVDD = CPVDD2 = 1.2 V; MICVDD = 3.1 V (powered from internal LDO); TA = +25ºC; 1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data. DAC to earpiece output (HPOUT3L+HPOUT3R, HPOUT4L+HPOUT4R, Mono Mode, RL = 16  BTL) Parameter Maximum output power SNR, defined in Table 3-1 Dynamic range, defined in Table 3-1 THD, defined in Table 3-1 THD+N, defined in Table 3-1 THD, defined in Table 3-1 THD+N, defined in Table 3-1 Output noise floor PSRR (DBVDD, CPVDD1, AVDD), defined in Table 3-1 PSRR (DCVDD, FLLVDD, CPVDD2), defined in Table 3-1 0.1% THD+N A-weighted, output signal = 2 VRMS A-weighted, –60 dBFS input PO = 75 mW PO = 75 mW PO = 5 mW PO = 5 mW A-weighted 100 mV (peak-peak) 217 Hz 100 mV (peak-peak) 10 kHz 100 mV (peak-peak) 217 Hz 100 mV (peak-peak) 10 kHz Min — — 110 — — — — — — — — — Typ Max Units 138 — mW 128 — dB 120 — dB –97 — dB –95 — dB –96 — dB –94 — dB 0.4 — VRMS 125 — dB 106 — dB 125 — dB 101 — dB Table 3-10. Digital Input/Output The following electrical characteristics are valid across the full range of recommended operating conditions. Digital I/O (except DMICDATn and DMICCLKn) 1,2 DMIC I/O (DMICDATn and DMICCLKn) 2,3 GPIOn Parameter Input HIGH level Minimum VDBVDD = 1.71–1.98 V 0.75 DBVDD VDBVDD = 2.5 V ±10% 0.8 DBVDD VDBVDD = 3.3 V ±10% 0.7 DBVDD — Input LOW level VDBVDD = 1.71–1.98 V VDBVDD = 2.5 V ±10% — VDBVDD = 3.3 V ±10% — VDBVDD = 1.71–1.98 V 0.75 DBVDD Output HIGH level VDBVDD = 2.5 V ±10% 0.65 DBVDD (IOH = 1 mA) VDBVDD = 3.3 V ±10% 0.7 DBVDD VDBVDDn = 1.71–1.98 V — Output LOW level VDBVDDn = 2.5 V ±10% — (IOL = 1mA) VDBVDDn = 3.3 V ±10% — Input capacitance — Input leakage –10 Pull-up/pull-down resistance (where applicable) 35 DMICDATn input HIGH level 0.65  VSUP DMICDATn input LOW level — DMICCLKn output HIGH level IOH = 1 mA 0.8  VSUP — DMICCLKn output LOW level IOL = –1 mA Input capacitance — Input leakage –1 Clock output frequency GPIO pin as OPCLK or FLL output — Typical — — — — — — — — — — — — — — — — — — 25 — — Maximum — — — 0.3 DBVDD 0.25 DBVDD 0.2 DBVDD — — — 0.25 DBVDD 0.3 DBVDD 0.15 DBVDD 5 10 55 — 0.35  VSUP — 0.2  VSUP 1 50 Units V V V V V V V V V V V V pF A k V V V V pF A MHz 1.Digital I/O is referenced to DBVDD. 2.Note that digital input pins should not be left unconnected or floating. 3.DMICDATn and DMICCLKn are referenced to a selectable supply, VSUP, according to the INn_DMIC_SUP fields. 15 DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-11. Miscellaneous Characteristics Test conditions (unless specified otherwise): DBVDD = CPVDD1 = AVDD = 1.8 V, DCVDD = FLLVDD = CPVDD2 = 1.2 V; MICVDD = 3.1 V (powered from internal LDO); TA = +25ºC; 1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data. Parameter Microphone bias Minimum bias voltage 2 Maximum bias voltage (MICBIASnx) 1 Bias voltage output step size Bias voltage accuracy Regulator Mode (MICBn_BYPASS = 0), VMICVDD – VMICBIAS >200 mV Bias current 3 Bypass Mode (MICBn_BYPASS = 1) Output noise density Regulator Mode (MICBn_BYPASS = 0), MICBn_LVL = 0x4, Load current = 1 mA, Measured at 1 kHz Integrated noise voltage Regulator Mode (MICBn_BYPASS = 0), MICBn_LVL = 0x4, Load current = 1 mA, 100 Hz to 7 kHz, A-weighted PSRR (DBVDD, CPVDD1, AVDD), defined in Table 3-1 100 mV (peak-peak) 217 Hz 100 mV (peak-peak) 10 kHz PSRR (DCVDD, FLLVDD, CPVDD2), defined in Table 3-1 100 mV (peak-peak) 217 Hz 100 mV (peak-peak) 10 kHz Regulator Mode (MICBn_BYPASS = 0), MICBn_EXT_CAP = 0 Load capacitance 3 Regulator Mode (MICBn_BYPASS = 0), MICBn_EXT_CAP = 1 Output discharge resistance MICBnx_ENA = 0, MICBnx_DISCH = 1 Switch closed, I = 1 mA General-purpose Switch resistance Switch open switch 4 External Headphone detection load impedance range: HPD_IMPEDANCE_RANGE = 00 Accessory Detection via HPDET1 (HPD_SENSE_ HPD_IMPEDANCE_RANGE = 01 Detect SEL = 0100) or HPDET2 (HPD_SENSE_ HPD_IMPEDANCE_RANGE = 10 SEL = 0101) HPD_IMPEDANCE_RANGE = 11 Headphone detection load impedance range: Detection via MICDETn or JACKDETn pins Headphone detection accuracy: HPD_IMPEDANCE_RANGE = 01 or 10 (HPD_DACVAL, HPDETn pin) HPD_IMPEDANCE_RANGE = 00 or 11 Headphone detection accuracy (HPD_LVL, MICDETn or JACKDETn pin) for MICDn_LVL[0] = 1 Microphone impedance detection range: for MICDn_LVL[1] = 1 (MICDn_ADC_MODE = 0, 2.2 k ±2% MICBIAS resistor. 5) for MICDn_LVL[2] = 1 for MICDn_LVL[3] = 1 for MICDn_LVL[8] = 1 Jack-detection input threshold voltage Detection on JACKDET1, Jack insertion (JACKDETn) Detection on JACKDET1, Jack removal Detection on JACKDET2/3, Jack insertion Detection on JACKDET2/3, Jack removal MICVDD Charge Output voltage Pump and Programmable output voltage step size LDO2_VSEL = 0x00–0x14 (0.9–1.4V ) Regulator (CP2 LDO2_VSEL = 0x14 to 0x27 (1.4 V–3.3 V) and LDO2) Maximum output current Start-up time 4.7 F on MICVDD Frequency-Lock Output frequency ed Loop (FLL1, Lock Time FREF = 32 kHz, FFLL = 49.152 MHz FLL2) FREF = 12 MHz, FFLL = 49.152 MHz RESET pin input RESET input pulse width 6 Min — — — –5% — — — Typ 1.5 2.8 0.1 — — — 50 — 4 Max Units — V — V — V +5% V 2.4 mA 5.0 mA — nV/Hz — VRMS — 105 — — 95 — — 99 — — 92 — — — 50 0.1 1.0 10 — 2 — — 40 — — 100 — 4 — 30 8 — 100 100 — 1000 1000 — 10000 400 — 6000 dB dB dB dB pF F k  M      –5 — +5 –10 — +10 –20 — +20 0 — 70 110 — 180 210 — 290 360 — 680 1000 — 30000 — 0.9 — — 1.65 — — 0.27 — — 0.9 — 0.9 2.7 3.3 — 25 — — 100 — — 8 — — 1.0 2.5 45 — 50 — 5 — — 1 — 1 — — % % %      V V V V V mV mV mA ms MHz ms ms s 1.No capacitor on MICBIASnx. In Regulator Mode, it is required that VMICVDD – VMICBIAS > 200 mV. 2.Regulator Mode (MICBn_BYPASS = 0), Load current  1.0 mA. 3.Bias current and load capacitance specifications are per MICBIAS generator (MICBIAS1 or MICBIAS2). 4.The GPSWnN pin voltage must not exceed GPSWnP + 0.3 V. See Table 3-2 for voltage limits applicable to the GPSWnP and GPSWnN pins. 5.These characteristics assume no other component is connected to MICDETn. 6.To trigger a hardware reset, the RESET input must be asserted for longer than this duration. 16 DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-12. Device Reset Thresholds The following electrical characteristics are valid across the full range of recommended operating conditions. Parameter Symbol Minimum Typical Maximum Units VAVDD — — 1.66 V VAVDD rising VAVDD falling 1.06 — 1.44 V VDCVDD — — 1.04 V DCVDD reset threshold VDCVDD rising VDCVDD falling 0.49 — 0.70 V VDBVDD — — 1.66 V DBVDD Reset threshold VDBVDD rising VDBVDD falling 1.06 — 1.44 V Note: The reset thresholds are derived from simulations only, across all operational and process corners. Device performance is not assured outside the voltage ranges defined in Table 3-3. AVDD reset threshold Table 3-13. System Clock and Frequency-Locked Loop (FLL) The following timing information is valid across the full range of recommended operating conditions. Parameter Minimum MCLK as input to FLL, FLLn_REFCLK_DIV = 00 74 MCLK as input to FLL, FLLn_REFCLK_DIV = 01 37 MCLK as input to FLL, FLLn_REFCLK_DIV = 10 18 MCLK as input to FLL, FLLn_REFCLK_DIV = 11 12.5 MCLK as direct SYSCLK or ASYNCCLK source 40 MCLK duty cycle MCLK as input to FLL 80:20 MCLK as direct SYSCLK or ASYNCCLK source 60:40 Frequency-locked FLL input frequency FLLn_REFCLK_DIV = 00 0.032 loop (FLL1, FLL2) FLLn_REFCLK_DIV = 01 0.064 FLLn_REFCLK_DIV = 11 0.128 FLLn_REFCLK_DIV = 11 0.256 Internal clocking SYSCLK frequency SYSCLK_FREQ = 000, SYSCLK_FRAC = 0 –1% SYSCLK_FREQ = 000, SYSCLK_FRAC = 1 –1% SYSCLK_FREQ = 001, SYSCLK_FRAC = 0 –1% SYSCLK_FREQ = 001, SYSCLK_FRAC = 1 –1% SYSCLK_FREQ = 010, SYSCLK_FRAC = 0 –1% SYSCLK_FREQ = 010, SYSCLK_FRAC = 1 –1% SYSCLK_FREQ = 011, SYSCLK_FRAC = 0 –1% SYSCLK_FREQ = 011, SYSCLK_FRAC = 1 –1% SYSCLK_FREQ = 100, SYSCLK_FRAC = 0 –1% SYSCLK_FREQ = 100, SYSCLK_FRAC = 1 –1% –1% ASYNCCLK frequency ASYNC_CLK_FREQ = 000 –1% ASYNC_CLK_FREQ = 001 –1% –1% ASYNC_CLK_FREQ = 010 –1% –1% ASYNC_CLK_FREQ = 011 –1% –1% ASYNC_CLK_FREQ = 100 –1% –1% DSPCLK frequency 5 Master clock MCLK cycle time timing (MCLK1, MCLK2, MCLK3) 1 Typical — — — — — — — — — — — 6.144 5.6448 12.288 11.2896 24.576 22.5792 49.152 45.1584 98.304 90.3168 6.144 5.6448 12.288 11.2896 24.576 22.5792 49.152 45.1584 98.304 90.3168 — Maximum — — — — — 20:80 40:60 13 26 52 80 +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% 150 Units ns ns ns ns ns % % MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 1.If MCLK1, MCLK2, or MCLK3 is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the frequency must be within 1% of the applicable SYSCLK_FREQ or ASYNC_CLK_FREQ setting. 17 DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-14. Digital Microphone (DMIC) Interface Timing The following timing information is valid across the full range of recommended operating conditions. Parameter 1 Symbol Minimum Typical Maximum Units DMICCLKn cycle time tCY 160 163 1432 ns DMICCLKn duty cycle — 45 — 55 % DMICCLKn rise/fall time (25-pF load, 1.8-V supply) tr, tf 5 — 30 ns DMICDATn (left) setup time to falling DMICCLK edge tLSU 15 — — ns DMICDATn (left) hold time from falling DMICCLK edge tLH 0 — — ns DMICDATn (right) setup time to rising DMICCLK edge tRSU 15 — — ns DMICDATn (right) hold time from rising DMICCLK edge tRH 0 — — ns Note: The voltage reference for the DMIC interfaces is selectable, using the INn_DMIC_SUP fields—each interface may be referenced to MICVDD, MICBIAS1, or MICBIAS2. 1.DMIC interface timing tCY DMICCLK (output) VOH VOL tr tRSU t RH DMICDAT (input) 18 (right data) tf tLSU t LH (left data) VIH VIL DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-15. Digital Speaker (PDM) Interface Timing The following timing information is valid across the full range of recommended operating conditions. Mode A 1 Mode B 2 Parameter SPKCLK cycle time SPKCLK duty cycle SPKCLK rise/fall time (25-pF load) SPKDAT set-up time to SPKCLK rising edge (left channel) SPKDAT hold time from SPKCLK rising edge (left channel) SPKDAT set-up time to SPKCLK falling edge (right channel) SPKDAT hold time from SPKCLK falling edge (right channel) SPKCLK cycle time SPKCLK duty cycle SPKCLK rise/fall time (25-pF load) SPKDAT enable from SPKCLK rising edge (right channel) SPKDAT disable to SPKCLK falling edge (right channel) SPKDAT enable from SPKCLK falling edge (left channel) SPKDAT disable to SPKCLK rising edge (left channel) Symbol tCY — tr, tf tLSU tLH tRSU tRH tCY — tr, tf tREN tRDIS tLEN tLDIS Minimum 160 45 2 30 30 30 30 160 45 2 — — — — 1.Digital speaker (PDM) interface timing—Mode A Typical 163 — — — — — — 163 — — — — — — Maximum 358 55 8 — — — — 358 55 8 15 5 15 5 t CY SPKCLK (output) VOH VOL tr tf t LH SPKDAT (output) tRH (left data) (right data) tLSU tRSU 2.Digital speaker (PDM) interface timing—Mode B VOH V OL tCY SPKCLK (output) V OH VOL tr SPKDAT (output) 19 Units ns % ns ns ns ns ns ns % ns ns ns ns ns tLEN tf t REN (left data) t LDIS V OH VOL (right data) tRDIS DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-16. Digital Audio Interface—Master Mode Test conditions (unless specified otherwise): CLOAD = 25 pF (output pins); BCLK slew (10% to 90%) = 3.7–5.6 ns; with the exception of the conditions noted, the following electrical characteristics are valid across the full range of recommended operating conditions. Parameter 1 AIFnBCLK cycle time AIFnBCLK pulse width high AIFnBCLK pulse width low AIFnLRCLK propagation delay from BCLK falling edge 2 AIFnTXDAT propagation delay from BCLK falling edge AIFnRXDAT setup time to BCLK rising edge AIFnRXDAT hold time from BCLK rising edge Master Mode, AIFnLRCLK setup time to BCLK rising edge Slave LRCLK AIFnLRCLK hold time from BCLK rising edge Notes: The descriptions above assume noninverted polarity of AIFnBCLK. Master Mode Symbol tBCY tBCH tBCL tLRD tDD tDSU tDH tLRSU tLRH Minimum 40 18 18 0 0 11 0 14 0 1.Digital audio interface timing—Master Mode. Note that BCLK and LRCLK outputs can be inverted if required; the figure shows the default, noninverted polarity. Typical — — — — — — — — — Maximum — — — 8.3 5 — — — — Units ns ns ns ns ns ns ns ns ns t BCY BCLK (output) tBCH LRCLK (output) TXDAT (output) tBCL t LRD t DD RXDAT (input) tDH t DSU 2.The timing of the AIFnLRCLK signal is selectable. If the LRCLK advance option is enabled, the LRCLK transition is timed relative to the preceding BCLK edge. Under the required condition that BCLK is inverted in this case, the LRCLK transition is still timed relative to the falling BCLK edge. 20 DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-17. Digital Audio Interface—Slave Mode The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. Parameter 1,2 AIFnBCLK cycle time AIFnBCLK pulse width high BCLK as direct SYSCLK or ASYNCCLK source All other conditions AIFnBCLK pulse width low BCLK as direct SYSCLK or ASYNCCLK source All other conditions AIFnLRCLK set-up time to BCLK rising edge CLOAD = 15 pF (output pins), BCLK slew (10%–90%) = 3 ns AIFnLRCLK hold time from BCLK rising edge AIFnTXDAT propagation delay from BCLK falling edge AIFnRXDAT set-up time to BCLK rising edge AIFnRXDAT hold time from BCLK rising edge Master LRCLK, AIFnLRCLK propagation delay from BCLK falling edge CLOAD = 25 pF (output pins), AIFnLRCLK set-up time to BCLK rising edge BCLK slew (10%–90%) = 6 ns AIFnLRCLK hold time from BCLK rising edge AIFnTXDAT propagation delay from BCLK falling edge AIFnRXDAT set-up time to BCLK rising edge AIFnRXDAT hold time from BCLK rising edge Master LRCLK, AIFnLRCLK propagation delay from BCLK falling edge Note: The descriptions above assume noninverted polarity of AIFnBCLK. 1.Digital audio interface timing—Slave Mode. Note that BCLK and LRCLK inputs can be inverted if required; the figure shows the default, noninverted polarity. Symbol Min Typ Max Units tBCY 40 — — ns 16 — — ns tBCH tBCH 14 — — ns 16 — — ns tBCL tBCL 14 — — ns tLRSU 7 — — ns tLRH 0 — — ns tDD 0 — 12.2 ns tDSU 2 — ns tDH 0 — ns tLRD — — 14.8 ns tLRSU 7 — ns tLRH 0 — ns tDD 0 — 14.2 ns 2 — ns tDSU tDH 0 — ns tLRD — — 15.9 ns tBCY BCLK (input) LRCLK (input) TXDAT (output) tBCH t BCL tLRH tLRSU tDD RXDAT (input) tDSU t DH 2.If AIFnBCLK or AIFnLRCLK is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the frequency must be within 1% of the applicable SYSCLK_FREQ or ASYNC_CLK_FREQ setting. Table 3-18. Digital Audio Interface Timing—TDM Mode The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. Parameter 1 Min Typ Max AIFnTXDAT enable time from BCLK falling edge 0 — — Master Mode—CLOAD (AIFnTXDAT) = 15 to 25 pF. BCLK slew (10%–90%) = 3.7ns to 5.6 ns. AIFnTXDAT disable time from BCLK falling edge — — 6 Slave Mode—CLOAD (AIFnTXDAT) = 15 pF). AIFnTXDAT enable time from BCLK falling edge 2 — — BCLK slew (10%–90%) = 3 ns AIFnTXDAT disable time from BCLK falling edge — — 12.2 Slave Mode—CLOAD (AIFnTXDAT) = 25 pF). AIFnTXDAT enable time from BCLK falling edge 2 — — BCLK slew (10%–90%) = 6 ns AIFnTXDAT disable time from BCLK falling edge — — 14.2 Note: If TDM operation is used on the AIFnTXDAT pins, it is important that two devices do not attempt to drive the AIFnTXDAT pin simultaneously. To support this requirement, the AIFnTXDAT pins can be configured to be tristated when not outputting data. 1.Digital audio interface timing— TDM Mode. The timing of the AIFnTXDAT tristating at the start and end of the data transmission is shown. BCLK TXDAT AIFnTXDAT undriven (tristate) AIFnTXDAT valid (codec output) AIFnTXDAT enable time 21 Units ns ns ns ns ns ns AIFnTXDAT valid AIFnTXDAT undriven (tristate) AIFnTXDAT disable time DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-19. Control Interface Timing—Two-Wire (I2C) Mode The following timing information is valid across the full range of recommended operating conditions. Parameter 1 SCLK frequency SCLK pulse-width low SCLK pulse-width high Hold time (start condition) Setup time (start condition) SDA, SCLK rise time (10%–90%) SCLK frequency > 1.7 MHz SCLK frequency > 1 MHz SCLK frequency  1 MHz SCLK frequency > 1.7 MHz SCLK frequency > 1 MHz SCLK frequency  1 MHz SDA, SCLK fall time (90%–10%) Setup time (stop condition) SDA setup time (data input) SDA hold time (data input) SDA valid time (data/ACK output) SCLK slew (90%–10%) = 20ns, CLOAD (SDA) = 15 pF SCLK slew (90%–10%) = 60ns, CLOAD (SDA) = 100 pF SCLK slew (90%–10%) = 160ns, CLOAD (SDA) = 400 pF SCLK slew (90%–10%) = 200ns, CLOAD (SDA) = 550 pF Pulse width of spikes that are suppressed 1.Control interface timing—I2C Mode START t1 Symbol — t1 t2 t3 t4 t6 t6 t6 t7 t7 t7 t8 t5 t9 t10 t10 t10 t10 tps t2 Min — 160 100 160 160 — — — — — — 160 40 0 — — — — 0 Typ — — — — — — — — — — — — — — — — — — — Max 3400 — — — — 80 160 2000 60 160 200 — — — 40 130 190 220 25 Units kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns STOP t6 SCLK (input) t4 t7 t3 t8 SDA t5 22 t9 t10 DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-20. Control Interface Timing—Four-Wire (SPI) Mode The following timing information is valid across the full range of recommended operating conditions. Parameter 1, 2 SS falling edge to SCLK rising edge SCLK falling edge to SS rising edge SCLK pulse cycle time SCLK pulse-width low SCLK pulse-width high MOSI to SCLK set-up time MOSI to SCLK hold time SCLK falling edge to MISO transition SYSCLK disabled (SYSCLK_ENA = 0) SYSCLK_ENA = 1, SYSCLK_FREQ = 000 SYSCLK_ENA = 1, SYSCLK_FREQ > 000 SCLK slew (90%–10%) = 5 ns, CLOAD (MISO) = 25 pF 1.Control interface timing—SPI Mode (write cycle) tSSU Symbol Min Typ Max Units tSSU 2.6 — — ns tSHO tSCY tSCY tSCY tSCL tSCH tDSU tDHO tDL 0 38.4 76.8 38.4 15.3 15.3 1.5 1.7 0 — — — — — — — — — — — — — — — — — 12.6 ns ns ns ns ns ns ns ns ns t SHO SS (input) tSCY SCLK (input) t SCH MOSI (input) tSCL tDSU tDHO 2.Control interface timing—SPI Mode (read cycle) SS (input) SCLK (input) MISO (output) tDL 23 DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-21. SLIMbus Interface Timing The following timing information is valid across the full range of recommended operating conditions. Parameter 1 Symbol Minimum Typ Maximum Units SLIMCLK cycle time 35 — — — ns SLIMCLK pulse width high 12 TCLKH — — ns TCLKL SLIMCLK pulse width low 12 — — ns 40 — — ns SLIMCLK SLIMCLK cycle time — 12 — — ns output SLIMCLK pulse width high TCLKH TCLKL 12 — — ns SLIMCLK pulse width low SLIMCLK slew CLOAD = 15 pF, SLIMCLK_DRV_STR = 0 SRCLK 0.09 x VDBVDD — 0.22 x VDBVDD V/ns rate (20%–80%) CLOAD = 70 pF, SLIMCLK_DRV_STR = 0 SRCLK 0.02 x VDBVDD — 0.05 x VDBVDD V/ns CLOAD = 70 pF, SLIMCLK_DRV_STR = 1 SRCLK 0.04 x VDBVDD — 0.11 x VDBVDD V/ns 3.5 — — ns SLIMDAT SLIMDAT setup time to SLIMCLK falling edge TSETUP input SLIMDAT hold time from SLIMCLK falling edge TH 2 — — ns SLIMDAT SLIMDAT time SLIMDAT_DRV_STR = 0, DBVDD = 1.71 V TDV — 4.7 8.1 ns CLOAD = 15 pF, SLIMDAT_DRV_STR = 1, DBVDD = 1.71 V TDV output for data output — 4.3 7.3 ns TDV CLOAD = 30 pF, SLIMDAT_DRV_STR = 0, DBVDD = 1.71 V valid (relative to — 6.8 11.8 ns TDV CLOAD = 30 pF, SLIMDAT_DRV_STR = 1, DBVDD = 1.71 V SLIMCLK rising — 5.8 10.0 ns TDV CLOAD = 50 pF, SLIMDAT_DRV_STR = 0, DBVDD = 1.71 V edge) — 9.6 16.6 ns TDV CLOAD = 50 pF, SLIMDAT_DRV_STR = 1, DBVDD = 1.71 V — 7.9 13.7 ns TDV CLOAD = 70 pF, SLIMDAT_DRV_STR = 0, DBVDD = 1.71 V — 12.4 21.5 ns TDV CLOAD = 70 pF, SLIMDAT_DRV_STR = 1, DBVDD = 1.71 V — 10.0 17.4 ns SLIMDAT slew CLOAD = 15 pF, SLIMDAT_DRV_STR = 0 SRDATA — — 0.64 x VDBVDD V/ns rate (20%–80%) CLOAD = 30 pF, SLIMDAT_DRV_STR = 0 SRDATA — — 0.35 x VDBVDD V/ns CLOAD = 30pF, SLIMDAT_DRV_STR = 1 SRDATA — — 0.46 x VDBVDD V/ns CLOAD = 70pF, SLIMDAT_DRV_STR = 0 SRDATA — — 0.16 x VDBVDD V/ns CLOAD = 70pF, SLIMCLK_DRV_STR = 1 SRDATA — — 0.21 x VDBVDD V/ns Other Driver disable time TDD — — 6 ns parameters Bus holder output impedance 0.1 x VDBVDD < V < 0.9 x VDBVDD RDATAS 18 — 50 kΩ Notes: • The signal timing information describes the timing requirements of the SLIMbus interface as a whole, not just the CS42L92 device. • TDV is the propagation delay from the rising SLIMCLK edge (at CS42L92 input) to the SLIMDAT output being achieved at the input to all devices across the bus. • TSETUP is the set-up time for SLIMDAT input (at CS42L92), relative to the falling SLIMCLK edge (at CS42L92). • TH is the hold time for SLIMDAT input (at CS42L92) relative to the falling SLIMCLK edge (at CS42L92). • For more details of the interface timing, refer to the MIPI Alliance Specification for Serial Low-Power Inter-Chip Media Bus (SLIMbus) SLIMCLK input 1.SLIMbus interface timing. VIH , VOH VIL , VOL SLIMCLK TCLKL TCLKH VIH VIL SLIMDAT TDV TSETUP TH VIL , VIH are the 35%/65% levels of the respective inputs. VOL , VOH are the 20%/80% levels of the respective outputs. The SLIMDAT output delay (TDV) is with respect to the input pads of all receiving devices. 24 DS1162F1 CS42L92 3 Characteristics and Specifications Table 3-22. JTAG Interface Timing Test conditions (unless specified otherwise): CLOAD = 25 pF (output pins); TCK slew (20%–80%) = 5 ns; with the exception of the conditions noted, the following electrical characteristics are valid across the full range of recommended operating conditions. Parameter 1 TCK cycle time TCK pulse width high TCK pulse width low TMS setup time to TCK rising edge TMS hold time from TCK rising edge TDI setup time to TCK rising edge TDI hold time from TCK rising edge TDO propagation delay from TCK falling edge TRST setup time to TCK rising edge TRST hold time from TCK rising edge TRST pulse-width low Symbol TCCY TCCH TCCL TMSU TMH TDSU TDH TDD TRSU TRH — 1.JTAG Interface timing Minimum 50 20 20 1 2 1 2 0 3 3 20 Typical — — — — — — — — — — — Maximum — — — — — — — 17 — — — Units ns ns ns ns ns ns ns ns ns ns ns tCCY TCK (input) TRST (input) t CCH t CCL t RSU tRH TMS (input) TDI (input) TDO (output) DS1162F1 tMSU tMH tDSU t DH t DD 25 CS42L92 3 Characteristics and Specifications Table 3-23. Typical Power Consumption Test conditions (unless specified otherwise): DBVDD = CPVDD1 = AVDD = 1.8 V, DCVDD = FLLVDD = CPVDD2 = 1.2 V; MICVDD = Off (CP2 and LDO2 disabled); TA = +25ºC; Fs = 48 kHz; 24-bit audio data, I2S Slave Mode; SYSCLK = 24.576 MHz (direct MCLK1 input). Operating Configuration Headphone playback Earpiece playback Stereo line record Sleep Mode AIF1 to DAC to HPOUT1 (stereo), Quiescent 32- load. 1-kHz sine wave, PO = 10 mW AIF1 to DAC to HPOUT1 (mono), Quiescent 32- load (BTL). 1-kHz sine wave, PO = 30 mW Analog line to ADC to AIF1, 1-kHz sine wave, -1 dBFS output MICVDD = 1.8V (CP2 and LDO2 bypass enabled). Accessory detect enabled (JD1_ENA = 1) Typical I1.2V (mA) 1.8 37.8 1.2 61.7 1.1 Typical I1.8V (mA) 0.8 1.9 0.85 1.7 2.2 0.000 0.010 PTOT (mW) 3.6 48.78 2.97 77.1 5.28 0.018 Table 3-24. Typical Signal Latency Test conditions (unless specified otherwise): DBVDD = CPVDD1 = AVDD = 1.8 V, DCVDD = FLLVDD = CPVDD2 = 1.2 V; MICVDD = Off (CP2 and LDO2 disabled); TA = +25ºC; Fs = 48 kHz; 24-bit audio data, I2S Slave Mode; SYSCLK = 24.576 MHz (direct MCLK1 input). Operating Configuration AIF to DAC path—digital input (AIFn) to analog output (HPOUTn) ADC to AIF path—analog input (INn) to digital output (AIFn) 3 192 kHz input, 192 kHz output, Synchronous 96 kHz input, 96 kHz output, Synchronous 48 kHz input, 48 kHz output, Synchronous 44.1 kHz input, 44.1 kHz output, Synchronous 16 kHz input, 16 kHz output, Synchronous 8 kHz input, 8 kHz output, Synchronous 8 kHz input, 48 kHz output, Isochronous 1 16 kHz input, 48 kHz output, Isochronous 1 8 kHz input, 44.1 kHz output, Asynchronous 2 16 kHz input, 44.1 kHz output, Asynchronous 2 192 kHz input, 192 kHz output, Synchronous 96 kHz input, 96 kHz output, Synchronous 48 kHz input, 48 kHz output, Synchronous 44.1 kHz input, 44.1 kHz output, Synchronous 16 kHz input, 16 kHz output, Synchronous 8 kHz input, 8 kHz output, Synchronous 8 kHz input, 48 kHz output, Isochronous 1 16 kHz input, 48 kHz output, Isochronous 1 44.1 kHz input, 8 kHz output, Asynchronous 2 44.1 kHz input, 16 kHz output, Asynchronous 2 Latency (s) 237 269 358 374 629 1334 1939 993 1880 1084 50 96 193 212 558 1170 1696 861 1364 841 1.Signal is routed via the ISRC function in the isochronous cases only. 2.Signal is routed via the ASRC function in the asynchronous cases only. 3.Digital core high-pass filter is included in the signal path. 26 DS1162F1 CS42L92 4 Functional Description 4 Functional Description The CS42L92 is a highly integrated, low-power audio hub codec for mobile telephony and portable devices. It provides flexible, high-performance audio interfacing for handheld devices in a small and cost-effective package. The digital audio interfaces and hi-fi DACs support 32-bit playback, offering audiophile-quality playback at sample rates up to 384 kHz. Native audio playback is possible, concurrent with voice and ultrasonic input paths. Multiple analog outputs support a wide variety of the headphone/accessory configurations, including balanced stereo headphone loads. 4.1 Overview MICBIAS1A MICBIAS1B MICBIAS1C MICBIAS1D MICBIAS2A MICBIAS2B Charge Pumps LDO and MICBIAS Generators CS42L92 SUBGND DCVDD DBVDD FLLGND DGND FLLVDD CPVDD1 CPVDD2 CPGND AVDD AGND VREFC CP2CA CP2CB CP1C1A CP1C1B CP1VOUT1P CP1VOUT1N CP1C2A CP1C2B CP1VOUT2P CP1VOUT2N CP2VOUT MICVDD The CS42L92 block diagram is shown in Fig. 4-1. Reference Generator DAC HPOUTnL DAC HPOUTnR Digital Mixing Core SYSCLK ASYNCCLK SLIMbus Interface Control Interface (SPI/I2C) GPIO x4 SPKCLK SPKDAT JACKDET1 JACKDET2 JACKDET3 HPDET1 HPDET2 MICDET1/HPOUTFB1 MICDET2/HPOUTFB2 MICDET3/HPOUTFB3 MICDET4/HPOUTFB4 MICDET5/HPOUTFB5 GPSW1P GPSW1N GPSW2P GPSW2N Digital Audio Interfaces AIF1, AIF2, AIF3 Accessory Detect GPIO1 GPIO2 Clocking Control CIFMISO CIFMOSI/SDA CIFSCLK CIFSS CIFMODE AIFnBCLK AIFnLRCLK SLIMCLK AIF1TXDAT AIF1RXDAT AIF1BCLK AIF1LRCLK IRQ PDM Driver AEC (Echo Cancelation) Loop-Back SLIMCLK SLIMDAT1 SLIMDAT2 RESET 4 x ADC 4 x Stereo Digital Mic Interface AIF3TXDAT AIF3RXDAT AIF3BCLK AIF3LRCLK MCLK1 MCLK2 MCLK3 Programmable DSP Five-band equalizer (EQ) Dynamic range control (DRC) Low-pass/high-pass filter (LHPF) Asynchronous sample -rate conversion Automatic sample -rate detection Data format conversion Ultrasonic demodulator PWM signal generator Haptic control signal generator Input Select AIF2TXDAT AIF2RXDAT AIF2BCLK AIF2LRCLK IN1ALN/DMICCLK1, IN1BLN IN1ALP/DMICDAT1, IN1BLP IN1ARN/DMICCLK3 IN1ARP/DMICDAT3, IN1BR IN2ALN/DMICCLK2 IN2ALP/DMICDAT2, IN2BL IN2ARN/DMICCLK4 IN2ARP/DMICDAT4, IN2BR Figure 4-1. CS42L92 Block Diagram The CS42L92 combines fixed-function signal-processing blocks with a fully-flexible, all-digital audio mixing and routing engine for extensive use-case flexibility. The signal-processing blocks include high-/low-pass filters, EQ, dynamic range control, and sample-rate converters. The CS42L92 provides multiple digital audio interfaces, including SLIMbus, to provide independent and fully asynchronous connections to different processors (e.g., application processor, baseband processor, and wireless transceiver). A flexible clocking arrangement supports a wide variety of external clock references, including clocking derived from the digital audio interface. Two frequency-locked loop (FLL) circuits provide additional flexibility for system clocking, including low-power always-on operation. Seamless switching between clock sources is supported, and free-running modes are also available. Unused circuitry can be disabled under software control to save power; low leakage currents enable extended standby/off time in portable battery-powered applications. The CS42L92 always-on circuitry can be used in conjunction with the applications processor to wake up the device following a headphone jack-detection event. DS1162F1 27 CS42L92 4.1 Overview Versatile GPIO functionality is provided, including support for external accessory/push-button detection inputs. Comprehensive interrupt functions, with status reporting, are also provided. The integrated DSP provides a general-purpose signal processing capability; this is supported by general-purpose timer and event-logger functions. 4.1.1 Hi-Fi Audio Codec The CS42L92 is a high-performance, low-power audio codec that uses a simple analog architecture. Four ADCs are incorporated, with multiplexers to support up to eight analog inputs. Six DACs are incorporated, with two being switchable between two separate headphone output paths. The audio codec is controlled directly via register access. The simple analog architecture, combined with the integrated tone generator, enables straightforward device configuration and testing, minimizing debug time and reducing software effort. The CS42L92 input channels support up to eight analog inputs or up to eight digital inputs, multiplexed into four stereo input signal paths. In differential mode, the analog input path SNR is 104 dB (16-kHz sample rate, i.e., wideband voice mode). The input paths can be configured for low-power operation, ideal for analog or digital microphone input in always-on applications. Ultrasonic signal demodulation functions are provided, supporting a variety of presence-detection applications. The analog outputs comprise four 33-mW (125 dB SNR) stereo headphone amplifiers with ground-referenced output. The output drivers are designed to support many different system architectures and are compatible with line or headphone loads in single-ended or differential (BTL) configurations. Headphone outputs HPOUT1 and HPOUT2 offer 127 dB SNR and –100 dB THD+N performance with a stereo differential headphone load. Outputs HPOUT3 and HPOUT4 are multiplexed, with the respective DACs and signal paths common to both pairs of output drivers. Each output path supports independent mixing, equalization, filtering, gain controls. This allows each signal path to be individually tailored for the load characteristics. Selectable hi-fi filters support audiophile playback modes at sample rates up to 384 kHz. All outputs have integrated pop and click suppression features. The headphone output drivers are ground-referenced, powered from an integrated charge pump, enabling high quality, power efficient headphone playback without any requirement for DC blocking capacitors. Ground loop feedback is incorporated, providing rejection of noise on the ground connections. The CS42L92 is cost optimized for a wide range of mobile phone applications. External speaker amplifiers can be connected using the stereo PDM outputs; this can ease layout and electromagnetic compatibility by avoiding the need to run high-power speaker outputs over a long distance and across interconnects. 4.1.2 Digital Audio Core The CS42L92 uses a core architecture based on all-digital signal routing, making digital audio effects available on all signal paths, regardless of whether the source data input is analog or digital. The digital mixing desk allows different audio effects to be applied simultaneously on many independent paths, while supporting a variety of sample rates. Soft mute and unmute control ensures smooth transitions between use cases without interrupting existing audio streams elsewhere. Highly flexible digital mixing, including mixing between audio interfaces, is possible. The CS42L92 performs multichannel full-duplex asynchronous sample-rate conversion, providing use-case flexibility across a broad range of system architectures. Automatic sample-rate detection is provided, enabling seamless wideband/narrowband voice call handover. DRC functions are available for optimizing audio signal levels. In playback modes, the DRC can be used to maximize loudness, while limiting the signal level to avoid distortion, clipping, or battery droop, for high-power output drivers such as speaker amplifiers. In record modes, the DRC assists in applications where the signal level is unpredictable. The five-band parametric EQ functions can be used to compensate for the frequency characteristics of the output transducers. EQ functions can be cascaded to provide additional frequency control. Programmable high-pass and low-pass filters are also available for general filtering applications, such as removal of wind and other low-frequency noise. 28 DS1162F1 CS42L92 4.1 Overview 4.1.3 Digital Interfaces Three serial digital audio interfaces (AIFs) each support PCM, TDM, and I2S data formats for compatibility with most industry-standard chipsets. Each AIF supports eight input/output channels. Bidirectional operation at sample rates up to 384 kHz is supported. Data words of up to 32 bits can be routed through AIF1 and AIF3. Data-format conversion (DFC) functions are available to support different interface standards on the input and output signal paths. Eight digital PDM input channels are available (four stereo interfaces); these are typically used for digital microphones, powered from the integrated MICBIAS power-supply regulators. Two PDM output channels are also available (one stereo interface); these are typically used for external power amplifiers. Embedded mute codes provide a control mechanism for external PDM-input devices. The auxiliary PDM interface can be used to provide an audio path between an analog microphone connected to the CS42L92 and a digital input to an external audio processor. The auxiliary PDM interface operates in master or slave modes, and is configured on GPIO pins. The CS42L92 features a SLIMbus interface, compliant with the MIPI® SLIMbus specification, providing eight channels of audio input/output. Mixed audio sample rates are supported on the SLIMbus interface. The SLIMbus interface also supports read/write access to the CS42L92 control registers. An IEC-60958-3–compatible S/PDIF transmitter is incorporated, enabling stereo S/PDIF output on a GPIO pin. Standard S/PDIF sample rates of 32–192 kHz are supported. Control register access is supported by a configurable SPI/I2C control interface. The interface supports SPI slave operation up to 26 MHz or I2C slave operation up to 3.4 MHz. Full access to the register map is also provided via the SLIMbus port. 4.1.4 Other Features The CS42L92 incorporates a tone generator that can be used for beep functions through any of the audio signal paths. The tone generator provides two 1-kHz outputs, with configurable phase relationship, offering flexibility to create differential signals or test scenarios. A white-noise generator is provided that can be routed within the digital core. The noise generator can provide comfort noise in cases where silence (digital mute) is not desirable. Two pulse-width modulation (PWM) signal generators are incorporated. The duty cycle of each PWM signal can be modulated by an audio source or can be set to a fixed value using a control register setting. The PWM signal generators can be output directly on a GPIO pin. The CS42L92 supports up to 16 GPIO pins, offering a range of input/output functions for interfacing, for detection of external hardware, and for providing logic outputs to other devices. The CS42L92 provides two dedicated GPIO pins; a further 14 GPIOs are multiplexed with other functions. Comprehensive interrupt functionality is also provided for monitoring internal and external event conditions. The integrated DSP provides a general-purpose signal processing capability; this is supported by general-purpose timer and event-logger functions. A signal generator for controlling haptics devices is included, compatible with both eccentric rotating mass (ERM) and linear resonant actuator (LRA) haptics devices. The haptics signal generator is highly configurable and can execute programmable drive event profiles, including reverse drive control. An external vibe actuator can be driven using the PDM digital output path. A smart accessory interface is included, supporting a wide variety of system configurations. Jack detection, accessory sensing, and impedance measurement is provided, for external headset and push-button detection. Dual headphone connections (e.g., 3.5 mm and USB-C) can be detected simultaneously. Accessory detection can be used as a wake-up trigger from low-power standby. Microphone activity detection with interrupt is also available. DS1162F1 29 CS42L92 4.2 Input Signal Path System clocking can be derived from the MCLK1, MCLK2, or MCLK3 input pins. Alternatively, the SLIMbus interface, or the audio interfaces (configured in Slave Mode), can be used to provide a clock reference. The CS42L92 also provides two integrated FLL circuits for clock frequency conversion and stability. The flexible clocking architecture supports low-power always-on operation, with reference frequencies down to 32 kHz. Seamless switching between clock sources is supported; free-running FLL modes are also available. The CS42L92 is powered from 1.8- and 1.2-V external supplies. Integrated charge-pump and LDO-regulator circuits are used to generate supply rails for internal functions and to support powering or biasing of external microphones. Power consumption is optimized across a wide variety of voice and multimedia use cases. 4.2 Input Signal Path The CS42L92 provides flexible input channels, supporting up to eight analog inputs or up to eight digital inputs. Selectable combinations of analog (mic or line) and digital inputs are multiplexed into four stereo input signal paths. Input paths IN1 and IN2 support analog and digital inputs; input paths IN3 and IN4 support digital inputs only. The analog input paths support single-ended and differential configurations, programmable gain control, and are digitized using a high performance sigma-delta ADC. The analog input paths can be configured for low-power operation, ideal for always-on applications. Analog inputs can be configured as input to the auxiliary PDM interface, providing an audio path between an analog microphone connected to the CS42L92 and a digital input to an external audio processor. The digital input paths interface directly with external digital microphones; a separate microphone interface clock is provided for four separate stereo pairs of digital microphones. Two microphone bias (MICBIAS) generators provide a low-noise reference for biasing electret condenser microphones (ECMs) or for use as a low-noise supply for MEMS microphones and digital microphones. Switchable outputs from the MICBIAS generators allow six separate reference/supply outputs to be independently controlled. Digital volume control is available on all inputs (analog and digital), with programmable ramp control for smooth, glitch-free operation. A configurable signal-detect function is available on each input signal path. Ultrasonic signal demodulation functions are provided on the input signal paths, supporting a variety of presence-detection applications. The input signal paths and control fields are shown in Fig. 4-2. 30 DS1162F1 CS42L92 4.2 Input Signal Path IN1BLN IN1ALN/DMICCLK1 IN1L ADC + IN1ALP/DMICDAT1 IN_VD_RAMP[2:0] p. 40 IN_VI_RAMP[2:0] p. 40 IN1_MODE p. 38 - IN1BLP IN_HPF_CUT[2:0] p. 38 IN1L_SRC[1:0] p. 38 IN1L_PGA_VOL[6:0] p. 38 IN1L_LP_MODE p. 38 CLK IN1L_HPF p. 38 Digital Mic Interface DAT IN1L_VOL[7:0] p. 41 IN1L_MUTE p. 41 IN1L_ENA p. 36 IN3_OSR[2:0] p. 39 IN3_DMIC_SUP[1:0] p. 39 IN1R_SRC[1:0] p. 38 - IN1BR IN1ARN/DMICCLK3 + IN1ARP/DMICDAT3 IN1R ADC IN1R_PGA_VOL[6:0] p. 38 IN1R_LP_MODE p. 38 CLK IN1R_HPF p. 38 IN3L Digital Mic Interface DAT IN1R_VOL[7:0] p. 41 IN1R_MUTE p. 41 IN1R_ENA p. 36 IN3_OSR[2:0] p. 39 IN3_DMIC_SUP[1:0] p. 39 IN3L_HPF p. 39 IN3L_VOL[7:0] p. 41 IN3L_MUTE p. 41 IN3L_ENA p. 36 IN3R IN3R_HPF p. 39 IN2BL IN2L_SRC[1:0] p. 39 IN2ALN/DMICCLK2 - IN3R_VOL[7:0] p. 42 IN3R_MUTE p. 42 IN3R_ENA p. 36 IN2L ADC + IN2ALP/DMICDAT2 IN2_MODE p. 39 IN2L_PGA_VOL[6:0] p. 39 IN2L_LP_MODE p. 39 CLK IN2L_HPF p. 39 Digital Mic Interface DAT IN2L_VOL[7:0] p. 41 IN2L_MUTE p. 41 IN2L_ENA p. 36 IN4_OSR[2:0] p. 40 IN4_DMIC_SUP[1:0] p. 40 IN2BR IN2R_SRC[1:0] p. 39 IN2ARN/DMICCLK4 - IN2R ADC + IN2ARP/DMICDAT4 IN2R_PGA_VOL[6:0] p. 39 IN2R_LP_MODE p. 39 CLK DAT Digital Mic Interface IN4_OSR[2:0] p. 40 IN4_DMIC_SUP[1:0] p. 40 IN2R_HPF p. 39 IN2R_VOL[7:0] p. 41 IN2R_MUTE p. 41 IN2R_ENA p. 36 IN4L IN4L_HPF p. 40 IN4L_VOL[7:0] p. 42 IN4L_MUTE p. 42 IN4L_ENA p. 36 IN4R IN4R_HPF p. 40 IN4R_VOL[7:0] p. 42 IN4R_MUTE p. 42 IN4R_ENA p. 36 Figure 4-2. Input Signal Paths DS1162F1 31 CS42L92 4.2 Input Signal Path 4.2.1 Analog Microphone Input Up to eight analog microphones can be connected to the CS42L92, either in single-ended or differential configuration. The input configuration and pin selection is controlled using INnx_SRC, as described in Section 4.2.6. The CS42L92 includes external accessory-detection circuits that can report the presence of a microphone and the status of a hook switch or other push buttons. When using this function, it is recommended to use the IN1ALx, IN1BLx, or IN1BR analog microphone input paths to ensure best immunity to electrical transients arising from the push buttons. For single-ended input, the microphone signal is connected to the noninverting input of the PGAs. The inverting inputs of the PGAs are connected to an internal reference in this configuration. For differential input, the noninverted microphone signal is connected to the noninverting input of the PGAs and the inverted (or noisy ground) signal is connected to the inverting input pins. The gain of the input PGAs is controlled via register settings, as defined in Section 4.2.6. Note that the input impedance of the analog input paths is fixed across all PGA gain settings. The ECM analog input configurations are shown in Fig. 4-3 and Fig. 4-4. The integrated MICBIAS generators provide a low noise reference for biasing the ECMs. MICBIAS MICBIAS INnAxP, INnBLP, INnBx INnAxP, INnBLP, INnBx INnAxN, IN1BLN ECM + PGA – To ADC ECM INnAxN, IN1BLN + PGA – To ADC GND VREF VREF GND Figure 4-3. Single-Ended ECM Input Figure 4-4. Differential ECM Input Pseudodifferential connection is also possible—this is similar to the configuration shown in Fig. 4-4, but the GND connection is directly to the microphone (and INnxN capacitor), instead of via a resistor. The typical connections for pseudodifferential input are shown in Fig. 4-5. Note that pseudodifferential input is the recommended configuration if the accessory-detection functions are used on this input path. The INnx_SRC field settings are the same for pseudodifferential connection as for differential. The IN1ALN pin can be used as the inverting input connection for the IN1L and IN1R paths concurrently. This allows two microphones to be supported, in pseudodifferential configuration, while minimizing the number of pin connections required—see Fig. 4-6. 32 DS1162F1 CS42L92 4.2 Input Signal Path MICBIASnx MICBIAS INnAxP, INnBLP, INnBx IN1ALP ECM + PGA – INnAxN, IN1BLN To ADC IN1BR ECM ECM VREF IN1ALN GND GND Figure 4-5. Pseudodifferential ECM Input GND Figure 4-6. Pseudodifferential IN1L/IN1R Input Analog MEMS microphones can be connected to the CS42L92 in a similar manner to the ECM configurations. Typical configurations are shown in Fig. 4-7 and Fig. 4-8. In this configuration, the integrated MICBIAS generators provide a low-noise power supply for the microphones. MICBIAS VDD MEMS Mic OUT INnAxP, INnBLP, INnBx GND INnAxN, IN1BLN MICBIAS + PGA – GND VREF Figure 4-7. Single-Ended MEMS Input Note: 4.2.2 To ADC MEMS Mic VDD OUT-P OUT-N GND GND INnAxP, INnBLP, INnBx INnAxN, IN1BLN + PGA – To ADC VREF Figure 4-8. Differential MEMS Input The MICVDD pin can also be used (instead of MICBIAS) as a reference or power supply for external microphones. The MICBIAS outputs are recommended, because they offer better noise performance and independent enable/ disable control. Analog Line Input Line inputs can be connected to the CS42L92 in a similar manner to the mic inputs. Single-ended and differential configurations are supported on each analog input path, using the INnx_SRC bits as described in Section 4.2.6. The analog line input configurations are shown in Fig. 4-9 and Fig. 4-10. Note that the microphone bias (MICBIAS) is not used for line input connections. DS1162F1 33 CS42L92 4.2 Input Signal Path INnAxP, INnBLP, INnBx Line INnAxP, INnBLP, INnBx Line INnAxN, IN1BLN + PGA – To ADC INnAxN, IN1BLN + PGA – To ADC GND VREF VREF Figure 4-9. Single-Ended Line Input 4.2.3 Figure 4-10. Differential Line Input DMIC Input As many as eight digital microphones can be connected to the CS42L92. DMIC operation on input paths IN1–IN4 is selected using IN1_MODE and IN2_MODE, as described in Section 4.2.6. In DMIC mode, two channels of audio data are multiplexed on the associated DMICDATn pin. Each stereo DMIC interface is clocked using the respective DMICCLKn output. If DMIC input is enabled, the CS42L92 outputs the DMIC clock on the applicable DMICCLKn pins. The DMICCLKn frequency is controlled by the respective INn_OSR field, as described in Table 4-1 and Table 4-3. Note that, if the 384- or 768-kHz DMICCLKn frequency is selected, the maximum valid sample rate for the respective paths is restricted as described in Table 4-1. If the input sample rates are set globally using IN_RATE (i.e., IN_RATE_ MODE = 0), all input paths are affected similarly. Note that SYSCLK must be present and enabled when using the DMIC inputs; see Section 4.16 for details of SYSCLK and the associated registers. The DMIC clock frequencies in Table 4-1 assume that the SYSCLK frequency is a multiple of 6.144 MHz (SYSCLK_ FRAC = 0). If the SYSCLK frequency is a multiple of 5.6448 MHz (SYSCLK_FRAC = 1), the DMIC clock frequencies are scaled accordingly. Table 4-1. DMICCLK Frequency Condition INn_OSR = 010 INn_OSR = 011 INn_OSR = 100 INn_OSR = 101 INn_OSR = 110 DMIC Clock Frequency 384 kHz 768 kHz 1.536 MHz 3.072 MHz 6.144 MHz Valid Sample Rates Up to 48 kHz Up to 96 kHz Up to 192 kHz Up to 192 kHz Up to 192 kHz Signal Passband Up to 4 kHz Up to 8 kHz Up to 20 kHz Up to 20 kHz Up to 96 kHz The voltage reference for the DMIC interfaces is selectable, using INn_DMIC_SUP; each interface may be referenced to MICVDD, MICBIAS1, or MICBIAS2. The voltage reference for each digital input path should be set equal to the applicable power supply of the respective microphones. A pair of digital microphones is connected as shown in Fig. 4-11. The microphones must be configured to ensure that the left mic transmits a data bit when DMICCLK is high and the right mic transmits a data bit when DMICCLK is low. The CS42L92 samples the DMIC data at the end of each DMICCLK phase. Each microphone must tristate its data output when the other microphone is transmitting. Note that the CS42L92 provides integrated pull-down resistors on the DMICDATn pins. This provides a flexible capability for interfacing with other devices. 34 DS1162F1 CS42L92 4.2 Input Signal Path MICVDD or MICBIASnx DMICCLKn Digital Microphone Interface DMICDATn VDD VDD CLK DATA VDD Digital Mic The DMIC inputs are referenced to MICVDD, MICBIAS1, or MICBIAS2. CLK DATA Digital Mic The supply for each digital microphone should provide the same voltage as the applicable reference. CHAN CHAN AGND Figure 4-11. DMIC Input Two DMIC channels are interleaved on DMICDATn. The DMIC interface timing is shown in Fig. 4-12. Each microphone must tristate its data output when the other microphone is transmitting. DMIC clock output Hi-Z Left mic output 1 2 Right mic output DMICDATn pin (Left and right channels interleaved) 1 1 2 1 2 1 2 2 1 2 Figure 4-12. DMIC Interface Timing 4.2.4 Input Signal Path Enable The input signal paths are enabled using the bits described in Table 4-2. The respective bits must be enabled for analog or digital input on the respective input paths. The input signal paths are muted by default. It is recommended that deselecting the mute should be the final step of the path enable control sequence. Similarly, the mute should be selected as the first step of the path-disable control sequence. The input signal path mute functions are controlled using the bits described in Table 4-4. The MICVDD power domain must be enabled when using the analog input signal paths. This power domain is provided using an internal charge pump (CP2) and LDO regulator (LDO2). See Section 4.19 for details of these circuits. The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The ASYNCCLK and 32-kHz clock may also be required, depending on the path configuration. See Section 4.16 for details of the system clocks. DS1162F1 35 CS42L92 4.2 Input Signal Path The CS42L92 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the input signal paths and associated ADCs. If the frequency is too low, an attempt to enable an input signal path fails. Note that active signal paths are not affected under such circumstances. The status bits in Register R769 indicate the status of each input signal path. If an underclocked error condition occurs, these bits indicate which input signal paths have been enabled. Table 4-2. Input Signal Path Enable Register Address R768 (0x0300) Input_Enables R769 (0x0301) Input_Enables_Status 36 Bit 7 Label IN4L_ENA Default 0 6 IN4R_ENA 0 5 IN3L_ENA 0 4 IN3R_ENA 0 3 IN2L_ENA 0 2 IN2R_ENA 0 1 IN1L_ENA 0 0 IN1R_ENA 0 7 IN4L_ENA_STS 0 6 IN4R_ENA_STS 0 5 IN3L_ENA_STS 0 4 IN3R_ENA_STS 0 3 IN2L_ENA_STS 0 2 IN2R_ENA_STS 0 1 IN1L_ENA_STS 0 0 IN1R_ENA_STS 0 Description Input Path 4 (left) enable 0 = Disabled 1 = Enabled Input Path 4 (right) enable 0 = Disabled 1 = Enabled Input Path 3 (left) enable 0 = Disabled 1 = Enabled Input Path 3 (right) enable 0 = Disabled 1 = Enabled Input Path 2 (left) enable 0 = Disabled 1 = Enabled Input Path 2 (right) enable 0 = Disabled 1 = Enabled Input Path 1 (left) enable 0 = Disabled 1 = Enabled Input Path 1 (right) enable 0 = Disabled 1 = Enabled Input Path 4 (left) enable status 0 = Disabled 1 = Enabled Input Path 4 (right) enable status 0 = Disabled 1 = Enabled Input Path 3 (left) enable status 0 = Disabled 1 = Enabled Input Path 3 (right) enable status 0 = Disabled 1 = Enabled Input Path 2 (left) enable status 0 = Disabled 1 = Enabled Input Path 2 (right) enable status 0 = Disabled 1 = Enabled Input Path 1 (left) enable status 0 = Disabled 1 = Enabled Input Path 1 (right) enable status 0 = Disabled 1 = Enabled DS1162F1 CS42L92 4.2 Input Signal Path 4.2.5 Input Signal Path Sample-Rate Control The input signal paths may be selected as input to the digital mixers or signal-processing functions within the CS42L92 digital core. The sample rate for the input signal paths can be set globally, or can be configured independently for each input channel. The IN_RATE_MODE bit (defined in Table 4-3) controls whether the input sample rates are set globally using IN_RATE, or independently for each input channel using the INnx_RATE fields (where n is 1–4 and x is L or R for the left/right channels respectively). The IN_RATE and INnx_RATE fields are defined in Table 4-26. Note that sample-rate conversion is required when routing the input signal paths to any signal chain that is asynchronous or configured for a different sample rate. 4.2.6 Input Signal Path Configuration The CS42L92 supports up to eight analog inputs or up to eight digital inputs. Selectable combinations of analog (mic or line) and digital inputs are multiplexed into four stereo input signal paths. Input paths IN1 and IN2 can be configured for single-ended, differential, or DMIC operation. The analog input configuration and pin selection is controlled using the INnx_SRC bits; digital input mode is selected by setting INn_MODE. Input paths IN3 and IN4 support digital inputs only. Note that the external pin connections are shared with the IN1R and IN2R analog input paths—the following restrictions apply: • If IN3L or IN3R input paths are enabled, IN1R analog input is restricted to differential (IN1BR–IN1ALN) or single-ended (IN1BR) configurations only. • If IN4L or IN4R input paths are enabled, IN2R analog input is restricted to single-ended (IN2BR) configuration only. A configurable high-pass filter (HPF) is provided on the left and right channels of each input path. The applicable cut-off frequency is selected using IN_HPF_CUT. The filter can be enabled on each path independently using the INnx_HPF bits. The analog input signal paths (single-ended or differential) each incorporate a PGA to provide gain in the range 0 dB to +31 dB in 1-dB steps. Note that these PGAs do not provide pop suppression functions; it is recommended that the gain should not be adjusted while the respective signal path is enabled. The analog input PGA gain is controlled using INnL_PGA_VOL and INnR_PGA_VOL. Note that separate volume control is provided for the left and right channels of each stereo pair. If DMIC input is selected, the respective DMICCLKn frequency is controlled by the respective INn_OSR field. If a signal path is configured for DMIC input, the voltage reference for the associated input/output pins is selectable using the INn_DMIC_SUP fields—each interface may be referenced to MICVDD, MICBIAS1, or MICBIAS2. The voltage reference for each digital input path should be set equal to the applicable power supply of the respective microphones. The CS42L92 input paths can be configured for power-saving operation, ideal for always-on applications. The low-power configurations allow the power consumption to be optimized with respect to the required audio performance characteristics. • If a signal path is configured for analog input, low-power operation can be selected by setting the respective INnx_ LP_MODE bit. Mid-power operation can be configured by setting INn_OSR = 100 for the respective signal paths. (Note that the INnx_LP_MODE bit should be cleared in the mid-power configuration.) Note that the maximum input-signal level is reduced by 6 dB if mid-power operation is selected—see Table 3-4. • If a signal path is configured for digital input, the respective DMICCLKn frequency can be configured using the INn_ OSR bits. Reducing the DMICCLKn frequency reduces power consumption at the expense of audio performance. The INn_OSR field also supports high performance DMIC mode, when 6.144 MHz DMICCLK is selected. If 384- or 768-kHz DMICCLKn frequency is selected, the maximum sample rate for the respective paths is restricted as described in Table 4-1. If the input sample rates are set globally using IN_RATE (i.e., IN_RATE_MODE = 0), all input paths are affected similarly. The MICVDD voltage is generated by an internal charge pump and LDO regulator. The MICBIASn outputs are derived from MICVDD; see Section 4.19. DS1162F1 37 CS42L92 4.2 Input Signal Path The input signal paths are configured using the fields described in Table 4-3. Table 4-3. Input Signal Path Configuration Register Address R776 (0x0308) Input_Rate R780 (0x030C) HPF_Control R784 (0x0310) IN1L_Control R785 (0x0311) ADC_Digital_ Volume_1L R786 (0x0312) DMIC1L_Control R788 (0x0314) IN1R_Control R789 (0x0315) ADC_Digital_ Volume_1R 38 Bit 10 Label IN_RATE_ MODE Default Description 1 Input Path Sample Rate Configuration 0 = Global control (all input paths configured using IN_RATE) 1 = Individual channel control (using the respective INnx_RATE fields) 2:0 IN_HPF_ 010 Input Path HPF Select. Controls the cut-off frequency of the input path HPF circuits. CUT[2:0] 000 = 2.5 Hz 010 = 10 Hz 100 = 40 Hz 001 = 5 Hz 011 = 20 Hz All other codes are reserved 15 IN1L_HPF 0 Input Path 1 (Left) HPF Enable 0 = Disabled 1 = Enabled 12:11 IN1_DMIC_ 00 Input Path 1 DMIC Reference Select (sets the DMICDAT1 and DMICCLK1 logic levels) SUP[1:0] 00 = MICVDD 10 = MICBIAS2 01 = MICBIAS1 11 = Reserved 10 IN1_MODE 0 Input Path 1 Mode 0 = Analog input 1 = Digital input 7:1 IN1L_PGA_ 0x40 Input Path 1 (Left) PGA Volume (applicable to analog input only) VOL[6:0] 0x00 to 0x3F = Reserved 0x42 = 2 dB 0x60 to 0x7F = Reserved 0x40 = 0 dB … (1-dB steps) 0x41 = 1 dB 0x5F = 31 dB 14:13 IN1L_ 00 Input Path 1 (Left) Source SRC[1:0] 00 = Differential (IN1ALP–IN1ALN) 10 = Differential (IN1BLP–IN1BLN) 01 = Single-ended (IN1ALP) 11 = Single-ended (IN1BLP) 11 IN1L_LP_ 0 Input Path 1 (Left) Low-Power Mode (applicable to analog input only) MODE 0 = High Performance Mode 1 = Low Power Mode 10:8 IN1_ 101 Input Path 1 Oversample Rate Control OSR[2:0] If analog input is selected, this field is used to select Mid-Power Mode. 100 = Mid Power Mode All other codes are reserved 101 = Normal If digital input is selected, this field controls the DMICCLK1 frequency. 010 = 384 kHz 101 = 3.072 MHz 011 = 768 kHz 110 = 6.144 MHz 100 = 1.536 MHz All other codes are reserved 15 IN1R_HPF 0 Input Path 1 (Right) HPF Enable 0 = Disabled 1 = Enabled 7:1 IN1R_PGA_ 0x40 Input Path 1 (Right) PGA Volume (applicable to analog input only) VOL[6:0] 0x00 to 0x3F = Reserved 0x42 = 2 dB 0x60 to 0x7F = Reserved 0x40 = 0 dB … (1-dB steps) 0x41 = 1 dB 0x5F = 31 dB 14:13 IN1R_ 00 Input Path 1 (Right) Source SRC[1:0] 00 = Differential (IN1ARP–IN1ARN) 10 = Differential (IN1BR–IN1ALN) 01 = Single-ended (IN1ARP) 11 = Single-ended (IN1BR) 11 IN1R_LP_ 0 Input Path 1 (Right) Low-Power Mode (applicable to analog input only) MODE 0 = High Performance Mode 1 = Low Power Mode DS1162F1 CS42L92 4.2 Input Signal Path Table 4-3. Input Signal Path Configuration (Cont.) Register Address R792 (0x0318) IN2L_Control Bit 15 Label IN2L_HPF 12:11 IN2_DMIC_ SUP[1:0] R793 (0x0319) ADC_Digital_ Volume_2L 10 IN2_MODE 7:1 IN2L_PGA_ VOL[6:0] 14:13 IN2L_ SRC[1:0] 11 R794 (0x031A) DMIC2L_Control R796 (0x031C) IN2R_Control R797 (0x0319) ADC_Digital_ Volume_2R R800 (0x0320) IN3L_Control IN2L_LP_ MODE 10:8 IN2_ OSR[2:0] 15 IN2R_HPF 7:1 IN2R_PGA_ VOL[6:0] 14:13 IN2R_ SRC[1:0] 11 IN2R_LP_ MODE 15 IN3L_HPF 12:11 IN3_DMIC_ SUP[1:0] R802 (0x0322) DMIC3L_Control R804 (0x0324) IN3R_Control DS1162F1 10:8 IN3_ OSR[2:0] 15 IN3R_HPF Default Description 0 Input Path 2 (Left) HPF Enable 0 = Disabled 1 = Enabled 00 Input Path 2 DMIC Reference Select (sets the DMICDAT2 and DMICCLK2 logic levels) 00 = MICVDD 10 = MICBIAS2 01 = MICBIAS1 11 = Reserved 0 Input Path 2 Mode 0 = Analog input 1 = Digital input 0x40 Input Path 2 (Left) PGA Volume (applicable to analog input only) 0x00 to 0x3F = Reserved 0x42 = 2 dB 0x60 to 0x7F = Reserved 0x40 = 0 dB … (1-dB steps) 0x41 = 1 dB 0x5F = 31 dB 00 Input Path 2 (Left) Source 00 = Differential (IN2ALP–IN2ALN) 10 = Differential (IN2BL–IN2ALN) 01 = Single-ended (IN2ALP) 11 = Single-ended (IN2BL) 0 Input Path 2 (Left) Low-Power Mode (applicable to analog input only) 0 = High Performance Mode 1 = Low Power Mode 101 Input Path 2 Oversample Rate Control If analog input is selected, this field is used to select Mid-Power Mode. 100 = Mid Power Mode All other codes are reserved 101 = Normal If digital input is selected, this field controls the DMICCLK2 frequency. 010 = 384 kHz 101 = 3.072 MHz 011 = 768 kHz 110 = 6.144 MHz 100 = 1.536 MHz All other codes are reserved 0 Input Path 2 (Right) HPF Enable 0 = Disabled 1 = Enabled 0x40 Input Path 2 (Right) PGA Volume (applicable to analog input only) 0x00 to 0x3F = Reserved 0x42 = 2 dB 0x60 to 0x7F = Reserved 0x40 = 0 dB … (1-dB steps) 0x41 = 1 dB 0x5F = 31 dB 00 Input Path 2 (Right) Source 00 = Differential (IN2ARP–IN2ARN) 10 = Differential (IN2BR–IN2ARN) 01 = Single-ended (IN2ARP) 11 = Single-ended (IN2BR) 0 Input Path 2 (Right) Low-Power Mode (applicable to analog input only) 0 = High Performance Mode 1 = Low Power Mode 0 Input Path 3 (Left) HPF Enable 0 = Disabled 1 = Enabled 00 Input Path 3 DMIC Reference Select (sets the DMICDAT3 and DMICCLK3 logic levels) 00 = MICVDD 10 = MICBIAS2 01 = MICBIAS1 11 = Reserved 101 Input Path 3 Oversample Rate Control - selects the DMICCLK3 frequency. 010 = 384 kHz 101 = 3.072 MHz 011 = 768 kHz 110 = 6.144 MHz 100 = 1.536 MHz All other codes are reserved 0 Input Path 3 (Right) HPF Enable 0 = Disabled 1 = Enabled 39 CS42L92 4.2 Input Signal Path Table 4-3. Input Signal Path Configuration (Cont.) Register Address R808 (0x0328) IN4L_Control R810 (0x032A) DMIC4L_Control R812 (0x032C) IN4R_Control 4.2.7 Bit 15 Label IN4L_HPF Default Description 0 Input Path 4 (Left) HPF Enable 0 = Disabled 1 = Enabled 12:11 IN4_DMIC_ 00 Input Path 4 DMIC Reference Select (sets the DMICDAT4 and DMICCLK4 logic levels) SUP[1:0] 00 = MICVDD 10 = MICBIAS2 01 = MICBIAS1 11 = Reserved 10:8 IN4_ 101 Input Path 4 Oversample Rate Control - selects the DMICCLK4 frequency. OSR[2:0] 010 = 384 kHz 101 = 3.072 MHz 011 = 768 kHz 110 = 6.144 MHz 100 = 1.536 MHz All other codes are reserved 15 IN4R_HPF 0 Input Path 4 (Right) HPF Enable 0 = Disabled 1 = Enabled Input Signal Path Digital Volume Control A digital volume control is provided on each input signal path, providing –64 dB to +31.5 dB gain control in 0.5-dB steps. An independent mute control is also provided for each input signal path. Whenever the gain or mute setting is changed, the signal path gain is ramped up or down to the new settings at a programmable rate. For increasing gain (or unmute), the rate is controlled by IN_VI_RAMP. For decreasing gain (or mute), the rate is controlled by IN_VD_RAMP. Note: The IN_VI_RAMP and IN_VD_RAMP fields should not be changed while a volume ramp is in progress. The IN_VU bits control the loading of the input signal path digital volume and mute controls. When IN_VU is cleared, the digital volume and mute settings are loaded into the respective control register, but do not change the signal path gain. The digital volume and mute settings on all of the input signal paths are updated when a 1 is written to IN_VU. This makes it possible to update the gain of multiple signal paths simultaneously. Note that, although the digital-volume controls provide 0.5-dB steps, the internal circuits provide signal gain adjustment in 0.125-dB steps. This allows a very high degree of gain control and smooth volume ramping under all operating conditions. Note: The 0 dBFS level of the IN1–IN4 digital input paths is not equal to the 0 dBFS level of the CS42L92 digital core. The maximum digital input signal level is –6 dBFS (see Table 3-7). Under 0 dB gain conditions, a –6 dBFS input signal corresponds to a 0 dBFS input to the CS42L92 digital core functions. The digital volume control registers are described in Table 4-4 and Table 4-5. Table 4-4. Input Signal Path Digital Volume Control Register Address R777 (0x0309) Input_Volume_ Ramp 40 Bit 6:4 Label IN_VD_RAMP[2:0] Default 010 2:0 IN_VI_RAMP[2:0] 010 Description Input Volume Decreasing Ramp Rate (seconds/6 dB). This field should not be changed while a volume ramp is in progress. 000 = 0 ms 011 = 2 ms 110 = 15 ms 001 = 0.5 ms 100 = 4 ms 111 = 30 ms 010 = 1 ms 101 = 8 ms Input Volume Increasing Ramp Rate (seconds/6 dB). This field should not be changed while a volume ramp is in progress. 000 = 0 ms 011 = 2 ms 110 = 15 ms 001 = 0.5 ms 100 = 4 ms 111 = 30 ms 010 = 1 ms 101 = 8 ms DS1162F1 CS42L92 4.2 Input Signal Path Table 4-4. Input Signal Path Digital Volume Control (Cont.) Register Address R785 (0x0311) ADC_Digital_ Volume_1L Bit 9 Label IN_VU 8 IN1L_MUTE 7:0 R789 (0x0315) ADC_Digital_ Volume_1R 9 IN_VU 8 IN1R_MUTE 7:0 R793 (0x0319) ADC_Digital_ Volume_2L IN_VU 8 IN2L_MUTE IN_VU 8 IN2R_MUTE IN2R_VOL[7:0] 9 IN_VU 8 IN3L_MUTE 7:0 DS1162F1 IN2L_VOL[7:0] 9 7:0 R801 (0x0321) ADC_Digital_ Volume_3L IN1R_VOL[7:0] 9 7:0 R797 (0x031D) ADC_Digital_ Volume_2R IN1L_VOL[7:0] IN3L_VOL[7:0] Default Description See Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Footnote 1 Signal Paths Volume and Mute settings to be updated simultaneously 1 Input Path 1 (Left) Digital Mute 0 = Unmute 1 = Mute 0x80 Input Path 1 (Left) Digital Volume (see Table 4-5 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64 dB 0x80 = 0 dB 0xC0 to 0xFF = Reserved 0x01 = –63.5 dB … (0.5-dB steps) … (0.5-dB steps) 0xBF = +31.5 dB See Input Signal Paths Volume and Mute Update Footnote 1 Writing 1 to this bit causes the Input Signal Paths Volume and Mute settings to be updated simultaneously 1 Input Path 1 (Right) Digital Mute 0 = Unmute 1 = Mute 0x80 Input Path 1 (Right) Digital Volume (see Table 4-5 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64 dB 0x80 = 0 dB 0xC0 to 0xFF = Reserved 0x01 = –63.5 dB … (0.5-dB steps) … (0.5-dB steps) 0xBF = +31.5 dB See Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Footnote 1 Signal Paths Volume and Mute settings to be updated simultaneously 1 Input Path 2 (Left) Digital Mute 0 = Unmute 1 = Mute 0x80 Input Path 2 (Left) Digital Volume (see Table 4-5 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64 dB 0x80 = 0 dB 0xC0 to 0xFF = Reserved 0x01 = –63.5 dB … (0.5-dB steps) … (0.5-dB steps) 0xBF = +31.5 dB See Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Footnote 1 Signal Paths Volume and Mute settings to be updated simultaneously 1 Input Path 2 (Right) Digital Mute 0 = Unmute 1 = Mute 0x80 Input Path 2 (Right) Digital Volume (see Table 4-5 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64 dB 0x80 = 0 dB 0xC0 to 0xFF = Reserved 0x01 = –63.5 dB … (0.5-dB steps) … (0.5-dB steps) 0xBF = +31.5 dB See Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Footnote 1 Signal Paths Volume and Mute settings to be updated simultaneously 1 Input Path 3 (Left) Digital Mute 0 = Unmute 1 = Mute 0x80 Input Path 3 (Left) Digital Volume (see Table 4-5 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64 dB 0x80 = 0 dB 0xC0 to 0xFF = Reserved 0x01 = –63.5 dB … (0.5-dB steps) … (0.5-dB steps) 0xBF = +31.5 dB 41 CS42L92 4.2 Input Signal Path Table 4-4. Input Signal Path Digital Volume Control (Cont.) Register Address R805 (0x0325) ADC_Digital_ Volume_3R Bit 9 Label IN_VU Default Description See Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Footnote 1 Signal Paths Volume and Mute settings to be updated simultaneously 8 IN3R_MUTE 1 Input Path 3 (Right) Digital Mute 0 = Unmute 1 = Mute 7:0 IN3R_VOL[7:0] 0x80 Input Path 3 (Right) Volume (see Table 4-5 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64 dB 0x80 = 0 dB 0xC0 to 0xFF = Reserved 0x01 = –63.5 dB … (0.5-dB steps) … (0.5-dB steps) 0xBF = +31.5 dB R809 (0x0329) 9 IN_VU See Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Footnote 1 Signal Paths Volume and Mute settings to be updated simultaneously ADC_Digital_ Volume_4L 8 IN4L_MUTE 1 Input Path 4 (Left) Digital Mute 0 = Unmute 1 = Mute 7:0 IN4L_VOL[7:0] 0x80 Input Path 4 (Left) Digital Volume (see Table 4-5 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64 dB 0x80 = 0 dB 0xC0 to 0xFF = Reserved 0x01 = –63.5 dB … (0.5-dB steps) … (0.5-dB steps) 0xBF = +31.5 dB R813 (0x032D) 9 IN_VU See Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Footnote 1 Signal Paths Volume and Mute settings to be updated simultaneously ADC_Digital_ Volume_4R 8 IN4R_MUTE 1 Input Path 4 (Right) Digital Mute 0 = Unmute 1 = Mute 7:0 IN4R_VOL[7:0] 0x80 Input Path 4 (Right) Digital Volume (see Table 4-5 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64 dB 0x80 = 0 dB 0xC0 to 0xFF = Reserved 0x01 = –63.5 dB … (0.5-dB steps) … (0.5-dB steps) 0xBF = +31.5 dB 1. Default is not applicable to these write-only bits Table 4-5 lists the input signal path digital volume settings. Table 4-5. Input Signal Path Digital Volume Range Input Volume Register 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 42 Volume (dB) –64.0 –63.5 –63.0 –62.5 –62.0 –61.5 –61.0 –60.5 –60.0 –59.5 –59.0 –58.5 –58.0 –57.5 –57.0 –56.5 –56.0 –55.5 Input Volume Register 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 Volume (dB) –39.5 –39.0 –38.5 –38.0 –37.5 –37.0 –36.5 –36.0 –35.5 –35.0 –34.5 –34.0 –33.5 –33.0 –32.5 –32.0 –31.5 –31.0 Input Volume Register 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 Volume (dB) –15.0 –14.5 –14.0 –13.5 –13.0 –12.5 –12.0 –11.5 –11.0 –10.5 –10.0 –9.5 –9.0 –8.5 –8.0 –7.5 –7.0 –6.5 Input Volume Register 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 Volume (dB) 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 DS1162F1 CS42L92 4.2 Input Signal Path Table 4-5. Input Signal Path Digital Volume Range (Cont.) Input Volume Register 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 4.2.8 Volume (dB) –55.0 –54.5 –54.0 –53.5 –53.0 –52.5 –52.0 –51.5 –51.0 –50.5 –50.0 –49.5 –49.0 –48.5 –48.0 –47.5 –47.0 –46.5 –46.0 –45.5 –45.0 –44.5 –44.0 –43.5 –43.0 –42.5 –42.0 –41.5 –41.0 –40.5 –40.0 Input Volume Register 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 Volume (dB) –30.5 –30.0 –29.5 –29.0 –28.5 –28.0 –27.5 –27.0 –26.5 –26.0 –25.5 –25.0 –24.5 –24.0 –23.5 –23.0 –22.5 –22.0 –21.5 –21.0 –20.5 –20.0 –19.5 –19.0 –18.5 –18.0 –17.5 –17.0 –16.5 –16.0 –15.5 Input Volume Register 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 Volume (dB) –6.0 –5.5 –5.0 –4.5 –4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 Input Volume Register 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0–0xFF Volume (dB) 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 22.5 23.0 23.5 24.0 24.5 25.0 25.5 26.0 26.5 27.0 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 Reserved Input Signal Path Signal-Detect Control The CS42L92 provides a digital signal-detect function for the input signal path. This enables system actions to be triggered by signal detection and allows the device to remain in a low-power state until a valid audio signal is detected. A mute function is integrated with the signal-detect circuit, ensuring the respective digital audio path remains at zero until the detection threshold level is reached. Signal detection is also indicated via the interrupt controller. The signal-detect function is supported on input paths IN1–IN4 in analog and digital configurations. (For input paths IN1 and IN2, digital input is selected by setting the respective INn_MODE bit.) Note that the valid operating conditions for this function vary, depending on the applicable signal-path configuration. • The signal-detect function is supported on analog input paths for sample rates up to 16 kHz. • The signal-detect function is supported on digital input paths for sample rates up to 16 kHz (if DMICCLKn  768kHz) and up to 48 kHz (if DMICCLKn  2.8224 MHz). For each input path, the signal-detect function is enabled by setting the respective INnx_SIG_DET_ENA bit. The detection threshold level is set using IN_SIG_DET_THR—this applies to all input paths. If the signal-detect function is enabled, the respective input channel is muted if the signal level is below the configured threshold. If the input signal exceeds the threshold level, the respective channel is immediately unmuted. DS1162F1 43 CS42L92 4.2 Input Signal Path If the input signal falls below the threshold level, the mute is applied. To prevent erroneous behavior, a time delay is applied before muting the input signal—the channel is only muted if the signal level remains below the threshold level for longer than the hold time. The hold time is set using IN_SIG_DET_HOLD. Note that the signal-level detection is performed in the digital domain, after the ADC, PGA, digital mute and digital volume controls—the respective input channel must be enabled and unmuted when using the signal-detect function. The signal-detect function is an input to the interrupt control circuit and can be used to trigger an interrupt event; see Section 4.15. Note that the respective interrupt event represents the logic OR of the signal detection on all input channels and does not provide indication of which input channel caused the interrupt. To avoid multiple interrupts, the signal-detect interrupt can be reasserted only after all input channels have fallen below the trigger threshold level. The input path signal-detection control registers are described in Table 4-6. Table 4-6. Input Signal Path Signal-Detect Control Register Address R786 (0x0312) DMIC1L_Control Bit 15 Label IN1L_SIG_DET_ ENA R790 (0x0316) DMIC1R_Control 15 IN1R_SIG_DET_ ENA R794 (0x031A) DMIC2L_Control 15 IN2L_SIG_DET_ ENA R798 (0x031E) DMIC2R_Control 15 IN2R_SIG_DET_ ENA R802 (0x0320) DMIC3L_Control 15 IN3L_SIG_DET_ ENA R806 (0x0326) DMIC3R_Control 15 IN3R_SIG_DET_ ENA R810 (0x032A) DMIC4L_Control 15 IN4L_SIG_DET_ ENA R814 (0x032E) DMIC4R_Control 15 IN4R_SIG_DET_ ENA R832 (0x0340) Signal_Detect_Globals 8:4 IN_SIG_DET_ THR[4:0] 3:0 IN_SIG_DET_ HOLD[3:0] 4.2.9 Default Description 0 Input Path 1 (Left) Signal-Detect Enable 0 = Disabled 1 = Enabled 0 Input Path 1 (Right) Signal-Detect Enable 0 = Disabled 1 = Enabled 0 Input Path 2 (Left) Signal-Detect Enable 0 = Disabled 1 = Enabled 0 Input Path 2 (Right) Signal-Detect Enable 0 = Disabled 1 = Enabled 0 Input Path 3 (Left) Signal-Detect Enable 0 = Disabled 1 = Enabled 0 Input Path 3 (Right) Signal-Detect Enable 0 = Disabled 1 = Enabled 0 Input Path 4 (Left) Signal-Detect Enable 0 = Disabled 1 = Enabled 0 Input Path 4 (Right) Signal-Detect Enable 0 = Disabled 1 = Enabled 0x00 Input Signal Path Signal-Detect Threshold 0x0A = –72.2 dB 0x00 = –30.1 dB 0x05 = –54.2 dB 0x0B = –74.7 dB 0x06 = –56.7 dB 0x01 = –36.1 dB 0x0C = –78.3 dB 0x07 = –60.2 dB 0x02 = –42.1 dB 0x08 = –66.2 dB 0x0D = –80.8 dB 0x03 = –48.2 dB 0x04 = –50.7 dB 0x09 = –68.7 dB All other codes are reserved 0001 Input Signal Path Signal-Detect Hold Time (delay before signal detect indication is deasserted) 0000 = Reserved ... (4-ms steps) 1100 = 96–100 ms 0001 = 4–8 ms 1001 = 36–40 ms 1101 = 192–196 ms 1110 = 384–388 ms 0010 = 8–12 ms 1010 = 40–44 ms 1111 = 768–772 ms 1011 = 48–52 ms 0011 = 12–16 ms Ultrasonic Signal Demodulation The CS42L92 provides ultrasonic signal-processing functions on the input signal paths. Configurable filters and demodulator functions enable ultrasonic signals to be translated down to the audio band and routed through the digital mixer core. Two ultrasonic processing blocks are incorporated, with independent configuration controls for each. 44 DS1162F1 CS42L92 4.2 Input Signal Path The input source for the ultrasonic blocks is configured using the USn_SRC fields (where n identifies the applicable block US1 or US2). The input signal gain is set using USn_GAIN. The input frequency range is selected by USn_FREQ. The ultrasonic functions can be supported on any of the input signal paths (IN1–IN4). The inputs to the ultrasonic functions are independent of the enable, mute, and digital-volume settings of the respective input signal paths—the ultrasonic functions do not require the selected input signal paths to be enabled, and the mute/digital-volume settings of the input signal paths have no effect on the ultrasonic functions. The system clock, SYSCLK, must be present and enabled when using the ultrasonic functions. The SYSCLK frequency must be a multiple of 6.144 MHz (SYSCLK_FRAC = 0) in this case. See Section 4.16 for details of SYSCLK and the associated registers. The ultrasonic demodulator function is enabled by setting USn_ENA. The frequency band and signal gain are selected using USn_FREQ and USn_GAIN respectively. The output from the ultrasonic demodulator is a frequency-modulated image of the selected input frequency range. The folding frequency that characterizes the frequency modulation is set according to the USn_FREQ setting—see Table 4-7. The relationship between input and output frequencies is described in Eq. 4-1. F OUT = F IN – F FOLD Equation 4-1. Ultrasonic Demodulator Characteristic Note that, depending on the input frequency range and the folding frequency, FFOLD, the modulated output in respect of certain input frequencies may overlap others. This effect arises if the folding frequency lies within the input frequency range, with the result that two different input frequencies will each be modulated to the same output frequency. This effect is limited to the outer edges of the input frequency range in all cases. Amplitude response across the input frequency range is flat to within 1.5 dB in all cases. The demodulated ultrasonic outputs can be selected as input to the digital mixers or signal-processing functions within the digital core by setting the respective x_SRCn fields as described in Section 4.3.1. The sample rate for the demodulated ultrasonic output is configured using USn_RATE—see Table 4-26. The selected sample rate must be one of the SYSCLK-related rates, and must be equal to the output rate set by USn_FREQ (see Table 4-7). Note that sample-rate conversion is required when routing the ultrasonic signals to any signal chain that is asynchronous or configured for a different sample rate. The characteristics associated with the USn_FREQ field setting are shown in Table 4-7. Table 4-7. Ultrasonic Frequency Control Condition Input Frequency Band Output Sample Rate USn_FREQ = 000 USn_FREQ = 001 USn_FREQ = 010 USn_FREQ = 011 24.5–40.5 kHz 18–22 kHz 16–24 kHz 20–28 kHz 32 kHz 8 kHz 16 kHz 16 kHz Demodulator Folding Frequency (FFOLD) 40.42 kHz 18.29 kHz 16 kHz 20.21 kHz The ultrasonic demodulation control registers are described in Table 4-8. DS1162F1 45 CS42L92 4.2 Input Signal Path Table 4-8. Ultrasonic Signal Demodulation Control Register Address Bit Label R4224 (0x1080) 13:12 US1_GAIN[1:0] US1_Ctrl_0 11:8 6:4 0 R4226 (0x1082) US2_Ctrl_0 Default Description 10 Ultrasonic Demodulator 1 Gain 00 = Disabled (no signal) 10 = 1 dB 01 = –5 dB 11 = 7 dB 0x0 Ultrasonic Demodulator 1 Source 0x0 = IN1L 0x3 = IN2R 0x1 = IN1R 0x4 = IN3L 0x2 = IN2L 0x5 = IN3R US1_SRC[3:0] US1_FREQ[2:0] 011 US1_ENA 0 13:12 US2_GAIN[1:0] 11:8 6:4 0 10 US2_SRC[3:0] 0x0 US2_FREQ[2:0] 011 US2_ENA 0 Ultrasonic Demodulator 1 Frequency 000 = 24.5–40.5 kHz 010 = 16–24 kHz 001 = 18–22 kHz 011 = 20–28 kHz Ultrasonic Demodulator 1 Enable 0 = Disabled 1 = Enabled Ultrasonic Demodulator 2 Gain 00 = Disabled (no signal) 10 = 1 dB 01 = –5 dB 11 = 7 dB Ultrasonic Demodulator 2 Source 0x0 = IN1L 0x3 = IN2R 0x1 = IN1R 0x4 = IN3L 0x2 = IN2L 0x5 = IN3R Ultrasonic Demodulator 2 Frequency 000 = 24.5–40.5 kHz 010 = 16–24 kHz 001 = 18–22 kHz 011 = 20–28 kHz Ultrasonic Demodulator 2 Enable 0 = Disabled 1 = Enabled 0x6 = IN4L 0x7 = IN4R All other codes are reserved All other codes are reserved 0x6 = IN4L 0x7 = IN4R All other codes are reserved All other codes are reserved 4.2.10 Auxiliary PDM Interface The auxiliary PDM interface supports a one-channel digital output derived from one of the CS42L92 analog input paths. This can be used to provide an audio path between an analog microphone connected to the CS42L92 and a digital input to an external audio processor. The auxiliary PDM interface signal path is shown in Fig. 4-13. IN1xLN - IN1xLP IN1L ADC Auxiliary PDM interface + IN1R IN2L IN2R CLK DAT GPIO configuration GPIO3/GPIO10 GPIO4/GPIO9 AUXPDM1_SRC[3:0] p. 48 The Auxiliary PDM interface takes one of the analog input paths as its signal source. The signal path (e.g., IN1L) does not need to be enabled. In Master Mode, CLK is output from the CS42L92. In Slave Mode, CLK is input to the CS42L92. In Slave Mode, the GPIO9 and GPIO10 pins must be used. Figure 4-13. Auxiliary PDM Interface The input source for the auxiliary PDM interface is selected using AUXPDM1_SRC. Note that the selected input path must be configured for analog input—the auxiliary PDM function is not supported for the DMICDATn inputs. 46 DS1162F1 CS42L92 4.2 Input Signal Path Note: The input to the auxiliary PDM interface is independent of the enable, mute, and digital-volume settings of the respective input signal path—the auxiliary PDM function does not require the selected input signal paths to be enabled, and the mute/digital-volume settings of the input signal paths have no effect on the auxiliary PDM function. The auxiliary PDM interface is enabled by setting AUXPDM1_ENA. Note that the other auxiliary PDM control fields should be configured before enabling the interface. The external connections (GPIO pins) should also be configured before enabling the interface; the AUXPDM1_ENA bit should be set as the final step of the enable sequence. The AUXPDM1_ ENA bit should be cleared before changing the interface configuration. The output signal can be muted and unmuted using AUXPDM1_MUTE. The interface operates in master or slave modes, selected using the AUXPDM1_MSTR bit. In Master Mode, the clock (CLK) signal is generated by the CS42L92; in Slave Mode, the CLK signal is an input to the CS42L92. The CLK frequency is selected using the AUXPDM1_CLK_FREQ field. For each setting of this field, the actual frequency depends on whether SYSCLK is configured for 48- or 44.1-kHz related sample rates. See Section 4.16 for details of the system clocks. Note that the CLK frequency must be configured in master and slave modes, using the AUXPDM1_CLK_ FREQ field. The timing of the data (DAT) output signal can be controlled using AUXPDM1_TXEDGE. This selects whether the DAT output changes on the rising or falling edge of CLK. The auxiliary PDM interface timing is shown in Fig. 4-14. In Master Mode, the clock and data outputs are driven synchronously by the CS42L92. In Slave Mode, the timing of the output data is controlled by the external clock input. In Slave Mode, the CS42L92 system clock (SYSCLK) must be synchronized to the CLK input. This is achieved by using one of the FLLs to generate the system clock, with AIF2BCLK configured as the FLL clock reference. (If the auxiliary PDM interface is configured in Slave Mode, the CLK input is supported on the AIF2BCLK/GPIO10 pin.) Further details of the FLLs are provided in Section 4.16.8. Aux PDM clock Aux PDM data (AUXPDM1_TXEDGE = 0) Aux PDM data (AUXPDM1_TXEDGE = 1) Figure 4-14. Auxiliary PDM Interface Timing The external connections associated with the auxiliary PDM interface are implemented on GPIO pins, which must be configured for the respective CLK and DAT functions. The auxiliary PDM signals are alternative functions available on specific GPIO pins only. See Section 4.14 to configure the GPIO pins for the auxiliary PDM interface. Note that the output pins (including the CLK function, if Master Mode is selected) must be configured as outputs using the respective GPn_DIR fields. • In Master Mode, the CLK output can be configured on the GPIO3 or GPIO10 pins. The DAT output can be configured on GPIO4 or GPIO9. • In Slave Mode, the CLK input is supported on GPIO10 only. The DAT output is supported on GPIO9. The auxiliary PDM interface control registers are described in Table 4-9. DS1162F1 47 CS42L92 4.2 Input Signal Path Table 4-9. Auxiliary PDM Interface Control Register Address R4288 (0x10C0) AUXPDM1_Ctrl_0 R4281 (0x10C1) AUXPDM1_Ctrl_1 Bit 11:8 Label AUXPDM1_SRC[3:0] Default Description 0x0 Auxiliary PDM 1 Source 0x0 = IN1L 0x3 = IN2R 0x1 = IN1R All other codes are reserved 0x2 = IN2L Note that the selected input source must be configured for analog input— digital input paths are not supported. The Auxiliary PDM interface must be disabled when updating this field. 4 AUXPDM1_TXEDGE 0 Auxiliary PDM 1 Timing 0 = Output data is driven on rising edge of AUXPDM1_CLK 1 = Output data is driven on falling edge of AUXPDM1_CLK The Auxiliary PDM interface must be disabled when updating this field. 3 AUXPDM1_MSTR 1 Auxiliary PDM 1 Master Mode select 0 = AUXPDM1_CLK Slave Mode (input) 1 = AUXPDM1_CLK Master mode (output) The Auxiliary PDM interface must be disabled when updating this field. 2 AUXPDM1_MUTE 0 Auxiliary PDM 1 Mute 0 = Unmute 1 = Mute 0 AUXPDM1_ENA 0 Auxiliary PDM 1 Enable 0 = Disabled 1 = Enabled 15:14 AUXPDM1_FREQ[1:0] 01 Auxiliary PDM 1 CLK Rate 00 = 3.072 MHz (2.8824 MHz) 10 = 1.536 MHz (1.4112 MHz) 01 = 2.048 MHz (1.8816 MHz) 11 = 768 kHz (705.6 kHz) The frequencies in brackets apply for 44.1 kHz–related sample rates only (i.e., if SYSCLK_FRAC = 1). The Auxiliary PDM interface must be disabled when updating this field. 4.2.11 DMIC Pin Configuration DMIC operation on input paths IN1–IN4 is selected using INn_MODE, as described in Table 4-3. If DMIC is selected, the respective DMICCLKn and DMICDATn pins are configured as digital outputs and inputs, respectively. The CS42L92 provides integrated pull-down resistors on each DMICDATn pin. This provides a flexible capability for interfacing with other devices. The DMICDATn pull-down resistors can be configured independently using the bits described in Table 4-10. Note that, if the DMICDATn DMIC input paths are disabled, the pull-down is disabled on the respective pin. Table 4-10. DMIC Interface Pull-Down Control Register Address R840 (0x0348) Dig_Mic_Pad_Ctrl 48 Bit 3 Label DMICDAT4_PD Default 0 2 DMICDAT3_PD 0 1 DMICDAT2_PD 0 0 DMICDAT1_PD 0 Description DMICDAT4 Pull-Down Control 0 = Disabled 1 = Enabled DMICDAT3 Pull-Down Control 0 = Disabled 1 = Enabled DMICDAT2 Pull-Down Control 0 = Disabled 1 = Enabled DMICDAT1 Pull-Down Control 0 = Disabled 1 = Enabled DS1162F1 CS42L92 4.3 Digital Core 4.3 Digital Core The CS42L92 digital core provides extensive mixing and processing capabilities for multiple signal paths. The configuration is highly flexible and supports virtually every conceivable input/output connection between the available processing blocks. The digital core provides parametric equalization (EQ) functions, DRC, and low-/high-pass filters (LHPF). The CS42L92 supports multiple signal paths through the digital core. Stereo full-duplex sample-rate conversion is provided to allow digital audio to be routed between input (ADC) paths, output (DAC) paths, digital audio interfaces (AIF1–AIF3) and SLIMbus paths operating at different sample rates or referenced to asynchronous clock domains. Data-format conversion (DFC) functions are available to support different interface standards on the input and output signal paths. The integrated DSP provides a general-purpose signal processing capability; this is supported by general-purpose timer and event-logger functions. Note that the DSP configuration data is lost whenever the DCVDD power domain is removed; the DSP configuration data must be downloaded to the CS42L92 each time the device is powered up. The digital core incorporates a S/PDIF transmitter that can provide a stereo S/PDIF output on a GPIO pin. Standard sample rates of 32–192 kHz can be supported. The CS42L92 incorporates a tone generator that can be used for beep functions through any of the audio signal paths. A white-noise generator is incorporated, to provide comfort noise in cases where silence (digital mute) is not desirable. A haptic signal generator is provided, for use with external haptic devices (e.g., mechanical vibration actuators). Two pulse-width modulation (PWM) signal generators are also provided; the PWM waveforms can be modulated by an audio source within the digital core and can be output on a GPIO pin. An overview of the digital-core mixing and signal-processing functions is provided in Fig. 4-15. The control registers associated with the digital-core signal paths are shown in Fig. 4-16 through Fig. 4-33. The full list of digital mixer control registers (R1600–R3576) is provided in Section 6. Generic register field definitions are provided in Table 4-11. The digital audio core is predominantly a 24-bit architecture, but also provides support for 32-bit signal paths. Audio data samples of up to 32 bits can be received via the AIF1, AIF3, and SLIMbus input channels and routed to the AIF1, AIF3, SLIMbus, S/PDIF, and DAC output paths. The respective output mixers provide full support for 32-bit data words. Note that all other signal paths and signal-processing blocks within the digital core are limited to 24-bit data length; data samples are truncated to 24-bit length if they are routed through any function that does not support 32-bit data words. DS1162F1 49 CS42L92 4.3 Digital Core DSP1 Silence (mute) IN1L signal path IN1R signal path AEC1 Loopback IN2L signal path DSP1 Ch 1 + AEC2 Loopback DSP1 Ch 2 IN2R signal path IN3L signal path DSP1 Ch 3 DSP Core Ultrasonic 1 path IN3R signal path DSP1 Ch 4 IN4L signal path IN4R signal path + Ultrasonic 2 path DSP1 Ch 5 DSP1 Ch 6 ISRC2 ISRC1 ASRC1 ASRC1 Left Asynchronous Sample Rate Converter (ASRC) Isochronous Sample Rate Converter (ISRC) ASRC1 Right ASRC1 Left ISRCn DEC1 ASRC1 Right ISRCn DEC2 OUT5 OUT3 OUT2 OUT1 ISRCn INT1 ISRCn INT2 + Stereo Output Paths DFC8 DFC7 DFC6 DFC5 DFC DFC4 DFC3 DFC2 DFC1 DFC DFCn OUTnL output + OUTnR output DFCn SLIMbus SLIMbus = 8 input , 8 output PWM2 PWM1 + PWM LHPF + LHPFn AIFn TX1 output EQ4 EQ3 EQ2 EQ1 (GPIO pin) + Haptic Signal Generator AIF1 (GPIO pin) + S/PDIF AIF3 AIF2 LHPF4 LHPF3 LHPF2 LHPF1 EQ + AIFn TX2 output EQn + AIFn TX... output Haptic Output DRC2 DRC1 White Noise Generator + AIFn TX... output + DRCn Left Noise Generator etc... DRC + Tone Generator Tone Generator 1 AIFn RX1 DRCn Right AIF1 = 8 input , 8 output AIF2 = 8 input , 8 output AIF3 = 8 input , 8 output AIFn RX2 AIFn RX... Tone Generator 2 AIFn RX... Figure 4-15. Digital Core 50 DS1162F1 CS42L92 4.3 Digital Core 4.3.1 Digital-Core Mixers The CS42L92 provides an extensive digital mixing capability. The digital-core mixing and signal-processing blocks are shown in Fig. 4-15. A four-input digital mixer is associated with many of these functions, as shown. The digital mixer circuit is identical in each instance, providing up to four selectable input sources, with independent volume control on each input. The control registers associated with the digital-core signal paths are shown in Fig. 4-16–Fig. 4-33. The full list of digital mixer control registers (R1600–R3576) is provided in Section 6. Further description of the associated control registers is provided throughout Section 4.3. Generic register field definitions are provided in Table 4-11. The digital mixer input sources are selected using the associated x_SRCn fields; the volume control is implemented via the associated x_VOLn fields. The ASRC, ISRC, DFC, and DSP auxiliary input functions support selectable input sources, but do not incorporate any digital mixing. The respective input source (x_SRCn) fields are identical to those of the digital mixers. The x_SRCn fields select the input sources for the respective mixer or signal-processing block. Note that the selected input sources must be configured for the same sample rate as the blocks to which they are connected. Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.15 and Section 4.3.16. The DFCs provide support for different data types, including floating point formats. Note that, if unsigned or floating point data is present within the digital core, some restrictions on the valid signal routing options apply—see Section 4.3.13. A status bit is associated with each configurable input source. If an underclocked error condition occurs, these bits indicate which signal paths have been enabled. The generic register field definition for the digital mixers is provided in Table 4-11. DS1162F1 51 CS42L92 4.3 Digital Core Table 4-11. Digital-Core Mixer Control Registers Register Address Bit Label R1600 (0x0640) 15 x_STSn to R3576 (0x0DF8) 7:1 x_VOLn 7:0 x_SRCn 4.3.2 Default Description 0 [Digital Core function] input n status 0 = Disabled 1 = Enabled 0x40 [Digital Core mixer] input n volume. (–32 dB to +16 dB in 1-dB steps) 0x00 to 0x20 = –32 dB ... (1-dB steps) 0x50 = +16 dB 0x21 = –31 dB 0x40 = 0 dB 0x51 to 0x7F = +16 dB 0x22 = –30 dB ... (1-dB steps) 0x00 [Digital Core function] input n source select 0x63 = LHPF4 0x2E = AIF2 RX7 0x00 = Silence (mute) 0x68 = DSP1 Channel 1 0x2F = AIF2 RX8 0x04 = Tone generator 1 0x69 = DSP1 Channel 2 0x30 = AIF3 RX1 0x05 = Tone generator 2 0x6A = DSP1 Channel 3 0x31 = AIF3 RX2 0x06 = Haptic generator 0x6B = DSP1 Channel 4 0x08 = AEC Loop-Back 1 0x32 = AIF3 RX3 0x6C = DSP1 Channel 5 0x09 = AEC Loop-Back 2 0x33 = AIF3 RX4 0x6D = DSP1 Channel 6 0x34 = AIF3 RX5 0x0D = Noise generator 0x90 = ASRC1 IN1 Left 0x35 = AIF3 RX6 0x10 = IN1L signal path 0x91 = ASRC1 IN1 Right 0x36 = AIF3 RX7 0x11 = IN1R signal path 0x92 = ASRC1 IN2 Left 0x37 = AIF3 RX8 0x12 = IN2L signal path 0x93 = ASRC1 IN2 Right 0x38 = SLIMbus RX1 0x13 = IN2R signal path 0xA0 = ISRC1 INT1 0x39 = SLIMbus RX2 0x14 = IN3L signal path 0xA1 = ISRC1 INT2 0x3A = SLIMbus RX3 0x15 = IN3R signal path 0xA4 = ISRC1 DEC1 0x3B = SLIMbus RX4 0x16 = IN4L signal path 0xA5 = ISRC1 DEC2 0x3C = SLIMbus RX5 0x17 = IN4R signal path 0xA8 = ISRC2 INT1 0x3D = SLIMbus RX6 0x20 = AIF1 RX1 0xA9 = ISRC2 INT2 0x3E = SLIMbus RX7 0x21 = AIF1 RX2 0xAC = ISRC2 DEC1 0x3F = SLIMbus RX8 0x22 = AIF1 RX3 0xAD = ISRC2 DEC2 0x50 = EQ1 0x23 = AIF1 RX4 0xF0 = US1 0x51 = EQ2 0x24 = AIF1 RX5 0xF1 = US2 0x52 = EQ3 0x25 = AIF1 RX6 0xF8 = DFC1 0x53 = EQ4 0x26 = AIF1 RX7 0xF9 = DFC2 0x58 = DRC1 Left 0x27 = AIF1 RX8 0xFA = DFC3 0x59 = DRC1 Right 0x28 = AIF2 RX1 0xFB = DFC4 0x5A = DRC2 Left 0x29 = AIF2 RX2 0xFC = DFC5 0x5B = DRC2 Right 0x2A = AIF2 RX3 0xFD = DFC6 0x60 = LHPF1 0x2B = AIF2 RX4 0xFE = DFC7 0x61 = LHPF2 0x2C = AIF2 RX5 0xFF = DFC8 0x62 = LHPF3 0x2D = AIF2 RX6 Digital-Core Inputs The digital core comprises multiple input paths, as shown in Fig. 4-16. Any of these inputs may be selected as a source to the digital mixers or signal-processing functions within the CS42L92 digital core. Note that the outputs from other blocks within the digital core may also be selected as input to the digital mixers or signal-processing functions within the CS42L92 digital core. Those input sources, which are not shown in Fig. 4-16, are described separately throughout Section 4.3. The hexadecimal numbers in Fig. 4-16 indicate the corresponding x_SRCn setting for selection of that signal as an input to another digital-core function. The sample rate for the input signal paths is configured by using the applicable IN_RATE, AIFn_RATE, SLIMRXn_RATE, or USn_RATE field; see Table 4-26. Note that sample-rate conversion is required when routing the input signal paths to any signal chain that is asynchronous or configured for a different sample rate. 52 DS1162F1 CS42L92 4.3 Digital Core Silence (mute) (0x00) AEC1 Loopback (0x08) AEC2 Loopback (0x09) IN1L signal path (0x10) IN1R signal path (0x11) IN2L signal path (0x12) IN2R signal path (0x13) IN3L signal path (0x14) IN3R signal path (0x15) IN4L signal path (0x16) IN4R signal path (0x17) AIF1 RX1 (0x20) AIF1 RX2 (0x21) AIF1 RX3 (0x22) AIF1 RX4 (0x23) AIF1 RX5 (0x24) AIF1 RX6 (0x25) AIF1 RX7 (0x26) AIF1 RX8 (0x27) AIF2 RX1 (0x28) AIF2 RX2 (0x29) AIF2 RX3 (0x2A) AIF2 RX4 (0x2B) AIF2 RX5 (0x2C) AIF2 RX6 (0x2D) AIF2 RX7 (0x2E) AIF2 RX8 (0x2F) AIF3 RX1 (0x30) AIF3 RX2 (0x31) AIF3 RX3 (0x32) AIF3 RX4 (0x33) AIF3 RX5 (0x34) AIF3 RX6 (0x35) AIF3 RX7 (0x36) AIF3 RX8 (0x37) SLIMbus RX1 (0x38) SLIMbus RX2 (0x39) SLIMbus RX3 (0x3A) SLIMbus RX4 (0x3B) SLIMbus RX5 (0x3C) SLIMbus RX6 (0x3D) SLIMbus RX7 (0x3E) SLIMbus RX8 (0x3F) Ultrasonic 1 (0xF0) Ultrasonic 2 (0xF1) Figure 4-16. Digital-Core Inputs 4.3.3 Digital-Core Output Mixers The digital core comprises multiple output paths. The output paths associated with AIF1–AIF3 are shown in Fig. 4-17. The output paths associated with OUT1–OUT5 are shown in Fig. 4-18. The output paths associated with the SLIMbus interface are shown in Fig. 4-19. A four-input mixer is associated with each output. The four input sources are selectable in each case, and independent volume control is provided for each path. DS1162F1 53 CS42L92 4.3 Digital Core The AIF1–AIF3 output mixer control fields (see Fig. 4-17) are located at register addresses R1792–R1983 (0x0700–0x07BF). The OUT1–OUT5 output mixer control fields (see Fig. 4-18) are located at addresses R1664–R1743 (0x0680–0x06CF). The SLIMbus output mixer control fields (see Fig. 4-19) are located at addresses R1984–R2047 (0x07C0–0x07FF). The full list of digital mixer control registers (R1600–R3576) is provided in Section 6. Generic register field definitions are provided in Table 4-11. The x_SRCn fields select the input sources for the respective mixers. Note that the selected input sources must be configured for the same sample rate as the mixer to which they are connected. Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.15 and Section 4.3.16. The sample rate for the output signal paths is configured using the applicable OUT_RATE, AIFn_RATE, or SLIMTXn_ RATE fields; see Table 4-26. Note that sample-rate conversion is required when routing the output signal paths to any signal chain that is asynchronous or configured for a different sample rate. The OUT_RATE, AIFn_RATE, or SLIMTXn_RATE fields must not be changed if any of the respective x_SRCn fields is nonzero. The associated x_SRCn fields must be cleared before writing new values to OUT_RATE, AIFn_RATE, or SLIMTXn_RATE. A minimum delay of 125 s must be allowed between clearing the x_SRCn fields and writing to the associated OUT_RATE, AIFn_RATE, or SLIMTXn_RATE fields. See Table 4-26 for details. The AIF1, AIF3, SLIMbus, and DAC (OUT1–OUT3) output mixers provide full support for 32-bit data words. Audio data samples up to 32 bits are supported on the AIF1, AIF3, and SLIMbus input channels, which can be routed to the AIF1, AIF3, SLIMbus, and DAC (OUT1–OUT3) output paths. Note that other signal paths and signal-processing blocks within the digital core are limited to 24-bit data length; data samples are truncated to 24-bit length if they are routed through any function that does not support 32-bit data words. The CS42L92 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the output mixer paths. If the frequency is too low, an attempt to enable an output mixer path fails. Note that active signal paths are not affected under such circumstances. The status bits in registers R1600–R3576 indicate the status of each digital mixer. If an underclocked error condition occurs, these bits indicate which mixers have been enabled. 54 DS1162F1 CS42L92 4.3 Digital Core x_SRCn p. 52 x_VOLn p. 52 … AIF1TXnMIX_SRC1 AIF1TXnMIX_VOL1 … AIF1TXnMIX_SRC2 AIF1TXnMIX_VOL2 … AIF1TXnMIX_SRC3 AIF1TXnMIX_VOL3 … AIF1TXnMIX_SRC4 AIF1TXnMIX_VOL4 + AIF1 TXn CS42L92 supports eight AIF1 output mixers, i.e., n = 1–8 … AIF2TXnMIX_SRC1 AIF2TXnMIX_VOL1 … AIF2TXnMIX_SRC2 AIF2TXnMIX_VOL2 … AIF2TXnMIX_SRC3 AIF2TXnMIX_VOL3 … AIF2TXnMIX_SRC4 AIF2TXnMIX_VOL4 + AIF2 TXn CS42L92 supports eight AIF2 output mixers, i.e., n = 1–8 … AIF3TXnMIX_SRC1 AIF3TXnMIX_VOL1 … AIF3TXnMIX_SRC2 AIF3TXnMIX_VOL2 … AIF3TXnMIX_SRC3 AIF3TXnMIX_VOL3 … AIF3TXnMIX_SRC4 AIF3TXnMIX_VOL4 + AIF3 TXn CS42L92 supports eight AIF3 output mixers, i.e., n = 1–8 Figure 4-17. Digital-Core AIF Outputs DS1162F1 55 CS42L92 4.3 Digital Core x_SRCn p. 52 x_VOLn p. 52 … OUTnLMIX_SRC1 OUTnLMIX_VOL1 … OUTnLMIX_SRC2 OUTnLMIX_VOL2 … OUTnLMIX_SRC3 OUTnLMIX_VOL3 … OUTnLMIX_SRC4 OUTnLMIX_VOL4 … OUTnRMIX_SRC1 OUTnRMIX_VOL1 … OUTnRMIX_SRC2 OUTnRMIX_VOL2 … OUTnRMIX_SRC3 OUTnRMIX_VOL3 … OUTnRMIX_SRC4 OUTnRMIX_VOL4 + OUTn Left + OUTn Right CS42L92 supports four stereo output mixer pairs, i.e., n = 1, 2, 3, or 5 Figure 4-18. Digital-Core OUTn Outputs x_SRCn p. 52 x_VOLn p. 52 … SLIMTXnMIX_SRC1 SLIMTXnMIX_VOL1 … SLIMTXnMIX_SRC2 SLIMTXnMIX_VOL2 … SLIMTXnMIX_SRC3 SLIMTXnMIX_VOL3 … SLIMTXnMIX_SRC4 SLIMTXnMIX_VOL4 + SLIMbus TXn CS42L92 supports eight SLIMbus output mixers, i.e., n = 1–8 Figure 4-19. Digital-Core SLIMbus Outputs 4.3.4 Five-Band Parametric Equalizer (EQ) The digital core provides four EQ processing blocks as shown in Fig. 4-20. A four-input mixer is associated with each EQ. The four input sources are selectable in each case, and independent volume control is provided for each path. Each EQ block supports one output. The EQ provides selective control of five frequency bands as follows: • 56 The low-frequency band (Band 1) filter can be configured as a peak filter or as a shelving filter. If configured as a shelving filter, it provides adjustable gain below the Band 1 cut-off frequency. As a peak filter, it provides adjustable gain within a defined frequency band that is centered on the Band 1 frequency. DS1162F1 CS42L92 4.3 Digital Core • The midfrequency bands (Band 2–Band 4) filters are peak filters that provide adjustable gain around the respective center frequency. • The high-frequency band (Band 5) filter is a shelving filter that provides adjustable gain above the Band 5 cut-off frequency. x_SRCn p. 52 x_VOLn p. 52 … EQnMIX_SRC1 EQnMIX_VOL1 … EQnMIX_SRC2 EQnMIX_VOL2 … EQnMIX_SRC3 EQnMIX_VOL3 … EQnMIX_SRC4 EQnMIX_VOL4 + EQ Five-band Equalizer EQ1 (0x50) EQ2 (0x51) EQ3 (0x52) EQ4 (0x53) CS42L92 supports four EQ blocks, i.e., n = 1–4 Figure 4-20. Digital-Core EQ Blocks The EQ1–EQ4 mixer control fields (see Fig. 4-20) are located at register addresses R2176–R2207 (0x0880–0x089F). The full list of digital-mixer control registers (R1600–R3576) is provided in Section 6. Generic register field definitions are provided in Table 4-11. The x_SRCn fields select the input sources for the respective EQ processing blocks. Note that the selected input sources must be configured for the same sample rate as the EQ to which they are connected. Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.15 and Section 4.3.16. The hexadecimal numbers in Fig. 4-20 indicate the corresponding x_SRCn setting for selection of that signal as an input to another digital-core function. The sample rate for the EQ function is configured using FX_RATE; see Table 4-26. Note that the EQ, DRC, and LHPF functions must be configured for the same sample rate. Sample-rate conversion is required when routing the EQ signal paths to any signal chain that is asynchronous or configured for a different sample rate. The FX_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields must be cleared before writing a new value to FX_RATE. A minimum delay of 125 s must be allowed between clearing the x_SRCn fields and writing to FX_RATE. See Table 4-26 for details. The cut-off or center frequencies for the five-band EQ are set by using the coefficients held in the registers identified in Table 4-12. These coefficients are derived using tools provided in Cirrus Logic’s WISCE™ evaluation-board control software; please contact your Cirrus Logic representative for details. Table 4-12. EQ Coefficient Registers EQ EQ1 EQ2 EQ3 EQ4 Register Addresses R3602 (0x0E10) to R3620 (0x0E24) R3624 (0x0E28) to R3642 (0x0E3A) R3646 (0x0E3E) to R3664 (0x0E53) R3668 (0x0E54) to R3686 (0x0E66) The control registers associated with the EQ functions are described in Table 4-13. DS1162F1 57 CS42L92 4.3 Digital Core Table 4-13. EQ Enable and Gain Control Register Address R3585 (0x0E01) FX_Ctrl2 Bit Label 15:4 FX_STS[11:0] R3600 (0x0E10) EQ1_1 15:11 10:6 5:1 0 R3601 (0x0E11) EQ1_2 15:11 EQ1_B4_GAIN[4:0] 10:6 EQ1_B5_GAIN[4:0] 0 EQ1_B1_MODE EQ1_B1_GAIN[4:0] EQ1_B2_GAIN[4:0] EQ1_B3_GAIN[4:0] EQ1_ENA R3602 (0x0E12) to 15:0 EQ1_B1_* R3620 (0x0E24) EQ1_B2_* EQ1_B3_* EQ1_B4_* EQ1_B5_* R3622 (0x0E26) 15:11 EQ2_B1_GAIN[4:0] EQ2_1 10:6 EQ2_B2_GAIN[4:0] 5:1 0 R3623 (0x0E27) EQ2_2 EQ2_B3_GAIN[4:0] EQ2_ENA 15:11 EQ2_B4_GAIN[4:0] 10:6 EQ2_B5_GAIN[4:0] 0 EQ2_B1_MODE R3624 (0x0E28) to 15:0 EQ2_B1_* R3642 (0x0E3A) EQ2_B2_* EQ2_B3_* EQ2_B4_* EQ2_B5_* R3644 (0x0E3C) 15:11 EQ3_B1_GAIN[4:0] 10:6 EQ3_B2_GAIN[4:0] EQ3_1 5:1 EQ3_B3_GAIN[4:0] 0 EQ3_ENA R3645 (0x0E3D) EQ3_2 58 15:11 EQ3_B4_GAIN[4:0] 10:6 EQ3_B5_GAIN[4:0] 0 EQ3_B1_MODE Default Description 0x00 LHPF, DRC, EQ Enable Status. Indicates the status of each respective signal-processing function. Each bit is coded as follows: 0 = Disabled 1 = Enabled [11] = EQ4 [7] = DRC2 (Right) [3] = LHPF4 [10] = EQ3 [6] = DRC2 (Left) [2] = LHPF3 [9] = EQ2 [5] = DRC1 (Right) [1] = LHPF2 [8] = EQ1 [4] = DRC1 (Left) [0] = LHPF1 0x0C EQ1 Band 1 Gain 1 (–12 dB to +12 dB in 1-dB steps) 0x0C EQ1 Band 2 Gain 1 (–12 dB to +12 dB in 1-dB steps) 0x0C EQ1 Band 3 Gain 1 (–12 dB to +12 dB in 1-dB steps) 0 EQ1 Enable 0 = Disabled 1 = Enabled 0x0C EQ1 Band 4 Gain 1 (–12 dB to +12 dB in 1-dB steps) 0x0C EQ1 Band 5 Gain 1 (–12 dB to +12 dB in 1-dB steps) 0 EQ1 Band 1 Mode 0 = Shelving filter 1 = Peak filter — EQ1 Frequency Coefficients. Refer to WISCE evaluation board control software for the derivation of these field values. 0x0C 0x0C 0x0C 0 0x0C 0x0C 0 — 0x0C 0x0C 0x0C 0 0x0C 0x0C 0 EQ2 Band 1 Gain 1 –12 dB to +12 dB in 1-dB steps EQ2 Band 2 Gain 1 –12 dB to +12 dB in 1-dB steps EQ2 Band 3 Gain 1 –12 dB to +12 dB in 1-dB steps EQ2 Enable 0 = Disabled 1 = Enabled EQ2 Band 4 Gain 1 (–12 dB to +12 dB in 1-dB steps) EQ2 Band 5 Gain 1 (–12 dB to +12 dB in 1-dB steps) EQ2 Band 1 Mode 0 = Shelving filter 1 = Peak filter EQ2 Frequency Coefficients. Refer to WISCE evaluation board control software for the derivation of these field values. EQ3 Band 1 Gain 1 (–12 dB to +12 dB in 1-dB steps) EQ3 Band 2 Gain 1 (–12 dB to +12 dB in 1-dB steps) EQ3 Band 3 Gain 1 (–12 dB to +12 dB in 1-dB steps) EQ3 Enable 0 = Disabled 1 = Enabled EQ3 Band 4 Gain1 (–12 dB to +12 dB in 1-dB steps) EQ3 Band 5 Gain 1 (–12 dB to +12 dB in 1-dB steps) EQ3 Band 1 Mode 0 = Shelving filter 1 = Peak filter DS1162F1 CS42L92 4.3 Digital Core Table 4-13. EQ Enable and Gain Control (Cont.) Register Address Bit Label Default Description R3646 (0x0E3E) to 15:0 EQ3_B1_* — EQ3 Frequency Coefficients. Refer to WISCE evaluation board control software for the derivation of these field values. R3664 (0x0E50) EQ3_B2_* EQ3_B3_* EQ3_B4_* EQ3_B5_* R3666 (0x0E52) 15:11 EQ4_B1_GAIN[4:0] 0x0C EQ4 Band 1 Gain 1 (–12 dB to +12 dB in 1-dB steps) 10:6 EQ4_B2_GAIN[4:0] 0x0C EQ4 Band 2 Gain 1 (–12 dB to +12 dB in 1-dB steps) EQ4_1 5:1 EQ4_B3_GAIN[4:0] 0x0C EQ4 Band 3 Gain 1 (–12 dB to +12 dB in 1-dB steps) 0 EQ4_ENA 0 EQ4 Enable 0 = Disabled 1 = Enabled R3667 (0x0E53) 15:11 EQ4_B4_GAIN[4:0] 0x0C EQ4 Band 4 Gain 1 (–12 dB to +12 dB in 1-dB steps) EQ4_2 10:6 EQ4_B5_GAIN[4:0] 0x0C EQ4 Band 5 Gain 1 (–12 dB to +12 dB in 1-dB steps 0 EQ4_B1_MODE 0 EQ4 Band 1 Mode 0 = Shelving filter 1 = Peak filter R3668 (0x0E54) to 15:0 EQ4_B1_* — EQ4 Frequency Coefficients. Refer to WISCE evaluation board control software for R3686 (0x0E66) the derivation of these field values. EQ4_B2_* EQ4_B3_* EQ4_B4_* EQ4_B5_* 1.See Table 4-14 for gain range. Table 4-14 lists the EQ gain control settings. Table 4-14. EQ Gain-Control Range EQ Gain Setting Gain (dB) EQ Gain Setting Gain (dB) 00000 –12 01101 +1 00001 –11 01110 +2 00010 –10 01111 +3 00011 –9 10000 +4 00100 –8 10001 +5 00101 –7 10010 +6 00110 –6 10011 +7 00111 –5 10100 +8 01000 –4 10101 +9 01001 –3 10110 +10 01010 –2 10111 +11 01011 –1 11000 +12 01100 0 11001–11111 Reserved The CS42L92 automatically checks to confirm whether the SYSCLK frequency is high enough to support the commanded EQ and digital mixing functions. If an attempt is made to enable an EQ signal path, and there are insufficient SYSCLK cycles to support it, the attempt does not succeed. Note that any signal paths that are already active are not affected under such circumstances. The FX_STS field in register R3585 indicates the status of each EQ, DRC, and LHPF signal path. If an underclocked error condition occurs, this field indicates which EQ, DRC, or LHPF signal paths have been enabled. The status bits in registers R1600–R3576 indicate the status of each digital mixer. If an underclocked error condition occurs, these bits indicate which mixers have been enabled. DS1162F1 59 CS42L92 4.3 Digital Core 4.3.5 Dynamic Range Control (DRC) The digital core provides two stereo DRC processing blocks, as shown in Fig. 4-21. A four-input mixer is associated with each DRC input channel. The input sources are selectable in each case, and independent volume control is provided for each path. The stereo DRC blocks support two outputs each. The function of the DRC is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range, for example, when recording from microphones built into a handheld system or to restrict the dynamic range of an output signal path. To improve intelligibility in the presence of loud impulsive noises, the DRC can apply compression and automatic level control to the signal path. It incorporates anticlip and quick-release features for handling transients. The DRC also incorporates a noise-gate function that provides additional attenuation of very low-level input signals. This means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these conditions. A signal-detect function is provided within the DRC; this can be used to detect the presence of an audio signal and to trigger other events. It can also be used as an interrupt event or to trigger the control-write sequencer. Note that DRC triggering of the control-write sequencer is supported for DRC1 only. x_SRCn p. 52 x_VOLn p. 52 … DRCnLMIX_SRC1 DRCnLMIX_VOL1 … DRCnLMIX_SRC2 DRCnLMIX_VOL2 … DRCnLMIX_SRC3 DRCnLMIX_VOL3 … DRCnLMIX_SRC4 DRCnLMIX_VOL4 … DRCnRMIX_SRC1 DRCnRMIX_VOL1 … DRCnRMIX_SRC2 DRCnRMIX_VOL2 … DRCnRMIX_SRC3 DRCnRMIX_VOL3 … DRCnRMIX_SRC4 DRCnRMIX_VOL4 + DRC Dynamic Range Controller + DRC Dynamic Range Controller DRC1 Left (0x58) DRC2 Left (0x5A) DRC1 Right (0x59) DRC2 Right (0x5B) CS42L92 supports two stereo DRC blocks, i.e., n = 1 or 2 Figure 4-21. Dynamic Range Control (DRC) Block The DRC1 and DRC2 mixer control fields (see Fig. 4-21) are located at register addresses R2240–R2271 (0x08C0–0x08DF). The full list of digital mixer control registers (R1600–R3576) is provided in Section 6. Generic register field definitions are provided in Table 4-11. The x_SRCn fields select the input sources for the respective DRC processing blocks. Note that the selected input sources must be configured for the same sample rate as the DRC to which they are connected. Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.15 and Section 4.3.16. 60 DS1162F1 CS42L92 4.3 Digital Core The hexadecimal numbers in Fig. 4-21 indicate the corresponding x_SRCn setting for selection of that signal as an input to another digital-core function. The sample rate for the DRC function is configured using FX_RATE; see Table 4-26. Note that the EQ, DRC, and LHPF functions must all be configured for the same sample rate. Sample-rate conversion is required when routing the DRC signal paths to any signal chain that is asynchronous or configured for a different sample rate. The FX_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields must be cleared before writing a new value to FX_RATE. A minimum delay of 125 s must be allowed between clearing the x_SRCn fields and writing to FX_RATE. See Table 4-26 for details. The DRC functions are enabled using the control registers described in Table 4-15. Table 4-15. DRC Enable Register Address R3712 (0x0E80) DRC1_ctrl1 R3720 (0x0E88) DRC2_ctrl1 Bit 1 Label DRC1L_ENA Default 0 0 DRC1R_ENA 0 1 DRC2L_ENA 0 0 DRC2R_ENA 0 Description DRC1 (left) enable 0 = Disabled 1 = Enabled DRC1 (right) enable 0 = Disabled 1 = Enabled DRC2 (left) enable 0 = Disabled 1 = Enabled DRC2 (right) enable 0 = Disabled 1 = Enabled The following description of the DRC is applicable to each DRC. The associated control fields are described in Table 4-17 and Table 4-18 for DRC1 and DRC2 respectively. 4.3.5.1 DRC Compression, Expansion, and Limiting The DRC supports two different compression regions, separated by a knee at a specific input amplitude. In the region above the knee, the compression slope DRCn_HI_COMP applies; in the region below the knee, the compression slope DRCn_LO_COMP applies. Note that n identifies the applicable DRC 1 or 2. The DRC also supports a noise-gate region, where low-level input signals are heavily attenuated. This function can be enabled or disabled according to the application requirements. The DRC response in this region is defined by the expansion slope DRCn_NG_EXP. For additional attenuation of signals in the noise-gate region, an additional knee can be defined (shown as Knee 2 in Fig. 4-22). When this knee is enabled, this introduces an infinitely steep drop-off in the DRC response pattern between the DRCn_LO_COMP and DRCn_NG_EXP regions. The overall DRC compression characteristic in steady state (i.e., where the input amplitude is near constant) is shown in Fig. 4-22. DS1162F1 61 CS42L92 4.3 Digital Core DRCn Output Amplitude (dB) (Y0) Knee 1 DRCn_KNEE_OP Knee 2 C DR P OM C _ LO n_ OMP HI_C _ n C DR DR Cn _N G _E XP DRCn_KNEE2_OP DRCn_KNEE2_IP DRCn_KNEE_IP 0dB DRCn Input Amplitude (dB) Figure 4-22. DRC Response Characteristic The slope of the DRC response is determined by DRCn_HI_COMP and DRCn_LO_COMP. A slope of 1 indicates constant gain in this region. A slope less than 1 represents compression (i.e., a change in input amplitude produces only a smaller change in output amplitude). A slope of 0 indicates that the target output amplitude is the same across a range of input amplitudes; this is infinite compression. When the noise gate is enabled, the DRC response in this region is determined by DRCn_NG_EXP. A slope of 1 indicates constant gain in this region. A slope greater than 1 represents expansion (i.e., a change in input amplitude produces a larger change in output amplitude). When the DRCn_KNEE2_OP knee is enabled (Knee 2 in Fig. 4-22), this introduces the vertical line in the response pattern shown, resulting in infinitely steep attenuation at this point in the response. The DRC parameters are listed in Table 4-16. Table 4-16. DRC Response Parameters Parameters 1 2 3 4 5 6 7 Parameter DRCn_KNEE_IP DRCn_KNEE_OP DRCn_HI_COMP DRCn_LO_COMP DRCn_KNEE2_IP DRCn_NG_EXP DRCn_KNEE2_OP Description Input level at Knee 1 (dB) Output level at Knee 2 (dB) Compression ratio above Knee 1 Compression ratio below Knee 1 Input level at Knee 2 (dB) Expansion ratio below Knee 2 Output level at Knee 2 (dB) The noise gate is enabled by setting DRCn_NG_ENA. When the noise gate is not enabled, Parameters 5–7 (see Table 4-16) are ignored, and the DRCn_LO_COMP slope applies to all input signal levels below Knee 1. The DRCn_KNEE2_OP knee is enabled by setting DRCn_KNEE2_OP_ENA. If this bit is not set, Parameter 7 is ignored and the Knee 2 position always coincides with the low end of the DRCn_LO_COMP region. The Knee 1 point in Fig. 4-22 is determined by DRCn_KNEE_IP and DRCn_KNEE_OP. 62 DS1162F1 CS42L92 4.3 Digital Core Parameter Y0, the output level for a 0 dB input, is not specified directly but can be calculated from the other parameters using Eq. 4-2. Y0 = DRCn_KNEE_OP –  DRCn_KNEE_IP  DRCn_HI_COMP  Equation 4-2. DRC Compression Calculation 4.3.5.2 Gain Limits The minimum and maximum gain applied by the DRC is set by DRCn_MINGAIN, DRCn_MAXGAIN, and DRCn_NG_ MINGAIN. These limits can be used to alter the DRC response from that shown in Fig. 4-22. If the range between maximum and minimum gain is reduced, the extent of the dynamic range control is reduced. The minimum gain in the compression regions of the DRC response is set by DRCn_MINGAIN. The minimum gain in the noise-gate region is set by DRCn_NG_MINGAIN. The minimum gain limit prevents excessive attenuation of the signal path. The maximum gain limit set by DRCn_MAXGAIN prevents quiet signals (or silence) from being excessively amplified. 4.3.5.3 Dynamic Characteristics The dynamic behavior determines how quickly the DRC responds to changing signal levels. Note that the DRC responds to the average (RMS) signal amplitude over a period of time. The DRCn_ATK determines how quickly the DRC gain decreases when the signal amplitude is high. The DRCn_DCY determines how quickly the DRC gain increases when the signal amplitude is low. These fields are described in Table 4-17 and Table 4-18. The register defaults are suitable for general-purpose microphone use. 4.3.5.4 Anticlip Control The DRC includes an anticlip function to avoid signal clipping when the input amplitude rises very quickly. This function uses a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically increasing the gain attack rate when required. The anticlip function is enabled using the DRCn_ANTICLIP bit. Note that the feed-forward processing increases the latency in the input signal path. The anticlip feature operates entirely in the digital domain; it cannot be used to prevent signal clipping in the analog domain nor in the source signal. Analog clipping can only be prevented by reducing the analog signal gain or by adjusting the source signal. It is recommended to disable the anticlip function if the quick-release function (see Section 4.3.5.5) is enabled. 4.3.5.5 Quick Release Control The DRC includes a quick-release function to handle short transient peaks that are not related to the intended source signal. For example, in handheld microphone recording, transient signal peaks sometimes occur due to user handling, key presses or accidental tapping against the microphone. The quick-release function ensures that these transients do not cause the intended signal to be masked by the longer time constant of DRCn_DCY. The quick-release function is enabled by setting the DRCn_QR bit. When this bit is enabled, the DRC measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a transient peak that may not be related to the intended source signal. If the crest factor exceeds the level set by DRCn_QR_THR, the normal decay rate (DRCn_ DCY) is ignored and a faster decay rate (DRCn_QR_DCY) is used instead. It is recommended to disable the quick-release function if the anticlip function (see Section 4.3.5.4) is enabled. DS1162F1 63 CS42L92 4.3 Digital Core 4.3.5.6 Signal Activity Detect The DRC incorporates a configurable signal-detect function, allowing the signal level at the DRC input to be monitored and to be used to trigger other events. This can be used to detect the presence of a microphone signal on an ADC or DMIC channel or to detect an audio signal received over the digital audio interface. The DRC signal-detect function is enabled by setting DRCn_SIG_DET. Note that the respective DRCn must also be enabled. The detection threshold is either a peak level (crest factor) or an RMS level, depending on DRCn_SIG_DET_ MODE. When peak level is selected, the threshold is determined by DRCn_SIG_DET_PK, which defines the applicable crest factor (peak-to-RMS ratio) threshold. If RMS level is selected, the threshold is set using DRCn_SIG_DET_RMS. The DRC signal-detect function is an input to the interrupt control circuit and can be used to trigger an interrupt event; see Section 4.15. The control-write sequencer can be triggered by the DRC1 signal-detect function. This is enabled by setting DRC1_ WSEQ_SIG_DET_ENA. See Section 4.18. Note that signal detection is supported on DRC1 and DRC2, but the triggering of the control-write sequencer is available on DRC1 only. 4.3.5.7 DRC Register Controls The DRC1 control registers are described in Table 4-17. Table 4-17. DRC1 Control Registers Register Address Bit Label R3585 (0x0E01) 15:4 FX_STS[11:0] FX_Ctrl2 64 Default Description 0x00 LHPF, DRC, EQ enable status. Indicates the status of each respective signal-processing function. Each bit is coded as follows: 0 = Disabled 1 = Enabled [11] = EQ4 [7] = DRC2 (Right) [3] = LHPF4 [10] = EQ3 [6] = DRC2 (Left) [2] = LHPF3 [9] = EQ2 [5] = DRC1 (Right) [1] = LHPF2 [8] = EQ1 [4] = DRC1 (Left) [0] = LHPF1 DS1162F1 CS42L92 4.3 Digital Core Table 4-17. DRC1 Control Registers (Cont.) Register Address Bit Label R3712 (0x0E80) 15:11 DRC1_SIG_ DET_RMS[4:0] DRC1_ctrl1 R3713 (0x0E81) DRC1_ctrl2 DS1162F1 Default Description 0x00 DRC1 Signal-Detect RMS Threshold. RMS signal level for signal-detect to be indicated when DRC1_SIG_DET_MODE = 1. 0x00 = –30 dB …. (1.5-dB steps) 0x1F = –76.5 dB 0x01 = –31.5 dB 0x1E = –75 dB 10:9 DRC1_SIG_ 00 DRC1 Signal-Detect Peak Threshold. This is the Peak/RMS ratio, or Crest Factor, level DET_PK[1:0] for signal-detect to be indicated when DRC1_SIG_DET_MODE = 0. 00 = 12 dB 10 = 24 dB 01 = 18 dB 11 = 30 dB 8 DRC1_NG_ENA 0 DRC1 Noise-Gate Enable 0 = Disabled 1 = Enabled 7 DRC1_SIG_ 0 DRC1 Signal-Detect Mode DET_MODE 0 = Peak threshold mode 1 = RMS threshold mode 6 DRC1_SIG_DET 0 DRC1 Signal-Detect Enable 0 = Disabled 1 = Enabled 5 DRC1_KNEE2_ 0 DRC1 KNEE2_OP Enable OP_ENA 0 = Disabled 1 = Enabled 4 DRC1_QR 1 DRC1 Quick-release Enable 0 = Disabled 1 = Enabled 3 DRC1_ANTICLIP 1 DRC1 Anticlip Enable 0 = Disabled 1 = Enabled 2 DRC1_WSEQ_ 0 DRC1 Signal-Detect Write Sequencer Select SIG_DET_ENA 0 = Disabled 1 = Enabled 12:9 DRC1_ATK[3:0] 0100 DRC1 Gain attack rate (seconds/6 dB) 1010 = 92.8 ms 0101 = 2.9 ms 0000 = Reserved 1011 = 185.6 ms 0110 = 5.8 ms 0001 = 181 s 1100 to 1111 = Reserved 0111 = 11.6 ms 0010 = 363 s 1000 = 23.2 ms 0011 = 726 s 1001 = 46.4 ms 0100 = 1.45 ms 8:5 DRC1_DCY[3:0] 1001 DRC1 Gain decay rate (seconds/6 dB) 1010 = 1.49 s 0101 = 46.5 ms 0000 = 1.45 ms 0001 = 2.9 ms 0110 = 93 ms 1011 = 2.97 s 1100 to 1111 = Reserved 0010 = 5.8 ms 0111 = 186 ms 0011 = 11.6 ms 1000 = 372 ms 1001 = 743 ms 0100 = 23.25 ms 4:2 DRC1_ 100 DRC1 Minimum gain to attenuate audio signals MINGAIN[2:0] 000 = 0 dB 011 = –24 dB 11X = Reserved 001 = –12 dB 100 = –36 dB 010 = –18 dB 101 = Reserved 1:0 DRC1_ 11 DRC1 Maximum gain to boost audio signals (dB) MAXGAIN[1:0] 00 = 12 dB 10 = 24 dB 01 = 18 dB 11 = 36 dB 65 CS42L92 4.3 Digital Core Table 4-17. DRC1 Control Registers (Cont.) Register Address Bit Label R3714 (0x0E82) 15:12 DRC1_NG_ MINGAIN[3:0] DRC1_ctrl3 11:10 DRC1_NG_ EXP[1:0] R3715 (0x0E83) DRC1_ctrl4 R3716 (0x0E84) DRC1_ctrl5 9:8 DRC1_QR_ THR[1:0] 7:6 DRC1_QR_ DCY[1:0] 5:3 DRC1_HI_ COMP[2:0] 2:0 DRC1_LO_ COMP[2:0] 10:5 DRC1_KNEE_ IP[5:0] 4:0 DRC1_KNEE_ OP[4:0] 9:5 DRC1_KNEE2_ IP[4:0] 4:0 DRC1_KNEE2_ OP[4:0] Default Description 0000 DRC1 Minimum gain to attenuate audio signals when the Noise Gate is active. 0000 = –36 dB 0101 = –6 dB 1010 = 24 dB 0110 = 0 dB 1011 = 30 dB 0001 = –30 dB 0010 = –24 dB 0111 = 6 dB 1100 = 36 dB 0011 = –18 dB 1000 = 12 dB 1101 to 1111 = Reserved 0100 = –12 dB 1001 = 18 dB 00 DRC1 Noise-Gate slope 00 = 1 (no expansion) 10 = 4 01 = 2 11 = 8 00 DRC1 Quick-release threshold (crest factor in dB) 00 = 12 dB 10 = 24 dB 01 = 18 dB 11 = 30 dB 00 DRC1 Quick-release decay rate (seconds/6 dB) 00 = 0.725 ms 10 = 5.8 ms 01 = 1.45 ms 11 = Reserved 011 DRC1 Compressor slope (upper region) 000 = 1 (no compression) 011 = 1/8 11X = Reserved 001 = 1/2 100 = 1/16 010 = 1/4 101 = 0 000 DRC1 Compressor slope (lower region) 000 = 1 (no compression) 011 = 1/8 11X = Reserved 001 = 1/2 100 = 0 010 = 1/4 101 = Reserved 0x00 DRC1 Input signal level at the compressor knee. 0x00 = 0 dB 0x02 = –1.5 dB 0x3C = –45 dB 0x01 = –0.75 dB … (–0.75-dB steps) 0x3D–0x3F = Reserved 0x00 DRC1 Output signal at the compressor knee. 0x00 = 0 dB 0x02 = –1.5 dB 0x1E = –22.5 dB 0x01 = –0.75 dB … (–0.75 dB steps) 0x1F = Reserved 0x00 DRC1 Input signal level at the noise-gate threshold, Knee 2. 0x00 = –36 dB 0x02 = –39 dB 0x1E = –81 dB 0x01 = –37.5 dB … (-1.5-dB steps) 0x1F = –82.5 dB Applicable if DRC1_NG_ENA = 1 0x00 DRC1 Output signal at the noise-gate threshold, Knee 2. 0x00 = –30 dB 0x02 = –33 dB 0x1E = –75 dB 0x01 = –31.5 dB … (–1.5dB steps) 0x1F = –76.5 dB Applicable only if DRC1_KNEE2_OP_ENA = 1 The DRC2 control registers are described in Table 4-18. Table 4-18. DRC2 Control Registers Register Address Bit Label R3585 (0x0E01) 15:4 FX_STS[11:0] FX_Ctrl2 66 Default Description 0x00 LHPF, DRC, EQ Enable Status. Indicates the status of each respective signal-processing function. Each bit is coded as follows: 0 = Disabled 1 = Enabled [7] = DRC2 (Right) [3] = LHPF4 [11] = EQ4 [10] = EQ3 [6] = DRC2 (Left) [2] = LHPF3 [9] = EQ2 [5] = DRC1 (Right) [1] = LHPF2 [8] = EQ1 [4] = DRC1 (Left) [0] = LHPF1 DS1162F1 CS42L92 4.3 Digital Core Table 4-18. DRC2 Control Registers (Cont.) Register Address Bit Label R3720 (0x0E88) 15:11 DRC2_SIG_ DET_RMS[4:0] DRC2_ctrl1 R3721 (0x0E89) DRC2_ctrl2 DS1162F1 Default Description 0x00 DRC2 Signal-Detect RMS Threshold. This is the RMS signal level for signal-detect to be indicated when DRC2_SIG_DET_MODE = 1. 0x00 = –30 dB …. (1.5-dB steps) 0x1E = –75 dB 0x01 = –31.5 dB 0x1F = –76.5 dB 10:9 DRC2_SIG_ 00 DRC2 Signal-Detect Peak Threshold. Peak/RMS ratio, or Crest Factor, level for DET_PK[1:0] signal-detect to be indicated when DRC2_SIG_DET_MODE = 0. 00 = 12 dB 10 = 24 dB 01 = 18 dB 11 = 30 dB 8 DRC2_NG_ENA 0 DRC2 Noise-Gate Enable 0 = Disabled 1 = Enabled 7 DRC2_SIG_ 0 DRC2 Signal-Detect Mode DET_MODE 0 = Peak threshold mode 1 = RMS threshold mode 6 DRC2_SIG_DET 0 DRC2 Signal-Detect Enable 0 = Disabled 1 = Enabled 5 DRC2_KNEE2_ 0 DRC2 KNEE2_OP Enable OP_ENA 0 = Disabled 1 = Enabled 4 DRC2_QR 1 DRC2 Quick-release Enable 0 = Disabled 1 = Enabled 3 DRC2_ANTICLIP 1 DRC2 Anticlip Enable 0 = Disabled 1 = Enabled 12:9 DRC2_ATK[3:0] 0100 DRC2 Gain attack rate (seconds/6 dB) 1010 = 92.8 ms 0101 = 2.9 ms 0000 = Reserved 1011 = 185.6 ms 0110 = 5.8 ms 0001 = 181 s 1100 to 1111 = Reserved 0111 = 11.6 ms 0010 = 363 s 1000 = 23.2 ms 0011 = 726 s 1001 = 46.4 ms 0100 = 1.45 ms 8:5 DRC2_DCY[3:0] 1001 DRC2 Gain decay rate (seconds/6 dB) 1010 = 1.49 s 0101 = 46.5 ms 0000 = 1.45 ms 1011 = 2.97 s 0110 = 93 ms 0001 = 2.9 ms 1100 to 1111 = Reserved 0111 = 186 ms 0010 = 5.8 ms 1000 = 372 ms 0011 = 11.6 ms 0100 = 23.25 ms 1001 = 743 ms 4:2 DRC2_ 100 DRC2 Minimum gain to attenuate audio signals MINGAIN[2:0] 000 = 0 dB 011 = –24 dB 11X = Reserved 001 = –12 dB (default) 100 = –36 dB 010 = –18 dB 101 = Reserved 1:0 DRC2_ 11 DRC2 Maximum gain to boost audio signals (dB) MAXGAIN[1:0] 00 = 12 dB 10 = 24 dB 01 = 18 dB 11 = 36 dB 67 CS42L92 4.3 Digital Core Table 4-18. DRC2 Control Registers (Cont.) Register Address Bit Label R3722 (0x0E8A) 15:12 DRC2_NG_ MINGAIN[3:0] DRC2_ctrl3 11:10 DRC2_NG_ EXP[1:0] R3723 (0x0E8B) DRC2_ctrl4 R3724 (0x0E8C) DRC2_ctrl5 9:8 DRC2_QR_ THR[1:0] 7:6 DRC2_QR_ DCY[1:0] 5:3 DRC2_HI_ COMP[2:0] 2:0 DRC2_LO_ COMP[2:0] 10:5 DRC2_KNEE_ IP[5:0] 4:0 DRC2_KNEE_ OP[4:0] 9:5 DRC2_KNEE2_ IP[4:0] 4:0 DRC2_KNEE2_ OP[4:0] Default Description 0000 DRC2 Minimum gain to attenuate audio signals when the Noise Gate is active. 0000 = –36 dB 0101 = –6 dB 1010 = 24 dB 0110 = 0 dB 1011 = 30 dB 0001 = –30 dB 0010 = –24 dB 0111 = 6 dB 1100 = 36 dB 0011 = –18 dB 1000 = 12 dB 1101 to 1111 = Reserved 0100 = –12 dB 1001 = 18 dB 00 DRC2 Noise-Gate slope 00 = 1 (no expansion) 10 = 4 01 = 2 11 = 8 00 DRC2 Quick-release threshold (crest factor in dB) 00 = 12 dB 10 = 24 dB 01 = 18 dB 11 = 30 dB 00 DRC2 Quick-release decay rate (seconds/6 dB) 00 = 0.725 ms 10 = 5.8 ms 01 = 1.45 ms 11 = Reserved 011 DRC2 Compressor slope (upper region) 000 = 1 (no compression) 011 = 1/8 11X = Reserved 001 = 1/2 100 = 1/16 010 = 1/4 101 = 0 000 DRC2 Compressor slope (lower region) 000 = 1 (no compression) 011 = 1/8 11X = Reserved 001 = 1/2 100 = 0 010 = 1/4 101 = Reserved 000000 DRC2 Input signal level at the compressor knee. 0x00 = 0 dB 0x02 = –1.5 dB 0x3C = –45 dB 0x01 = –0.75 dB … (–0.75-dB steps) 0x3D–0x3F = Reserved 00000 DRC2 Output signal at the compressor knee. 0x00 = 0 dB 0x02 = –1.5 dB 0x1E = –22.5 dB 0x01 = –0.75 dB … (–0.75 dB steps) 0x1F = Reserved 00000 DRC2 Input signal level at the noise-gate threshold, Knee 2. 0x00 = –36 dB 0x02 = –39 dB 0x1E = –81 dB 0x01 = –37.5 dB … (-1.5-dB steps) 0x1F = –82.5 dB Applicable only if DRC2_NG_ENA = 1. 00000 DRC2 Output signal at the noise-gate threshold, Knee 2. 0x00 = –30 dB 0x02 = –33 dB 0x1E = –75 dB 0x01 = –31.5 dB … (–1.5dB steps) 0x1F = –76.5 dB Applicable only if DRC2_KNEE2_OP_ENA = 1. The CS42L92 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded DRC and digital mixing functions. If the frequency is too low, an attempt to enable a DRC signal path fails. Note that active signal paths are not affected under such circumstances. The FX_STS field in register R3585 indicates the status of each EQ, DRC, and LHPF signal path. If an underclocked error condition occurs, this field indicates which EQ, DRC, or LHPF signal paths have been enabled. The status bits in registers R1600–R3576 indicate the status of each digital mixer. If an underclocked error condition occurs, these bits indicate which mixers have been enabled. 4.3.6 Low-/High-Pass Digital Filter (LHPF) The digital core provides four LHPF processing blocks as shown in Fig. 4-23. A four-input mixer is associated with each filter. The four input sources are selectable in each case, and independent volume control is provided for each path. Each LHPF block supports one output. The LHPF /HPF can be used to remove unwanted out-of-band noise from a signal path. Each filter can be configured either as a low-pass filter (LPF) or a high-pass filter (HPF). 68 DS1162F1 CS42L92 4.3 Digital Core x_SRCn p. 52 x_VOLn p. 52 … LHPFnMIX_SRC1 LHPFnMIX_VOL1 … LHPFnMIX_SRC2 LHPFnMIX_VOL2 + … LHPFnMIX_SRC3 LHPFnMIX_VOL3 Low-Pass filter (LPF) / High-Pass filter (HPF) … LHPFnMIX_SRC4 LHPFnMIX_VOL4 LHPF LHPF1 (0x60) LHPF2 (0x61) LHPF3 (0x62) LHPF4 (0x63) CS42L92 supports four LHPF blocks, i.e., n = 1–4 Figure 4-23. Digital-Core LPF/HPF Blocks The LHPF1–LHPF4 mixer control fields, shown in Fig. 4-23, are located at register addresses R2304–R2335 (0x0900–0x091F). The full list of digital mixer control registers (R1600–R3576) is provided in Section 6. Generic register field definitions are provided in Table 4-11. The x_SRCn fields select the input sources for the respective LHPF processing blocks. Note that the selected input sources must be configured for the same sample rate as the LHPF to which they are connected. Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.15 and Section 4.3.16. The hexadecimal numbers in Fig. 4-23 indicate the corresponding x_SRCn setting for selection of that signal as an input to another digital-core function. The sample rate for the LHPF function is configured using FX_RATE; see Table 4-26. Note that the EQ, DRC, and LHPF functions must all be configured for the same sample rate. Sample-rate conversion is required when routing the LHPF signal paths to any signal chain that is asynchronous or configured for a different sample rate. The FX_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields must be cleared before writing a new value to FX_RATE. A minimum delay of 125 s must be allowed between clearing the x_SRCn fields and writing to FX_RATE. See Table 4-26 for details. The control registers associated with the LHPF functions are described in Table 4-19. The cut-off frequencies for the LHPF blocks are set by using the coefficients held in registers R3777, R3781, R3785, and R3789 for LHPF1, LHPF2, LHPF3 and LHPF4 respectively. These coefficients are derived using tools provided in Cirrus Logic’s WISCE evaluation board control software; please contact your Cirrus Logic representative for details. Table 4-19. Low-Pass Filter/High-Pass Filter Register Address Bit Label R3585 (0x0E01) 15:4 FX_STS[11:0] FX_Ctrl2 DS1162F1 Default Description 0x00 LHPF, DRC, EQ Enable Status. Indicates the status of the respective signal-processing functions. Each bit is coded as follows: 0 = Disabled 1 = Enabled [11] = EQ4 [7] = DRC2 (Right) [3] = LHPF4 [10] = EQ3 [6] = DRC2 (Left) [2] = LHPF3 [9] = EQ2 [5] = DRC1 (Right) [1] = LHPF2 [8] = EQ1 [4] = DRC1 (Left) [0] = LHPF1 69 CS42L92 4.3 Digital Core Table 4-19. Low-Pass Filter/High-Pass Filter (Cont.) Register Address Bit Label R3776 (0x0EC0) 1 LHPF1_MODE HPLPF1_1 0 R3777 (0x0EC1) HPLPF1_2 R3780 (0x0EC4) HPLPF2_1 R3781 (0x0EC5) HPLPF2_2 R3784 (0x0EC8) HPLPF3_1 R3785 (0x0EC9) HPLPF3_2 R3788 (0x0ECC) HPLPF4_1 R3789 (0x0ECD) HPLPF4_2 LHPF1_ENA 15:0 LHPF1_COEFF[15:0] 1 LHPF2_MODE 0 LHPF2_ENA 15:0 LHPF2_COEFF[15:0] 1 LHPF3_MODE 0 LHPF3_ENA 15:0 LHPF3_COEFF[15:0] 1 LHPF4_MODE 0 LHPF4_ENA 15:0 LHPF4_COEFF[15:0] Default Description 0 Low-/High-Pass Filter 1 Mode 0 = Low Pass 1 = High Pass 0 Low-/High-Pass Filter 1 Enable 0 = Disabled 1 = Enabled 0x0000 Low-/High-Pass Filter 1 Frequency Coefficient Refer to WISCE evaluation board control software for the derivation of this field value. 0 Low-/High-Pass Filter 2 Mode 0 = Low Pass 1 = High Pass 0 Low-/High-Pass Filter 2 Enable 0 = Disabled 1 = Enabled 0x0000 Low-/High-Pass Filter 2 Frequency Coefficient Refer to WISCE evaluation board control software for the derivation of this field value. 0 Low-/High-Pass Filter 3 Mode 0 = Low Pass 1 = High Pass 0 Low-/High-Pass Filter 3 Enable 0 = Disabled 1 = Enabled 0x0000 Low-/High-Pass Filter 3 Frequency Coefficient Refer to WISCE evaluation board control software for the derivation of this field value. 0 Low-/High-Pass Filter 4 Mode 0 = Low Pass 1 = High Pass 0 Low-/High-Pass Filter 4 Enable 0 = Disabled 1 = Enabled 0x0000 Low-/High-Pass Filter 4 Frequency Coefficient Refer to WISCE evaluation board control software for the derivation of this field value. The CS42L92 performs automatic checks to confirm whether the SYSCLK frequency is high enough to support the commanded LHPF and digital mixing functions. If the frequency is too low, an attempt to enable an LHPF signal path fails. Note that active signal paths are not affected under such circumstances. The FX_STS field in register R3585 indicates the status of each EQ, DRC, and LHPF signal path. If an underclocked error condition occurs, this field indicates which EQ, DRC, or LHPF signal paths have been enabled. The status bits in registers R1600–R3576 indicate the status of each digital mixer. If an underclocked error condition occurs, these bits indicate which mixers have been enabled. 4.3.7 Digital-Core DSP The digital core provides one programmable DSP processing block as shown in Fig. 4-24. The DSP block supports eight inputs (Left, Right, Aux1, Aux2, … Aux6). A four-input mixer is associated with the left and right inputs, providing further expansion of the number of input paths. Each of the input sources is selectable, and independent volume control is provided for left and right input mixer channels. The DSP block supports six outputs. The functionality of the DSP processing block is not fixed; application-specific algorithms can be implemented according to different customer requirements. The procedure for configuring the CS42L92 DSP functions is tailored to each customer’s application; please contact your Cirrus Logic representative for details. 70 DS1162F1 CS42L92 4.3 Digital Core For details of the DSP firmware requirements relating to clocking, register access, and code execution, refer to Section 4.4.3. x_SRCn p. 52 x_VOLn p. 52 … DSP1LMIX_SRC1 DSP1LMIX_VOL1 … DSP1LMIX_SRC2 DSP1LMIX_VOL2 … DSP1LMIX_SRC3 DSP1LMIX_VOL3 … DSP1LMIX_SRC4 + DSP1 Channel 1 (0x68) DSP1 Channel 2 (0x69) DSP1LMIX_VOL4 DSP1 Channel 3 (0x6A) DSP DSP1 Channel 4 (0x6B) DSP1RMIX_VOL4 … DSP1AUX6_SRC DSP1RMIX_VOL3 … DSP1RMIX_SRC4 … DSP1AUX5_SRC … DSP1RMIX_SRC3 DSP1 Channel 6 (0x6D) + … DSP1AUX4_SRC DSP1RMIX_VOL2 … DSP1AUX3_SRC … DSP1RMIX_SRC2 DSP1 Channel 5 (0x6C) … DSP1AUX2_SRC DSP1RMIX_VOL1 … DSP1AUX1_SRC … DSP1RMIX_SRC1 Figure 4-24. Digital-Core DSP Block The DSP mixer input control fields (see Fig. 4-24) are located at register addresses R2368–R2424 (0x0940–0x0978). The full list of digital mixer control registers (R1600–R3576) is provided in Section 6. Generic register field definitions are provided in Table 4-11. The x_SRCn fields select the input sources for the DSP processing block. Note that the selected input sources must be configured for the same sample rate as the DSP. Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.16. The hexadecimal numbers in Fig. 4-24 indicate the corresponding x_SRCn setting for selection of that signal as an input to another digital-core function. The sample rate for the DSP functions is configured using the DSP1_RATE field; see Table 4-26. Sample-rate conversion is required when routing the DSP signal paths to any signal chain that is configured for a different sample rate. The DSP1_RATE field must not be changed if any of the respective x_SRCn fields is nonzero. The associated x_SRCn fields must be cleared before writing new values to DSP1_RATE. A minimum delay of 125 s must be allowed between clearing the x_SRCn fields and writing to the DSP1_RATE field. See Table 4-26 for details. The CS42L92 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the required DSP mixing functions. If the frequency is too low, an attempt to enable a DSP mixer path fails. Note that active signal paths are not affected under such circumstances. DS1162F1 71 CS42L92 4.3 Digital Core The status bits in registers R1600–R3576 indicate the status of each digital mixer. If an underclocked error condition occurs, these bits indicate which mixers have been enabled. 4.3.8 S/PDIF Output Generator The CS42L92 incorporates an IEC-60958-3–compatible S/PDIF output generator, as shown in Fig. 4-25; this provides a stereo S/PDIF output on a GPIO pin. The S/PDIF transmitter allows full control over the S/PDIF validity bits and channel status information. The input sources to the S/PDIF transmitter are selectable for each channel, and independent volume control is provided for each path. The *TX1 and *TX2 fields control Channels A and B (respectively) of the S/PDIF output. The S/PDIF signal can be output directly on a GPIO pin. See Section 4.14 to configure a GPIO pin for this function. Note that the S/PDIF signal cannot be selected as input to the digital mixers or signal-processing functions within the CS42L92 digital core. … SPDIF1TX1_SRC Channel A SPDIF1TX1_VOL … SPDIF1TX2_SRC S/PDIF Channel B SPDIF1TX2_VOL GPIO (GPn_FN = 0x04C) SPD1_ENA p. 73 SPD1_RATE[4:0] p. 86 x_SRCn p. 52 x_VOLn p. 52 Figure 4-25. Digital-Core S/PDIF Output Generator The S/PDIF input control fields (see Fig. 4-25) are located at register addresses R2048–R2057 (0x0800–0x0809). The full list of digital mixer control registers (R1600–R3576) is provided in Section 6. Generic register field definitions are provided in Table 4-11. The x_SRCn fields select the input sources for the two S/PDIF channels. Note that the selected input sources must be synchronized to the SYSCLK clocking domain, and configured for the same sample rate as the S/PDIF generator. Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.15 and Section 4.3.16. The sample rate of the S/PDIF generator is configured using SPD1_RATE; see Table 4-26. The S/PDIF transmitter supports sample rates in the range 32–192 kHz. Note that sample-rate conversion is required when linking the S/PDIF generator to any signal chain that is asynchronous or configured for a different sample rate. The SPD1_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields must be cleared before writing a new value to SPD1_RATE. A minimum delay of 125 s must be allowed between clearing the x_SRCn fields and writing to SPD1_RATE. See Table 4-26 for details. The S/PDIF generator is enabled by setting SPD1_ENA, as described in Table 4-20. The S/PDIF output contains audio data derived from the selected sources. Audio samples up to 24-bit width can be accommodated. The validity bits and the channel status bits in the S/PDIF data are configured using the corresponding fields in registers R1474 (0x5C2) to R1477 (0x5C5). Refer to the S/PDIF specification (IEC60958-3 Digital Audio Interface - Consumer) for full details of the S/PDIF protocol and configuration parameters. 72 DS1162F1 CS42L92 4.3 Digital Core Table 4-20. S/PDIF Output Generator Control Register Address R1474 (0x05C2) SPD1_TX_Control Bit 13 12 0 15:8 7:6 5:3 2 1 0 R1476 (0x05C4) 15:12 SPD1_TX_ 11:8 Channel_Status_2 7:4 3:0 R1477 (0x05C5) 11:8 SPD1_TX_ 7:5 Channel_Status_3 4 3:2 1:0 R1475 (0x05C3) SPD1_TX_ Channel_Status_1 Label SPD1_VAL2 SPD1_VAL1 SPD1_ENA Default 0 0 0 SPD1_CATCODE[7:0] SPD1_CHSTMODE[1:0] SPD1_PREEMPH[2:0] SPD1_NOCOPY SPD1_NOAUDIO SPD1_PRO SPD1_FREQ[3:0] SPD1_CHNUM2[3:0] SPD1_CHNUM1[3:0] SPD1_SRCNUM[3:0] SPD1_ORGSAMP[3:0] SPD1_TXWL[2:0] SPD1_MAXWL SPD1_SC31_30[1:0] SPD1_CLKACU[1:0] 0x00 00 000 0 0 0 0000 1011 0000 0001 0000 000 0 00 00 Description S/PDIF Validity (Subframe B) S/PDIF Validity (Subframe A) S/PDIF Generator Enable 0 = Disabled 1 = Enabled S/PDIF Category code S/PDIF Channel Status mode S/PDIF Preemphasis mode S/PDIF Copyright status S/PDIF Audio/nonaudio indication S/PDIF Consumer Mode/Professional Mode S/PDIF Indicated sample frequency S/PDIF Channel number (Subframe B) S/PDIF Channel number (Subframe A) S/PDIF Source number S/PDIF Original sample frequency S/PDIF Audio sample word length S/PDIF Maximum audio sample word length S/PDIF Channel Status [31:30] Transmitted Clock accuracy The S/PDIF output generator provides full support for 32-bit data words. Audio data samples up to 32 bits are supported on the AIF1, AIF3, and SLIMbus input channels, which can be routed to the S/PDIF output. Note that other signal paths and signal-processing blocks within the digital core are limited to 24-bit data length; data samples are truncated to 24-bit length if they are routed through any function that does not support 32-bit data words. The CS42L92 automatically checks to confirm whether the SYSCLK frequency is high enough to support the digital mixer paths. If an attempt is made to enable the S/PDIF generator, and there are insufficient SYSCLK cycles to support it, the attempt does not succeed. Note that any active signal paths are unaffected under such circumstances. The status bits in registers R1600–R3576 indicate the status of each digital mixer. If an underclocked error condition occurs, these bits indicate which mixers have been enabled. 4.3.9 Tone Generator The CS42L92 incorporates a tone generator that can be used for beep functions through any of the audio signal paths. The tone generator provides two 1-kHz outputs, with configurable phase relationship, offering flexibility to create differential signals or test scenarios. 1-kHz Tone Generator Tone Generator 1 (0x04) Tone Generator 2 (0x05) TONE1_ENA p. 74 TONE2_ENA p. 74 TONE_OFFSET[1:0] p. 74 TONE_RATE[4:0] p. 85 TONE1_OVD p. 74 TONE1_LVL[23:8] p. 74 TONE2_OVD p. 74 TONE2_LVL[23:8] p. 74 Figure 4-26. Digital-Core Tone Generator The tone generator outputs can be selected as input to any of the digital mixers or signal-processing functions within the CS42L92 digital core. The hexadecimal numbers in Fig. 4-26 indicate the corresponding x_SRCn setting for selection of that signal as an input to another digital-core function. DS1162F1 73 CS42L92 4.3 Digital Core The sample rate for the tone generator is configured using TONE_RATE. See Table 4-26. Note that sample-rate conversion is required when routing the tone generator outputs to any signal chain that is asynchronous or configured for a different sample rate. The tone generator outputs are enabled by setting the TONE1_ENA and TONE2_ENA bits as described in Table 4-21. The phase relationship is configured using TONE_OFFSET. The tone generator outputs can also provide a configurable DC signal level, for use as a test signal. The DC output is selected using the TONEn_OVD bits, and the DC signal amplitude is configured using the TONEn_LVL fields, as described in Table 4-21. Table 4-21. Tone Generator Control Register Address Bit Label Default Description R32 (0x0020) 9:8 TONE_ 00 Tone Generator Phase Offset. Sets the phase of Tone Generator 2 relative to Tone OFFSET[1:0] Generator 1 Tone_Generator_1 00 = 0° (in phase) 01 = 90° ahead 10 = 180° ahead 11 = 270° ahead 5 TONE2_ 0 Tone Generator 2 Override OVD 0 = Disabled (1-kHz tone output) 1 = Enabled (DC signal output) The DC signal level, when selected, is configured using TONE2_LVL[23:0] 4 TONE1_ 0 Tone Generator 1 Override OVD 0 = Disabled (1-kHz tone output) 1 = Enabled (DC signal output) The DC signal level, when selected, is configured using TONE1_LVL[23:0] 1 TONE2_ENA 0 Tone Generator 2 Enable 0 = Disabled 1 = Enabled 0 TONE1_ENA 0 Tone Generator 1 Enable 0 = Disabled 1 = Enabled R33 (0x0021) 15:0 TONE1_ 0x1000 Tone Generator 1 DC output level LVL[23:8] Tone_Generator_2 TONE1_LVL[23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. The digital core 0 dBFS level corresponds to 0x10_0000 (+1) or 0xF0_0000 (–1). R34 (0x0022) 7:0 TONE1_ 0x00 Tone Generator 1 DC output level LVL[7:0] Tone_Generator_3 TONE1_LVL[23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. The digital core 0 dBFS level corresponds to 0x10_0000 (+1) or 0xF0_0000 (–1). R35 (0x0023) 15:0 TONE2_ 0x1000 Tone Generator 2 DC output level LVL[23:8] Tone_Generator_4 TONE2_LVL[23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. The digital core 0 dBFS level corresponds to 0x10_0000 (+1) or 0xF0_0000 (–1). R36 (0x0024) 7:0 TONE2_ 0x00 Tone Generator 2 DC output level LVL[7:0] Tone_Generator_5 TONE2_LVL[23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. The digital core 0 dBFS level corresponds to 0x10_0000 (+1) or 0xF0_0000 (–1). 4.3.10 Noise Generator The CS42L92 incorporates a white-noise generator that can be routed within the digital core. The main purpose of the noise generator is to provide comfort noise in cases where silence (digital mute) is not desirable. 74 DS1162F1 CS42L92 4.3 Digital Core White Noise Generator Noise Generator (0x0D) NOISE_GEN_ENA p. 75 NOISE_GEN_GAIN[4:0] p. 75 NOISE_GEN_RATE[4:0] p. 85 Figure 4-27. Digital-Core Noise Generator The noise generator can be selected as input to any of the digital mixers or signal-processing functions within the CS42L92 digital core. The hexadecimal number (0x0D) in Fig. 4-27 indicates the corresponding x_SRCn setting for selection of the noise generator as an input to another digital-core function. The sample rate for the noise generator is configured using NOISE_GEN_RATE. See Table 4-26. Note that sample-rate conversion is required when routing the noise generator output to any signal chain that is asynchronous or configured for a different sample rate. The noise generator is enabled by setting NOISE_GEN_ENA, described in Table 4-22. The signal level is configured using NOISE_GEN_GAIN. Table 4-22. Noise Generator Control Register Address R160 (0x00A0) Comfort_Noise_ Generator Bit 5 Label NOISE_GEN_ ENA Default 0 4:0 NOISE_GEN_ GAIN[4:0] 0x00 Description Noise Generator Enable 0 = Disabled 1 = Enabled Noise generator signal level 0x00 = –114 dBFS …(6-dB steps) All other codes are reserved 0x01 = –108 dBFS 0x11 = –6 dBFS 0x02 = –102 dBFS 0x12 = 0 dBFS 4.3.11 Haptic Signal Generator The CS42L92 incorporates a signal generator for use with haptic devices (e.g., mechanical vibration actuators). The haptic signal generator is compatible with both eccentric rotating mass (ERM) and linear resonant actuator (LRA) haptic devices. The haptic signal generator is highly configurable, and includes the capability to execute a programmable event profile comprising three distinct operating phases. The resonant frequency of the haptic signal output (for LRA devices) is selectable, providing support for many different actuator components. The haptic signal generator is a digital signal generator, which is incorporated within the digital core of the CS42L92. In a typical use case the haptic signal may be routed, via one of the digital-core output mixers, to the digital PDM output. An external amplifier can be used to drive the haptic device, as shown in Fig. 4-28. DS1162F1 75 CS42L92 4.3 Digital Core Digital Core Output Mixer Haptic Signal Generator Haptic Output (06h) HAP_ACT p. 76 HAP_CTRL[1:0] p. 76 ONESHOT_TRIG p. 76 LRA_FREQ[14:0] p. 77 HAP_RATE[4:0] p. 85 Output Volume PDM Output + OUTnxMIX_SRCn OUTnxMIX_VOLn External Amplifier Haptic Device x_SRCn p. 52 x_VOLn p. 52 Figure 4-28. Digital-Core Haptic Signal Generator The hexadecimal number (0x06) in Fig. 4-28 indicates the corresponding x_SRCn setting for selection of the haptic signal generator as an input to another digital-core function. The haptic signal generator is selected as input to one of the digital-core output mixers by setting the x_SRCn field of the applicable output mixer to 0x06. The sample rate for the haptic signal generator is configured using the HAP_RATE field. See Table 4-26. Note that sample-rate conversion is required when routing the haptic signal generator output to any signal chain that is asynchronous or configured for a different sample rate. The haptic signal generator is configured for an ERM or LRA actuator using the HAP_ACT bit. The required resonant frequency is configured using the LRA_FREQ field. Note that the resonant frequency is only applicable to LRA actuators. The signal generator can be enabled in continuous mode or configured for one-shot mode using the HAP_CTRL field, as described in Table 4-23. In one-shot mode, the output is triggered by writing to the ONESHOT_TRIG bit. In one-shot mode, the signal generator profile comprises the distinct phases (1, 2, 3). The duration and intensity of each output phase is programmable. In continuous mode, the signal intensity is controlled using the PHASE2_INTENSITY field only. In the case of an ERM actuator (HAP_ACT = 0), the haptic output is a DC signal level, which may be positive or negative, as selected by the x_INTENSITY fields. For an LRA actuator (HAP_ACT = 1), the haptic output is an AC signal; selecting a negative signal level corresponds to a 180° phase inversion. In some applications, phase inversion may be desirable during the final phase, to halt the physical motion of the haptic device. Table 4-23. Haptic Signal Generator Control Register Address Bit Label R144 (0x0090) 4 ONESHOT_ TRIG Haptics_Control_1 3:2 HAP_CTRL[1:0] 1 76 HAP_ACT Default Description 0 Haptic One-Shot Trigger. Writing 1 starts the one-shot profile (i.e., Phase 1, Phase 2, Phase 3) 00 Haptic Signal Generator Control 00 = Disabled 10 = One-Shot 01 = Continuous 11 = Reserved 0 Haptic Actuator Select 0 = Eccentric rotating mass (ERM) 1 = Linear resonant actuator (LRA) DS1162F1 CS42L92 4.3 Digital Core Table 4-23. Haptic Signal Generator Control (Cont.) Register Address Bit Label R145 (0x0091) 14:0 LRA_ FREQ[14:0] Haptics_Control_2 Default Description 0x7FFF Haptic Resonant Frequency. Selects the haptic signal frequency (LRA actuator only, HAP_ACT = 1) Haptic Frequency (Hz) = System Clock/(2 x (LRA_FREQ+1)), where System Clock = 6.144 MHz or 5.6448 MHz, derived by division from SYSCLK or ASYNCCLK. If HAP_RATE < 1000, SYSCLK is the clock source, and the applicable System Clock frequency is determined by SYSCLK. If HAP_RATE  1000, ASYNCCLK is the clock source, and the applicable System Clock frequency is determined by ASYNCCLK. Valid for haptic frequency in the range 100–250 Hz For 6.144-MHz System Clock: For 5.6448-MHz System Clock: 0x77FF = 100 Hz 0x6E3F = 100 Hz 0x4491 = 175 Hz 0x3EFF = 175 Hz 0x2FFF = 250 Hz 0x2C18 = 250 Hz R146 (0x0092) 7:0 PHASE1_ 0x00 Haptic Output Level (Phase 1). Selects the signal intensity of Phase 1 in one-shot mode. INTENSITY[7:0] Haptics_phase_1_ Coded as 2’s complement. Range is ± Full Scale (FS). intensity For ERM actuator, this selects the DC signal level for the haptic output. For LRA actuator, this selects the AC peak amplitude; negative values correspond to a 180° phase shift. R147 (0x0093) 8:0 PHASE1_ 0x000 Haptic Output Duration (Phase 1). Selects the duration of Phase 1 in one-shot mode. DURATION[8:0] Haptics_Control_ 0x000 = 0 ms phase_1_duration 0x001 = 0.625 ms 0x002 = 1.25 ms … (0.625-ms steps) 0x1FF = 319.375 ms R148 (0x0094) 7:0 PHASE2_ 0x00 Haptic Output Level (Phase 2) INTENSITY[7:0] Haptics_phase_2_ Selects the signal intensity in Continuous mode or Phase 2 of one-shot mode. intensity Coded as 2’s complement. Range is ± Full Scale (FS). For ERM actuator, this selects the DC signal level for the haptic output. For LRA actuator, this selects the AC peak amplitude; Negative values correspond to a 180° phase shift. 10:0 PHASE2_ 0x000 Haptic Output Duration (Phase 2). Selects the duration of Phase 2 in one-shot mode. R149 (0x0095) DURATION[10:0] 0x000 = 0 ms 0x002 = 1.25 ms 0x7FF = 1279.375 ms Haptics_phase_2_ duration 0x001 = 0.625 ms … (0.625-ms steps) 7:0 PHASE3_ 0x00 Haptic Output Level (Phase 3). Selects the signal intensity of Phase 3 in one-shot mode. R150 (0x0096) INTENSITY[7:0] Coded as 2’s complement. Haptics_phase_3_ intensity Range is ± Full Scale (FS). For ERM actuator, this selects the DC signal level for the haptic output. For LRA actuator, this selects the AC peak amplitude; Negative values correspond to a 180° phase shift. R151 (0x0097) 8:0 PHASE3_ 0x000 Haptic Output Duration (Phase 3). Selects the duration of Phase 3 in one-shot mode. DURATION[8:0] 0x1FF = 319.375 ms Haptics_phase_3_ 0x000 = 0 ms 0x002 = 1.25 ms duration 0x001 = 0.625 ms … (0.625-ms steps) R152 (0x0098) 0 ONESHOT_STS 0 Haptic One-Shot status Haptics_Status 0 = One-Shot event not in progress 1 = One-Shot event in progress 4.3.12 PWM Generator The CS42L92 incorporates two PWM signal generators as shown in Fig. 4-29. The duty cycle of each PWM signal can be modulated by an audio source, or can be set to a fixed value using a control register setting. A four-input mixer is associated with each PWM generator. The four input sources are selectable in each case, and independent volume control is provided for each path. PWM signal generators can be output directly on a GPIO pin. See Section 4.14 to configure a GPIO pin for this function. Note that the PWM signal generators cannot be selected as input to the digital mixers or signal-processing functions within the CS42L92 digital core. DS1162F1 77 CS42L92 4.3 Digital Core When PWMn_OVD = 0, the PWM duty cycle is controlled by the respective digital audio mixer . When PWMn_OVD = 1, the PWM duty cycle is set by PWMn _LVL. PWM sample rate and clocking frequency are selected using PWM _RATE and PWM_CLK_SEL. … PWM1MIX_SRC1 PWM1MIX_VOL1 … PWM1MIX_SRC2 PWM1MIX_VOL2 … PWM1MIX_SRC3 PWM1MIX_VOL3 … PWM1MIX_SRC4 PWM1MIX_VOL4 + PWM1 PWM1_ENA p. 79 PWM1_OVD p. 79 PWM1_LVL[9:0] p. 79 GPIO (GPn_FN = 0x048) PWM_RATE[4:0] p. 85 PWM_CLK_SEL[2:0] p. 79 … PWM2MIX_SRC1 PWM2MIX_VOL1 … PWM2MIX_SRC2 PWM2MIX_VOL2 … PWM2MIX_SRC3 PWM2MIX_VOL3 … PWM2MIX_SRC4 PWM2MIX_VOL4 + PWM2 PWM2_ENA p. 79 PWM2_OVD p. 79 PWM2_LVL[9:0] p. 79 GPIO (GPn_FN = 0x049) x_SRCn p. 52 x_VOLn p. 52 Figure 4-29. Digital-Core PWM Generator The PWM1 and PWM2 mixer control fields (see Fig. 4-29) are located at register addresses R1600–R1615 (0x0640–0x064F). The full list of digital mixer control registers (R1600–R3576) is provided in Section 6. Generic register field definitions are provided in Table 4-11. The x_SRCn fields select the input sources for the respective mixers. Note that the selected input sources must be configured for the same sample rate as the mixer to which they are connected. Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.15 and Section 4.3.16. The PWM sample rate (cycle time) is configured using PWM_RATE. See Table 4-26. Note that sample-rate conversion is required when linking the PWM generators to any signal chain that is asynchronous or configured for a different sample rate. The PWM_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields must be cleared before writing a new value to PWM_RATE. A minimum delay of 125 s must be allowed between clearing the x_SRCn fields and writing to PWM_RATE. See Table 4-26 for details. The PWM generators are enabled by setting PWM1_ENA and PWM2_ENA, respectively, as described in Table 4-24. Under default conditions (PWMn_OVD = 0), the duty cycle of the PWM generators is controlled by an audio signal path; a 4-input mixer is associated with each PWM generator, as shown in Fig. 4-29. When the PWMn_OVD bit is set, the duty cycle of the respective PWM generator is set to a fixed ratio; in this case, the duty cycle ratio is configurable using the PWMn_LVL fields. The PWM generator clock frequency is selected using PWM_CLK_SEL. For best performance, the highest available setting should be used. Note that the PWM generator clock must not be set to a higher frequency than SYSCLK (if PWM_ RATE < 1000) or ASYNCCLK (if PWM_RATE  1000). 78 DS1162F1 CS42L92 4.3 Digital Core Table 4-24. PWM Generator Control Register Address Bit Label R48 (0x0030) 10:8 PWM_CLK_ SEL[2:0] PWM_Drive_1 Default 000 5 PWM2_OVD 0 4 PWM1_OVD 0 1 PWM2_ENA 0 0 PWM1_ENA 0 R49 (0x0031) PWM_Drive_2 9:0 PWM1_LVL[9:0] 0x100 R50 (0x0032) PWM_Drive_3 9:0 PWM2_LVL[9:0] 0x100 Description PWM Clock Select 000 = 6.144 MHz (5.6448 MHz) 001 = 12.288 MHz (11.2896 MHz) 010 = 24.576 MHz (22.5792 MHz) All other codes are reserved. The frequencies in brackets apply for 44.1 kHz–related sample rates only. PWM_CLK_SEL controls the resolution of the PWM generator; higher settings correspond to higher resolution. The PWM Clock must be less than or equal to SYSCLK (if PWM_RATE < 1000) or less than or equal to ASYNCCLK (if PWM_RATE  1000). PWM2 Generator Override 0 = Disabled (PWM duty cycle is controlled by audio source) 1 = Enabled (PWM duty cycle is controlled by PWM2_LVL). PWM1 Generator Override 0 = Disabled (PWM1 duty cycle is controlled by audio source) 1 = Enabled (PWM1 duty cycle is controlled by PWM1_LVL). PWM2 Generator Enable 0 = Disabled 1 = Enabled PWM1 Generator Enable 0 = Disabled 1 = Enabled PWM1 Override Level. Sets the PWM1 duty cycle when PWM1_OVD = 1. Coded as 2’s complement. 0x000 = 50% duty cycle 0x200 = 0% duty cycle PWM2 Override Level. Sets the PWM2 duty cycle when PWM2_OVD = 1. Coded as 2’s complement. 0x000 = 50% duty cycle 0x200 = 0% duty cycle The CS42L92 automatically checks to confirm that the SYSCLK frequency is high enough to support the digital mixer paths. If an attempt is made to enable a PWM signal mixer path, without sufficient SYSCLK cycles to support it, the attempt fails. Note that any signal paths that are already active are not affected under such circumstances. The status bits in registers R1600–R3576 indicate the status of each digital mixer. If an underclocked error condition occurs, these bits indicate which mixers have been enabled. 4.3.13 Data Format Conversion The digital mixing and signal-processing functions on the CS42L92 are designed to route audio data in signed fixed point format. Data format converter (DFC) blocks are incorporated in the digital core, with the capability to convert audio data between signed, unsigned, and floating-point formats. The DFCs enable the flexibility to support many different interface standards on the input and output signal paths. They can also be used to apply dithering to digital audio data. The digital core provides eight DFC blocks as shown in Fig. 4-30. Each DFC supports one input and one output path only. DS1162F1 79 CS42L92 4.3 Digital Core x_SRCn p. 52 … DFCn_SRC DFC Data Format Converter DFCn_ENA DFCn_RX_DATA_TYPE DFCn_RATE DFCn_RX_DATA_WIDTH DFCn_DITH_ENA DFCn_TX_DATA_TYPE DFCn_TX_DATA_WIDTH DFC1 (0xF8) DFC2 (0xF9) DFC3 (0xFA) DFC4 (0xFB) DFC5 (0xFC) DFC6 (0xFD) DFC7 (0xFE) DFC8 (0xFF) CS42L92 supports eight DFC blocks, i.e., n = 1–8 Figure 4-30. Digital-Core DFC Blocks The DFC1–DFC8 input control fields (see Fig. 4-30) are located at register addresses R3520–R3576 (0x0DC0–0x0DF8). The full list of digital-mixer control registers (R1600–R3576) is provided in Section 6. Generic register field definitions are provided in Table 4-11. The x_SRCn fields select the input sources for the respective DFCs. Note that the selected input sources must be configured for the same sample rate as the DFC to which they are connected. Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.15 and Section 4.3.16. The hexadecimal numbers in Fig. 4-30 indicate the corresponding x_SRCn setting for selection of that signal as an input to another digital-core function. The sample rate for each converter DFCn is configured using the respective DFCn_RATE field; see Table 4-26. Note that sample-rate conversion is required when routing the DFC paths to any signal chain that is asynchronous or configured for a different sample rate. The DFCn_RATE fields must not be changed if the associated x_SRCn field is nonzero. The associated x_SRCn field must be cleared before writing a new value to DFCn_RATE. A minimum delay of 125 s must be allowed between clearing the x_SRCn field and writing to the associated DFCn_RATE field. See Table 4-26 for details. The DFC is enabled by setting DFCn_ENA. The input data format is configured using the DFCn_RX_DATA_TYPE and DFCn_RX_DATA_WIDTH fields. Valid data types are signed fixed point, unsigned fixed point, and three different floating point configurations. If a fixed point data type is selected, the data width (number of data bits) is selected using DFCn_RX_DATA_WIDTH. The DFC input can be any of the digital core inputs or signal processing blocks. If the input data type is unsigned or floating point format, one of the AIF or SLIMbus RX channels must be selected as the DFC input source—unsigned and floating point data types are not valid selections with any other source within the digital core. The output data format is configured using the DFCn_TX_DATA_TYPE and DFCn_TX_DATA_WIDTH fields. Valid data types are signed fixed point, unsigned fixed point, and floating point formats. If a fixed point data type is selected, the data width (number of data bits) is selected using DFCn_TX_DATA_WIDTH. The DFC output can be selected as input to any of the digital mixers or signal-processing functions within the CS42L92 digital core. If the DFC output data type is unsigned fixed point or floating point format, it must be routed directly to the AIF or SLIMbus TX channels using the respective digital-core output mixers—unsigned fixed point or floating point data is not valid as input to any other digital core functions. Note: 80 If unsigned fixed point or floating point data is routed from a DFC output to an AIF or SLIMbus TX channel, the DFC must be the only enabled signal path in the respective output mixer, and the associated volume selection must be 0 dB. DS1162F1 CS42L92 4.3 Digital Core The DFC can apply dithering to its output data; this is enabled by setting DFCn_DITH_ENA. Note that dithering is only valid if the output data is in fixed point format (signed or unsigned). If the output data type is floating point, the DFCn_ DITH_ENA bit must be cleared. The dither function can be used to improve the noise characteristics of signals routed in the digital core. Dithering is particularly recommended if truncating audio data (e.g., from 32- to 24-bit format) as it converts the truncation/quantization errors into benign background noise. The DFCs provide input to the interrupt control circuit and can be used to trigger an interrupt event if saturation (arithmetic error) is detected; see Section 4.15. The control registers associated with the DFCs are described in Table 4-25. Table 4-25. Digital-Core DFC Control Register Address R5248 (0x1480) DFC1_CTRL_W0 R5254 (0x1486) DFC2_CTRL_W0 R5260 (0x148C) DFC3_CTRL_W0 R5266 (0x1492) DFC4_CTRL_W0 R5272 (0x1498) DFC5_CTRL_W0 R5278 (0x149E) DFC6_CTRL_W0 R5284 (0x14A4) DFC7_CTRL_W0 R5290 (0x14AA) DFC8_CTRL_W0 R5250 (0x1482) DFC1_RX_W0 R5256 (0x1488) DFC2_RX_W0 R5262 (0x148E) DFC3_RX_W0 R5268 (0x1494) DFC4_RX_W0 R5274 (0x149A) DFC5_RX_W0 R5280 (0x14A0) DFC6_RX_W0 R5286 (0x14A6) DFC7_RX_W0 R5292 (0x14AC) DFC8_RX_W0 R5252 (0x1488) DFC1_TX_W0 R5258 (0x148A) DFC2_TX_W0 R5264 (0x1490) DFC3_TX_W0 R5270 (0x1494) DFC4_TX_W0 R5276 (0x149C) DFC5_TX_W0 R5282 (0x14A2) DFC6_TX_W0 R5288 (0x14A8) DFC7_TX_W0 R5294 (0x14AE) DFC8_TX_W0 DS1162F1 Bit 1 0 Label DFCn_DITH_ENA DFCn_ENA Default Description 0 DFCn dither enable (valid for fixed point output data only) 0 = Disabled 1 = Enabled 0 DFCn enable 0 = Disabled 1 = Enabled 12:8 DFCn_RX_DATA_ WIDTH[4:0] 0x1F 2:0 DFCn_RX_DATA_ TYPE[2:0] 000 12:8 DFCn_TX_DATA_ WIDTH[4:0] 0x1F 2:0 000 DFCn_TX_DATA_ TYPE[2:0] DFCn input data width (valid for fixed point data types only) 0x00 to 0x06 = Reserved 0x09 = 10 bits 0x07 = 8 bits ... 0x08 = 9 bits 0x1F = 32 bits DFCn input data type 000 = Signed, fixed point 001 = Unsigned, fixed point 010 = Single-precision floating point (binary32) 100 = Half-precision floating point (binary16) 101 = ARM-alternative half-precision floating point All other codes are reserved. DFCn output data width (valid for fixed point data types only) 0x00 to 0x06 = Reserved 0x09 = 10 bits 0x07 = 8 bits ... 0x08 = 9 bits 0x1F = 32 bits DFCn output data type 000 = Signed, fixed point 001 = Unsigned, fixed point 010 = Single-precision floating point (binary32) 100 = Half-precision floating point (binary16) 101 = ARM-alternative half-precision floating point All other codes are reserved. 81 CS42L92 4.3 Digital Core The CS42L92 automatically checks to confirm whether the SYSCLK frequency is high enough to support the commanded DFC and digital mixing functions. If an attempt is made to enable DFC signal path, and there are insufficient SYSCLK cycles to support it, the attempt does not succeed. Note that any signal paths that are already active are not affected under such circumstances. The status bits in registers R1600–R3576 indicate the status of each digital mixer. If an underclocked error condition occurs, these bits indicate which mixers have been enabled. 4.3.14 Sample-Rate Control The CS42L92 supports multiple signal paths through the digital core. Stereo full-duplex sample-rate conversion is provided to allow digital audio to be routed between interfaces operating at different sample rates and/or referenced to asynchronous clock domains. Two independent clock domains are supported for the audio signal paths, referenced to SYSCLK and ASYNCCLK respectively, as described in Section 4.16. Every digital signal path must be synchronized either to SYSCLK or to ASYNCCLK. Up to five different sample rates may be in use at any time on the CS42L92. Three of these sample rates must be synchronized to SYSCLK; the remaining two, where required, must be synchronized to ASYNCCLK. Sample-rate conversion is required when routing any audio path between digital functions that are asynchronous or configured for different sample rates. The asynchronous sample-rate converter (ASRC) supports two-way stereo conversion paths between the SYSCLK and ASYNCCLK domains. The ASRC is described in Section 4.3.15. There are two isochronous sample-rate converters (ISRCs). Each ISRC supports two-way, two-channel conversion paths between sample rates on the SYSCLK domain, or between sample rates on the ASYNCCLK domain. The ISRCs are described in Section 4.3.16. The sample rate of different blocks within the CS42L92 digital core are controlled as shown in Fig. 4-31. The x_RATE fields select the applicable sample rate for each respective group of digital functions. The x_RATE fields must not be changed if any of the x_SRCn fields associated with the respective functions is nonzero. The associated x_SRCn fields must be cleared before writing new values to the x_RATE fields. A minimum delay of 125 s must be allowed between clearing the x_SRCn fields and writing to the associated x_RATE fields. See Table 4-26 for details. 82 DS1162F1 CS42L92 4.3 Digital Core DSP1 – DSP1_RATE Silence (mute) IN1L signal path IN1R signal path AEC1 Loopback IN2L signal path IN2R signal path DSP1 Ch 1 + AEC2 Loopback DSP1 Ch 2 OUT_RATE IN3L signal path DSP1 Ch 3 DSP Core Ultrasonic 1 path IN3R signal path DSP1 Ch 4 US1_RATE IN4L signal path IN4R signal path + Ultrasonic 2 path DSP1 Ch 5 US2_RATE IN_RATE, or INnx_RATE DSP1 Ch 6 ISRC2 ISRC1 ASRC1 ASRC1 Left Asynchronous Sample Rate Converter (ASRC) Isochronous Sample Rate Converter (ISRC) ASRC1 Right ASRC1 Left ISRCn DEC1 ASRC1 Right ISRCn DEC2 ASRC1_RATE1 ASRC1_RATE2 DFC8 – DFC8_RATE DFC7 – DFC7_RATE DFC6 – DFC6_RATE DFC5 – DFC5_RATE DFC OUT5 OUT3 OUT2 OUT1 ISRCn INT1 ISRCn INT2 OUT_RATE + ISRCn_FSL Stereo Output Paths ISRCn_FSH DFC4 – DFC4_RATE DFC3 – DFC3_RATE DFC2 – DFC2_RATE DFC1 – DFC1_RATE DFC DFCn OUTnL output + OUTnR output DFCn SLIMbus SLIMRXn_RATE (n = 1..8) SLIMTXn_RATE (n = 1..8) SLIMbus = 8 input , 8 output PWM_RATE FX_RATE PWM2 PWM1 + PWM AIF3 – AIF3_RATE AIF2 – AIF2_RATE LHPF4 LHPF3 LHPF2 LHPF1 AIF1 – AIF1_RATE (GPIO pin) + LHPF + LHPFn AIFn TX1 output SPD1_RATE S/PDIF HAP_RATE Haptic Signal Generator EQ4 EQ3 EQ2 EQ1 (GPIO pin) + AIFn TX2 output EQn AIFn TX... output DRC2 DRC1 + AIFn TX... output + DRCn Left Noise Generator etc... DRC AIFn RX1 TONE_RATE + Tone Generator + Haptic Output NOISE_GEN_RATE White Noise Generator EQ + Tone Generator 1 DRCn Right AIF1 = 8 input , 8 output AIF2 = 8 input , 8 output AIF3 = 8 input , 8 output AIFn RX2 AIFn RX... Tone Generator 2 AIFn RX... Figure 4-31. Digital-Core Sample-Rate Control The input signal paths may be selected as input to the digital mixers or signal-processing functions. The sample rate for the input signal paths can either be set globally (using IN_RATE), or can be configured independently for each input channel (using the respective INnx_RATE fields). The applicable mode depends on IN_RATE_MODE, as described in DS1162F1 83 CS42L92 4.3 Digital Core Table 4-3. The ultrasonic demodulator circuits can be selected as input to the digital mixers or signal-processing functions. The sample rate for these signals are configured using US1_RATE and US2_RATE. The selected sample rate must be equal to the output rate of the demodulator function, set by the respective USn_FREQ field—see Section 4.2.9. The output signal paths are derived from the respective output mixers. The sample rate for the output signal paths is configured using OUT_RATE. The sample rate of the AEC loop-back path is also set by OUT_RATE. Clocking for the DACs and output signal path circuits must also be configured using the OUT_CLK_SRC field—see Section 4.11.2. The AIFn RX inputs may be selected as input to the digital mixers or signal-processing functions. The AIFn TX outputs are derived from the respective output mixers. The sample rates for digital audio interfaces (AIF1–AIF3) are configured using the AIFn_RATE fields (where n identifies the applicable AIF 1, 2, or 3) respectively. The SLIMbus interface supports up to eight input channels and eight output channels. The sample rate of each channel can be configured independently, using SLIMTXn_RATE and SLIMRXn_RATE. Note that the SLIMbus interface provides simultaneous support for SYSCLK-referenced and ASYNCCLK-referenced sample rates on different channels. For example, 48-kHz and 44.1-kHz SLIMbus audio paths can be simultaneously supported. The EQ, DRC, and LHPF functions can be enabled in any signal path within the digital core. The sample rate for these functions is configured using FX_RATE. Note that the EQ, DRC, and LHPF functions must all be configured for the same sample rate. The DSP functions can be enabled in any signal path within the digital core. The applicable sample rate is configured using the DSP1_RATE field. The S/PDIF transmitter can be enabled on a GPIO pin. Stereo inputs to this function can be configured from any of the digital-core inputs, mixers, or signal-processing functions. The sample rate of the S/PDIF transmitter is configured using SPD1_RATE. The tone generator and noise generator can be selected as input to any of the digital mixers or signal-processing functions. The sample rates for these sources are configured using the TONE_RATE and NOISE_GEN_RATE fields, respectively. The haptic signal generator can be used to control an external vibe actuator. In a typical use case the haptic signal may be routed, via one of the digital-core output mixers, to the digital PDM output (OUT5). The sample rate for the haptic signal generator is configured using HAP_RATE. The PWM signal generators can be modulated by an audio source, derived from the associated signal mixers. The sample rate (cycle time) for the PWM signal generators is configured using PWM_RATE. The DFCn blocks can be enabled in signal paths within the digital core. The applicable sample rates are configured using the DFCn_RATE fields (where n identifies the applicable DFC block). The sample-rate control registers are described in Table 4-26. Refer to the field descriptions for details of the valid selections in each case—note that the input (ADC) and output (DAC) signal paths must always be associated with the SYSCLK clocking domain; different sample rates may be selected concurrently, but both these rates must be synchronized to SYSCLK. The control registers associated with the ASRC and ISRCs are described in Table 4-27 and Table 4-28. Note that 32-bit register addressing is used from R12888 (0x3000) upwards; 16-bit format is used otherwise. The registers noted in Table 4-26 contain a mixture of 16-bit and 32-bit register addresses. 84 DS1162F1 CS42L92 4.3 Digital Core Table 4-26. Digital-Core Sample-Rate Control Register Address Bit Label Default Description R32 (0x0020) 15:11 TONE_RATE[4:0] 0x00 Tone Generator Sample Rate Tone_Generator_1 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. R48 (0x0030) 15:11 PWM_RATE[4:0] 0x00 PWM Frequency (sample rate) PWM_Drive_1 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. All PWMnMIX_SRCm fields must be cleared before changing PWM_RATE. R144 (0x0090) 15:11 HAP_RATE[4:0] 0x00 Haptic Signal Generator Sample Rate Haptics_Control_1 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. R160 (0x00A0) 15:11 NOISE_GEN_ 0x00 Noise Generator Sample Rate RATE[4:0] Comfort_Noise_ 0x00 = SAMPLE_RATE_1 Generator 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. R776 (0x0308) 15:11 IN_RATE[4:0] 0x00 Input Signal Paths Sample Rate (only valid if IN_RATE_MODE = 0) Input_Rate 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. If 384 kHz/768 kHz DMIC rate is selected on any of the input paths (INn_ OSR = 01X), the input paths sample rate is valid up to 48 kHz/96 kHz respectively. DS1162F1 85 CS42L92 4.3 Digital Core Table 4-26. Digital-Core Sample-Rate Control (Cont.) Register Address R787 (0x0313) IN1L_Rate_ Control R791 (0x0317) IN1R_Rate_ Control R795 (0x031B) IN2L_Rate_ Control R799 (0x031F) IN2R_Rate_ Control R803 (0x0323) IN3L_Rate_ Control R807 (0x0327) IN3R_Rate_ Control R811 (0x032B) IN4L_Rate_ Control R815 (0x032F) IN4R_Rate_ Control R1032 (0x0408) Output_Rate_1 Bit Label 15:11 IN1L_RATE[4:0] R1283 (0x0503) AIF1_Rate_Ctrl R1347 (0x0543) AIF2_Rate_Ctrl R1411 (0x0583) AIF3_Rate_Ctrl R1474 (0x05C2) SPD1_TX_Control 86 15:11 IN1R_RATE[4:0] 15:11 IN2L_RATE[4:0] Default Description 0x00 Input Path n (Left/Right) Sample Rate (only valid if IN_RATE_MODE = 1) 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x00 0x02 = SAMPLE_RATE_3 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. 0x00 If 384 kHz/768 kHz DMIC rate is selected (INn_OSR = 01X), the INnL/INnR sample rate is valid up to 48 kHz/96 kHz respectively. 15:11 IN2R_RATE[4:0] 0x00 15:11 IN3L_RATE[4:0] 0x00 15:11 IN3R_RATE[4:0] 0x00 15:11 IN4L_RATE[4:0] 0x00 15:11 IN4R_RATE[4:0] 0x00 15:11 OUT_RATE[4:0] 0x00 15:11 AIF1_RATE[4:0] 0x00 15:11 AIF2_RATE[4:0] 0x00 15:11 AIF3_RATE[4:0] 0x00 8:4 SPD1_RATE[4:0] 0x00 Output Signal Paths Sample Rate 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–384 kHz. All OUTnxMIX_SRCm fields must be cleared before changing OUT_RATE. AIFn Audio Interface Sample Rate 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–384 kHz. All AIFnTXMIX_SRCm fields must be cleared before changing AIFn_RATE. S/PDIF Transmitter Sample Rate 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 32–192 kHz. All SPDIF1TXn_SRC fields must be cleared before changing SPD1_RATE. DS1162F1 CS42L92 4.3 Digital Core Table 4-26. Digital-Core Sample-Rate Control (Cont.) Register Address Bit Label R1509 (0x05E5) 15:11 SLIMRX2_ RATE[4:0] SLIMbus_Rates_1 7:3 SLIMRX1_ RATE[4:0] R1510 (0x05E6) 15:11 SLIMRX4_ RATE[4:0] SLIMbus_Rates_2 7:3 SLIMRX3_ RATE[4:0] R1511 (0x05E7) 15:11 SLIMRX6_ RATE[4:0] SLIMbus_Rates_3 7:3 SLIMRX5_ RATE[4:0] R1512 (0x05E8) 14:15 SLIMRX8_ RATE[4:0] SLIMbus_Rates_4 7:3 SLIMRX7_ RATE[4:0] R1513 (0x05E9) 15:11 SLIMTX2_ RATE[4:0] SLIMbus_Rates_5 7:3 SLIMTX1_ RATE[4:0] R1514 (0x05EA) 15:11 SLIMTX4_ RATE[4:0] SLIMbus_Rates_6 7:3 SLIMTX3_ RATE[4:0] R1515 (0x05EB) 15:11 SLIMTX6_ RATE[4:0] SLIMbus_Rates_7 7:3 SLIMTX5_ RATE[4:0] R1516 (0x05EC) 15:11 SLIMTX8_ RATE[4:0] SLIMbus_Rates_8 7:3 SLIMTX7_ RATE[4:0] R3584 (0x0E00) 15:11 FX_RATE[4:0] FX_Ctrl1 Default Description 0x00 SLIMbus RX Channel n Sample Rate 0x00 = SAMPLE_RATE_1 0x00 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x00 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 0x00 All other codes are reserved. 0x00 The selected sample rate is valid in the range 8–384 kHz. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 R4225 (0x1081) US1_Ctrl_1 15:11 US1_RATE[4:0] 0x00 R4227 (0x1083) US2_Ctrl_1 15:11 US2_RATE[4:0] 0x00 DS1162F1 SLIMbus TX Channel n Sample Rate 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–384 kHz. All SLIMTXnMIX_SRCm fields must be cleared before changing SLIMTXn_RATE. FX Sample Rate (EQ, LHPF, DRC) 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. All EQnMIX_SRCm, DRCnxMIX_SRCm, and LHPFnMIX_SRCm fields must be cleared before changing FX_RATE. Ultrasonic Demodulator 1 Sample Rate 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 All other codes are reserved. The selected sample rate must be the same as the output rate set by US1_FREQ (i.e., 8, 16, or 32 kHz). Ultrasonic Demodulator 2 Sample Rate 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 All other codes are reserved. The selected sample rate must be the same as the output rate set by US2_FREQ (i.e., 8, 16, or 32 kHz). 87 CS42L92 4.3 Digital Core Table 4-26. Digital-Core Sample-Rate Control (Cont.) Register Address Bit R5248 (0x1480) 6:2 DFC1_CTRL_W0 R5254 (0x1486) 6:2 DFC2_CTRL_W0 R5260 (0x148C) 6:2 DFC3_CTRL_W0 R5266 (0x1492) 6:2 DFC4_CTRL_W0 R5272 (0x1498) 6:2 DFC5_CTRL_W0 R5278 (0x149E) 6:2 DFC6_CTRL_W0 R5284 (0x14A4) 6:2 DFC7_CTRL_W0 R5290 (0x14AA) 6:2 DFC8_CTRL_W0 R1048064 (0xF_ 15:11 FE00) DSP1_Config_1 Label DFC1_RATE[4:0] DFC2_RATE[4:0] DFC3_RATE[4:0] DFC4_RATE[4:0] DFC5_RATE[4:0] Default Description 0x00 DFCn Sample Rate 0x00 = SAMPLE_RATE_1 0x00 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x00 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 0x00 All other codes are reserved. 0x00 The selected sample rate is valid in the range 8–192 kHz. The DFCn_SRC field must be cleared before changing DFCn_RATE. DFC6_RATE[4:0] 0x00 DFC7_RATE[4:0] 0x00 DFC8_RATE[4:0] 0x00 DSP1_RATE[4:0] 0x00 DSP1 Sample Rate 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–384 kHz. All DSP1xMIX_SRCm fields must be cleared before changing DSP1_RATE. 4.3.15 Asynchronous Sample-Rate Converter (ASRC) The CS42L92 supports multiple signal paths through the digital core. Two independent clock domains are supported for the audio signal paths, referenced to SYSCLK and ASYNCCLK respectively, as described in Section 4.16. Every digital signal path must be synchronized either to SYSCLK or to ASYNCCLK. The ASRC provides stereo, two-way signal paths between two sample rates, as shown in Fig. 4-32. Each of the sample rates may be referenced to the SYSCLK or ASYNCCLK domain. The clock domains and sample rates associated with the ASRC signal paths are selected using the ASRC1_RATE1 and ASRC1_RATE2 fields. • ASRC1_RATE1 selects the clock domain and sample rate of the inputs to the ASRC1 IN1x paths, and the outputs from the ASRC1 IN2x paths. • ASRC1_RATE2 selects the clock domain and sample rate of the inputs to the ASRC1 IN2x paths, and the outputs from the ASRC1 IN1x paths. Note that it is possible to select two sample rates for the ASRC that are each referenced to the same clock domain. This provides flexibility to switch between synchronous and asynchronous use cases without changing the signal routing configuration of the affected audio paths. See Section 4.16 for details of the sample-rate control registers. The ASRC supports sample rates from 8–192 kHz. The ratio of the applicable SAMPLE_RATE_n and ASYNC_SAMPLE_ RATE_n fields must not exceed 6. The ASRC1_RATE1 and ASRC1_RATE2 fields must not be changed if any of the respective x_SRCn fields is nonzero. The associated x_SRCn fields must be cleared before writing new values to ASRC1_RATE1 or ASRC1_RATE2. A minimum delay of 125 s must be allowed between clearing the x_SRCn fields and writing to the associated ASRC1_ RATE1 or ASRC1_RATE2 fields. See Table 4-27 for details. 88 DS1162F1 CS42L92 4.3 Digital Core The ASRC signal paths are enabled using the ASRC1_INnx_ENA bits, as follows: • The ASRC1 IN1 (left and right) paths convert from the ASRC1_RATE1 sample rate to the ASRC1_RATE2 sample rate. These paths are enabled by setting the ASRC1_IN1L_ENA and ASRC1_IN1R_ENA bits, respectively. • The ASRC1 IN2 (left and right) paths convert from the ASRC1_RATE2 sample rate to the ASRC1_RATE1 sample rate. These paths are enabled by setting the ASRC1_IN2L_ENA and ASRC1_IN2R_ENA bits, respectively. Synchronization (lock) between different clock domains is not instantaneous when the clocking or sample rate configurations are updated. The lock status of each ASRC path is an input to the interrupt control circuit and can be used to trigger an interrupt event; see Section 4.15. The ASRC lock status of each ASRC path can be output directly on a GPIO pin as an external indication of ASRC lock. See Section 4.14 to configure a GPIO pin for this function. The CS42L92 performs automatic checks to confirm that the SYSCLK or ASYNCCLK frequency is high enough to support the commanded ASRC and digital mixing functions. If the frequency is too low, an attempt to enable an ASRC signal path fails. Note that active signal paths are not affected under such circumstances. The status bits in register R3809 indicate the status of each ASRC signal path. If an underclocked error condition occurs, these bits indicate which ASRC signal paths have been enabled. The status bits in registers R1600–R3576 indicate the status of each digital mixer. If an underclocked error condition occurs, these bits indicate which mixers have been enabled. The ASRC signal paths and control registers are shown in Fig. 4-32. The ASRC provides asynchronous conversion between the SYSCLK and ASYNCCLK clock domains. ASRC1_RATE1 selects the sample rate of the ASRC1 IN1x inputs, and the ASRC1 IN2x outputs. ASRC1_RATE2 selects the sample rate of the ASRC1 IN2x inputs, and the ASRC1 IN1x outputs. Each sample rate may be referenced to either the SYSCLK or ASYNCCLK clock domain.. ASRC1_RATE1 … ASRC1IN1L_SRC … ASRC1IN1R_SRC ASRC1 IN2L (0x92) ASRC1 IN2R (0x93) ASRC1_IN2L_ENA p. 90 ASRC1_IN2R_ENA p. 90 ASRC1_RATE2 ASRC1_IN1L_ENA p. 90 ASRC1 IN1L (0x90) ASRC1_IN1R_ENA p. 90 ASRC1 IN1R (0x91) … ASRC1IN2L_SRC … ASRC1IN2R_SRC x_SRCn p. 52 Figure 4-32. Asynchronous Sample-Rate Converters (ASRCs) The ASRC1 input control fields (see Fig. 4-32) are located at register addresses R2688–R2712 (0x0A80–0x0A98). DS1162F1 89 CS42L92 4.3 Digital Core The full list of digital mixer control registers (R1600–R3576) is provided in Section 6. Generic register field definitions are provided in Table 4-11. The x_SRCn fields select the input sources for the ASRC paths. Note that the selected input sources must be configured for the same sample rate as the ASRC to which they are connected. The hexadecimal numbers in Fig. 4-32 indicate the corresponding x_SRCn setting for selection of that signal as an input to another digital-core function. The fields associated with the ASRC are described in Table 4-27. Table 4-27. Digital-Core ASRC Control Register Address R3808 (0x0EE0) ASRC1_ENABLE 90 Bit 3 Label ASRC1_IN2L_ ENA Default 0 2 ASRC1_IN2R_ ENA 0 1 ASRC1_IN1L_ ENA 0 0 ASRC1_IN1R_ ENA 0 Description ASRC1 IN2 (left) enable (Left channel from ASRC1_RATE2 sample rate to ASRC1_RATE1 sample rate) 0 = Disabled 1 = Enabled ASRC1 IN2 (right) enable (Right channel from ASRC1_RATE2 sample rate to ASRC1_RATE1 sample rate) 0 = Disabled 1 = Enabled ASRC1 IN1 (left) enable (Left channel from ASRC1_RATE1 sample rate to ASRC1_RATE2 sample rate) 0 = Disabled 1 = Enabled ASRC1 IN1 (right) enable (Right channel from ASRC1_RATE1 sample rate to ASRC1_RATE2 sample rate) 0 = Disabled 1 = Enabled DS1162F1 CS42L92 4.3 Digital Core Table 4-27. Digital-Core ASRC Control (Cont.) Register Address R3809 (0x0EE1) ASRC1_STATUS Bit 3 Label ASRC1_IN2L_ ENA_STS Default 0 2 ASRC1_IN2R_ ENA_STS 0 1 ASRC1_IN1L_ ENA_STS 0 0 ASRC1_IN1R_ ENA_STS 0 R3810 (0x0EE2) ASRC1_RATE1 15:11 ASRC1_ RATE1[4:0] 0x00 R3811 (0x0EE3) ASRC1_RATE2 15:11 ASRC1_ RATE2[4:0] 0x08 Description ASRC1 IN2 (left) enable status (Left channel from ASRC1_RATE2 sample rate to ASRC1_RATE1 sample rate) 0 = Disabled 1 = Enabled ASRC1 IN2 (right) enable status (Right channel from ASRC1_RATE2 sample rate to ASRC1_RATE1 sample rate) 0 = Disabled 1 = Enabled ASRC1 IN1 (left) enable status (Left channel from ASRC1_RATE1 sample rate to ASRC1_RATE2 sample rate) 0 = Disabled 1 = Enabled ASRC1 IN1 (right) enable status (Right channel from ASRC1_RATE1 sample rate to ASRC1_RATE2 sample rate) 0 = Disabled 1 = Enabled ASRC1 Sample Rate select for ASRC1 IN1x inputs and ASRC1 IN2x outputs 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. All ASRC1_IN1x_SRC fields must be cleared before changing ASRC1_RATE1. ASRC1 Sample Rate select for ASRC1 IN2x inputs and ASRC1 IN1x outputs 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. All ASRC1_IN1x_SRC fields must be cleared before changing ASRC1_RATE1. 4.3.16 Isochronous Sample-Rate Converter (ISRC) The CS42L92 supports multiple signal paths through the digital core. The ISRCs provide sample-rate conversion between synchronized sample rates on the SYSCLK clock domain, or between synchronized sample rates on the ASYNCCLK clock domain. There are two ISRCs on the CS42L92. Each ISRC provides two stereo signal paths between two different sample rates, as shown in Fig. 4-33. The sample rates associated with each ISRC can be set independently. Note that the two sample rates associated with any single ISRC must both be referenced to the same clock domain (SYSCLK or ASYNCCLK). • When an ISRC is used on the SYSCLK domain, the associated sample rates may be selected from SAMPLE_ RATE_1, SAMPLE_RATE_2, or SAMPLE_RATE_3. • When an ISRC is used on the ASYNCCLK domain, the associated sample rates are ASYNC_SAMPLE_RATE_1 and ASYNC_SAMPLE_RATE_2. See Section 4.16 for details of the sample-rate control registers. Each ISRC converts between a sample rate selected by ISRCn_FSL and a sample rate selected by ISRCn_FSH, (where n identifies the applicable ISRC 1 or 2). The higher of the two sample rates must be selected by ISRCn_FSH in each case. DS1162F1 91 CS42L92 4.3 Digital Core The ISRCs support sample rates in the range 8–384 kHz. For each ISRC, the ratio of the applicable SAMPLE_RATE_n or ASYNC_SAMPLE_RATE_n fields must not exceed 24. The sample-rate conversion ratio must be an integer (1–24) or equal to 1.5. The ISRCn_FSL and ISRCn_FSH fields must not be changed if any of the respective x_SRCn fields is nonzero. The associated x_SRCn fields must be cleared before writing new values to ISRCn_FSL or ISRCn_FSH. A minimum delay of 125 s must be allowed between clearing the x_SRCn fields and writing to the associated ISRCn_FSL or ISRCn_FSH fields. See Table 4-28 for details. The ISRC signal paths are enabled using the ISRCn_INTm_ENA and ISRCn_DECm_ENA bits, as follows: • The ISRCn interpolation paths (increasing sample rate) are enabled by setting the ISRCn_INTm_ENA bits, (where m identifies the applicable channel). • The ISRCn decimation paths (decreasing sample rate) are enabled by setting the ISRCn_DECm_ENA bits. The CS42L92 performs automatic checks to confirm that the SYSCLK or ASYNCCLK frequency is high enough to support the commanded ISRC and digital mixing functions. If the frequency is too low, an attempt to enable an ISRC signal path fails. Note that active signal paths are not affected under such circumstances. The status bits in registers R1600–R3576 indicate the status of each digital mixer. If an underclocked error condition occurs, these bits indicate which mixers have been enabled. The ISRC signal paths and control registers are shown in Fig. 4-33. ISRC provides sample-rate conversions between synchronized sample rates on the SYSCLK or ASYNCCLK domain. Both sample rates must be referenced to the same clock domain (SYSCLK or AYSNCCLK). ISRCn_FSL identifies the lower of the two sample rates. ISRCn_FSH identifies the higher of the two sample rates. ISRCn_FSL ISRCn_FSH … ISRCnINT1_SRC ISRCn_INT1_ENA ISRC1 INT1 (0xA0) ISRC2 INT1 (0xA8) … ISRCnINT2_SRC ISRCn_INT2_ENA ISRC1 INT2 (0xA1) ISRC2 INT2 (0xA9) ISRC1 DEC1 (0xA4) ISRC2 DEC1 (0xAC) ISRCn_DEC1_ENA … ISRCnDEC1_SRC ISRC1 DEC2 (0xA5) ISRC2 DEC2 (0xAD) ISRCn_DEC2_ENA … ISRCnDEC2_SRC CS42L92 supports two ISRC blocks, i.e., n = 1–2 Figure 4-33. Isochronous Sample-Rate Converters (ISRCs) The ISRC input control fields (see Fig. 4-33) are located at register addresses R2816–R2920 (0x0B00–0x0B68). The full list of digital mixer control registers (R1600–R3576) is provided in Section 6. Generic register field definitions are provided in Table 4-11. 92 DS1162F1 CS42L92 4.3 Digital Core The x_SRC fields select the input sources for the respective ISRC processing blocks. Note that the selected input sources must be configured for the same sample rate as the ISRC to which they are connected. The hexadecimal numbers in Fig. 4-33 indicate the corresponding x_SRC setting for selection of that signal as an input to another digital-core function. The fields associated with the ISRCs are described in Table 4-28. Table 4-28. Digital-Core ISRC Control Register Address Bit Label R3824 (0x0EF0) 15:11 ISRC1_FSH[4:0] ISRC1_CTRL_1 R3825 (0x0EF1) ISRC1_CTRL_2 R3826 (0x0EF2) ISRC1_CTRL_3 R3827 (0x0EF3) ISRC2_CTRL_1 DS1162F1 15:11 ISRC1_FSL[4:0] 15 ISRC1_INT1_ENA 14 ISRC1_INT2_ENA 9 ISRC1_DEC1_ ENA 8 ISRC1_DEC2_ ENA 15:11 ISRC2_FSH[4:0] Default Description 0x00 ISRC1 High Sample Rate (Sets the higher of the ISRC1 sample rates) 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. The ISRC1_FSH and ISRC1_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC1_DECn_SRC fields must be cleared before changing ISRC1_FSH. 0x00 ISRC1 Low Sample Rate (Sets the lower of the ISRC1 sample rates) 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. The ISRC1_FSH and ISRC1_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC1_INTn_SRC fields must be cleared before changing ISRC1_FSL. 0 ISRC1 INT1 Enable (Interpolation Channel 1 path from ISRC1_FSL rate to ISRC1_ FSH rate) 0 = Disabled 1 = Enabled 0 ISRC1 INT2 Enable (Interpolation Channel 2 path from ISRC1_FSL rate to ISRC1_ FSH rate) 0 = Disabled 1 = Enabled 0 ISRC1 DEC1 Enable (Decimation Channel 1 path from ISRC1_FSH rate to ISRC1_ FSL rate) 0 = Disabled 1 = Enabled 0 ISRC1 DEC2 Enable (Decimation Channel 2 path from ISRC1_FSH rate to ISRC1_ FSL rate) 0 = Disabled 1 = Enabled 0x00 ISRC2 High Sample Rate (Sets the higher of the ISRC2 sample rates) 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. The ISRC2_FSH and ISRC2_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC2_DECn_SRC fields must be cleared before changing ISRC2_FSH. 93 CS42L92 4.4 DSP Firmware Control Table 4-28. Digital-Core ISRC Control (Cont.) Register Address Bit Label R3828 (0x0EF4) 15:11 ISRC2_FSL[4:0] ISRC2_CTRL_2 R3829 (0x0EF5) ISRC2_CTRL_3 15 ISRC2_INT1_ENA 14 ISRC2_INT2_ENA 9 ISRC2_DEC1_ ENA 8 ISRC2_DEC2_ ENA Default Description 0x00 ISRC2 Low Sample Rate (Sets the lower of the ISRC2 sample rates) 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x08 = ASYNC_SAMPLE_RATE_1 0x09 = ASYNC_SAMPLE_RATE_2 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. The ISRC2_FSH and ISRC2_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC2_INTn_SRC fields must be cleared before changing ISRC2_FSL. 0 ISRC2 INT1 Enable (Interpolation Channel 1 path from ISRC2_FSL rate to ISRC2_ FSH rate) 0 = Disabled 1 = Enabled 0 ISRC2 INT2 Enable (Interpolation Channel 2 path from ISRC2_FSL rate to ISRC2_ FSH rate) 0 = Disabled 1 = Enabled 0 ISRC2 DEC1 Enable (Decimation Channel 1 path from ISRC2_FSH rate to ISRC2_ FSL rate) 0 = Disabled 1 = Enabled 0 ISRC2 DEC2 Enable (Decimation Channel 2 path from ISRC2_FSH rate to ISRC2_ FSL rate) 0 = Disabled 1 = Enabled 4.4 DSP Firmware Control The CS42L92 digital core incorporates one programmable DSP processing block, capable of running a range of application-specific algorithms. Different firmware configurations can be loaded onto the DSP, enabling the CS42L92 to be customized for specific application requirements. Full read/write access to the device register map is supported from the DSP core. The DSP can be clocked at up to 75 MHz, corresponding to 75 MIPS. A software programming guide can be provided to assist users in developing their own software algorithms—please contact your Cirrus Logic representative for further information. To use the programmable DSP, the required firmware configuration must first be loaded onto the device by writing the appropriate files to the CS42L92 register map. The firmware configuration comprises program, data, and coefficient content. Details of the DSP firmware memory registers are provided in Section 4.4.1. Note that the WISCE evaluation board control software provides support for easy loading of program, data, and coefficient content onto the CS42L92. Please contact your Cirrus Logic representative for more details of the WISCE evaluation board control software. After loading the DSP firmware, the DSP functions must be enabled using the associated control fields. The audio signal paths to and from the DSP processing block are configured as described in Section 4.3. Note that the DSP firmware must be loaded and enabled before audio signal paths can be enabled. 4.4.1 DSP Firmware Memory and Register Mapping The DSP firmware memory is programmed by writing to the registers referenced in Table 4-29. Note that clocking is not required for access to the firmware registers by the host processor. 94 DS1162F1 CS42L92 4.4 DSP Firmware Control The CS42L92 program, data, and coefficient register memory space is described in Table 4-29. The full register map listing is provided in Section 6. The program firmware parameters are formatted as 40-bit words. For this reason, 3 x 32-bit register addresses are required for every 2 x 40-bit words. Table 4-29. DSP Program, Data, and Coefficient Registers DSP Number Description DSP1 Program memory X-Data memory Y-Data memory Coefficient memory Register Address 0x08_0000–0x08_2FFE 0x0A_0000–0x0A_1FFE 0x0C_0000–0x0C_1FFE 0x0E_0000–0x0E_1FFE Number of Registers 6144 4096 4096 4096 DSP Memory Size 4k x 40-bit words 4k x 24-bit words 4k x 24-bit words 4k x 24-bit words The X-memory on the DSP supports read/write access to all register fields throughout the device, including the codec control registers, and the other firmware-memory regions of DSP core itself. Access to the register address space is supported using a number of register windows within the X-memory on the DSP. Note that the register window space is additional to the X-data memory size described in Table 4-29. Addresses 0xC000 to 0xDFFF in X-memory map directly to addresses 0x0000 to 0x1FFF in the device register space. This fixed register window contains primarily the codec control registers; it also includes the virtual DSP control registers (described in Section 4.4.7). Each X-memory address within this window maps onto one 16-bit register in the codec memory space. Four movable register windows are also provided, starting at X-memory addresses 0xF000, 0xF400, 0xF800, and 0xFC00 respectively. Each window represents 1024 addresses in the X-memory space. The start address, within the corresponding device register space, for each window is configured using DSP1_EXT_[A/B/C/D]_PAGE (where A defines the first window, B defines the second window, etc.). Two mapping modes are supported and are selected using the DSP1_EXT_[A/B/C/D]_PSIZE16 bits for the respective window. In 16-Bit Mode, each address within the window maps onto one 16-bit register in the device memory space; the window equates to 1024 x 16-bit registers. In 32-Bit Mode, each address within the window maps onto two 16-bit registers in the device memory space; the window equates to 1024 x 32-bit registers. Note that the X-memory is only 24-bits wide; as a result, the upper 8 bits of the odd-numbered register addresses are not mapped, and cannot be accessed, in 32-Bit Mode. The DSP1_EXT_[A/B/C/D]_PAGE fields are defined with an LSB = 512. Accordingly, the base address of each window must be aligned with 512-word boundaries. Note that the base addresses are entirely independent of each other; for example, overlapping windows are permissible if required, and there is no requirement for the A/B/C/D windows to be at incremental locations. The register map window functions are shown in Fig. 4-34. Further information on the definition and usage of the DSP firmware memories is provided in the software programming guide; contact your Cirrus Logic representative if required. DS1162F1 95 CS42L92 Page D Base Address 0xFFFF Register Window D Page C Base Address 0xFC00 0xF800 0xF400 Register Window C Register Window B Page B Base Address Register Window A 0xF000 Internal DSP Control Page A Base Address 0xE000 Write Sequencer, DSP Peripherals, and DSP Firmware Address Space 4.4 DSP Firmware Control Moveable Register Window D Moveable Register Window C Moveable Register Window B Moveable Register Window A Virtual DSP Ctrl 0x3000 0xD000 16-bits 0x2000 0xC000 CODEC Register Address Space X Data Memory (shared DSP2/DSP3) X Data Memory 0x0000 24-bits DSP X-Memory Map 0x0000 Fixed codec Register Window 16-bits Audio Hub Register Map Figure 4-34. X-Data Memory Map Note that the full CS42L92 register space is shown here as 16-bit width. (SPI/I2C register access uses 32-bit data width at 0x3000 and above.) However, the window base address fields (DSP1_EXT_[A/B/C/D]_PAGE) are referenced to 16-bit width, and 16-bit register mapping is shown. Hence, the device register map is shown here entirely as 16-bit width for ease of explanation. The control registers associated with the register map window functions are described in Table 4-30. 96 DS1162F1 CS42L92 4.4 DSP Firmware Control Table 4-30. X-Data Memory and Clocking Control Register Address R1048148 (0xF_FE54) DSP1_Ext_window_A Bit 31 Label DSP1_EXT_A_PSIZE16 15:0 DSP1_EXT_A_PAGE[15:0] R1048150 (0xF_FE56) DSP1_Ext_window_B 31 DSP1_EXT_B_PSIZE16 15:0 DSP1_EXT_B_PAGE[15:0] R1048152 (0xF_FE58) DSP1_Ext_window_C 31 DSP1_EXT_C_PSIZE16 15:0 DSP1_EXT_C_PAGE[15:0] R1048154 (0xF_FE5A) DSP1_Ext_window_D 31 DSP1_EXT_D_PSIZE16 15:0 DSP1_EXT_D_PAGE[15:0] 4.4.2 Default Description 0 Register Window A page width select 0 = 32-bit 1 = 16-bit Note that, in 32-Bit Mode, only the lower 24 bits can be accessed. 0x0000 Sets the Base Address of Register Window A in X-memory. Coded as LSB = 512 (0x200) 0 Register Window B page width select 0 = 32-bit 1 = 16-bit Note that, in 32-Bit Mode, only the lower 24 bits can be accessed. 0x0000 Sets the Base Address of Register Window B in X-memory. Coded as LSB = 512 (0x200) 0 Register Window C page width select 0 = 32-bit 1 = 16-bit Note that, in 32-Bit Mode, only the lower 24 bits can be accessed. 0x0000 Sets the Base Address of Register Window C in X-memory. Coded as LSB = 512 (0x200) 0 Register Window D page width select 0 = 32-bit 1 = 16-bit Note that, in 32-Bit Mode, only the lower 24 bits can be accessed. 0x0000 Sets the Base Address of Register Window D in X-memory. Coded as LSB = 512 (0x200) DSP Memory Locking The DSP core has the capability for read/write access to all register fields throughout the device, including the codec control registers, DSP peripheral control registers, and the virtual DSP control registers. Access to these registers is supported via the DSP’s X-memory (using the register windows), as described in Section 4.4.1. The CS42L92 provides a register-locking feature that blocks DSP register-write attempts to invalid register regions, preventing the firmware from making unintentional changes to register and memory contents. An interrupt event and associated debug information are generated if any write-access attempt is blocked; this can be used to assist software development and debug. The register map and DSP firmware memories are partitioned into four regions; each region can be locked independently. This allows full flexibility to lock different register/memory regions according to the applicable DSP firmware configuration. The DSP has direct access to its own X-, Y-, Z-, and P- memories; this is always enabled and cannot be locked. Access to the codec registers, DSP peripheral registers, and the virtual DSP registers is effected using the X-memory register windows (fixed codec window, and four configurable windows)—write access to these locations is governed by the register-locking configuration settings. The virtual DSP registers occupy addresses within the codec register space; these registers represent one of the lockable regions within the register map—two independent locks are provided for the codec and virtual DSP registers. Note: A DSP register window can be mapped onto the X-, Y-, Z-, or P- memory region of the DSP. In this event, write access via that window is governed by the register locks, potentially blocking the DSP from accessing its own memory. This is not the intended use of the register lock, however. The lockable register/memory regions are defined in Table 4-31. DS1162F1 97 CS42L92 4.4 DSP Firmware Control Table 4-31. DSP Memory Locking Regions Region Region 0 Region 1 Region 2 Region 3 Description Virtual DSP registers Codec registers DSP peripheral control registers DSP1 memory Register Address 0x00_1000–0x00_2FFF 0x00_0000–0x03_FFFE 0x04_0000–0x07_FFFE 0x08_0000–0x09_FFFE Notes Excludes memory lock and watchdog reset registers Excludes virtual DSP registers — — The register locks are controlled using the DSP1_CTRL_REGIONm_LOCK fields (where m identifies the register/memory region). The associated lock determines whether the DSP core is granted write access to region m. To change the lock status, two writes must be made to the respective register field: • Writing 0x5555, followed by 0xAAAA, sets the respective lock • Writing 0xCCCC, followed by 0x3333, clears the respective lock The status of each lock can be read from the DSP1_CTRL_REGIONm_LOCK_STS bits. Write access to the DSP1_CTRL_REGIONm_LOCK fields is always possible. This means that the DSP core always has write access for configuring the memory-access locks. The DSP memory locking function is an input to the interrupt control circuit and can be used to trigger an interrupt event if an invalid register write is attempted—see Section 4.4.5. Additional status and control fields are provided for debug purposes, as described in Section 4.4.6. The control registers associated with the DSP memory locking functions are described in Table 4-32. Table 4-32. DSP Memory Locking Control Register Address R1048164 (0xF_FE64) DSP1_Region_lock_sts_0 R1048166 (0xF_FE66) DSP1_Region_lock_1___ DSP1_Region_lock_0 R1048168 (0xF_FE68) DSP1_Region_lock_3___ DSP1_Region_lock_2 Bit 3 2 1 0 31:16 Label DSP1_CTRL_REGION3_LOCK_STS DSP1_CTRL_REGION2_LOCK_STS DSP1_CTRL_REGION1_LOCK_STS DSP1_CTRL_REGION0_LOCK_STS DSP1_CTRL_REGION1_LOCK[15:0] 15:0 DSP1_CTRL_REGION0_LOCK[15:0] 31:16 DSP1_CTRL_REGION3_LOCK[15:0] 15:0 DSP1_CTRL_REGION2_LOCK[15:0] Default 0 0 0 0 See Footnote 1 See Footnote 1 See Footnote 1 See Footnote 1 Description DSP1 memory region m lock status 0 = Unlocked 1 = Locked (write access is blocked) DSP1 memory region m lock. Write 0x5555, then 0xAAAA, to set the lock. Write 0xCCCC, then 0x3333, to clear the lock. 1. Default is not applicable to these write-only fields 4.4.3 DSP Firmware Control The configuration and control of the DSP firmware is described in the following subsections. 4.4.3.1 DSP Memory The DSP memory (program, X-data, Y-data, and coefficient) is enabled by setting DSP1_MEM_ENA. This memory must be enabled (DSP1_MEM_ENA = 1) for read/write access, code execution, and DMA functions. The DSP memory is disabled, and the contents lost, whenever the DSP1_MEM_ENA bit is cleared. The DSP1_RAM_RDY status bit indicates whether the DSP memory is ready for read/write access. The DSP memory should not be accessed until this bit has been set. The DSP1_MEM_ENA bit is not affected by software reset; it remains in its previous state under software reset conditions. Accordingly, the DSP memory contents are maintained through software reset, provided DCVDD is held above its reset threshold. The DSP firmware memory is always cleared under power-on reset, hardware reset, and Sleep Mode conditions. See Section 5.2 for a summary of the CS42L92 reset behavior. 98 DS1162F1 CS42L92 4.4 DSP Firmware Control 4.4.3.2 DSP Clocking Clocking is required for the DSP processing block, when executing software or when supporting DMA functions. (Note that clocking is not required for access to the firmware registers by the host processor.) Clocking within the DSP is enabled and disabled automatically, as required by the DSP core and DMA channel status. The clock source for each DSP is derived from DSPCLK. See Section 4.16 for details of how to configure DSPCLK. The clock frequency for the DSP is selected using DSP1_CLK_FREQ_SEL. The DSP clock frequency must be less than or equal to the DSPCLK frequency. The DSP1_CLK_FREQ_STS field indicates the clock frequency for the DSP core. This can be used to confirm the clock frequency, in cases where code execution has a minimum clock frequency requirement. The DSP1_CLK_FREQ_STS field is only valid when the core is running code; typical usage of this field would be for the DSP core itself to read the clock status and to take action as applicable, in particular, if the available clock does not meet the application requirements. Note that, depending on the DSPCLK frequency and the available clock dividers, the DSP1 clock frequency may differ from the selected clock. In most cases, the DSP1 clock frequency equals or exceeds the requested frequency. A lower frequency is implemented if limited by either the DSPCLK frequency or the maximum DSP1 clocking frequency. The DSPCLK configuration provides input to the interrupt control circuit and can be used to trigger an interrupt event when the DSP1 clock frequency is less than the requested frequency; see Section 4.15. 4.4.3.3 DSP Code Execution After the DSP firmware has been loaded, and the clocks configured, the DSP block is enabled by setting DSP1_CORE_ ENA. When the DSP is configured and enabled, the firmware execution can be started by writing 1 to DSP1_START. Alternative methods to trigger the firmware execution can also be configured using the DSP1_START_IN_SEL field. Using the DSP1_START_IN_SEL field, the DSP firmware execution can be linked to the respective DMA function, the IRQ2 status, or to the FIFO status in the event logger: • DMA function: firmware execution commences when all enabled DSP input (WDMA) channel buffers have been filled, and all enabled DSP output (RDMA) channel buffers have been emptied • IRQ2: firmware execution commences when one or more of the unmasked IRQ2 events has occurred • Event logger status: firmware execution commences when the FIFO not-empty status is asserted within the event logger To enable firmware execution on the DSP block, the DSP1_CORE_ENA bit must be set. Note that the usage of the DSP1_ START bit may vary depending on the particular firmware that is being executed: in some applications (e.g., when an alternative trigger is selected using DSP1_START_IN_SEL), writing to the DSP1_START bit is not required. 4.4.3.4 DSP Watchdog Timer A watchdog timer is provided for the DSP, which can be used to detect software lock-ups, and other conditions that require corrective action in order to resume the intended DSP behavior. The DSP1 watchdog is enabled using DSP1_WDT_ENA. The timeout period is configured using DSP1_WDT_MAX_ COUNT. In normal operation, the watchdog should be reset regularly—this action is used to confirm that the DSP code is running correctly. The watchdog is reset by writing 0x5555, followed by 0xAAAA, to the DSP1_WDT_RESET field. The watchdog status bit, DSP1_WDT_TIMEOUT_STS, is set if the timeout period elapses before the watchdog is reset; this event typically signals that a lock-up or other error condition has occurred. The DSP watchdog is an input to the interrupt control circuit and can be used to trigger an interrupt event if the timeout period elapses—see Section 4.4.5. Note that write access to the DSP1_WDT_RESET field is not affected by the register locking mechanism (see Section 4.4.2). This means that the DSP core always has write access to reset the watchdog. DS1162F1 99 CS42L92 4.4 DSP Firmware Control 4.4.3.5 DSP Control Registers The DSP memory, clocking, code-execution, and watchdog control registers are described in Table 4-33. The audio signal paths connecting to/from the DSP processing block are configured as described in Section 4.3. Note that the DSP firmware must be loaded and enabled before audio signal paths can be enabled. Table 4-33. DSP Control Registers Register Address R1048064 (0xF_ FE00) Bit 4 Label DSP1_MEM_ENA 1 DSP1_CORE_ENA 0 DSP1_START DSP1_Config_1 R1048066 (0xF_ FE02) DSP1_Config_2 R1048070 (0xF_ FE06) DSP1_Status_2 R1048072 (0xF_ FE08) DSP1_Status_3 R1048074 (0xF_ FE0A) DSP1_Watchdog_1 15:0 DSP1_CLK_FREQ_ SEL[15:0] 0 DSP1_CLK_AVAIL 15:0 DSP1_CLK_FREQ_ STS[15:0] 4:1 DSP1_WDT_MAX_ COUNT[3:0] 0 DSP1_WDT_ENA R1048120 (0xF_ FE38) DSP1_External_Start 4:0 DSP1_START_IN_ SEL[4:0] R1048158 (0xF_ FE5E) DSP1_Watchdog_2 R1048186 (0xF_ FE7A) DSP1_Region_lock_ ctrl_0 15:0 DSP1_WDT_ RESET[15:0] 4.4.4 13 DSP1_WDT_ TIMEOUT_STS Default Description 0 DSP1 memory control 0 = Disabled 1 = Enabled The DSP1 memory contents are lost when DSP1_MEM_ENA =0. Note that this bit is not affected by software reset; it remains in its previous condition. 0 DSP1 enable. Controls the DSP1 firmware execution 0 = Disabled 1 = Enabled — DSP1 start Write 1 to start DSP1 firmware execution 0x0000 DSP1 clock frequency select Coded as LSB = 1/64 MHz, Valid from 5.6 to 75 MHz. The DSP1 clock must be less than or equal to the DSPCLK frequency. The DSP1 clock is generated by division of DSPCLK, and may differ from the selected frequency. The DSP1 clock frequency can be read from DSP1_ CLK_FREQ_STS. 0 DSP1 clock availability (read only) 0 = No Clock 1 = Clock Available This bit exists for legacy software support only; it is not recommended for future designs—it may be unreliable on the latest device architectures. 0x0000 DSP1 clock frequency (read only). Valid only when the respective DSP core is enabled. Coded as LSB = 1/64 MHz. 0x0 DSP1 watchdog timeout value. 0xA = 2 s 0x5 = 64 ms 0x0 = 2 ms 0xB = 4 s 0x6 = 128 ms 0x1 = 4 ms 0xC = 8 s 0x7 = 256 ms 0x2 = 8 ms 0xD–0xF = reserved 0x8 = 512 ms 0x3 = 16 ms 0x9 = 1 s 0x4 = 32 ms 0 DSP1 watchdog enable 0 = Disabled 1 = Enabled 0x00 DSP1 firmware execution control. Selects the trigger for DSP1 firmware execution. 0x00 = DMA 0x0B = IRQ2 0x10 = Event Logger 1 All other codes are reserved. Note that the DSP1_START bit also starts the DSP1 firmware execution, regardless of this field setting. 0x0000 DSP1 watchdog reset. Write 0x5555, followed by 0xAAAA, to reset the watchdog. 0 DSP1 watchdog timeout status This bit, when set, indicates that the watchdog timeout has occurred. This bit is latched when set; it is cleared when the watchdog is disabled or reset. DSP Direct Memory Access (DMA) Control The DSP provides a multichannel DMA function; this is configured using the registers described in Table 4-34. 100 DS1162F1 CS42L92 4.4 DSP Firmware Control There are eight WDMA (DSP input) and six RDMA (DSP output) channels; these are enabled using the DSP1_WDMA_ CHANNEL_ENABLE and DSP1_RDMA_CHANNEL_ENABLE fields. The status of each WDMA channel is indicated in DSP1_WDMA_ACTIVE_CHANNELS. The DMA can access the X-data memory or Y-data memory associated with the DSP block. The applicable memory is selected using bit [15] of the respective x_START_ADDRESS field for each DMA channel. The start address of each DMA channel is configured as described in Table 4-34. Note that the required address is defined relative to the base address of the selected (X-data or Y-data) memory. The buffer length of the DMA channels is configured using the DSP1_DMA_BUFFER_LENGTH field. The selected buffer length applies to all enabled DMA channels. Note that the start-address fields and buffer-length fields are defined in 24-bit DSP data word units. This means that the LSB of these fields represents one 24-bit DSP memory word. This differs from the CS42L92 register map layout described in Table 4-29. The parameters of a DMA channel (i.e., start address or offset address) must not be changed while the respective DMA is enabled. All of the DMA channels must be disabled before changing the DMA buffer length. Each DMA channel uses a twin buffer mechanism to support uninterrupted data flow through the DSP. The buffers are called ping and pong, and are of configurable size, as noted above. Data is transferred to/from each of the buffers in turn. When the ping input data buffer is full, the DSP1_PING_FULL bit is set, and a DSP start signal is generated. The start signal from the DMA is typically used to start firmware execution, as noted in Table 4-33. Meanwhile, further DSP input data fills up the pong buffer. When the pong input buffer is full, the DSP1_PONG_FULL bit is set, and another DSP start signal is generated. The DSP firmware must take care to read the input data from the applicable buffer, in accordance with the DSP1_PING_FULL and DSP1_PONG_FULL status bits. Twin buffers are also used on the DSP output (RDMA) channels. The output ping buffers are emptied at the same time as the input ping buffers are filled; the output pong buffers are emptied at the same time that the input pong buffers are filled. The DSP core supports 24-bit signal processing. Under default conditions, the DSP audio data is in 2’s complement Q3.20 format (i.e., 0xF00000 corresponds to the –1.0 level, and 0x100000 corresponds to the +1.0 level; a sine wave with peak values of ±1.0 corresponds to the 0 dBFS level). If DSP1_DMA_WORD_SEL is set, audio data is transferred to and from the DSP in Q0.23 format. The applicable format should be set according to the requirements of the specific DSP firmware. Note that the DSP core is optimized for Q3.20 audio data processing; Q0.23 data can be supported, but the firmware implementation may incur a reduction in power efficiency due to the higher MIPS required for arithmetic operations in non-native data word format. The DMA function is an input to the interrupt control circuit—see Section 4.4.5. The respective interrupt event is triggered if all enabled input (WDMA) channel buffers have been filled and all enabled output (RDMA) channel buffers have been emptied. Further details of the DMA are provided in the software programming guide; contact your Cirrus Logic representative if required. DS1162F1 101 CS42L92 4.4 DSP Firmware Control Table 4-34. DMA Control Register Address R1048068 (0xF_FE04) DSP1_Status_1 Bit 31 Label DSP1_PING_FULL Default 0 30 DSP1_PONG_FULL 0 23:16 DSP1_WDMA_ACTIVE_ CHANNELS[7:0] 0x00 R1048080 (0xF_FE10) 31:16 DSP1_START_ADDRESS_ WDMA_BUFFER_1[15:0] DSP1_WDMA_Buffer_1 0x0000 15:0 DSP1_START_ADDRESS_ WDMA_BUFFER_0[15:0] 0x0000 R1048082 (0xF_FE12) 31:16 DSP1_START_ADDRESS_ WDMA_BUFFER_3[15:0] DSP1_WDMA_Buffer_2 15:0 DSP1_START_ADDRESS_ WDMA_BUFFER_2[15:0] 0x0000 R1048084 (0xF_FE14) 31:16 DSP1_START_ADDRESS_ WDMA_BUFFER_5[15:0] DSP1_WDMA_Buffer_3 15:0 DSP1_START_ADDRESS_ WDMA_BUFFER_4[15:0] 0x0000 R1048086 (0xF_FE16) 31:16 DSP1_START_ADDRESS_ WDMA_BUFFER_7[15:0] DSP1_WDMA_Buffer_4 15:0 DSP1_START_ADDRESS_ WDMA_BUFFER_6[15:0] 0x0000 R1048096 (0xF_FE20) DSP1_RDMA_Buffer_1 31:16 DSP1_START_ADDRESS_ RDMA_BUFFER_1[15:0] 0x0000 15:0 DSP1_START_ADDRESS_ RDMA_BUFFER_0[15:0] 0x0000 31:16 DSP1_START_ADDRESS_ RDMA_BUFFER_3[15:0] 0x0000 15:0 DSP1_START_ADDRESS_ RDMA_BUFFER_2[15:0] 0x0000 31:16 DSP1_START_ADDRESS_ RDMA_BUFFER_5[15:0] 0x0000 15:0 DSP1_START_ADDRESS_ RDMA_BUFFER_4[15:0] 0x0000 R1048098 (0xF_FE22) DSP1_RDMA_Buffer_2 R1048100 (0xF_FE24) DSP1_RDMA_Buffer_3 102 0x0000 0x0000 0x0000 Description DSP1 WDMA Ping Buffer Status 0 = Not Full 1 = Full DSP1 WDMA Pong Buffer Status 0 = Not Full 1 = Full DSP1 WDMA Channel Status There are eight WDMA channels; each bit of this field indicates the status of the respective WDMA channel. Each bit is coded as follows: 0 = Inactive 1 = Active DSP1 WDMA Channel 1 Start Address Bit [15] = Memory select 0 = X-data memory 1 = Y-data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP1_WDMA_CHANNEL_OFFSET bit. DSP1 WDMA Channel 0 Start Address Field description is as above. DSP1 WDMA Channel 3 Start Address Field description is as above. DSP1 WDMA Channel 2 Start Address Field description is as above. DSP1 WDMA Channel 5 Start Address Field description is as above. DSP1 WDMA Channel 4 Start Address Field description is as above. DSP1 WDMA Channel 7 Start Address Field description is as above. DSP1 WDMA Channel 6 Start Address Field description is as above. DSP1 RDMA Channel 1 Start Address Bit [15] = Memory select 0 = X-data memory 1 = Y-data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP1_RDMA_CHANNEL_OFFSET bit. DSP1 RDMA Channel 0 Start Address Field description is as above. DSP1 RDMA Channel 3 Start Address Field description is as above. DSP1 RDMA Channel 2 Start Address Field description is as above. DSP1 RDMA Channel 5 Start Address Field description is as above. DSP1 RDMA Channel 4 Start Address Field description is as above. DS1162F1 CS42L92 4.4 DSP Firmware Control Table 4-34. DMA Control (Cont.) Register Address R1048112 (0xF_FE30) DSP1_DMA_Config_1 Bit Label 23:16 DSP1_WDMA_CHANNEL_ ENABLE[7:0] Default 0x00 13:0 DSP1_DMA_BUFFER_ LENGTH[13:0] 0x0000 R1048114 (0xF_FE32) DSP1_DMA_Config_2 R1048116 (0xF_FE34) DSP1_DMA_Config_3 7:0 DSP1_WDMA_CHANNEL_ OFFSET[7:0] 0x00 21:16 DSP1_RDMA_CHANNEL_ OFFSET[5:0] 0x00 R1048118 (0xF_FE36) DSP1_DMA_Config_4 4.4.5 5:0 DSP1_RDMA_CHANNEL_ ENABLE[5:0] 0x00 0 DSP1_DMA_WORD_SEL 0 Description DSP1 WDMA Channel Enable There are eight WDMA channels; each bit of this field enables the respective WDMA channel. Each bit is coded as follows: 0 = Disabled 1 = Enabled DSP1 DMA Buffer Length Selects the amount of data transferred in each DMA channel. The LSB represents one 24-bit DSP memory word. DSP1 WDMA Channel Offset There are eight WDMA channels; each bit of this field offsets the start Address of the respective WDMA channel. Each bit is coded as follows: 0 = No offset 1 = Offset by 0x8000 DSP1 RDMA Channel Offset There are six RDMA channels; each bit of this field offsets the start Address of the respective RDMA channel. Each bit is coded as follows: 0 = No offset 1 = Offset by 0x8000 DSP1 RDMA Channel Enable There are six RDMA channels; each bit of this field enables the respective RDMA channel. Each bit is coded as follows: 0 = Disabled 1 = Enabled DSP1 Data Word Format 0 = Q3.20 format (4 integer bits, 20 fractional bits) 1 = Q0.23 format (1 integer bit, 23 fractional bits) The data word format should be set according to the requirements of the applicable DSP firmware. DSP Interrupts The DSP core provides inputs to the interrupt circuit and can be used to trigger an interrupt event when the associated conditions occur. The following interrupts are provided for DSP core: • DMA interrupt—Asserted when all enabled DSP input (WDMA) channel buffers have been filled, and all enabled DSP output (RDMA) channel buffers have been emptied • DSP Start 1, DSP Start 2 interrupts—Asserted when the respective start signal is triggered • DSP Busy interrupt—Asserted when the DSP is busy (i.e., when firmware execution or DMA processes are started) • DSP Bus Error interrupt—Asserted when a locked register address, invalid memory address, or watchdog timeout error is detected The CS42L92 also provides 16 control bits that allow the DSP core to generate programmable interrupt events. When a 1 is written to these bits (see Table 4-35), the respective DSP interrupt (DSP_IRQn_EINTx) is triggered. The associated interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal. See Section 4.15 for further details. Table 4-35. DSP Interrupts Register Address R5632 (0x1600) ADSP2_IRQ0 R5633 (0x1601) ADSP2_IRQ1 DS1162F1 Bit 1 0 1 0 Label DSP_IRQ2 DSP_IRQ1 DSP_IRQ4 DSP_IRQ3 Default 0 0 0 0 Description DSP IRQ2. Write 1 to trigger the DSP_IRQ2_EINTn interrupt. DSP IRQ1. Write 1 to trigger the DSP_IRQ1_EINTn interrupt. DSP IRQ4. Write 1 to trigger the DSP_IRQ4_EINTn interrupt. DSP IRQ3. Write 1 to trigger the DSP_IRQ3_EINTn interrupt. 103 CS42L92 4.4 DSP Firmware Control Table 4-35. DSP Interrupts (Cont.) Register Address R5634 (0x1602) ADSP2_IRQ2 R5635 (0x1603) ADSP2_IRQ3 R5636 (0x1604) ADSP2_IRQ4 R5637 (0x1605) ADSP2_IRQ5 R5638 (0x1606) ADSP2_IRQ6 R5639 (0x1607) ADSP2_IRQ7 4.4.6 Bit 1 0 1 0 1 0 1 0 1 0 1 0 Label DSP_IRQ6 DSP_IRQ5 DSP_IRQ8 DSP_IRQ7 DSP_IRQ10 DSP_IRQ9 DSP_IRQ12 DSP_IRQ11 DSP_IRQ14 DSP_IRQ13 DSP_IRQ16 DSP_IRQ15 Default 0 0 0 0 0 0 0 0 0 0 0 0 Description DSP IRQ6. Write 1 to trigger the DSP_IRQ6_EINTn interrupt. DSP IRQ5. Write 1 to trigger the DSP_IRQ5_EINTn interrupt. DSP IRQ8. Write 1 to trigger the DSP_IRQ8_EINTn interrupt. DSP IRQ7. Write 1 to trigger the DSP_IRQ7_EINTn interrupt. DSP IRQ10. Write 1 to trigger the DSP_IRQ10_EINTn interrupt. DSP IRQ9. Write 1 to trigger the DSP_IRQ9_EINTn interrupt. DSP IRQ12. Write 1 to trigger the DSP_IRQ12_EINTn interrupt. DSP IRQ11. Write 1 to trigger the DSP_IRQ11_EINTn interrupt. DSP IRQ14. Write 1 to trigger the DSP_IRQ14_EINTn interrupt. DSP IRQ13. Write 1 to trigger the DSP_IRQ13_EINTn interrupt. DSP IRQ16. Write 1 to trigger the DSP_IRQ16_EINTn interrupt. DSP IRQ15. Write 1 to trigger the DSP_IRQ15_EINTn interrupt. DSP Debug Support General-purpose registers are provided for the DSP. These have no assigned function and can be used to assist in algorithm development. The JTAG interface provides test and debug access to the CS42L92, as described in Section 4.20. The JTAG interface clock can be enabled for the DSP core using DSP1_DBG_CLK_ENA. Note that, when the JTAG interface is used to access the DSP core, the DSP1_CORE_ENA bit must also be set. The DSP1_LOCK_ERR_STS bit indicates that the DSP attempted to write to a locked register address. The DSP1_ ADDR_ERR_STS bit indicates that the DSP attempted to access an invalid memory address (i.e., an address whose contents are undefined). Once set, these bits remain set until a 1 is written to DSP1_ERR_CLEAR. The DSP1_PMEM_ERR_ADDR and DSP1_XMEM_ERR_ADDR fields contain the program memory and X-data memory addresses associated with a locked register address error condition. If DSP1_LOCK_ERR_STS is set, these fields correspond to the first-detected locked register address error. Note that no subsequent error event can be reported in these fields until the DSP1_LOCK_ERR_STS is cleared. Note: The DSP1_PMEM_ERR_ADDR value is the prefetched address of a code instruction that has not yet been executed; it does not point directly to the instruction that caused the error. The DSP1_BUS_ERR_ADDR field indicates the register/memory address that resulted in a register-access error. The field relates either to a locked register address error or to an invalid memory address error, as follows: • If DSP1_LOCK_ERR_STS is set, the DSP1_BUS_ERR_ADDR value corresponds to the first-detected locked register address error. Note that no subsequent error event can be reported in this field until DSP1_LOCK_ERR_ STS is cleared. • If DSP1_ADDR_ERR_STS is set, and DSP1_LOCK_ERR_STS is clear, the DSP1_BUS_ERR_ADDR field corresponds to the most recent invalid memory address error. • If the DSP1_LOCK_ERR_STS and DSP1_ADDR_ERR_STS are both clear, the DSP1_BUS_ERR_ADDR field is undefined. Note: The DSP1_BUS_ERR_ADDR value is coded using a byte-referenced address, so the actual register address is equal to DSP1_BUS_ERR_ADDR / 2. If the register-access error is the result of an attempt to access the virtual DSP registers, a register address of 0 is reported. If the DSP1_ERR_PAUSE bit is set, the DSP code execution stops immediately on detection of a locked register address error. This enables debug information to be retrieved from the DSP core during code development. In this event, code execution can be restarted by clearing the DSP1_ERR_PAUSE bit. Alternatively, the DSP core can restarted by clearing and setting DSP1_CORE_ENA (described in Section 4.4.3.3). 104 DS1162F1 CS42L92 4.4 DSP Firmware Control Table 4-36. DSP Debug Support Register Address R1048064 (0xF_FE00) DSP1_Config_1 Description DSP1 Debug Clock Enable 0 = Disabled 1 = Enabled R1048128 (0xF_FE40) 31:16 DSP1_SCRATCH_1[15:0] 0x0000 DSP1 Scratch Register 1 DSP1_Scratch_1 15:0 DSP1_SCRATCH_0[15:0] 0x0000 DSP1 Scratch Register 0 R1048130 (0xF_FE42) 31:16 DSP1_SCRATCH_3[15:0] 0x0000 DSP1 Scratch Register 3 DSP1_Scratch_2 15:0 DSP1_SCRATCH_2[15:0] 0x0000 DSP1 Scratch Register 2 R1048146 (0xF_FE52) 23:0 DSP1_BUS_ERR_ADDR[23:0] 0x00_0000 Contains the register address of a memory region lock or memory address error event. DSP1_Bus_Error_Addr Note the associated register address is equal to DSP1_ BUS_ERR_ADDR / 2. R1048186 (0xF_FE7A) 15 DSP1_LOCK_ERR_STS 0 DSP1 memory region lock error status. DSP1_Region_lock_ctrl_0 This bit, when set, indicates that DSP1 attempted to write to a locked register address. This bit is latched when set; it is cleared when a 1 is written to DSP1_ERR_CLEAR. 14 DSP1_ADDR_ERR_STS 0 DSP1 memory address error status. This bit, when set, indicates that DSP1 attempted to access an undefined locked register address. This bit is latched when set; it is cleared when a 1 is written to DSP1_ERR_CLEAR. 1 DSP1_ERR_PAUSE 0 DSP1 bus address error control. Configures the DSP1 response to a memory region lock error event. 0 = No action 1 = Pause DSP1 code execution 0 DSP1_ERR_CLEAR 0 Write 1 to clear the memory region lock error and memory address error status bits. 30:16 DSP1_PMEM_ERR_ADDR[14:0] 0x0000 Contains the program memory address of a memory R1048188 (0xF_FE7C) region lock error event. Note this is the prefetched DSP1_PMEM_Err_Addr___ address of a subsequent instruction; it does not point XMEM_ERR_Addr directly to the address that caused the error. 15:0 DSP1_XMEM_ERR_ADDR[15:0] 0x0000 Contains the X-data memory address of a memory region lock error event. 4.4.7 Bit 3 Label DSP1_DBG_CLK_ENA Default 0 Virtual DSP Registers The DSP control registers are described throughout Section 4.4. Each control register has a unique location within the CS42L92 register map. An additional set of DSP control registers is also defined, which can be used in firmware to access the DSP control fields: the virtual DSP (or DSP 0) registers are defined at address R4096 (0x1000) in the device register map. The full register map listing is provided in Section 6. Note that read/write access to the virtual DSP registers is only possible via firmware running on the integrated DSP core. When DSP firmware accesses the virtual registers, the registers are automatically mapped onto the DSP1 control registers. The virtual DSP registers are designed to allow software to be transferable across different DSPs (e.g., on multicore devices) without modification to the software code. The virtual DSP registers are defined at register addresses R4096–R4192 (0x1000–0x1060) in the device register map. Note that these registers cannot be accessed directly at the addresses shown; they can be only accessed through DSP firmware code, using the register window function shown in Fig. 4-34. The virtual DSP registers are located at address 0xD000 in the X-data memory map. DS1162F1 105 CS42L92 4.5 DSP Peripheral Control 4.5 DSP Peripheral Control The CS42L92 incorporates a suite of DSP peripheral functions that can be integrated together to provide an enhanced capability for DSP applications. Configurable event log functions provide multichannel monitoring of internal and external signals. The general-purpose timer provides time-stamp data for the event logger; it also supports the watchdog and other miscellaneous time-based functions. Maskable GPIO provides an efficient mechanism for the DSP core to access the required input and output signals. The DSP peripherals are designed to provide a comprehensive DSP capability, operating with a high degree of autonomy from the host processor. 4.5.1 Event Logger The CS42L92 provides an event log function, supporting multichannel, edge-sensitive monitoring and recording of internal or external signals. 4.5.1.1 Overview The event logger allows status information to be captured from a large number of sources, to be prioritized and acted upon as required. For the purposes of the event logger, an event is recorded when a logic transition (edge) is detected on a selected signal source. The logged events are held in a FIFO buffer, which is managed by the application software. A 32-bit time stamp, derived from the general-purpose timer, is associated and recorded with each FIFO index, to provide a comprehensive record of the detected events. The event logger must be associated with the general-purpose timer. The timer is the source of time stamp data for any logged events. If DSPCLK is disabled, the timer also provides the clock source for the event logger. (If DSPCLK is enabled, DSPCLK is used as the clock source instead.) A maximum of one event per cycle of the clock source can be logged. If more than one event occurs within the cycle time, the highest priority (lowest channel number) event is logged at the rising edge of the clock. In this case, any lower priority events are queued, and are logged as soon as no higher priority events are pending. It is possible for recurring events on a high-priority channel to be logged, while low-priority ones remain queued. Note that recurring instances of queued events are not logged. The event logger can use a slow clock (e.g., 32 kHz), but higher clock frequencies may also be commonly used, depending on the application and use case. The clock frequency determines the maximum possible event logging rate. 4.5.1.2 Event Logger Control The event logger is enabled by setting EVENTLOG1_ENA. The event logger can be reset by writing 1 to EVENTLOG1_ RST—executing this function clears all the event logger status flags and clears the contents of the FIFO buffer. The associated timer (and time-stamp source) is selected using EVENTLOG1_TIME_SEL. Note that the event logger must be disabled (EVENTLOG1_ENA = 0) when selecting the timer source. 4.5.1.3 Input Channel Configuration The event logger allows up to 16 input channels to be configured for detection and logging. The EVENTLOG1_CHx_SEL field selects the applicable input source for each channel (where x identifies the channel number, 1 to 16). The polarity selection and debounce options are configured using the EVENTLOG1_CHx_POL and EVENTLOG1_CHx_DB bits respectively. To avoid filling the FIFO buffer with repeated instances of any event, a selectable filter is provided for each input channel. If the EVENTLOG1_CHx_FILT bit is set, new events on the respective channel are ignored by the event logger if the unread entries in the FIFO buffer indicate a previous event of the same type (i.e., same input source and same polarity). The read/write pointers of the FIFO buffer (see Section 4.5.1.4) are used to determine which FIFO entries are unread (i.e., have not yet been read by the host processor). 106 DS1162F1 CS42L92 4.5 DSP Peripheral Control The input channels can be enabled or disabled freely, using EVENTLOG1_CHx_ENA, without having to disable the event logger entirely. An input channel must be disabled whenever the associated x_SEL, x_FILT, x_POL, or x_DB fields are written. It is possible to reconfigure input channels while the event logger is enabled, provided the channels being reconfigured are disabled when doing so. The available input sources include GPIO inputs, external accessory status (jack, mic, sensors), and signals generated by the integrated DSP core. A list of the valid input sources for the event logger is provided in Table 4-38. Note that, to log both rising and falling events from any source, two separate input channels must be configured—one for each polarity. If an input channel is configured for rising edge detection (EVENTLOG1_CHx_POL = 0), and the corresponding input signal is asserted (Logic 1) at the time when the event logger is enabled, an event is logged in respect of this initial state. Similarly, if an input channel is configured for falling edge detection, and is deasserted (Logic 0) when the event logger is enabled, a corresponding event is logged. If rising and falling edges are both configured for detection, an event is always logged in respect of the initial condition. 4.5.1.4 FIFO Buffer Each event (signal transition) that meets the criteria of an enabled channel is written to the 16-stage FIFO buffer. The buffer is filled cyclically, but does not overwrite unread data when full. A status bit is provided to indicate if the buffer fills up completely. Note that the FIFO behavior is not enforced or fully implemented in the device hardware, but assumes that a compatible software implementation is in place. New events are written to the buffer in a cyclic manner, but the data can be read out in any order, if desired. The designed FIFO behavior requires the software to update the read pointer (RPTR) in the intended manner for smooth operation. The entire contents of the 16-stage FIFO buffer can be accessed directly in the register map. Each FIFO index (y = 0 to 15) comprises the EVENTLOG1_FIFOy_ID (identifying the source signal of the associated log event), the EVENTLOG1_ FIFOy_POL (the polarity of the respective event transition), and the EVENTLOG1_FIFOy_TIME field (containing the 32-bit time stamp from the timer). The FIFO buffer is managed using EVENTLOG1_FIFO_WPTR and EVENTLOG1_FIFO_RPTR. The write pointer (WPTR) field identifies the index location (0 to 15) in which the next event is logged. The read pointer (RPTR) field identifies the index location of the first set of unread data, if any exists. Both of these fields are initialized to 0 when the event logger is reset. • If RPTR  WPTR, the buffer contains new data. The number of new events is equal to the difference between the two pointer values (WPTR – RPTR, allowing for wraparound beyond Index 15). For example, if WPTR = 12 and RPTR = 8, this means that there are four unread data sets in the buffer, at index locations 8, 9, 10, and 11. After reading the new data from the buffer, the RPTR value should be incremented by the corresponding amount (e.g., increment by 4, in the example described above). Note that the RPTR value can either be incremented once for each read, or can be incremented in larger steps after a batch read. • If RPTR = WPTR, the buffer is either empty (0 events) or full (16 events). In this case, the status bits described in Section 4.5.1.5 confirm the current status of the buffer. 4.5.1.5 Status Bits The EVENTLOG1_CHx_STS bits indicate the status of the source signal for the respective input channel. Note that the status indication is not valid for all input source selections—it is not possible to provide indication of transitory events (e.g., microphone accessory detection). The EVENTLOG1_NOT_EMPTY bit indicates whether the FIFO buffer is empty. If this bit is set, it indicates one or more new sets of data in the FIFO. The EVENTLOG1_WMARK_STS bit indicates when the number of FIFO index locations available for new events reaches a configurable threshold, known as the watermark level. The watermark level is held in the EVENTLOG1_FIFO_WMARK field. DS1162F1 107 CS42L92 4.5 DSP Peripheral Control The EVENTLOG1_FULL bit indicates when the FIFO buffer is full. If this bit is set, it indicates that there are 16 sets of new event data in the FIFO. Note that this does not mean that a buffer overflow condition has occurred, but further events are not logged or indicated until the buffer has been cleared. Note: 4.5.1.6 Following a buffer full condition, the FIFO operation resumes as soon as the RPTR field has been updated to a new value. Writing the same value to RPTR does not restart the FIFO operation, even if the entire buffer contents have been read. After all of the required data has been read from the buffer, the RPTR value should be set equal to the WPTR value; an intermediate (different) value must also be written to the RPTR field in order to clear the buffer full status and restart the FIFO operation. Interrupts, GPIO, Write Sequencer, and DSP Firmware Control The control-write sequencer is automatically triggered whenever the NOT_EMPTY status of the event log buffer is asserted. See Section 4.18 for further details. The event log status flags are inputs to the interrupt control circuit and can be used to trigger an interrupt event when the respective FIFO condition (full, not empty, or watermark level) occurs; see Section 4.15. The event log status can be output directly on a GPIO pin as an external indication of the event logger; see Section 4.14 to configure a GPIO pin for this function. The event log NOT_EMPTY status can also be selected as a start trigger for DSP firmware execution; see Section 4.4. 4.5.1.7 Event Logger Control Registers The event logger control registers are described in Table 4-37. Table 4-37. Event Logger (EVENTLOG1) Control Register Address R294912 (0x4_8000) Bit 1 Label EVENTLOG1_RST 0 EVENTLOG1_ENA EVENTLOG1_CONTROL R294916 (0x4_8004) EVENTLOG1_TIMER_SEL 1:0 EVENTLOG1_TIMER_ SEL[1:0] R294924 (0x4_800C) EVENTLOG1_FIFO_ CONTROL1 3:0 EVENTLOG1_FIFO_ WMARK[3:0] R294926 (0x4_800E) EVENTLOG1_FIFO_ POINTER1 18 EVENTLOG1_FULL 17 EVENTLOG1_WMARK_STS 16 EVENTLOG1_NOT_EMPTY 11:8 EVENTLOG1_FIFO_ WPTR[3:0] 3:0 108 EVENTLOG1_FIFO_ RPTR[3:0] Default Description 0 Event Log Reset Write 1 to reset the status outputs and clear the FIFO buffer. 0 Event Log Enable 0 = Disabled 1 = Enabled 00 Event Log Timer Source Select 00 = Timer 1 All other codes are reserved. Note that the event log must be disabled when updating this field. 0x1 Event Log FIFO Watermark. The watermark status output is asserted when the number of FIFO locations available for new events is less than or equal to the FIFO watermark. Valid from 0 to 15. 0 Event Log FIFO Full Status. This bit, when set, indicates that the FIFO buffer is full. It is cleared when a new value is written to the FIFO read pointer, or when the event log is Reset. 0 Event Log FIFO Watermark Status. This bit, when set, indicates that the FIFO space available for new events to be logged is less than or equal to the watermark threshold. 0 Event Log FIFO Not-Empty Status. This bit, when set, indicates one or more new sets of logged event data in the FIFO. 0x0 Event Log FIFO Write Pointer. Indicates the FIFO index location in which the next event is logged. This is a read-only field. 0x0 Event Log FIFO Read Pointer. Indicates the FIFO index location of the first set of unread data, if any exists. For the intended FIFO behavior, this field must be incremented after the respective data has been read. DS1162F1 CS42L92 4.5 DSP Peripheral Control Table 4-37. Event Logger (EVENTLOG1) Control (Cont.) Register Address R294944 (0x4_8020) EVENTLOG1_CH_ENABLE R294948 (0x4_8024) EVENTLOG1_CH_STATUS DS1162F1 Bit 15 Label EVENTLOG1_CH16_ENA 14 EVENTLOG1_CH15_ENA 13 EVENTLOG1_CH14_ENA 12 EVENTLOG1_CH13_ENA 11 EVENTLOG1_CH12_ENA 10 EVENTLOG1_CH11_ENA 9 EVENTLOG1_CH10_ENA 8 EVENTLOG1_CH9_ENA 7 EVENTLOG1_CH8_ENA 6 EVENTLOG1_CH7_ENA 5 EVENTLOG1_CH6_ENA 4 EVENTLOG1_CH5_ENA 3 EVENTLOG1_CH4_ENA 2 EVENTLOG1_CH3_ENA 1 EVENTLOG1_CH2_ENA 0 EVENTLOG1_CH1_ENA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EVENTLOG1_CH16_STS EVENTLOG1_CH15_STS EVENTLOG1_CH14_STS EVENTLOG1_CH13_STS EVENTLOG1_CH12_STS EVENTLOG1_CH11_STS EVENTLOG1_CH10_STS EVENTLOG1_CH9_STS EVENTLOG1_CH8_STS EVENTLOG1_CH7_STS EVENTLOG1_CH6_STS EVENTLOG1_CH5_STS EVENTLOG1_CH4_STS EVENTLOG1_CH3_STS EVENTLOG1_CH2_STS EVENTLOG1_CH1_STS Default Description 0 Event Log Channel 16 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 15 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 14 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 13 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 12 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 11 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 10 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 9 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 8 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 7 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 6 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 5 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 4 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 3 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 2 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 1 Enable 0 = Disabled, 1 = Enabled 0 Event Log Channel 16 Status 0 Event Log Channel 15 Status 0 Event Log Channel 14 Status 0 Event Log Channel 13 Status 0 Event Log Channel 12 Status 0 Event Log Channel 11 Status 0 Event Log Channel 10 Status 0 Event Log Channel 9 Status 0 Event Log Channel 8 Status 0 Event Log Channel 7 Status 0 Event Log Channel 6 Status 0 Event Log Channel 5 Status 0 Event Log Channel 4 Status 0 Event Log Channel 3 Status 0 Event Log Channel 2 Status 0 Event Log Channel 1 Status 109 CS42L92 4.5 DSP Peripheral Control Table 4-37. Event Logger (EVENTLOG1) Control (Cont.) Register Address R294976 (0x4_8040) EVENTLOG1_CH1_DEFINE to R295006 (0x4_805E) EVENTLOG1_CH16_DEFINE R295040 (0x4_8080) EVENTLOG1_FIFO0_READ R295042 (0x4_8082) EVENTLOG1_FIFO0_TIME R295044 (0x4_8084) EVENTLOG1_FIFO1_READ R295046 (0x4_8086) EVENTLOG1_FIFO1_TIME R295048 (0x4_8088) EVENTLOG1_FIFO2_READ R295050 (0x4_808A) EVENTLOG1_FIFO2_TIME R295052 (0x4_808C) EVENTLOG1_FIFO3_READ R295054 (0x4_808E) EVENTLOG1_FIFO3_TIME R295056 (0x4_8090) EVENTLOG1_FIFO4_READ R295058 (0x4_8092) EVENTLOG1_FIFO4_TIME R295060 (0x4_8094) EVENTLOG1_FIFO5_READ R295062 (0x4_8096) EVENTLOG1_FIFO5_TIME R295064 (0x4_8098) EVENTLOG1_FIFO6_READ R295066 (0x4_809A) EVENTLOG1_FIFO6_TIME R295068 (0x4_809C) EVENTLOG1_FIFO7_READ R295070 (0x4_809E) EVENTLOG1_FIFO7_TIME R295072 (0x4_80A0) EVENTLOG1_FIFO8_READ 110 Bit 15 Label EVENTLOG1_CHn_DB 14 EVENTLOG1_CHn_POL 13 EVENTLOG1_CHn_FILT 9:0 EVENTLOG1_CHn_SEL[9:0] 12 EVENTLOG1_FIFO0_POL 9:0 EVENTLOG1_FIFO0_ID[9:0] 31:0 EVENTLOG1_FIFO0_ TIME[31:0] 12 EVENTLOG1_FIFO1_POL 9:0 EVENTLOG1_FIFO1_ID[9:0] 31:0 EVENTLOG1_FIFO1_ TIME[31:0] 12 EVENTLOG1_FIFO2_POL 9:0 EVENTLOG1_FIFO2_ID[9:0] 31:0 EVENTLOG1_FIFO2_ TIME[31:0] 12 EVENTLOG1_FIFO3_POL 9:0 EVENTLOG1_FIFO3_ID[9:0] 31:0 EVENTLOG1_FIFO3_ TIME[31:0] 12 EVENTLOG1_FIFO4_POL 9:0 EVENTLOG1_FIFO4_ID[9:0] 31:0 EVENTLOG1_FIFO4_ TIME[31:0] 12 EVENTLOG1_FIFO5_POL 9:0 EVENTLOG1_FIFO5_ID[9:0] 31:0 EVENTLOG1_FIFO5_ TIME[31:0] 12 EVENTLOG1_FIFO6_POL 9:0 EVENTLOG1_FIFO6_ID[9:0] 31:0 EVENTLOG1_FIFO6_ TIME[31:0] 12 EVENTLOG1_FIFO7_POL 9:0 EVENTLOG1_FIFO7_ID[9:0] 31:0 EVENTLOG1_FIFO7_ TIME[31:0] 12 EVENTLOG1_FIFO8_POL 9:0 EVENTLOG1_FIFO8_ID[9:0] Default Description 0 Event Log Channel n debounce 0 = Disabled, 1 = Enabled Note that channel must be disabled when updating this field. 0 Event Log Channel n polarity 0 = Rising edge triggered, 1 = Falling edge triggered Note that channel must be disabled when updating this field. 0 Event Log Channel n filter 0 = Disabled, 1 = Enabled If the filter is enabled, the channel is ignored if the FIFO contains unread events of the same source/polarity. Note that channel must be disabled when updating this field. 0x000 Event Log Channel n source 1 Note that channel must be disabled when updating this field. 0 Event Log FIFO Index 0 polarity 0 = Rising edge, 1 = Falling edge 0x000 Event Log FIFO Index 0 source 1 0x0000 Event Log FIFO Index 0 Time _0000 0 Event Log FIFO Index 1 polarity 0 = Rising edge, 1 = Falling edge 0x000 Event Log FIFO Index 1 source 1 0x0000 Event Log FIFO Index 1 Time _0000 0 Event Log FIFO Index 2 polarity 0 = Rising edge, 1 = Falling edge 0x000 Event Log FIFO Index 2 source 1 0x0000 Event Log FIFO Index 2 Time _0000 0 Event Log FIFO Index 3 polarity 0 = Rising edge, 1 = Falling edge 0x000 Event Log FIFO Index 3 source 1 0x0000 Event Log FIFO Index 3 Time _0000 0 Event Log FIFO Index 4 polarity 0 = Rising edge, 1 = Falling edge 0x000 Event Log FIFO Index 4 source 1 0x0000 Event Log FIFO Index 4 Time _0000 0 Event Log FIFO Index 5 polarity Field description is as above. 0x000 Event Log FIFO Index 5 source 1 0x0000 Event Log FIFO Index 5 Time _0000 0 Event Log FIFO Index 6 polarity 0 = Rising edge, 1 = Falling edge 0x000 Event Log FIFO Index 6 source 1 0x0000 Event Log FIFO Index 6 Time _0000 0 Event Log FIFO Index 7 polarity 0 = Rising edge, 1 = Falling edge 0x000 Event Log FIFO Index 7 source 1 0x0000 Event Log FIFO Index 7 Time _0000 0 Event Log FIFO Index 8 polarity 0 = Rising edge, 1 = Falling edge 0x000 Event Log FIFO Index 8 source 1 DS1162F1 CS42L92 4.5 DSP Peripheral Control Table 4-37. Event Logger (EVENTLOG1) Control (Cont.) Register Address R295074 (0x4_80A2) EVENTLOG1_FIFO8_TIME R295076 (0x4_80A4) EVENTLOG1_FIFO9_READ Bit Label 31:0 EVENTLOG1_FIFO8_ TIME[31:0] 12 EVENTLOG1_FIFO9_POL Default Description 0x0000 Event Log FIFO Index 8 Time _0000 0 Event Log FIFO Index 9 polarity 0 = Rising edge, 1 = Falling edge 0x000 Event Log FIFO Index 9 source 1 0x0000 Event Log FIFO Index 9 Time _0000 9:0 EVENTLOG1_FIFO9_ID[9:0] R295078 (0x4_80A6) 31:0 EVENTLOG1_FIFO9_ TIME[31:0] EVENTLOG1_FIFO9_TIME R295080 (0x4_80A8) 12 EVENTLOG1_FIFO10_POL 0 Event Log FIFO Index 10 polarity EVENTLOG1_FIFO10_READ 0 = Rising edge, 1 = Falling edge 9:0 EVENTLOG1_FIFO10_ID[9:0] 0x000 Event Log FIFO Index 10 source 1 R295082 (0x4_80AA) 31:0 EVENTLOG1_FIFO10_ 0x0000 Event Log FIFO Index 10 Time TIME[31:0] _0000 EVENTLOG1_FIFO10_TIME R295084 (0x4_80AC) EVENTLOG1_FIFO11_READ R295086 (0x4_80AE) EVENTLOG1_FIFO11_TIME R295088 (0x4_80B0) EVENTLOG1_FIFO12_READ R295090 (0x4_80B2) EVENTLOG1_FIFO12_TIME R295092 (0x4_80B4) EVENTLOG1_FIFO13_READ R295094 (0x4_80B6) EVENTLOG1_FIFO13_TIME R295096 (0x4_80B8) EVENTLOG1_FIFO14_READ R295098 (0x4_80BA) EVENTLOG1_FIFO14_TIME R295100 (0x4_80BC) EVENTLOG1_FIFO15_READ R295102 (0x4_80BE) EVENTLOG1_FIFO15_TIME 12 EVENTLOG1_FIFO11_POL 0 Event Log FIFO Index 11 polarity 0 = Rising edge, 1 = Falling edge 9:0 EVENTLOG1_FIFO11_ID[9:0] 0x000 Event Log FIFO Index 11 source 1 31:0 EVENTLOG1_FIFO11_ 0x0000 Event Log FIFO Index 11 Time TIME[31:0] _0000 12 EVENTLOG1_FIFO12_POL 0 12 EVENTLOG1_FIFO13_POL 0 12 EVENTLOG1_FIFO14_POL 0 12 EVENTLOG1_FIFO15_POL 0 Event Log FIFO Index 12 polarity 0 = Rising edge, 1 = Falling edge 9:0 EVENTLOG1_FIFO12_ID[9:0] 0x000 Event Log FIFO Index 12 source 1 31:0 EVENTLOG1_FIFO12_ 0x0000 Event Log FIFO Index 12 Time TIME[31:0] _0000 Event Log FIFO Index 13 polarity 0 = Rising edge, 1 = Falling edge 9:0 EVENTLOG1_FIFO13_ID[9:0] 0x000 Event Log FIFO Index 13 source 1 31:0 EVENTLOG1_FIFO13_ 0x0000 Event Log FIFO Index 13 Time TIME[31:0] _0000 Event Log FIFO Index 14 polarity 0 = Rising edge, 1 = Falling edge 9:0 EVENTLOG1_FIFO14_ID[9:0] 0x000 Event Log FIFO Index 14 source 1 31:0 EVENTLOG1_FIFO14_ 0x0000 Event Log FIFO Index 14 Time TIME[31:0] _0000 Event Log FIFO Index 15 polarity 0 = Rising edge, 1 = Falling edge 9:0 EVENTLOG1_FIFO15_ID[9:0] 0x000 Event Log FIFO Index 15 source 1 31:0 EVENTLOG1_FIFO15_ 0x0000 Event Log FIFO Index 15 Time TIME[31:0] _0000 1.See Table 4-38 for valid channel source selections 4.5.1.8 Event Logger Input Sources A list of the valid input sources for the event logger is provided in Table 4-38. The EDGE type noted is coded as S (single edge) or D (dual edge). Note that a single-edge input source only provides valid input to the event logger in the default (rising edge triggered) polarity. Take care when enabling IRQ1 or IRQ2 as an input source for the event logger; a recursive loop, where the IRQn signal is also an output from the event logger, must be avoided. Table 4-38. Event Logger Input Sources ID 3 4 9 24 25 Description irq1 irq2 sysclk_fail fll1_lock fll2_lock DS1162F1 Edge D D S D D ID 137 160 161 162 163 Description asrc1_in2_lock dsp_irq1 dsp_irq2 dsp_irq3 dsp_irq4 Edge D S S S S ID 258 259 260 261 262 Description gpio3 gpio4 gpio5 gpio6 gpio7 Edge D D D D D 111 CS42L92 4.5 DSP Peripheral Control Table 4-38. Event Logger Input Sources (Cont.) ID 28 29 30 32 33 34 40 41 80 88 89 96 97 98 99 100 101 104 105 128 129 130 136 Description sysclk_err asyncclk_err dspclk_err frame_start_g1r1 frame_start_g1r2 frame_start_g1r3 frame_start_g2r1_sys frame_start_g2r2_sys hpdet micdet1 micdet2 jd1_rise jd1_fall jd2_rise jd2_fall micd_clamp_rise micd_clamp_fall jd3_rise jd3_fall drc1_sig_det drc2_sig_det inputs_sig_det asrc1_in1_lock 4.5.2 Edge D D D S S S S S S S S S S S S S S S S D D D D ID 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 184 185 236 256 257 Description dsp_irq5 dsp_irq6 dsp_irq7 dsp_irq8 dsp_irq9 dsp_irq10 dsp_irq11 dsp_irq12 dsp_irq13 dsp_irq14 dsp_irq15 dsp_irq16 hp1l_sc hp1r_sc hp2l_sc hp2r_sc hp3l_sc hp3r_sc hp4l_sc hp4r_sc dfc_saturate gpio1 gpio2 Edge S S S S S S S S S S S S S S S S S S S S S D D ID 263 264 265 266 267 268 269 270 271 320 336 352 368 384 416 432 448 464 512 560 561 562 563 Description gpio8 gpio9 gpio10 gpio11 gpio12 gpio13 gpio14 gpio15 gpio16 Timer1 event1_not_empty event1_full event1_wmark dsp1_dma dsp1_start1 dsp1_start2 dsp1_start dsp1_busy dsp1_bus_err alarm1_ch1 alarm1_ch2 alarm1_ch3 alarm1_ch4 Edge D D D D D D D D D S S S S S S S S D S S S S S Alarm Generators The CS42L92 provides four alarm-generator circuits are associated with the general-purpose timer. These can be used to generate interrupt events according to the count value of the timer. The alarm interrupts can be either one-off events, or can be configured for cyclic (repeated) triggers. 4.5.2.1 Alarm Control The alarm is enabled by writing 1 to the ALM1_CHn_START bit (where n identifies the respective alarm, 1–4). The alarm is disabled by writing 1 to ALM1_CHn_STOP. The operating mode of each alarm is configured using ALM1_CHn_TRIG_MODE. In each mode, the alarm events are controlled by the alarm-trigger value, ALM1_CHn_TRIG_VAL. • In Absolute Mode, the alarm output is triggered when the timer count value is equal to the alarm trigger value. • In Relative Mode, the alarm output is triggered when the timer count value has incremented by a number equal to the alarm trigger value—this mode counts the number of clock cycles after the ALM1_CHn_START bit is written. • In Combination Mode, the alarm output is initially triggered as described for the Absolute Mode; the alarm then operates as described for the Relative Mode. When the alarm output is triggered, an output signal is asserted for the respective alarm. The output is asserted for a duration that is configured using ALM1_CHn_PULSE_DUR. The resulting signal can be output directly on a GPIO pin. If an alarm is enabled and an update is written to ALM1_CHn_TRIG_VAL or ALM1_CHn_PULSE_DUR, the new value is loaded into the respective control register, but does not reconfigure the alarm immediately. If the ALM1_CHn_UPD bit is set, the alarm-trigger and pulse-duration values are updated when the alarm is next triggered. The alarm-trigger and pulse-duration settings can also be updated by writing 1 to ALM1_CHn_START. Note that, if an alarm is enabled, the general-purpose timer must be configured for continuous, count-up operation. The TIMER1_MAX_COUNT value must be greater than the respective ALM1_CHn_TRIG_VAL setting. 112 DS1162F1 CS42L92 4.5 DSP Peripheral Control 4.5.2.2 Interrupts and GPIO Output The alarm generators provide input to the interrupt control circuit and can be used to trigger an interrupt event when the alarm-trigger conditions are met. An interrupt event is triggered on the rising edge of the alarm output signal. The alarm output status bits, TIMER_ALM1_CHn_STSx, are asserted for a duration that is configured using ALM1_CHn_ PULSE_DUR. Note that the TIMER_ALM1_CHn_STS1 and TIMER_ALM1_CHn_STS2 bits provide the same information. See Section 4.15 for details of the CS42L92 interrupt controller. The alarm status can be output directly on a GPIO pin as an external indication of the alarm events. See Section 4.14 to configure a GPIO pin for this function. 4.5.2.3 Alarm Control Registers The alarm control registers are described in Table 4-39. Table 4-39. Alarm (ALM1) Control Register Address R303104 (0x4A000) ALM1_CFG R303120 (0x4A010) ALM1_CONFIG1 R303122 (0x4A012) ALM1_CTRL1 R303124 (0x4A014) ALM1_TRIG_VAL1 R303126 (0x4A016) ALM1_PULSE_DUR1 R303128 (0x4A018) ALM1_STATUS1 DS1162F1 Bit 0 Label ALM1_TIMER_ SEL Default Description 0 Alarm block ALM1 timer source select 0 = Timer 1 All other codes are reserved. All ALM1 channels must be disabled when updating this register. 4 ALM1_CH1_ 0 Channel 1 continuous mode select CONT 0 = Single mode 1 = Continuous mode Channel 1 must be disabled (ALM1_CH1_STS = 0) when updating this field. 1:0 ALM1_CH1_ 00 Channel 1 trigger mode select TRIG_MODE[1:0] 00 = Absolute Mode: Alarm is triggered when the count value of the timer source is equal to ALM1_CH1_TRIG_VAL. 01 = Relative Mode: Alarm is triggered when the count value has incremented by a number equal to ALM1_CH1_TRIG_VAL. 10 = Combination Mode: Alarm is initially triggered as described for Absolute Mode; the alarm then operates as described for Relative Mode. 11 = Reserved Channel 1 must be disabled (ALM1_CH1_STS = 0) when updating this field. 15 ALM1_CH1_UPD 0 Channel 1 update control—Write 1 to indicate a new trigger value or pulse duration is ready to be applied. If Channel 1 is enabled and ALM1_CH1_UPD is set, the ALM1_CH1_TRIG_VAL and ALM1_CH1_PULSE_DUR settings are updated when the alarm is next triggered or by writing 1 to ALM1_CH1_START. If Channel 1 is disabled, the ALM1_CH1_UPD bit has no effect, and the ALM1_ CH1_TRIG_VAL and ALM1_CH1_PULSE_DUR settings are updated immediately when writing to the respective fields. 4 ALM1_CH1_ — Channel 1 stop control—Write 1 to disable Channel 1 STOP 0 ALM1_CH1_ — Channel 1 start control—Write 1 to enable or restart Channel 1 START 31:0 ALM1_CH1_ 0x0000 Channel 1 alarm trigger value TRIG_VAL[31:0] _0000 31:0 ALM1_CH1_ 0x0000 Channel 1 alarm output pulse duration PULSE_ _0000 The pulse duration is referenced to the count rate of the selected timer source DUR[31:0] 0 ALM1_CH1_STS 0 Channel 1 status 0 = Disabled 1 = Enabled 113 CS42L92 4.5 DSP Peripheral Control Table 4-39. Alarm (ALM1) Control (Cont.) Register Address R303136 (0x4A020) ALM1_CONFIG2 R303138 (0x4A022) ALM1_CTRL2 R303140 (0x4A024) ALM1_TRIG_VAL2 R303142 (0x4A026) ALM1_PULSE_DUR2 R303144 (0x4A028) ALM1_STATUS2 R303152 (0x4A030) ALM1_CONFIG3 R303154 (0x4A032) ALM1_CTRL3 R303156 (0x4A034) ALM1_TRIG_VAL3 114 Bit 4 Label ALM1_CH2_ CONT Default Description 0 Channel 2 continuous mode select 0 = Single mode 1 = Continuous mode Channel 2 must be disabled (ALM1_CH2_STS = 0) when updating this field. 1:0 ALM1_CH2_ 00 Channel 2 trigger mode select TRIG_MODE[1:0] 00 = Absolute Mode: Alarm is triggered when the count value of the timer source is equal to ALM1_CH2_TRIG_VAL. 01 = Relative Mode: Alarm is triggered when the count value has incremented by a number equal to ALM1_CH2_TRIG_VAL. 10 = Combination Mode: Alarm is initially triggered as described for Absolute Mode; the alarm then operates as described for Relative Mode. 11 = Reserved Channel 2 must be disabled (ALM1_CH2_STS = 0) when updating this field. 15 ALM1_CH2_UPD 0 Channel 2 update control—Write 1 to indicate a new trigger value or pulse duration is ready to be applied. If Channel 2 is enabled and ALM1_CH2_UPD is set, the ALM1_CH2_TRIG_VAL and ALM1_CH2_PULSE_DUR settings are updated when the alarm is next triggered or by writing 1 to ALM1_CH2_START. If Channel 2 is disabled, the ALM1_CH2_UPD bit has no effect, and the ALM1_ CH2_TRIG_VAL and ALM1_CH2_PULSE_DUR settings are updated immediately when writing to the respective fields. 4 ALM1_CH2_ — Channel 2 stop control—Write 1 to disable Channel 2 STOP 0 ALM1_CH2_ — Channel 2 start control—Write 1 to enable or restart Channel 2 START 31:0 ALM1_CH2_ 0x0000 Channel 2 alarm trigger value TRIG_VAL[31:0] _0000 31:0 ALM1_CH2_ 0x0000 Channel 2 alarm output pulse duration PULSE_ _0000 The pulse duration is referenced to the count rate of the selected timer source DUR[31:0] 0 ALM1_CH2_STS 0 Channel 2 status 0 = Disabled 1 = Enabled 4 ALM1_CH3_ 0 Channel 3 continuous mode select CONT 0 = Single mode 1 = Continuous mode Channel 3 must be disabled (ALM1_CH3_STS = 0) when updating this field. 1:0 ALM1_CH3_ 00 Channel 3 trigger mode select TRIG_MODE[1:0] 00 = Absolute Mode: Alarm is triggered when the count value of the timer source is equal to ALM1_CH3_TRIG_VAL. 01 = Relative Mode: Alarm is triggered when the count value has incremented by a number equal to ALM1_CH3_TRIG_VAL. 10 = Combination Mode: Alarm is initially triggered as described for Absolute Mode; the alarm then operates as described for Relative Mode. 11 = Reserved Channel 3 must be disabled (ALM1_CH3_STS = 0) when updating this field. 15 ALM1_CH3_UPD 0 Channel 3 update control—Write 1 to indicate a new trigger value or pulse duration is ready to be applied. If Channel 3 is enabled and ALM1_CH3_UPD is set, the ALM1_CH3_TRIG_VAL and ALM1_CH3_PULSE_DUR settings are updated when the alarm is next triggered or by writing 1 to ALM1_CH3_START. If Channel 3 is disabled, the ALM1_CH3_UPD bit has no effect, and the ALM1_ CH3_TRIG_VAL and ALM1_CH3_PULSE_DUR settings are updated immediately when writing to the respective fields. 4 ALM1_CH3_ — Channel 3 stop control—Write 1 to disable Channel 3 STOP 0 ALM1_CH3_ — Channel 3 start control—Write 1 to enable or restart Channel 3 START 31:0 ALM1_CH3_ 0x0000 Channel 3 alarm trigger value TRIG_VAL[31:0] _0000 DS1162F1 CS42L92 4.5 DSP Peripheral Control Table 4-39. Alarm (ALM1) Control (Cont.) Register Address R303158 (0x4A036) ALM1_PULSE_DUR3 R303160 (0x4A038) ALM1_STATUS3 R303168 (0x4A040) ALM1_CONFIG4 R303170 (0x4A042) ALM1_CTRL4 R303172 (0x4A044) ALM1_TRIG_VAL4 R303174 (0x4A046) ALM1_PULSE_DUR4 R303176 (0x4A048) ALM1_STATUS4 4.5.3 Bit Label Default Description 31:0 ALM1_CH3_ 0x0000 Channel 3 alarm output pulse duration PULSE_ _0000 The pulse duration is referenced to the count rate of the selected timer source DUR[31:0] 0 ALM1_CH3_STS 0 Channel 3 status 0 = Disabled 1 = Enabled 4 ALM1_CH4_ 0 Channel 4 continuous mode select CONT 0 = Single mode 1 = Continuous mode Channel 4 must be disabled (ALM1_CH4_STS = 0) when updating this field. 1:0 ALM1_CH4_ 00 Channel 4 trigger mode select TRIG_MODE[1:0] 00 = Absolute Mode: Alarm is triggered when the count value of the timer source is equal to ALM1_CH4_TRIG_VAL. 01 = Relative Mode: Alarm is triggered when the count value has incremented by a number equal to ALM1_CH4_TRIG_VAL. 10 = Combination Mode: Alarm is initially triggered as described for Absolute Mode; the alarm then operates as described for Relative Mode. 11 = Reserved Channel 4 must be disabled (ALM1_CH4_STS = 0) when updating this field. 15 ALM1_CH4_UPD 0 Channel 4 update control—Write 1 to indicate a new trigger value or pulse duration is ready to be applied. If Channel 4 is enabled and ALM1_CH4_UPD is set, the ALM1_CH4_TRIG_VAL and ALM1_CH4_PULSE_DUR settings are updated when the alarm is next triggered or by writing 1 to ALM1_CH4_START. If Channel 4 is disabled, the ALM1_CH4_UPD bit has no effect, and the ALM1_ CH4_TRIG_VAL and ALM1_CH4_PULSE_DUR settings are updated immediately when writing to the respective fields. 4 ALM1_CH4_ — Channel 4 stop control—Write 1 to disable Channel 4 STOP 0 ALM1_CH4_ — Channel 4 start control—Write 1 to enable or restart Channel 4 START 31:0 ALM1_CH4_ 0x0000 Channel 4 alarm trigger value TRIG_VAL[31:0] _0000 31:0 ALM1_CH4_ 0x0000 Channel 4 alarm output pulse duration PULSE_ _0000 The pulse duration is referenced to the count rate of the selected timer source DUR[31:0] 0 ALM1_CH4_STS 0 Channel 4 status 0 = Disabled 1 = Enabled General-Purpose Timer The CS42L92 incorporates a general-purpose timer, which supports a wide variety of uses. The general-purpose timer provides time-stamp data for the event logger; it also supports the watchdog and other miscellaneous time-based functions, providing additional capability for signal-processing applications. 4.5.3.1 Overview The timer allows time-stamp information to be associated with external signal detection, and other system events, enabling real-time data to be more easily integrated into user applications. The timer allows many advanced functions to be implemented with a high degree of autonomy from a host processor. The timer can use either internal system clocks, or external clock signals, as a reference. The selected reference is scaled down, using configurable dividers, to the required clock count frequency. 4.5.3.2 Timer Control The reference clock for the timer is selected using TIMER1_REFCLK_SRC. DS1162F1 115 CS42L92 4.5 DSP Peripheral Control If SYSCLK, ASYNCCLK, or DSPCLK is selected, a lower clock frequency, derived from the applicable system clock, can be selected using the TIMER1_REFCLK_FREQ_SEL field (for SYSCLK or ASYNCCLK source) or the TIMER1_ DSPCLK_FREQ_SEL field (for DSPCLK source). The applicable division ratio is determined automatically, assuming the respective clock source has been correctly configured as described in Section 4.16. Note that, depending on the DSPCLK frequency and the available clock dividers, the timer reference clock may differ from the selected clock if DSPCLK is the selected source. In most cases, the reference clock frequency equals or exceeds the requested frequency. A lower frequency is implemented if limited by either the DSPCLK frequency or the maximum TIMER1 clocking frequency. If any source other than DSPCLK is selected, the clock can be further divided using TIMER1_REFCLK_DIV. Division ratios in the range 1 to 128 can be selected. Note that, if DSPCLK is enabled, the CS42L92 synchronizes the selected reference clock to DSPCLK. As a result of this, if a non-DSPCLK is selected as source, the following additional constraints must be observed: the reference clock frequency (after TIMER1_REFCLK_FREQ_SEL and after TIMER1_REFCLK_DIV) must be less than DSPCLK / 3, and must be less than 12 MHz; it must also be close to 50% duty cycle. The TIMER1_REFCLK_DIV field can be used to ensure that these criteria are met. One final division, controlled by TIMER1_PRESCALE, determines the timer count frequency. This field is valid for all clock reference sources; division ratios in the range 1 to 128 can be selected. The output from this division corresponds to the frequency at which the TIMER1_COUNT field is incremented (or decremented). The maximum count value of the timer is determined by the TIMER1_MAX_COUNT field. This is the final count value (when counting up), or the initial count value (when counting down). The current value of the timer counter can be read from the TIMER1_CUR_COUNT field. The timer is started by writing 1 to TIMER1_START. Note that, if the timer is already running, it restarts from its initial value. The timer is stopped by writing 1 to TIMER1_STOP. The count direction (up or down) is selected using the TIMER1_DIR bit. The TIMER1_CONTINUOUS bit selects whether the timer automatically restarts after the end-of-count condition has been reached. The TIMER1_RUNNING_STS indicates whether the timer is running, or if it has stopped. Note that the timer should be stopped before making any changes to the timer control registers. The timer configuration should only be changed if TIMER1_RUNNING_STS = 0. 4.5.3.3 Interrupts and GPIO Output The timer status is an input to the interrupt control circuit and can be used to trigger an interrupt event after the final count value is reached; see Section 4.15. Note that the interrupt does not occur immediately when the final count value is reached; the interrupt is triggered at the point when the next update to the timer count value would be due. The timer status can be output directly on a GPIO pin as an external indication of the timer activity. See Section 4.14 to configure a GPIO pin for this function. 116 DS1162F1 CS42L92 4.5 DSP Peripheral Control 4.5.3.4 Timer Block Diagram and Control Registers The timer block is shown in Fig. 4-35. DSPCLK 32k Clock MCLK1 MCLK2 SYSCLK ASYNCCLK GPIO1 GPIO2 GPIO3 GPIO4 TIMER1_REFCLK_SRC[3:0] p. 118 If DSPCLK is enabled, and a clock source other than DSPCLK is selected, f ≤ DSPCLK/3, f ≤ 12MHz Divider Divider TIMER1_REFCLK_FREQ_SEL[2:0] p. 118 TIMER1_REFCLK_DIV[2:0] p. 118 TIMER1_PRESCALE[2:0] p. 118 SYSCLK / ASYNCCLK only Divide by 1, 2, 4, 8 … 64 except DSPCLK Divide by 1, 2, 4, 8 … 128 TIMER1_DSPCLK_FREQ_SEL[15:0] p. 119 Divider f = TIMER count rate DSPCLK only Figure 4-35. General-Purpose Timer The timer control registers are described in Table 4-40. DS1162F1 117 CS42L92 4.5 DSP Peripheral Control Table 4-40. General-Purpose Timer (TIMER1) Control Register Address R311296 (0x4_C000) Timer1_Control Default Description 0 Timer Continuous Mode select 0 = Single mode 1 = Continuous mode Timer must be stopped (TIMER1_RUNNING_STS = 0) when updating this field 20 TIMER1_DIR 0 Timer Count Direction 0 = Down 1 = Up Timer must be stopped (TIMER1_RUNNING_STS = 0) when updating this field 18:16 TIMER1_ 000 Timer Count Rate Prescale PRESCALE[2:0] 000 = Divide by 1 011 = Divide by 8 110 = Divide by 64 001 = Divide by 2 100 = Divide by 16 111 = Divide by 128 010 = Divide by 4 101 = Divide by 32 Timer must be stopped (TIMER1_RUNNING_STS = 0) when updating this field 14:12 TIMER1_ 000 Timer Reference Clock Divide (Not valid for DSPCLK source). REFCLK_DIV[2:0] 000 = Divide by 1 011 = Divide by 8 110 = Divide by 64 001 = Divide by 2 100 = Divide by 16 111 = Divide by 128 010 = Divide by 4 101 = Divide by 32 If DSPCLK is enabled, and DSPCLK is not selected as source, the output frequency from this divider must be set less than or equal to DSPCLK / 3, and less than or equal to 12 MHz. If DSPCLK is disabled, the output of this divider is used as clock reference for the event logger. In this case, the divider output corresponds to the frequency of event logging opportunities on the respective modules. Timer must be stopped (TIMER1_RUNNING_STS = 0) when updating this field 10:8 TIMER1_ 000 Timer Reference Frequency Select (SYSCLK or ASYNCCLK source) REFCLK_FREQ_ 000 = 6.144 MHz (5.6448 MHz) 010 = 24.576 MHz (22.5792 MHz) SEL[2:0] 001 = 12.288 MHz (11.2896 MHz) 011 = 49.152 MHz (45.1584 MHz) All other codes are reserved. The selected frequency must be less than or equal to the frequency of the source. Timer must be stopped (TIMER1_RUNNING_STS = 0) when updating this field. 3:0 TIMER1_ 0000 Timer Reference Source Select. REFCLK_ Timer must be stopped (TIMER1_RUNNING_STS=0) when updating this field. SRC[3:0] 1110 = GPIO3 1000 = SYSCLK 0000 = DSPCLK 1111 = GPIO4 1001 = ASYNCCLK 0001 = 32-kHz clock All other codes are 1100 = GPIO1 0100 = MCLK1 reserved. 1101 = GPIO2 0101 = MCLK2 R311298 (0x4_C002) 31:0 TIMER1_MAX_ 0x0000 Timer Maximum Count. COUNT[31:0] _0000 Final count value (when counting up). Starting count value (when counting down). Timer1_Count_Preset Timer must be stopped (TIMER1_RUNNING_STS = 0) when updating this field. R311302 (0x4_C006) 4 TIMER1_STOP 0 Timer Stop Control Timer1_Start_and_ Write 1 to stop. Stop 0 TIMER1_START 0 Timer Start Control Write 1 to start. If the timer is already running, it restarts from its initial value. 0 Timer Running Status R311304 (0x4_C008) 0 TIMER1_ RUNNING_STS 0 = Timer stopped Timer1_Status 1 = Timer running 118 Bit 21 Label TIMER1_ CONTINUOUS DS1162F1 CS42L92 4.5 DSP Peripheral Control Table 4-40. General-Purpose Timer (TIMER1) Control (Cont.) Register Address R311306 (0x4_C00A) Timer1_Count_ Readback R311308 (0x4_C00C) Timer1_DSP_Clock_ Config R311310 (0x4_C00E) Timer1_DSP_Clock_ Status 4.5.4 Bit Label 31:0 TIMER1_CUR_ COUNT[31:0] Default 0x0000 Timer Current Count value Description 15:0 TIMER1_ 0x0000 Timer Reference Frequency Select (DSPCLK source) DSPCLK_FREQ_ Coded as LSB = 1/64 MHz, Valid from 5.6 MHz to 148 MHz. SEL[15:0] The timer reference frequency must be less than or equal to the DSPCLK frequency. The timer reference is generated by division of DSPCLK, and may differ from the selected frequency. The timer reference frequency can be read from TIMER1_DSPCLK_FREQ_STS. Timer must be stopped (TIMER1_RUNNING_STS=0) when updating this field. 15:0 TIMER1_ 0x0000 Timer Reference Frequency (Read only) DSPCLK_FREQ_ Only valid when DSPCLK is the selected clock source. STS[15:0] Coded as LSB = 1/64 MHz. DSP GPIO The DSP GPIO function provides an advanced I/O capability, supporting enhanced flexibility for signal-processing applications. 4.5.4.1 Overview The CS42L92 supports up to 16 GPIO pins, which can be assigned to application-specific functions. There are 2 dedicated GPIO pins; the remaining 14 GPIOs are implemented as alternate functions to a pin-specific capability. The GPIOs can be used to provide status outputs and control signals to external hardware; the supported functions include interrupt output, FLL clock output, accessory detection status, and S/PDIF or PWM-coded audio channels; see Section 4.14. The GPIOs can support miscellaneous logic input and output, interfacing directly with the integrated DSPs, or with the host application software. A basic level of I/O functionality is described in Section 4.14, under the configuration where GPn_ FN = 0x001. The GPn_FN field selects the functionality for the respective pin, GPIOn. The DSP GPIO pins are accessed using maskable sets of I/O control registers; this allows the selected combinations of GPIOs to be controlled with ease, regardless of how the allocation of GPIO pins has been implemented in hardware. In a typical use case, one GPIO mask is defined for each DSP function; this provides a highly efficient mechanism for the DSP to independently access the respective input and output signals. 4.5.4.2 DSP GPIO Control The DSP GPIO function is selected by setting GPn_FN = 0x002 for the respective GPIO pin (where n identifies the applicable GPIOn pin). Each DSP GPIO is controlled using bits that determine the direction (input/output) and the logic state (0/1) of the pin. These bits are replicated in eight control sets; each which can determine the logic level of any DSP GPIO. Mask bits are provided within each control set, to determine which of the control sets has control of each DSP GPIO. To avoid logic contention, a DSP GPIO output must be controlled (unmasked) in a maximum of one control set at any time. Note that write access to the direction control bits (DSPGPn_SETx_DIR) and level control bits (DSPGPn_SETx_LVL) is only valid when the channel (DSPGPn) is unmasked in the respective control set. Writes to these fields are implemented for the unmasked DSP GPIOs, and are ignored in respect of the masked DSP GPIOs. Note that the level control bits (DSPGPn_SETx_LVL) provide output level control only—they cannot be used to read the status of DSP GPIO inputs. The logic level of the unmasked DSP GPIO outputs in any control set can be configured using a single register write. Writing to the output level control registers determines the logic level of the unmasked DSP GPIOs in that set only; all other outputs are unaffected. DS1162F1 119 CS42L92 4.5 DSP Peripheral Control DSP GPIO status bits are provided, indicating the logic level of every input or output pin that is configured as a DSP GPIO. The DSPGPn_STS bits also provide logic-level indication for any pin that is configured as a GPIO input, with GPn_ FN = 0x001.Note that there is only one set of DSP GPIO status bits. The status bits indicate the logic level of the DSP GPIO outputs. The respective pins are driven as outputs if configured as a DSP GPIO output, and unmasked in one of the control sets. Note that a DSP GPIO continues to be driven as an output, even if the mask bit is subsequently asserted in that set. The pin only ceases to be driven if it is configured as a DSP GPIO input and is unmasked in one of the control sets, or if the pin is configured as an input under a different GPn_ FN field selection. 4.5.4.3 Common Functions to Standard GPIOs The DSP GPIO functions are implemented alongside the standard GPIO capability, providing an alternative method of maskable I/O control for all of the GPIO pins. The DSP GPIO control bits in the register map are implemented in a manner that supports efficient read/write access for multiple GPIOs at once. The DSP GPIO logic is shown in Fig. 4-36, which also shows the control fields relating to the standard GPIO. The DSP GPIO function is selected by setting GPn_FN = 0x002 for the respective GPIO pin. Integrated pull-up and pull-down resistors are provided on each GPIO pin, which are also valid for DSP GPIO function. A bus keeper function is supported on the GPIO pins; this is enabled using the respective pull-up and pull-down control bits. The bus keeper function holds the logic level unchanged whenever the pin is undriven (e.g., if the signal is tristated). See Table 4-93 for details of the GPIO pull-up and pull-down control bits. 120 DS1162F1 CS42L92 4.5 DSP Peripheral Control 4.5.4.4 DSP GPIO Block Diagram and Control Registers Input / Output control Logic Level control DSPGPn_SET1_LVL DSPGPn_SET1_DIR Input / Output control Logic Level control DSPGPn_SET2_LVL DSPGPn_SET2_DIR Input / Output control Logic Level control DSPGPn_SET3_LVL DSPGPn_SET3_DIR Input / Output control Logic Level control DSPGPn_SET4_LVL DSPGPn_SET4_DIR Input / Output control Logic Level control DSPGPn_SET5_LVL DSPGPn_SET5_DIR Input / Output control Logic Level control DSPGPn_SET6_LVL DSPGPn_SET6_DIR Input / Output control Logic Level control DSPGPn_SET7_LVL DSPGPn_SET7_DIR Input / Output control Logic Level control DSPGPn_SET8_LVL DSPGPn_SET8_DIR Mask control DSPGPn_SET1_MASK Pin-Specific Function Mask control DSPGPn_SET2_MASK GPn_FN = 0x000 GPIO Control & Readback Mask control DSPGPn_SET3_MASK GPn_LVL p. 192 GPn_FN = 0x001 Mask control DSPGPn_SET4_MASK DSP GPIO Readback GPIOn GPn_FN = 0x002 DSPGPn_STS Mask control GPn_PU p. 193 GPn_PD p. 193 GPn_FN[9:0] p. 192 DSPGPn_SET5_MASK GPn_FN > 0x002 Other GPIO functions Mask control DSPGPn_SET6_MASK GPn_POL p. 192 GPn_OP_CFG p. 192 Mask control These bits have no effect if GPn_FN = 0x000 or 0x002. DSPGPn_SET7_MASK GPn_DB p. 192 Valid for GPn_LVL readback and GPIO IRQ event trigger only. GPn_DIR p. 193 Mask control DSPGPn_SET8_MASK These bits have no effect if GPn_FN = 0x000 or 0x002. If GPn_FN = 0x000, pin direction is set automatically . If GPn_FN = 0x002, pin direction is set by DSPGPn _SETx_DIR. Figure 4-36. DSP GPIO Control The control registers associated with the DSP GPIO are described in Table 4-41. DS1162F1 121 CS42L92 4.5 DSP Peripheral Control Table 4-41. DSP GPIO Control Register Address R315392 (0x4_D000) DSPGP_Status_1 R315424 (0x4_D020) DSPGP_SET1_Mask_1 R315456 (0x4_D040) DSPGP_SET2_Mask_1 R315488 (0x4_D060) DSPGP_SET3_Mask_1 R315520 (0x4_D080) DSPGP_SET4_Mask_1 R315552 (0x4_D0A0) DSPGP_SET5_Mask_1 R315584 (0x4_D0C0) DSPGP_SET6_Mask_1 R315616 (0x4_D0E0) DSPGP_SET7_Mask_1 R315648 (0x4_D100) DSPGP_SET8_Mask_1 R315432 (0x4_D028) DSPGP_SET1_Direction_1 R315464 (0x4_D048) DSPGP_SET2_Direction_1 R315496 (0x4_D068) DSPGP_SET3_Direction_1 R315528 (0x4_D088) DSPGP_SET4_Direction_1 R315560 (0x4_D0A8) DSPGP_SET5_Direction_1 R315592 (0x4_D0C8) DSPGP_SET6_Direction_1 R315624 (0x4_D0E8) DSPGP_SET7_Direction_1 R315656 (0x4_D108) DSPGP_SET8_Direction_1 122 Bit Label 15 DSPGP16_STS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 DSPGP15_STS DSPGP14_STS DSPGP13_STS DSPGP12_STS DSPGP11_STS DSPGP10_STS DSPGP9_STS DSPGP8_STS DSPGP7_STS DSPGP6_STS DSPGP5_STS DSPGP4_STS DSPGP3_STS DSPGP2_STS DSPGP1_STS DSPGP16_SETn_MASK 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 DSPGP15_SETn_MASK DSPGP14_SETn_MASK DSPGP13_SETn_MASK DSPGP12_SETn_MASK DSPGP11_SETn_MASK DSPGP10_SETn_MASK DSPGP9_SETn_MASK DSPGP8_SETn_MASK DSPGP7_SETn_MASK DSPGP6_SETn_MASK DSPGP5_SETn_MASK DSPGP4_SETn_MASK DSPGP3_SETn_MASK DSPGP2_SETn_MASK DSPGP1_SETn_MASK DSPGP16_SETn_DIR 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSPGP15_SETn_DIR DSPGP14_SETn_DIR DSPGP13_SETn_DIR DSPGP12_SETn_DIR DSPGP11_SETn_DIR DSPGP10_SETn_DIR DSPGP9_SETn_DIR DSPGP8_SETn_DIR DSPGP7_SETn_DIR DSPGP6_SETn_DIR DSPGP5_SETn_DIR DSPGP4_SETn_DIR DSPGP3_SETn_DIR DSPGP2_SETn_DIR DSPGP1_SETn_DIR Default Description 0 DSPGP16 Status Valid for DSPGP input and output 0 DSPGP15 Status 0 DSPGP14 Status 0 DSPGP13 Status 0 DSPGP12 Status 0 DSPGP11 Status 0 DSPGP10 Status 0 DSPGP9 Status 0 DSPGP8 Status 0 DSPGP7 Status 0 DSPGP6 Status 0 DSPGP5 Status 0 DSPGP4 Status 0 DSPGP3 Status 0 DSPGP2 Status 0 DSPGP1 Status 1 DSP SETn GPIO16 Mask Control 0 = Unmasked, 1 = Masked A GPIO pin should be unmasked in a maximum of one SET at any time. 1 DSP SETn GPIO15 Mask Control 1 DSP SETn GPIO14 Mask Control 1 DSP SETn GPIO13 Mask Control 1 DSP SETn GPIO12 Mask Control 1 DSP SETn GPIO11 Mask Control 1 DSP SETn GPIO10 Mask Control 1 DSP SETn GPIO9 Mask Control 1 DSP SETn GPIO8 Mask Control 1 DSP SETn GPIO7 Mask Control 1 DSP SETn GPIO6 Mask Control 1 DSP SETn GPIO5 Mask Control 1 DSP SETn GPIO4 Mask Control 1 DSP SETn GPIO3 Mask Control 1 DSP SETn GPIO2 Mask Control 1 DSP SETn GPIO1 Mask Control 1 DSP SETn GPIO16 Direction Control 0 = Output, 1 = Input 1 DSP SETn GPIO15 Direction Control 1 DSP SETn GPIO14 Direction Control 1 DSP SETn GPIO13 Direction Control 1 DSP SETn GPIO12 Direction Control 1 DSP SETn GPIO11 Direction Control 1 DSP SETn GPIO10 Direction Control 1 DSP SETn GPIO9 Direction Control 1 DSP SETn GPIO8 Direction Control 1 DSP SETn GPIO7 Direction Control 1 DSP SETn GPIO6 Direction Control 1 DSP SETn GPIO5 Direction Control 1 DSP SETn GPIO4 Direction Control 1 DSP SETn GPIO3 Direction Control 1 DSP SETn GPIO2 Direction Control 1 DSP SETn GPIO1 Direction Control DS1162F1 CS42L92 4.6 Digital Audio Interface Table 4-41. DSP GPIO Control (Cont.) Register Address R315440 (0x4_D030) DSPGP_SET1_Level_1 R315472 (0x4_D050) DSPGP_SET2_Level_1 R315504 (0x4_D070) DSPGP_SET3_Level_1 R315536 (0x4_D090) DSPGP_SET4_Level_1 R315568 (0x4_D0B0) DSPGP_SET5_Level_1 R315600 (0x4_D0D0) DSPGP_SET6_Level_1 R315632 (0x4_D0F0) DSPGP_SET7_Level_1 R315664 (0x4_D110) DSPGP_SET8_Level_1 Bit Label 15 DSPGP16_SETn_LVL 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSPGP15_SETn_LVL DSPGP14_SETn_LVL DSPGP13_SETn_LVL DSPGP12_SETn_LVL DSPGP11_SETn_LVL DSPGP10_SETn_LVL DSPGP9_SETn_LVL DSPGP8_SETn_LVL DSPGP7_SETn_LVL DSPGP6_SETn_LVL DSPGP5_SETn_LVL DSPGP4_SETn_LVL DSPGP3_SETn_LVL DSPGP2_SETn_LVL DSPGP1_SETn_LVL Default Description 0 DSP SETn GPIO16 Output Level 0 = Logic 0, 1 = Logic 1 0 DSP SETn GPIO15 Output Level 0 DSP SETn GPIO14 Output Level 0 DSP SETn GPIO13 Output Level 0 DSP SETn GPIO12 Output Level 0 DSP SETn GPIO11 Output Level 0 DSP SETn GPIO10 Output Level 0 DSP SETn GPIO9 Output Level 0 DSP SETn GPIO8 Output Level 0 DSP SETn GPIO7 Output Level 0 DSP SETn GPIO6 Output Level 0 DSP SETn GPIO5 Output Level 0 DSP SETn GPIO4 Output Level 0 DSP SETn GPIO3 Output Level 0 DSP SETn GPIO2 Output Level 0 DSP SETn GPIO1 Output Level 4.6 Digital Audio Interface The CS42L92 provides three audio interfaces, AIF1–AIF3. Each interface is independently configurable on the respective transmit (TX) and receive (RX) paths. Each AIF supports up to eight channels of input and output signal paths. The data sources for the audio interface transmit (TX) paths can be selected from any of the CS42L92 input signal paths, or from the digital-core processing functions. The audio interface receive (RX) paths can be selected as inputs to any of the digital-core processing functions or digital-core outputs. See Section 4.3 for details of the digital-core routing options. The digital audio interfaces provide flexible connectivity for multiple processors and other audio devices. Typical connections include applications processor, baseband processor, and wireless transceiver. Note that the SLIMbus interface also provides digital audio input/output paths, providing options for additional interfaces. A typical configuration is shown in Fig. 4-37. DS1162F1 123 CS42L92 4.6 Digital Audio Interface Applications Processor SLIMbus interface HDMI Device Audio Interface 1 Baseband Processor Audio Interface 2 Wireless Transceiver Audio Interface 3 CS42L92 Figure 4-37. Typical AIF Connections In the general case, the digital audio interface uses four pins: • TXDAT: data output • RXDAT: data input • BCLK: bit clock, for synchronization • LRCLK: left/right data-alignment clock In Master Mode, the clock signals BCLK and LRCLK are outputs from the CS42L92. In Slave Mode, these signals are inputs, as shown in Section 4.6.1. The following interface formats are supported on AIF1–AIF3: • DSP Mode A • DSP Mode B • I2S • Left-justified The left-justified and DSP-B formats are valid in Master Mode only (i.e., BCLK and LRCLK are outputs from the CS42L92). These modes cannot be supported in Slave Mode. The audio interface formats are described in Section 4.6.2. The bit order is MSB-first in each case. Mono PCM operation can be supported using the DSP modes. Refer to Table 3-16 through Table 3-18 for signal timing information. For typical applications, AIF data is encoded in 2’s complement (signed, fixed-point) format. This format is compatible with all of the digital mixing and signal-processing functions on the CS42L92. Other data types, including floating point formats, can be supported using the DFCs. Note that, if unsigned or floating point data is present within the digital core, some restrictions on the valid signal routing options apply—see Section 4.3.13. 124 DS1162F1 CS42L92 4.6 Digital Audio Interface 4.6.1 Master and Slave Mode Operation The CS42L92 digital audio interfaces can operate as a master or slave, as shown in Fig. 4-38 and Fig. 4-39. The associated control bits are described in Section 4.7. BCLK BCLK LRCLK CS42L92 TXDAT LRCLK Processor CS42L92 RXDAT Figure 4-38. Master Mode 4.6.2 TXDAT Processor RXDAT Figure 4-39. Slave Mode Audio Data Formats The CS42L92 digital audio interfaces can be configured to operate in I2S, left-justified, DSP-A, or DSP-B interface modes. Note that left-justified and DSP-B modes are valid in Master Mode only (i.e., BCLK and LRCLK are outputs from the CS42L92). The digital audio interfaces also provide flexibility to support multiple slots of audio data within each LRCLK frame. This flexibility allows multiple audio channels to be supported within a single LRCLK frame. The data formats described in this section are generic descriptions, assuming only one stereo pair of audio samples per LRCLK frame. In these cases, the AIF is configured to transmit (or receive) in the first available position in each frame (i.e., the Slot 0 position). The options for multichannel operation are described in Section 4.6.3. The audio data modes supported by the CS42L92 are described as follows. Note that the polarity of the BCLK and LRCLK signals can be inverted if required; the following descriptions all assume the default, noninverted polarity of these signals. • In DSP modes, the left channel MSB is available on either the first (Mode B) or second (Mode A) rising edge of BCLK following a rising edge of LRCLK. Right-channel data immediately follows left channel data. Depending on word length, BCLK frequency, and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In Master Mode, the LRCLK output resembles the frame pulse shown in Fig. 4-40 and Fig. 4-41. In Slave Mode, it is possible to use any length of frame pulse less than 1/Fs, providing the falling edge of the frame pulse occurs at least one BCLK period before the rising edge of the next frame pulse. PCM operation is supported in DSP interface mode. CS42L92 data that is output on the left channel is read as mono data by the receiving equipment. Mono PCM data received by the CS42L92 is treated as left-channel data. This may be routed to the left/right playback paths using the control fields described in Section 4.3. DS1162F1 125 CS42L92 4.6 Digital Audio Interface DSP Mode A data format is shown in Fig. 4-40. 1/Fs LRCLK In Slave Mode, the falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK LEFT CHANNEL RXDAT/ TXDAT 1 2 3 MSB RIGHT CHANNEL n-2 n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 4-40. DSP Mode A Data Format DSP Mode B data format is shown in Fig. 4-41. 1/Fs LRCLK In Slave Mode, the falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK LEFT CHANNEL RXDAT/ TXDAT 1 2 3 MSB n-2 RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 4-41. DSP Mode B Data Format • In I2S Mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency, and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. I2S Mode data format is shown in Fig. 4-42. 1/Fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK 1 BCLK RXDAT/ TXDAT 1 2 MSB 1 BCLK 3 n-2 n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 4-42. I2S Data Format (Assuming n-Bit Word Length) • In Left-Justified Mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency, and sample rate, there may be unused BCLK cycles before each LRCLK transition. Left-Justified Mode data format is shown in Fig. 4-43. 1/Fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK RXDAT/ TXDAT 1 MSB 2 3 n-2 n-1 Input Word Length (WL) n 1 2 3 n-2 n-1 n LSB Figure 4-43. Left-Justified Data Format (Assuming n-Bit Word Length) 126 DS1162F1 CS42L92 4.6 Digital Audio Interface 4.6.3 AIF Time-Slot Configuration Multichannel operation is supported on AIF1–AIF3, with up to eight channels of input and output on each. A high degree of flexibility is provided to define the position of the audio samples within each LRCLK frame; the audio channel samples may be arranged in any order within the frame. Note that, on each interface, all input and output channels must operate at the same sample rate (Fs). Each audio channel can be enabled or disabled independently on the transmit (TX) and receive (RX) signal paths. For each enabled channel, the audio samples are assigned to one time slot within the LRCLK frame. In DSP modes, the time slots are ordered consecutively from the start of the LRCLK frame. In I2S and left-justified modes, the even-numbered time slots are arranged in the first half of the LRCLK frame, and the odd-numbered time slots are arranged in the second half of the frame. The time slots are assigned independently for the transmit (TX) and receive (RX) signal paths. There is no requirement to assign every available time slot to an audio sample; slots may be left unused, if desired. Care is required, however, to ensure that no time slot is allocated to more than one audio channel. The number of BCLK cycles within a slot is configurable; this is the slot length. The number of valid data bits within a slot is also configurable; this is the word length. The number of BCLK cycles per LRCLK frame must be configured; it must be ensured that there are enough BCLK cycles within each LRCLK frame to transmit or receive all of the enabled audio channels. Examples of the AIF time-slot configurations are shown in Fig. 4-44 through Fig. 4-47. One example is shown for each of the four possible data formats. Fig. 4-44 shows an example of DSP Mode A format. Four enabled audio channels are shown, allocated to time slots 0 through 3. LRCLK BCLK TXDAT/ RXDAT Slot 0 Channel 1 Slot 0 AIF1[TX1/RX1]_SLOT = 0 Channel 2 Channel 3 Channel 4 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 ... Slot 1 AIF1[TX2/RX2]_SLOT = 1 Slot 2 AIF1[TX3/RX3]_SLOT = 2 Slot 3 AIF1[TX4/RX4]_SLOT = 3 Figure 4-44. DSP Mode A Example DS1162F1 127 CS42L92 4.6 Digital Audio Interface Fig. 4-45 shows an example of DSP Mode B format. Six enabled audio channels are shown, with time slots 4 and 5 unused. LRCLK BCLK TXDAT/ RXDAT Slot 0 Slot 1 Slot 2 Slot 4 Slot 5 Slot 6 Slot 7 ... Slot 2 AIF1[TX1/RX1]_SLOT = 2 Channel 1 Slot 3 AIF1[TX2/RX2]_SLOT = 3 Channel 2 Channel 3 Slot 3 Slot 0 AIF1[TX3/RX3]_SLOT = 0 Slot 1 AIF1[TX4/RX4]_SLOT = 1 Channel 4 Slot 6 AIF1[TX5/RX5]_SLOT = 6 Channel 5 Slot 7 AIF1[TX6/RX6]_SLOT = 7 Channel 6 Figure 4-45. DSP Mode B Example Fig. 4-46 shows an example of I2S format. Four enabled channels are shown, allocated to time slots 0 through 3. LRCLK BCLK TXDAT/ RXDAT Slot 0 Channel 1 Slot 0 AIF1[TX1/RX1]_SLOT = 0 Slot 2 Slot 4 ... Slot 1 Slot 3 Slot 5 ... Slot 1 AIF1[TX2/RX2]_SLOT = 1 Channel 2 Slot 2 AIF1[TX3/RX3]_SLOT = 2 Channel 3 Slot 3 AIF1[TX4/RX4]_SLOT = 3 Channel 4 Figure 4-46. I2S Example Fig. 4-47 shows an example of left-justified format. Six enabled channels are shown. LRCLK BCLK TXDAT/ RXDAT Slot 0 Slot 2 Slot 4 ... Slot 1 Slot 1 AIF1[TX3/RX3]_SLOT = 1 Slot 3 AIF1[TX4/RX4]_SLOT = 3 Channel 4 Channel 6 ... Slot 4 AIF1[TX2/RX2]_SLOT = 4 Channel 3 Channel 5 Slot 5 Slot 5 AIF1[TX1/RX1]_SLOT = 5 Channel 1 Channel 2 Slot 3 Slot 0 AIF1[TX5/RX5]_SLOT = 0 Slot 2 AIF1[TX6/RX6]_SLOT = 2 Figure 4-47. Left-Justified Example 128 DS1162F1 CS42L92 4.6 Digital Audio Interface 4.6.4 TDM Operation Between Three or More Devices The AIF operation described in Section 4.6.3 illustrates how multiple audio channels can be interleaved on a single TXDAT or RXDAT pin. The interface uses TDM to allocate time periods to each audio channel in turn. This form of TDM is implemented between two devices, using the electrical connections shown Fig. 4-38 or Fig. 4-39. It is also possible to implement TDM between three or more devices. This allows one codec to receive audio data from two other devices simultaneously on a single audio interface, as shown in Fig. 4-48, Fig. 4-49, and Fig. 4-50. The CS42L92 provides full support for TDM operation. The TXDAT pin can be tristated when not transmitting data, in order to allow other devices to transmit on the same wire. The behavior of the TXDAT pin is configurable, to allow maximum flexibility to interface with other devices in this way. Typical configurations of TDM operation between three devices are shown in Fig. 4-48, Fig. 4-49, and Fig. 4-50. BCLK BCLK CS42L92 CS42L92 or similar CODEC LRCLK LRCLK Processor TXDAT TXDAT RXDAT RXDAT BCLK LRCLK TXDAT RXDAT Figure 4-48. TDM with CS42L92 as Master DS1162F1 CS42L92 CS42L92 or similar CODEC Processor BCLK LRCLK TXDAT RXDAT Figure 4-49. TDM with Other Codec as Master 129 CS42L92 4.7 Digital Audio Interface Control BCLK CS42L92 LRCLK TXDAT Processor RXDAT CS42L92 or similar CODEC BCLK LRCLK TXDAT RXDAT Figure 4-50. TDM with Processor as Master 4.7 Digital Audio Interface Control This section describes the configuration of the CS42L92 digital audio interface paths. Each AIF supports up to eight input signal paths and up to eight output signal paths. The digital audio interfaces can be configured as master or slave interfaces; mixed master/slave configurations are also possible. Each input and output signal path can be independently enabled or disabled. The AIF output (TX) and AIF input (RX) paths use shared BCLK and LRCLK control signals. The digital audio interface supports flexible data formats, selectable word length, configurable time-slot allocations, and TDM tristate control. The AIF1 and AIF3 interfaces provide full support for 32-bit data words (input and output). Audio data samples up to 32 bits can be routed to the AIF1, AIF3, SLIMbus, S/PDIF, and DAC output paths. Note that other signal paths and signal-processing blocks within the digital core are limited to 24-bit data length; data samples are truncated to 24-bit length if they are routed through any function that does not support 32-bit data words. The audio interfaces can be reconfigured while enabled, including changes to the LRCLK frame length and the channel time-slot configurations. Care is required to ensure that any on-the-fly reconfiguration does not cause corruption to the active signal paths. Wherever possible, it is recommended to disable all channels before changing the AIF configuration. 4.7.1 AIF Sample-Rate Control The AIF RX inputs may be selected as input to the digital mixers or signal-processing functions within the CS42L92 digital core. The AIF TX outputs are derived from the respective output mixers. The sample rate for each digital audio interface AIFn is configured using the respective AIFn_RATE field—see Table 4-26. Note that sample-rate conversion is required when routing the AIF paths to any signal chain that is asynchronous or configured for a different sample rate. 130 DS1162F1 CS42L92 4.7 Digital Audio Interface Control 4.7.2 AIF Pin Configuration The external connections associated with each digital audio interface (AIF) are implemented on multifunction GPIO pins, which must be configured for the respective AIF functions when required. The AIF connections are pin-specific alternative functions available on specific GPIO pins. See Section 4.14 to configure the GPIO pins for AIF operation. Integrated pull-up and pull-down resistors can be enabled on the AIFnLRCLK, AIFnBCLK and AIFnRXDAT pins. This is provided as part of the GPIO functionality, and provides a flexible capability for interfacing with other devices. Each pull-up and pull-down resistor can be configured independently using the fields described in Table 4-93. If the pull-up and pull-down resistors are both enabled, the CS42L92 provides a bus keeper function on the respective pin. The bus-keeper function holds the logic level unchanged whenever the pin is undriven (e.g., if the signal is tristated). 4.7.3 AIF Master/Slave Control The digital audio interfaces can operate in master or slave modes and also in mixed master/slave configurations. In Master Mode, the BCLK and LRCLK signals are generated by the CS42L92 when any of the respective digital audio interface channels is enabled. In Slave Mode, these outputs are disabled by default to allow another device to drive these pins. Master Mode is selected on the AIFnBCLK pin by setting AIFn_BCLK_MSTR. In Master Mode, the AIFnBCLK signal is generated by the CS42L92 when one or more AIFn channels is enabled. If the AIFn_BCLK_FRC bit is set in BCLK Master Mode, the AIFnBCLK signal is output at all times, including when none of the AIFn channels is enabled. The AIFnBCLK signal can be inverted in master or slave modes using the AIFn_BCLK_INV bit. Master Mode is selected on the AIFnLRCLK pin by setting AIFn_LRCLK_MSTR. In Master Mode, the AIFnLRCLK signal is generated by the CS42L92 when one or more AIFn channels is enabled. If AIFn_LRCLK_FRC is set in LRCLK Master Mode, the AIFnLRCLK signal is output at all times, including when none of the AIFn channels is enabled. Note that AIFnLRCLK is derived from AIFnBCLK, and an internal or external AIFnBCLK signal must be present to generate AIFnLRCLK. The AIFnLRCLK signal can be inverted in master or slave modes using the AIFn_LRCLK_INV bit. The timing of the AIFnLRCLK signal is selectable using AIFn_LRCLK_ADV. If this bit is set, the LRCLK signal transition is advanced to the previous BCLK phase (as compared with the default behavior). Further details of this option, and conditions for valid use cases, are described in Section 4.7.3.1. The AIF1 master/slave control registers are described in Table 4-42. Table 4-42. AIF1 Master/Slave Control Register Address Bit Label R1280 (0x0500) 7 AIF1_ BCLK_INV AIF1_BCLK_Ctrl 6 AIF1_ BCLK_FRC 5 AIF1_ BCLK_ MSTR DS1162F1 Default Description 0 AIF1 Audio Interface BCLK Invert 0 = AIF1BCLK not inverted 1 = AIF1BCLK inverted 0 AIF1 Audio Interface BCLK Output Control 0 = Normal 1 = AIF1BCLK always enabled in Master Mode 0 AIF1 Audio Interface BCLK Master Select 0 = AIF1BCLK Slave Mode 1 = AIF1BCLK Master Mode 131 CS42L92 4.7 Digital Audio Interface Control Table 4-42. AIF1 Master/Slave Control (Cont.) Register Address Bit Label R1282 (0x0502) 4 AIF1_ LRCLK_ AIF1_Rx_Pin_Ctrl ADV Default Description 0 AIF1 Audio Interface LRCLK Advance 0 = Normal 1 = AIF1LRCLK transition is advanced to the previous BCLK phase 2 AIF1_ 0 AIF1 Audio Interface LRCLK Invert LRCLK_INV 0 = AIF1LRCLK not inverted 1 = AIF1LRCLK inverted 1 AIF1_ 0 AIF1 Audio Interface LRCLK Output Control LRCLK_ 0 = Normal FRC 1 = AIF1LRCLK always enabled in Master Mode 0 AIF1_ 0 AIF1 Audio Interface LRCLK Master Select LRCLK_ 0 = AIF1LRCLK Slave Mode MSTR 1 = AIF1LRCLK Master Mode The AIF2 master/slave control registers are described in Table 4-43. Table 4-43. AIF2 Master/Slave Control Register Address Bit Label Default Description R1344 (0x0540) 7 AIF2_BCLK_ 0 AIF2 Audio Interface BCLK Invert INV AIF2_BCLK_Ctrl 0 = AIF2BCLK not inverted 1 = AIF2BCLK inverted 6 AIF2_BCLK_ 0 AIF2 Audio Interface BCLK Output Control FRC 0 = Normal 1 = AIF2BCLK always enabled in Master Mode 5 AIF2_BCLK_ 0 AIF2 Audio Interface BCLK Master Select MSTR 0 = AIF2BCLK Slave Mode 1 = AIF2BCLK Master Mode R1346 (0x0542) 4 AIF2_ 0 AIF2 Audio Interface LRCLK Advance LRCLK_ADV AIF2_Rx_Pin_Ctrl 0 = Normal 1 = AIF2LRCLK transition is advanced to the previous BCLK phase 2 AIF2_ 0 AIF2 Audio Interface LRCLK Invert LRCLK_INV 0 = AIF2LRCLK not inverted 1 = AIF2LRCLK inverted 1 AIF2_ 0 AIF2 Audio Interface LRCLK Output Control LRCLK_FRC 0 = Normal 1 = AIF2LRCLK always enabled in Master Mode 0 AIF2_ 0 AIF2 Audio Interface LRCLK Master Select LRCLK_ 0 = AIF2LRCLK Slave Mode MSTR 1 = AIF2LRCLK Master Mode The AIF3 master/slave control registers are described in Table 4-44. Table 4-44. AIF3 Master/Slave Control Register Address Bit Label Default Description R1408 (0x0580) 7 AIF3_BCLK_ 0 AIF3 Audio Interface BCLK Invert INV AIF3_BCLK_Ctrl 0 = AIF3BCLK not inverted 1 = AIF3BCLK inverted 6 AIF3_BCLK_ 0 AIF3 Audio Interface BCLK Output Control FRC 0 = Normal 1 = AIF3BCLK always enabled in Master Mode 0 AIF3 Audio Interface BCLK Master Select 5 AIF3_BCLK_ MSTR 0 = AIF3BCLK Slave Mode 1 = AIF3BCLK Master Mode 132 DS1162F1 CS42L92 4.7 Digital Audio Interface Control Table 4-44. AIF3 Master/Slave Control (Cont.) Register Address Bit Label Default Description R1410 (0x0582) 4 AIF3_ 0 AIF3 Audio Interface LRCLK Advance LRCLK_ADV AIF3_Rx_Pin_Ctrl 0 = Normal 1 = AIF3LRCLK transition is advanced to the previous BCLK phase 2 AIF3_ 0 AIF3 Audio Interface LRCLK Invert LRCLK_INV 0 = AIF3LRCLK not inverted 1 = AIF3LRCLK inverted 1 AIF3_ 0 AIF3 Audio Interface LRCLK Output Control LRCLK_FRC 0 = Normal 1 = AIF3LRCLK always enabled in Master Mode 0 AIF3_ 0 AIF3 Audio Interface LRCLK Master Select LRCLK_ 0 = AIF3LRCLK Slave Mode MSTR 1 = AIF3LRCLK Master Mode 4.7.3.1 LRCLK Advance The timing of the AIFnLRCLK signal can be adjusted using AIFn_LRCLK_ADV. If this bit is set, the LRCLK signal transition is advanced to the previous BCLK phase (as compared with the default behavior). The LRCLK-advance option (AIFn_LRCLK_ADV = 1) is valid for DSP-A mode only, operating in Master Mode. Note: BCLK inversion must be enabled (AIFn_BCLK_INV = 1) if the LRCLK-advance option is enabled. The adjusted interface timing (AIFn_LRCLK_ADV = 1), is shown in Fig. 4-51. The left-channel MSB is available on the second rising edge of BCLK, 1.5 BCLK cycles after the LRCLK rising edge—assuming the BCLK output is inverted. 1/Fs LRCLK 1.5 BCLK BCLK LEFT CHANNEL RXDAT/ TXDAT 1 MSB 2 3 n-2 Input Word Length (WL) RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Figure 4-51. LRCLK advance—DSP-A Master Mode 4.7.4 AIF Signal Path Enable The AIF1–AIF3 interfaces support up to eight input (RX) channels and up to eight output (TX) channels. Each channel is enabled or disabled using the bits defined in Table 4-45, Table 4-46 and Table 4-47. The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The ASYNCCLK may also be required, depending on the path configuration. See Section 4.16 for details of the system clocks. The audio interfaces can be reconfigured if enabled, including changes to the LRCLK frame length and the channel time-slot configurations. Care is required to ensure that this on-the-fly reconfiguration does not cause corruption to the active signal paths. Wherever possible, it is recommended to disable all channels before changing the AIF configuration. The CS42L92 performs automatic checks to confirm that the SYSCLK and ASYNCCLK frequencies are high enough to support the commanded signal paths and processing functions. If the frequency is too low, an attempt to enable an AIF signal path fails. Note that active signal paths are not affected under such circumstances. DS1162F1 133 CS42L92 4.7 Digital Audio Interface Control The AIF1 signal-path-enable bits are described in Table 4-45. Table 4-45. AIF1 Signal Path Enable Register Address R1305 (0x0519) AIF1_Tx_Enables R1306 (0x051A) AIF1_Rx_Enables Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Label AIF1TX8_ENA AIF1TX7_ENA AIF1TX6_ENA AIF1TX5_ENA AIF1TX4_ENA AIF1TX3_ENA AIF1TX2_ENA AIF1TX1_ENA AIF1RX8_ENA AIF1RX7_ENA AIF1RX6_ENA AIF1RX5_ENA AIF1RX4_ENA AIF1RX3_ENA AIF1RX2_ENA AIF1RX1_ENA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description AIF1 Audio Interface TX Channel n Enable 0 = Disabled 1 = Enabled AIF1 Audio Interface RX Channel n Enable 0 = Disabled 1 = Enabled The AIF2 signal-path-enable bits are described in Table 4-46. Table 4-46. AIF2 Signal Path Enable Register Address R1369 (0x0559) AIF2_Tx_Enables R1370 (0x055A) AIF2_Rx_Enables Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Label AIF2TX8_ENA AIF2TX7_ENA AIF2TX6_ENA AIF2TX5_ENA AIF2TX4_ENA AIF2TX3_ENA AIF2TX2_ENA AIF2TX1_ENA AIF2RX8_ENA AIF2RX7_ENA AIF2RX6_ENA AIF2RX5_ENA AIF2RX4_ENA AIF2RX3_ENA AIF2RX2_ENA AIF2RX1_ENA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description AIF2 Audio Interface TX Channel n Enable 0 = Disabled 1 = Enabled AIF2 Audio Interface RX Channel n Enable 0 = Disabled 1 = Enabled The AIF3 signal-path-enable bits are described in Table 4-47. Table 4-47. AIF3 Signal Path Enable Register Address R1433 (0x0599) AIF3_Tx_Enables 134 Bit 7 6 5 4 3 2 1 0 Label AIF3TX8_ENA AIF3TX7_ENA AIF3TX6_ENA AIF3TX5_ENA AIF3TX4_ENA AIF3TX3_ENA AIF3TX2_ENA AIF3TX1_ENA Default 0 0 0 0 0 0 0 0 Description AIF3 Audio Interface TX Channel n Enable 0 = Disabled 1 = Enabled DS1162F1 CS42L92 4.7 Digital Audio Interface Control Table 4-47. AIF3 Signal Path Enable (Cont.) Register Address R1434 (0x059A) AIF3_Rx_Enables 4.7.5 Bit 7 6 5 4 3 2 1 0 Label AIF3RX8_ENA AIF3RX7_ENA AIF3RX6_ENA AIF3RX5_ENA AIF3RX4_ENA AIF3RX3_ENA AIF3RX2_ENA AIF3RX1_ENA Default 0 0 0 0 0 0 0 0 Description AIF3 Audio Interface RX Channel n Enable 0 = Disabled 1 = Enabled AIF BCLK and LRCLK Control The AIFnBCLK frequency is selected using the AIFn_BCLK_FREQ field. For each setting of this field, the actual frequency depends on whether AIFn is configured for a 48-kHz-related sample rate, as described in Table 4-48 through Table 4-50. • If AIFn_RATE < 1000 (Table 4-26), AIFn is referenced to the SYSCLK clocking domain and the applicable frequency depends upon the SAMPLE_RATE_1, SAMPLE_RATE_2 or SAMPLE_RATE_3 fields. • If AIFn_RATE  1000, AIFn is referenced to the ASYNCCLK clocking domain and the applicable frequency depends upon the ASYNC_SAMPLE_RATE_1 or ASYNC_SAMPLE_RATE_2 fields. The selected AIFnBCLK rate must be less than or equal to SYSCLK/2, or ASYNCCLK/2, as applicable. See Section 4.16 for details of SYSCLK and ASYNCCLK clock domains, and the associated control registers. The AIFnLRCLK frequency is controlled relative to AIFnBCLK by the AIFn_BCPF divider. Note that the BCLK rate must be configured in master and slave modes, using the AIFn_BCLK_FREQ fields. The LRCLK rates only require to be configured in Master Mode. The AIF1 BCLK/LRCLK control fields are described in Table 4-48. Table 4-48. AIF1 BCLK and LRCLK Control Register Address R1280 (0x0500) AIF1_ BCLK_Ctrl R1286 (0x0506) AIF1_Rx_ BCLK_Rate DS1162F1 Bit Label 4:0 AIF1_ BCLK_ FREQ[4:0] Default Description 0x0C AIF1BCLK Rate. The AIF1BCLK rate must be less than or equal to SYSCLK/2. 0x00–0x01 = Reserved 0x07 = 384 kHz (352.8 kHz) 0x0D = 3.072 MHz (2.8824 MHz) 0x02 = 64 kHz (58.8 kHz) 0x08 = 512 kHz (470.4 kHz) 0x0E = 4.096 MHz (3.7632 MHz) 0x03 = 96 kHz (88.2 kHz) 0x09 = 768 kHz (705.6 kHz) 0x0F = 6.144 MHz (5.6448 MHz) 0x04 = 128 kHz (117.6 kHz) 0x0A = 1.024 MHz (940.8 kHz) 0x10 = 8.192 MHz (7.5264 MHz) 0x05 = 192 kHz (176.4 kHz) 0x0B = 1.536 MHz (1.4112 MHz) 0x11 = 12.288 MHz (11.2896 MHz) 0x06 = 256 kHz (235.2 kHz) 0x0C = 2.048 MHz (1.8816 MHz) 0x12 = 24.576 MHz (22.5792 MHz) The frequencies in brackets apply for 44.1 kHz–related sample rates only. If AIF1_RATE < 1000, AIF1 is referenced to the SYSCLK clock domain. In this case, the 44.1 kHz–related frequencies apply if SAMPLE_RATE_n = 01XXX. If AIF1_RATE  1000, AIF1 is referenced to the ASYNCCLK clock domain. In this case, the 44.1 kHz–related frequencies apply if ASYNC_SAMPLE_RATE_n = 01XXX. 12:0 AIF1_ 0x0040 AIF1LRCLK Rate. Selects the number of BCLK cycles per AIF1LRCLK frame. AIF1LRCLK clock = BCPF[12:0] AIF1BCLK/AIF1_BCPF. Integer (LSB = 1), Valid from 8 to 8191. 135 CS42L92 4.7 Digital Audio Interface Control The AIF2 BCLK/LRCLK control fields are described in Table 4-49. Table 4-49. AIF2 BCLK and LRCLK Control Register Address R1344 (0x0540) AIF2_ BCLK_Ctrl Bit Label 4:0 AIF2_ BCLK_ FREQ[4:0] R1350 (0x0546) AIF2_Rx_ BCLK_Rate Default Description 0x0C AIF2BCLK Rate. The AIF2BCLK rate must be less than or equal to SYSCLK/2. 0x00–0x01 = Reserved 0x07 = 384 kHz (352.8 kHz) 0x0D = 3.072 MHz (2.8824 MHz) 0x02 = 64 kHz (58.8 kHz) 0x08 = 512 kHz (470.4 kHz) 0x0E = 4.096 MHz (3.7632 MHz) 0x03 = 96 kHz (88.2 kHz) 0x09 = 768 kHz (705.6 kHz) 0x0F = 6.144 MHz (5.6448 MHz) 0x04 = 128 kHz (117.6 kHz) 0x0A = 1.024 MHz (940.8 kHz) 0x10 = 8.192 MHz (7.5264 MHz) 0x05 = 192 kHz (176.4 kHz) 0x0B = 1.536 MHz (1.4112 MHz) 0x11 = 12.288 MHz (11.2896 MHz) 0x06 = 256 kHz (235.2 kHz) 0x0C = 2.048 MHz (1.8816 MHz) 0x12 = 24.576 MHz (22.5792 MHz) The frequencies in brackets apply for 44.1 kHz–related sample rates only. If AIF2_RATE < 1000, AIF2 is referenced to the SYSCLK clock domain. In this case, the 44.1 kHz–related frequencies apply if SAMPLE_RATE_n = 01XXX. If AIF2_RATE  1000, AIF2 is referenced to the ASYNCCLK clock domain. In this case, the 44.1 kHz–related frequencies apply if ASYNC_SAMPLE_RATE_n = 01XXX. 12:0 AIF2_ 0x0040 AIF2LRCLK Rate. Selects the number of BCLK cycles per AIF2LRCLK frame. AIF2LRCLK clock = BCPF[12:0] AIF2BCLK/AIF2_BCPF. Integer (LSB = 1), Valid from 8 to 8191. The AIF3 BCLK/LRCLK control fields are described in Table 4-50. Table 4-50. AIF3 BCLK and LRCLK Control Register Address R1408 (0x0580) AIF3_ BCLK_Ctrl Bit 4:0 AIF3_ BCLK_ FREQ[4:0] R1414 (0x0586) AIF3_Rx_ BCLK_Rate 4.7.6 Label Default Description 0x0C AIF3BCLK Rate. The AIF3BCLK rate must be less than or equal to SYSCLK/2. 0x00–0x01 = Reserved 0x07 = 384 kHz (352.8 kHz) 0x0D = 3.072 MHz (2.8824 MHz) 0x02 = 64 kHz (58.8 kHz) 0x08 = 512 kHz (470.4 kHz) 0x0E = 4.096 MHz (3.7632 MHz) 0x03 = 96 kHz (88.2 kHz) 0x09 = 768 kHz (705.6 kHz) 0x0F = 6.144 MHz (5.6448 MHz) 0x04 = 128 kHz (117.6 kHz) 0x0A = 1.024 MHz (940.8 kHz) 0x10 = 8.192 MHz (7.5264 MHz) 0x05 = 192 kHz (176.4 kHz) 0x0B = 1.536 MHz (1.4112 MHz) 0x11 = 12.288 MHz (11.2896 MHz) 0x06 = 256 kHz (235.2 kHz) 0x0C = 2.048 MHz (1.8816 MHz) 0x12 = 24.576 MHz (22.5792 MHz) The frequencies in brackets apply for 44.1 kHz–related sample rates only. If AIF3_RATE < 1000, AIF3 is referenced to the SYSCLK clock domain. In this case, the 44.1 kHz–related frequencies apply if SAMPLE_RATE_n = 01XXX. If AIF3_RATE  1000, AIF3 is referenced to the ASYNCCLK clock domain. In this case, the 44.1 kHz–related frequencies apply if ASYNC_SAMPLE_RATE_n = 01XXX. 12:0 AIF3_ 0x0040 AIF3LRCLK Rate. Selects the number of BCLK cycles per AIF3LRCLK frame. AIF3LRCLK clock = BCPF[12:0] AIF3BCLK/AIF3_BCPF. Integer (LSB = 1), Valid from 8 to 8191. AIF Digital Audio Data Control The fields controlling the audio data format, word length, and slot configurations for AIF1–AIF3 are described in Table 4-51 through Table 4-53 respectively. Note that left-justified and DSP-B modes are valid in Master Mode only (i.e., BCLK and LRCLK are outputs from the CS42L92). The AIFn slot length is the number of BCLK cycles in one time slot within the overall LRCLK frame. The word length is the number of valid data bits within each time slot. If the word length is less than the slot length, there are unused BCLK cycles at the end of each time slot. The AIFn word length and slot length are independently selectable for the input (RX) and output (TX) paths. For each AIF input (RX) and AIF output (TX) channel, the position of the audio data sample within the LRCLK frame is configurable. The x_SLOT fields define the time-slot position of the audio sample for the associated audio channel. Valid selections are Slot 0 upwards. The time slots are numbered as shown in Fig. 4-44 through Fig. 4-47. 136 DS1162F1 CS42L92 4.7 Digital Audio Interface Control Note that, in DSP modes, the time slots are ordered consecutively from the start of the LRCLK frame. In I2S and left-justified modes, the even-numbered time slots are arranged in the first half of the LRCLK frame, and the odd-numbered time slots are arranged in the second half of the frame. The AIF1 data control fields are described in Table 4-51. Table 4-51. AIF1 Digital Audio Data Control Register Address R1284 (0x0504) AIF1_Format Bit 2:0 R1287 (0x0507) AIF1_Frame_Ctrl_1 13:8 AIF1TX_WL[5:0] 0x18 7:0 0x18 R1288 (0x0508) AIF1_Frame_Ctrl_2 R1289 (0x0509) to R1296 (0x0510) R1297 (0x0511) to R1304 (0x0518) Label AIF1_FMT[2:0] AIF1TX_SLOT_ LEN[7:0] Default 000 13:8 AIF1RX_WL[5:0] 0x18 7:0 AIF1RX_SLOT_ LEN[7:0] 0x18 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 AIF1TX1_SLOT[5:0] AIF1TX2_SLOT[5:0] AIF1TX3_SLOT[5:0] AIF1TX4_SLOT[5:0] AIF1TX5_SLOT[5:0] AIF1TX6_SLOT[5:0] AIF1TX7_SLOT[5:0] AIF1TX8_SLOT[5:0] AIF1RX1_SLOT[5:0] AIF1RX2_SLOT[5:0] AIF1RX3_SLOT[5:0] AIF1RX4_SLOT[5:0] AIF1RX5_SLOT[5:0] AIF1RX6_SLOT[5:0] AIF1RX7_SLOT[5:0] AIF1RX8_SLOT[5:0] 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description AIF1 Audio Interface Format 000 = DSP Mode A 001 = DSP Mode B 010 = I2S mode 011 = Left-Justified mode Other codes are reserved. AIF1 TX Word Length (Number of valid data bits per slot) Integer (LSB = 1); Valid from 16 to 32 AIF1 TX Slot Length (Number of BCLK cycles per slot) Integer (LSB = 1); Valid from 16 to 128 AIF1 RX Word Length (Number of valid data bits per slot) Integer (LSB = 1); Valid from 16 to 32 AIF1 RX Slot Length (Number of BCLK cycles per slot) Integer (LSB = 1); Valid from 16 to 128 AIF1 TX Channel n Slot position Defines the TX time slot position of the Channel n audio sample Integer (LSB=1); Valid from 0 to 63 AIF1 RX Channel n Slot position Defines the RX time slot position of the Channel n audio sample Integer (LSB=1); Valid from 0 to 63 The AIF2 data control fields are described in Table 4-52. Table 4-52. AIF2 Digital Audio Data Control Register Address R1348 (0x0544) AIF2_Format Bit 2:0 R1351 (0x0547) AIF2_Frame_Ctrl_1 13:8 AIF2TX_WL[5:0] 0x18 7:0 0x18 DS1162F1 Label AIF2_FMT[2:0] AIF2TX_SLOT_ LEN[7:0] Default 000 Description AIF2 Audio Interface Format 000 = DSP Mode A 001 = DSP Mode B 010 = I2S mode 011 = Left-Justified mode Other codes are reserved. AIF2 TX Word Length (Number of valid data bits per slot) Integer (LSB = 1); Valid from 16 to 32 AIF2 TX Slot Length (Number of BCLK cycles per slot) Integer (LSB = 1); Valid from 16 to 128 137 CS42L92 4.7 Digital Audio Interface Control Table 4-52. AIF2 Digital Audio Data Control (Cont.) Register Address R1352 (0x0548) AIF2_Frame_Ctrl_2 R1353 (0x0549) to R1360 (0x0550) R1361 (0x0551) to R1368 (0x0558) Bit Label 13:8 AIF2RX_WL[5:0] Default 0x18 7:0 AIF2RX_SLOT_ LEN[7:0] 0x18 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 AIF2TX1_SLOT[5:0] AIF2TX2_SLOT[5:0] AIF2TX3_SLOT[5:0] AIF2TX4_SLOT[5:0] AIF2TX5_SLOT[5:0] AIF2TX6_SLOT[5:0] AIF2TX7_SLOT[5:0] AIF2TX8_SLOT[5:0] AIF2RX1_SLOT[5:0] AIF2RX2_SLOT[5:0] AIF2RX3_SLOT[5:0] AIF2RX4_SLOT[5:0] AIF2RX5_SLOT[5:0] AIF2RX6_SLOT[5:0] AIF2RX7_SLOT[5:0] AIF2RX8_SLOT[5:0] 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description AIF2 RX Word Length (Number of valid data bits per slot) Integer (LSB = 1); Valid from 16 to 32 AIF2 RX Slot Length (Number of BCLK cycles per slot) Integer (LSB = 1); Valid from 16 to 128 AIF2 TX Channel n Slot position Defines the TX time slot position of the Channel n audio sample Integer (LSB=1); Valid from 0 to 63 AIF2 RX Channel n Slot position Defines the RX time slot position of the Channel n audio sample Integer (LSB=1); Valid from 0 to 63 The AIF3 data control fields are described in Table 4-53. Table 4-53. AIF3 Digital Audio Data Control Register Address R1412 (0x0584) AIF3_Format Bit 2:0 R1415 (0x0587) AIF3_Frame_Ctrl_1 13:8 AIF3TX_WL[5:0] 0x18 7:0 0x18 R1416 (0x0588) AIF3_Frame_Ctrl_2 R1417 (0x0589) to R1424 (0x0590) 138 Label AIF3_FMT[2:0] AIF3TX_SLOT_ LEN[7:0] Default 000 13:8 AIF3RX_WL[5:0] 0x18 7:0 AIF3RX_SLOT_ LEN[7:0] 0x18 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 AIF3TX1_SLOT[5:0] AIF3TX2_SLOT[5:0] AIF3TX3_SLOT[5:0] AIF3TX4_SLOT[5:0] AIF3TX5_SLOT[5:0] AIF3TX6_SLOT[5:0] AIF3TX7_SLOT[5:0] AIF3TX8_SLOT[5:0] 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description AIF3 Audio Interface Format 000 = DSP Mode A 001 = DSP Mode B 010 = I2S mode 011 = Left-Justified mode Other codes are reserved. AIF3 TX Word Length (Number of valid data bits per slot) Integer (LSB = 1); Valid from 16 to 32 AIF3 TX Slot Length (Number of BCLK cycles per slot) Integer (LSB = 1); Valid from 16 to 128 AIF3 RX Word Length (Number of valid data bits per slot) Integer (LSB = 1); Valid from 16 to 32 AIF3 RX Slot Length (Number of BCLK cycles per slot) Integer (LSB = 1); Valid from 16 to 128 AIF3 TX Channel n Slot position Defines the TX time slot position of the Channel n audio sample Integer (LSB=1); Valid from 0 to 63 DS1162F1 CS42L92 4.7 Digital Audio Interface Control Table 4-53. AIF3 Digital Audio Data Control (Cont.) Register Address R1425 (0x0591) to R1432 (0x0598) 4.7.7 Bit 5:0 5:0 5:0 5:0 5:0 5:0 5:0 5:0 Label AIF3RX1_SLOT[5:0] AIF3RX2_SLOT[5:0] AIF3RX3_SLOT[5:0] AIF3RX4_SLOT[5:0] AIF3RX5_SLOT[5:0] AIF3RX6_SLOT[5:0] AIF3RX7_SLOT[5:0] AIF3RX8_SLOT[5:0] Default 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description AIF3 RX Channel n Slot position Defines the RX time slot position of the Channel n audio sample Integer (LSB=1); Valid from 0 to 63 AIF TDM and Tristate Control The AIFn output pins are tristated when the AIFn_TRI bit is set. Note that this function only affects output pins configured for the respective AIFn function—a GPIO pin that is configured for a different function is not affected by AIFn_TRI. See Section 4.14 to configure the GPIO pins. Under default conditions, the AIFnTXDAT output is held at Logic 0 when the CS42L92 is not transmitting data (i.e., during time slots that are not enabled for output by the CS42L92). If the AIFnTX_DAT_TRI bit is set, the CS42L92 tristates the respective AIFnTXDAT pin when not transmitting data, allowing other devices to drive the AIFnTXDAT connection. The AIF1 TDM and tristate control fields are described in Table 4-54. Table 4-54. AIF1 TDM and Tristate Control Register Address R1281 (0x0501) AIF1_Tx_Pin_Ctrl R1283 (0x0503) AIF1_Rate_Ctrl Bit 5 6 Label Default Description AIF1TX_DAT_TRI 0 AIF1TXDAT Tristate Control 0 = Logic 0 during unused time slots 1 = Tristated during unused time slots AIF1_TRI 0 AIF1 Audio Interface Tristate Control 0 = Normal 1 = AIF1 Outputs are tristated Note that this bit only affects output pins configured for the respective AIF1 function. The AIF2 TDM and tristate control fields are described in Table 4-55. Table 4-55. AIF2 TDM and Tristate Control Register Address R1345 (0x0541) AIF2_Tx_Pin_Ctrl R1347 (0x0543) AIF2_Rate_Ctrl Bit 5 6 Label Default Description AIF2TX_DAT_TRI 0 AIF2TXDAT Tristate Control 0 = Logic 0 during unused time slots 1 = Tristated during unused time slots AIF2_TRI 0 AIF2 Audio Interface Tristate Control 0 = Normal 1 = AIF2 Outputs are tristated Note that this bit only affects output pins configured for the respective AIF2 function. The AIF3 TDM and tristate control fields are described in Table 4-56. Table 4-56. AIF3 TDM and Tristate Control Register Address R1409 (0x0581) AIF3_Tx_Pin_Ctrl R1411 (0x0583) AIF3_Rate_Ctrl DS1162F1 Bit 5 6 Label Default Description AIF3TX_DAT_TRI 0 AIF3TXDAT Tristate Control 0 = Logic 0 during unused time slots 1 = Tristated during unused time slots AIF3_TRI 0 AIF3 Audio Interface Tristate Control 0 = Normal 1 = AIF3 Outputs are tristated Note that this bit only affects output pins configured for the respective AIF3 function. 139 CS42L92 4.8 SLIMbus Interface 4.8 SLIMbus Interface The SLIMbus protocol is highly configurable and adaptable, supporting multiple audio signal paths, and mixed sample rates simultaneously. It also supports control messaging and associated communications between devices. 4.8.1 SLIMbus Devices The SLIMbus components comprise different device classes (manager, framer, interface, generic). Each component on the bus has an interface device, which provides bus management services for the respective component. One or more components on the bus provide manager and framer device functions; the manager has the capabilities to administer the bus, although the framer is responsible for driving the CLK line and for driving the DATA required to establish the frame structure on the bus. Note that only one manager and one framer device is active at any time. The framer function can be transferred between devices when required. Generic devices provide the basic SLIMbus functionality for the associated ports, and for the transport protocol by which audio signal paths are established on the bus. 4.8.2 SLIMbus Frame Structure The SLIMbus bit stream is formatted within a defined structure of cells, slots, subframes, frames, and superframes: • A single data bit is known as a cell. • Four cells make a slot. • A frame consists of 192 slots. • Eight frames make a superframe. The bit stream structure is configurable to some extent, but the superframe definition always comprises 1536 slots. The transmitted/received bit rate can be configured according to system requirements and can be changed dynamically without interruption to active audio paths. The SLIMbus CLK frequency (also the bus bit rate) is defined by a root frequency (RF) and a clock gear (CG). In the top clock gear (Gear 10), the CLK frequency is equal to the root frequency. Each reduction in the clock gear halves the CLK frequency, and doubles the duration of the superframe. The SLIMbus bandwidth typically comprises control space (for bus messages, synchronization, etc.) and data space (for audio paths). The precise allocation is configurable and can be entirely control space, if required. The subframe definition comprises the number of slots per subframe (6, 8, 24 or 32) and the number of these slots per subframe allocated as control space. The applicable combination of subframe length and control space width are defined by the Subframe Mode (SM) parameter. The SLIMbus frame always comprises 192 slots, regardless of the subframe definition. A number of slots are allocated to control space, as noted above; the remaining slots are allocated to data space. Some of the control space is required for framing information and for the guide channel (see Section 4.8.3); the remainder of the control space are allocated to the message channel. Multiline SLIMbus comprises one or more secondary data line, supporting additional bandwidth and flexibility for data transfer over the bus. All data lines are synchronized to the bus clock; the RF and CG parameters are common to all data lines. Note that control space is allocated on the primary data line only—secondary lines are used exclusively for data space. Accordingly, the SM parameter is defined for the primary line only. 4.8.3 Control Space Framing information is provided in slots 0 and 96 of every frame. Slot 0 contains a 4-bit synchronization code; slot 96 contains the 32-bit framing information, transmitted 4 bits at a time over the eight frames that make up the SLIMbus superframe. The clock gear, root frequency, subframe configuration, along with some other parameters, are encoded within the framing information. 140 DS1162F1 CS42L92 4.8 SLIMbus Interface The guide channel occupies two slots within Frame 0. This provides the necessary information for a SLIMbus component to acquire and verify the frame synchronization. The guide channel occupies the first two control space slots within the first frame of the bit stream, excluding the framing information slots. Note that the exact slot allocation depends upon the applicable subframe mode. The message channel is allocated all of the control space not used by the framing information or the guide channel. The message channel enables SLIMbus devices to communicate with each other, using a priority-based mechanism defined in the MIPI specification. Messages may be broadcast to all devices on the bus, or can be addressed to specific devices using their allocated logical address (LA) or enumeration address (EA). Note that, device-specific messages are directed to a particular device (i.e., manager, framer, interface, or generic) within a component on the bus. 4.8.4 Data Space The data space can be organized into a maximum of 256 data channels. Each channel, identified by a unique channel number (CN), is a stream of one or more contiguous slots, organized in a consistent data structure that repeats at a fixed interval. A data channel is defined by its segment length (SL), (number of contiguous slots allocated), segment interval (spacing between the first slots of successive segments), and segment offset (the slot number of the first allocated slot within the superframe). The segment interval and segment offset are collectively defined by a segment distribution (SD), by which the SLIMbus manager may configure or reconfigure any data channel. Each segment may comprise TAG, AUX, and DATA portions. Any of these portions may have a length of zero; the exact composition depends on the transport protocol (TP) for the associated channel. The DATA portion must be wide enough to accommodate one full word of the data channel contents. Data words cannot be spread across multiple segments. The segment interval for each data channel represents the minimum spacing between consecutive data samples for that channel. (Note that the minimum spacing applies if every allocated segment is populated with new data; in many cases, additional bandwidth is allocated and not every allocated segment is used.) The segment interval gives rise to segment windows for each data channel, aligned to the start of every superframe. The segment window boundaries define the times within which each new data sample must be buffered, ready for transmission—adherence to these fixed boundaries allows slot allocations to be moved within a segment window, without altering the signal latency. The segment interval may be either shorter or longer than the frame length, but there is always an integer number of segment windows per superframe. To transfer data between devices on the SLIMbus interface, a data channel connection is established between a source and one or more destination (sink) ports. A unique port number (PN) address is defined for every active TX/RX port. Multiple data channels can share the same port address by assigning different end point (EP) values to each channel. The TP defines the flow control or handshaking method used by the ports associated with a data channel. The applicable flow control modes depend on the relationship between the audio sample rate (flow rate) and the SLIMbus CLK frequency. If the two rates are synchronized and integer related, no flow control is needed. In other cases, the flow may be regulated by the use of a presence bit, which can be set by the source device (pushed protocol) or by the sink device (pulled protocol). The data-channel structure is defined in terms of the TP, SD, SL, and data line (LN) parameters. For multiline operation, the LN value identifies the data line on which the channel is present. Note that the mapping of secondary data lines (1–7) with respect to the secondary data pins is configurable on each multiline SLIMbus component, using value elements associated with the respective interface device. See Section 4.9.3 for details of value elements. The data-channel content definition includes a presence rate (PR) parameter (describing the nominal sample rate for the audio channel) and a frequency locked (FL) bit (identifying whether the data source is synchronized to the SLIMbus CLK). The data length (DL) parameter defines the size of each data sample (number of slots). The auxiliary bits format (AF) and data type (DT) parameters provide support for non-PCM encoded data channels; the channel link (CL) parameter is an indicator that channel CN is related to the previous channel, CN-1. DS1162F1 141 CS42L92 4.9 SLIMbus Control Sequences For a given root frequency and clock gear, the SL and SD parameters define the amount of SLIMbus bandwidth that is allocated to a given data channel. The minimum bandwidth requirements of a data channel are represented by the presence rate (PR) and data length (DL) parameters. The allocated SLIMbus bandwidth must be equal to or greater than the bandwidth of the data to be transferred. The segment interval defines the repetition rate of the SLIMbus slots allocated to consecutive data samples for a given data channel. The presence rate (PR) is the nominal sample rate of the audio path. The segment rate (determined by the segment interval value) must be equal to or greater than the presence rate for a given data channel. The following constraints must be observed when configuring a SLIMbus channel: • If pushed or pulled transport protocol is selected, the segment rate must be greater than the presence rate to ensure that samples are not dropped as a result of clock drift. • If isochronous transport protocol is selected, the segment rate must be equal to the presence rate. Isochronous transport protocol should be selected only if the data source is frequency locked to the SLIMbus CLK (i.e., the data source is synchronized to the SLIMbus framer device). 4.9 SLIMbus Control Sequences This section describes the messages and general protocol associated with the SLIMbus system. Note: 4.9.1 The SLIMbus specification permits flexibility in core message support for different components. See Section 4.10 for details regarding which messages are supported on each of the SLIMbus devices present on the CS42L92. Device Management and Configuration This section describes the SLIMbus messages associated with configuring all devices on the SLIMbus interface. When the SLIMbus interface starts up, it is required that only one component provides the manager and framer device functions. Other devices can request connection to the bus after they have gained synchronization. The REPORT_PRESENT (DC, DCV) message may be issued by devices attempting to connect to the bus. The payload of this message contains the device class (DC) and device class version (DCV) parameters, describing the type of device that is attempting to connect. This message may be issued autonomously by the connecting device, or else in response to a REQUEST_SELF_ANNOUNCEMENT message from the manager device. After positively acknowledging the REPORT_PRESENT message, the manager device then issues the ASSIGN_ LOGICAL_ADDRESS (LA) message to allow the other device to connect to the bus. The payload of this message contains the logical address (LA) parameter only; this is the unique address by which the connected device sends and receives SLIMbus messages. The device is then said to be enumerated. Once a device has been successfully connected to the bus, the logical address (LA) parameter can be changed at any time using the CHANGE_LOGICAL_ADDRESS (LA) message. The RESET_DEVICE message commands an individual SLIMbus device to perform its reset procedure. As part of the reset, all associated ports are reset, and any associated data channels are canceled. Note that, if the RESET_DEVICE command is issued to an interface device, it causes a component reset (i.e., all devices within the associated component are reset). Under a component reset, every associated device releases its logical address, and the component becomes disconnected from the bus. 4.9.2 Information Management A memory map of information elements is defined for each device. This is arranged in 3 x 1-kB blocks, comprising core value elements, device class-specific value elements, and user value elements respectively, as described in the MIPI specification. Note that the contents of the user information portion for each CS42L92 SLIMbus device are reserved. Read/write access is implemented using the messages described as follows. Specific elements within the information map are identified using the element code (EC) parameter. In the case of read access, a unique transaction ID (TID) is assigned to each message relating to a particular read/write request. 142 DS1162F1 CS42L92 4.9 SLIMbus Control Sequences • The REQUEST_INFORMATION (TID, EC) message is used to instruct a device to respond with the indicated information. The payload of this message contains the transaction ID (TID) and the element code (EC). • The REQUEST_CLEAR_INFORMATION (TID, EC, CM) message is used to instruct a device to respond with the indicated information, and also to clear all, or parts, of the same information slice. The payload of this message contains the transaction ID (TID), element code (EC), and clear mask (CM). The clear mask field is used to select which elements are to be cleared as part of the instruction. • The REPLY_INFORMATION (TID, IS) message is used to provide output of a requested parameter. The payload of this message contains the transaction ID (TID) and the information slice (IS). The information slice bytes contain the value of the requested parameter. • The CLEAR_INFORMATION (EC, CM) message is used to clear all, or parts, of the indicated information slice. The payload of this message contains the element code (EC) and clear mask (CM). The clear mask field is used to select which elements are to be cleared as part of the instruction. • The REPORT_INFORMATION (EC, IS) message is used to inform other devices about a change in a specified element in the information map. The payload of this message contains the element code (EC) and the information slice (IS). The information slice bytes contain the new value of the applicable parameter. 4.9.3 Value Management (Including Register Access) A memory map of value elements is defined for each device. This is arranged in 3 x 1-kB blocks, comprising core value elements, device class-specific value elements, and user value elements respectively, as described in the MIPI specification. These elements are typically parameters used to configure device behavior. The user value elements of the interface device are used on CS42L92 to support read/write access to the register map. Details of how to access specific registers are described in Section 4.10. Note that, with the exception of the user value elements of the interface device, the contents of the user value portion for each CS42L92 SLIMbus device are reserved. Read/write access is implemented using the messages described as follows. Specific elements within the value map are identified using the element code (EC) parameter. In the case of read access, a unique transaction ID (TID) is assigned to each message relating to a particular read/write request. • The REQUEST_VALUE (TID, EC) message is used to instruct a device to respond with the indicated information. The payload of this message contains the transaction ID (TID) and the element code (EC). • The REPLY_VALUE (TID, VS) message is used to provide output of a requested parameter. The payload of this message contains the transaction ID (TID) and the value slice (VS). The value slice bytes contain the value of the requested parameter. • The CHANGE_VALUE (EC, VU) message is used to write data to a specified element in the value map. The payload of this message contains the element code (EC) and the value update (VU). The value update bytes contain the new value of the applicable parameter. 4.9.4 Frame and Clocking Management This section describes the SLIMbus messages associated with changing the frame or clocking configuration. One or more configuration messages may be issued as part of a reconfiguration sequence; all of the updated parameters become active at once, when the reconfiguration boundary is reached. • The BEGIN_RECONFIGURATION message is issued to define a reconfiguration boundary point: subsequent NEXT_* messages become active at the first valid superframe boundary following receipt of the RECONFIGURE_ NOW message. (A valid boundary must be at least two slots after the end of the RECONFIGURE_NOW message.) Both of these messages have no payload content. • The NEXT_ACTIVE_FRAMER (LAIF, NCo, NCi) message is used to select a new device as the active framer. The payload of this message includes the logical address, incoming framer (LAIF). Two other fields (NCo, NCi) define the number of clock cycles for which the CLK line shall be inactive during the handover. • The NEXT_SUBFRAME_MODE (SM) and NEXT_CLOCK_GEAR (CG) messages are used to reconfigure the SLIMbus clocking or framing definition. The payload of each is the respective subframe mode (SM) or clock gear (CG) respectively. DS1162F1 143 CS42L92 4.10 SLIMbus Interface Control • The NEXT_PAUSE_CLOCK (RT) message instructs the active framer to pause the bus. The payload of the message contains the restart time (RT), which indicates whether the interruption is to be of a specified time and/or phase duration. • The NEXT_RESET_BUS message instructs all components on the bus to be reset. In this case, all devices on the bus are reset and are disconnected from the bus. Subsequent reconnection to the bus follows the same process as when the bus is first initialized. • The NEXT_SHUTDOWN_BUS message instructs all devices that the bus is to be shut down. 4.9.5 Data Channel Configuration This section describes the SLIMbus messages associated with configuring a SLIMbus data channel. Note that the manager device is responsible for allocating the available bandwidth as required for each data channel. • The CONNECT_SOURCE (PN, EP, CN) and CONNECT_SINK (PN, EP, CN) messages are issued to the respective devices, defining the ports between which a data channel is to be established. The end point parameter allows up to eight channels to share the same port number. Multiple destinations (sinks) can be configured for a channel, if required. The payload of each message contains the port number (PN), end point (EP), and the channel number (CN) parameters. • The BEGIN_RECONFIGURATION message is issued to define a Reconfiguration Boundary point: subsequent NEXT_* messages become active at the first valid superframe boundary following receipt of the RECONFIGURE_ NOW message. A valid boundary must be at least two slots after the end of the RECONFIGURE_NOW message. • The NEXT_DEFINE_CHANNEL (CN, TP, SD, SL, LN) message informs the associated devices of the structure of the data channel. The payload of this message contains the channel number (CN), TP, SD, SL, and LN parameters for the data channel. • The NEXT_DEFINE_CONTENT (CN, FL, PR, AF, DT, CL, DL), or CHANGE_CONTENT (CN, FL, PR, AF, DT, CL, DL) message provides more detailed information about the data channel contents. The payload of this message contains the channel number (CN), frequency locked (FL), presence rate (PR), auxiliary bits format (AF), data type (DT), channel link (CL), and data length (DL) parameters. • The NEXT_ACTIVATE_CHANNEL (CN) message instructs the channel to be activated at the next reconfiguration boundary. The payload of this message contains the channel number (CN) only. • The RECONFIGURE_NOW message completes the reconfiguration sequence, causing all of the NEXT_ messages since the BEGIN_RECONFIGURATION to become active at the next valid superframe boundary. (A valid boundary must be at least two slots after the end of the RECONFIGURE_NOW message.) • Active channels can be reconfigured using the CHANGE_CONTENT, NEXT_DEFINE_CONTENT, or NEXT_ DEFINE_CHANNEL messages. Note that these changes can be effected without interrupting the data channel; the NEXT_DEFINE_CHANNEL, for example, may be used to change a segment distribution, in order to reallocate the SLIMbus bandwidth. • An active channel can be paused using the NEXT_DEACTIVATE_CHANNEL message and reinstated using the NEXT_ACTIVATE_CHANNEL message. • Data channels can be disconnected using the DISCONNECT_PORT or NEXT_REMOVE_CHANNEL messages. These messages provide equivalent functionality, but use different parameters (PN or CN respectively) to identify the affected signal path. 4.10 SLIMbus Interface Control The CS42L92 features a MIPI-compliant SLIMbus interface. It supports multichannel audio input/output and control register read/write access. The SLIMbus interface on CS42L92 comprises a generic device, framer device, interface device, and 16 data ports, providing up to 8 input (RX) channels and up to 8 output (TX) channels. Multiline capability is supported, offering additional bandwidth and system-level flexibility. The interface supports up to eight audio input channels and up to eight audio output channels. Mixed sample rates can be supported simultaneously. The audio signal paths associated with the SLIMbus interface are described in Section 4.3. 144 DS1162F1 CS42L92 4.10 SLIMbus Interface Control The SLIMbus interface also supports read/write access to the CS42L92 control registers via the value map of the interface device, as described in Section 4.10.5. The SLIMbus clocking rate and channel allocations are controlled by the manager device. The message channel and data channel bandwidth may be dynamically adjusted according to the application requirements. Note that the manager device functions are not implemented on the CS42L92, and these bandwidth allocation requirements are outside the scope of this data sheet. The SLIMbus interface provides full support for 32-bit data words (input and output). Audio data samples up to 32 bits can be routed to the AIF1, AIF3, SLIMbus, S/PDIF, and DAC output paths. Note that other signal paths and signal-processing blocks within the digital core are limited to 24-bit data length; data samples are truncated to 24-bit length if they are routed through any function that does not support 32-bit data words. 4.10.1 SLIMbus Device Parameters The SLIMbus interface on the CS42L92 comprises three devices. The enumeration address of each device within the SLIMbus interface is derived from the parameters noted in Table 4-57. Table 4-57. SLIMbus Device Parameters Description Generic Framer Interface Manufacturer ID 0x01FA 0x01FA 0x01FA Product Code 0x6371 0x6371 0x6371 Device ID 0x00 0x55 0x7F Instance Value Enumeration Address 0x00 01FA_6371_0000 0x00 01FA_6371_5500 0x00 01FA_6371_7F00 4.10.2 SLIMbus Message Support The SLIMbus interface on the CS42L92 supports bus messages as described in Table 4-58 and Table 4-59. Table 4-58. SLIMbus Message Support Category Device Management Messages Data Channel Management Messages Information Management Messages DS1162F1 Message Code MC[6:0] 0x01 0x02 0x04 0x08 0x09 0x0C 0x0F 0x10 0x11 0x14 0x18 0x20 0x21 0x24 0x28 0x29 Description REPORT_PRESENT (DC, DCV) ASSIGN_LOGICAL_ADDRESS (LA) RESET_DEVICE () CHANGE_LOGICAL_ADDRESS (LA) CHANGE_ARBITRATION_PRIORITY (AP) REQUEST_SELF_ANNOUNCEMENT () REPORT_ABSENT () CONNECT_SOURCE (PN, EP, CN) CONNECT_SINK (PN, EP, CN) DISCONNECT_PORT (PN) CHANGE_CONTENT (CN, FL, PR, AF, DT, CL, DL) REQUEST_INFORMATION (TID, EC) REQUEST_CLEAR_INFORMATION (TID, EC, CM) REPLY_INFORMATION (TID, IS) CLEAR_INFORMATION (EC, CM) REPORT_INFORMATION (EC, IS) Generic S D D D — D — D D D D D D S D — Framer S D D D — D — — — — — D D S D — Interface S D D D — D — — — — — D D S D S 145 CS42L92 4.10 SLIMbus Interface Control Table 4-58. SLIMbus Message Support (Cont.) Category Reconfiguration Messages Value Management Messages Message Code MC[6:0] 0x40 0x44 0x45 0x46 0x47 0x4A 0x4B 0x4C 0x50 0x51 0x54 0x55 0x58 0x5F 0x60 0x61 0x64 0x68 Description Generic BEGIN_RECONFIGURATION () D NEXT_ACTIVE_FRAMER (LAIF, NCo, NCi) — NEXT_SUBFRAME_MODE (SM) — NEXT_CLOCK_GEAR (CG) — NEXT_ROOT_FREQUENCY (RF) — NEXT_PAUSE_CLOCK (RT) — NEXT_RESET_BUS () — NEXT_SHUTDOWN_BUS () — NEXT_DEFINE_CHANNEL (CN, TP, SD, SL, LN) D NEXT_DEFINE_CONTENT (CN, FL, PR, AF, DT, CL, DL) D NEXT_ACTIVATE_CHANNEL (CN) D NEXT_DEACTIVATE_CHANNEL (CN) D NEXT_REMOVE_CHANNEL (CN) D RECONFIGURE_NOW () D REQUEST_VALUE (TID, EC) — REQUEST_CHANGE_VALUE (TID, EC, VU) — REPLY_VALUE (TID, VS) — CHANGE_VALUE (EC, VU) — Framer D D D D D D D D — — — — — D — — — — Interface D — D — — — — — — — — — — D D — S D Notes: • S = Supported as a source device only. • D = Supported as a destination device only. The CS42L92 SLIMbus component must be reset prior to scheduling a hardware reset or power-on reset. This can be achieved using the RESET_DEVICE message (issued to the CS42L92 interface device), or else using the NEXT_RESET_ BUS message. Additional notes on specific SLIMbus parameters are described in Table 4-59. Table 4-59. SLIMbus Parameter Support Parameter Code AF CG CL CM CN DC DCV DL DT EC EP FL IS LA LAIF LN NCi NCo 146 Description Auxiliary Bits Format Clock Gear Channel Link Clear Mask Comments — — — CS42L92 does not fully support this function. The CM bytes of the REQUEST_ CLEAR_INFORMATION or CLEAR_INFORMATION messages must not be sent to CS42L92 Devices. When either of these messages is received, all bits within the specified Information Slice are cleared. Channel Number — Device Class — Device Class Variation — Data Length — Data Type CS42L92 supports the following DT codes: 0x0 = Not indicated 0x1 = LPCM audio Note that 2’s complement PCM can be supported with DT = 0x0. Element Code — End Point — Frequency Locked — Information Slice — Logical Address — Logical Address, Incoming Framer — Data Line All LN codes (0–7) are supported. The LN value must be equal to one of the data lines that is mapped to one of the CS42L92 SLIMDATn pins. The mapping of the secondary SLIMDATn pins onto the SLIMbus data lines is configurable, using the value elements of the interface device. (Note that the primary data pin, SLIMDAT1, is always mapped to SLIMbus data line DATA0.) Number of Incoming Framer Clock Cycles — Number of Outgoing Framer Clock Cycles — DS1162F1 CS42L92 4.10 SLIMbus Interface Control Table 4-59. SLIMbus Parameter Support (Cont.) Parameter Code Description PN Port Number PR Presence Rate RF Root Frequency RT Restart Time SD Segment Distribution SL Segment Length SM TID TP Subframe Mode Transaction ID Transport Protocol VS VU Value Slice Value Update Comments Note that the Port Numbers of the CS42L92 SLIMbus paths are register-configurable, as described in Table 4-62. Note that the Presence Rate must be the same as the sample rate selected for the associated CS42L92 SLIMbus path. CS42L92 supports the following RF codes as Active Framer: 0x1 = 24.576 MHz 0x2 = 22.5792 MHz All codes are supported when CS42L92 is not the Active Framer. CS42L92 supports the following RT codes: 0x0 = Fast Recovery 0x2 = Unspecified Delay When either of these values is specified, the CS42L92 resumes toggling the CLK line within four cycles of the CLK line frequency. Note that any audio channels that are assigned the same SAMPLE_RATE_n or ASYNC_SAMPLE_RATE_n value must also be assigned the same Segment Interval. Note that any active data channels that are assigned the same Port Number must also be assigned the same Segment Length. — — CS42L92 supports the following TP codes, according to the applicable audio channel port: Audio TX channel ports: 0x0 (Isochronous Protocol) or 0x1 (Pushed Protocol) Audio RX channel ports: 0x0 (Isochronous Protocol) or 0x2 (Pulled Protocol) Note that any active data channels that are assigned the same Port Number must also be assigned the same Transport Protocol. — — 4.10.3 SLIMbus Clocking Control The clock frequency of the SLIMbus interface is not fixed, and may be set according to the application requirements. The clock frequency can be reconfigured dynamically as required. The CS42L92 SLIMbus interface includes a framer device. When configured as the active framer, the SLIMbus clock (SLIMCLK) is an output from the CS42L92. At other times, SLIMCLK is an input. The framer function can be transferred from one device to another; this is known as framer handover, and is controlled by the manager device. The supported root frequencies in active framer mode are 24.576 or 22.5792 MHz only. At other times, the supported root frequencies are as defined in the MIPI Alliance specification for SLIMbus. Under normal operating conditions, the SLIMbus interface operates with a fixed root frequency (RF); dynamic updates to the bus rate are applied using a selectable clock gear (CG) function. The root frequency and the clock gear setting are controlled by the manager device; these parameters are transmitted in every SLIMbus superframe to all devices on the bus. In Gear 10 (the highest clock gear setting), the SLIMCLK input (or output) frequency is equal to the root frequency. In lower gears, the SLIMCLK frequency is reduced by increasing powers of 2. The clock gear definition is shown in Table 4-60. Note: The 24.576MHz root frequency is an example only; other frequencies are also supported. Table 4-60. SLIMbus Clock Gear Selection Clock Gear 10 9 8 7 DS1162F1 Description Divide by 1 Divide by 2 Divide by 4 Divide by 8 SLIMCLK Frequency 1 24.576 MHz 12.288 MHz 6.144 MHz 3.072 MHz 147 CS42L92 4.10 SLIMbus Interface Control Table 4-60. SLIMbus Clock Gear Selection (Cont.) Clock Gear 6 5 4 3 2 1 Description Divide by 16 Divide by 32 Divide by 64 Divide by 128 Divide by 256 Divide by 512 SLIMCLK Frequency 1 1.536 MHz 768 kHz 384 kHz 192 kHz 96 kHz 48 kHz 1.Assuming 24.576-MHz root frequency If the CS42L92 is the active framer, the SLIMCLK output is synchronized to the SYSCLK or ASYNCCLK system clock, as selected by the SLIMCLK_SRC bit. The applicable system clock must be enabled and configured at the SLIMbus root frequency, whenever the CS42L92 is the active framer. If the CS42L92 is not the active framer, the SLIMCLK input can be used to provide a reference source for the FLLs. The frequency of this reference is controlled using SLIMCLK_REF_GEAR, as described in Table 4-61. The input clock reference for the FLLs is selected by using FLLn_REFCLK_SRC. If SLIMbus is selected as the clock source, the reference signal is generated using an adaptive divider on the SLIMCLK input. The divider automatically adapts to the SLIMbus clock gear (CG). If the clock gear on the bus is lower than the SLIMCLK_REF_GEAR, the selected reference frequency cannot be supported, and the SLIMbus clock reference is disabled. See Section 4.16 for details of system clocking and the FLLs. Table 4-61. SLIMbus Clock Reference Control Register Address R1507 (0x05E3) SLIMbus_Framer_ Ref_Gear Bit 4 Label SLIMCLK_SRC Default 0 3:0 SLIMCLK_REF_ GEAR[3:0] 0x0 Description SLIMbus Clock source Selects the SLIMbus reference clock in Active Framer mode. 0 = SYSCLK 1 = ASYNCCLK Note that the applicable clock must be enabled, and configured at the SLIMbus Root Frequency, in Active Framer mode. SLIMbus Clock Reference control. Sets the SLIMbus reference clock relative to the SLIMbus Root Frequency (RF). 0x0 = Clock stopped 0x4 = Gear 4. (RF/64) 0x8 = Gear 8. (RF/4) 0x1 = Gear 1. (RF/512) 0x5 = Gear 5. (RF/32) 0x9 = Gear 9. (RF/2) 0x2 = Gear 2. (RF/256) 0x6 = Gear 6. (RF/16) 0xA = Gear 10. (RF) 0x3 = Gear 3. (RF/128) 0x7 = Gear 7. (RF/8) All other codes are reserved 4.10.4 SLIMbus Audio Channel Control 4.10.4.1 Port Number Control The CS42L92 SLIMbus interface supports up to eight audio input (RX) channels and up to eight audio output (TX) channels. The port number and end point number for each channel is configurable using the fields described in Table 4-62. Table 4-62. SLIMbus Audio Port Number Control Register Address R1490 (0x05D2) SLIMbus_RX_Ports0 R1491 (0x05D3) SLIMbus_RX_Ports1 R1492 (0x05D4) SLIMbus_RX_Ports2 R1493 (0x05D5) SLIMbus_RX_Ports3 148 Bit 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 Label SLIMRX2_PORT_ADDR[7:0] SLIMRX1_PORT_ADDR[7:0] SLIMRX4_PORT_ADDR[7:0] SLIMRX3_PORT_ADDR[7:0] SLIMRX6_PORT_ADDR[7:0] SLIMRX5_PORT_ADDR[7:0] SLIMRX8_PORT_ADDR[7:0] SLIMRX7_PORT_ADDR[7:0] Default 0x01 0x00 0x03 0x02 0x05 0x04 0x07 0x06 Description SLIMbus RX Channel n Port number Bits [7:5] specify the End Point (valid from 0–7). Bits [4:0] specify the Port Number (valid from 0–31) DS1162F1 CS42L92 4.10 SLIMbus Interface Control Table 4-62. SLIMbus Audio Port Number Control (Cont.) Register Address R1494 (0x05D6) SLIMbus_TX_Ports0 R1495 (0x05D7) SLIMbus_TX_Ports1 R1496 (0x05D8) SLIMbus_TX_Ports2 R1497 (0x05D9) SLIMbus_TX_Ports3 Bit 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 Label SLIMTX2_PORT_ADDR[7:0] SLIMTX1_PORT_ADDR[7:0] SLIMTX4_PORT_ADDR[7:0] SLIMTX3_PORT_ADDR[7:0] SLIMTX6_PORT_ADDR[7:0] SLIMTX5_PORT_ADDR[7:0] SLIMTX8_PORT_ADDR[7:0] SLIMTX7_PORT_ADDR[7:0] Default 0x09 0x08 0x0B 0x0A 0x0D 0x0C 0x0F 0x0E Description SLIMbus TX Channel n Port number Valid from 0–31 Bits [7:5] specify the End Point (valid from 0–7). Bits [4:0] specify the Port Number (valid from 0–31) 4.10.4.2 Sample-Rate Control The SLIMbus audio inputs may be selected as input to the digital mixers or signal-processing functions within the CS42L92 digital core. The SLIMbus audio outputs are derived from the respective output mixers. The sample rate for each SLIMbus channel is configured using SLIMRXn_RATE and SLIMTXn_RATE—see Table 4-26. Note that the SLIMbus interface provides simultaneous support for SYSCLK-referenced and ASYNCCLK-referenced sample rates on different channels. For example, 48-kHz and 44.1-kHz SLIMbus audio paths can be simultaneously supported. Sample-rate conversion is required when routing the SLIMbus paths to any signal chain that is asynchronous or configured for a different sample rate. 4.10.4.3 Signal Path Enable The SLIMbus interface supports up to eight audio input (RX) channels and up to eight audio output (TX) channels. Each channel can be enabled or disabled using the fields defined in Table 4-63. Note: SLIMbus audio channels can be supported only when the corresponding ports have been enabled by the manager device (i.e., in addition to setting the respective enable bits). The status bits in Registers R1527 and R1528 indicate the status of each SLIMbus port. The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The ASYNCCLK may also be required, depending on the path configuration. See Section 4.16 for details of the system clocks. Table 4-63. SLIMbus Signal Path Enable Register Address R1525 (0x05F5) SLIMbus_RX_ Channel_Enable R1526 (0x05F6) SLIMbus_TX_ Channel_Enable DS1162F1 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Label SLIMRX8_ENA SLIMRX7_ENA SLIMRX6_ENA SLIMRX5_ENA SLIMRX4_ENA SLIMRX3_ENA SLIMRX2_ENA SLIMRX1_ENA SLIMTX8_ENA SLIMTX7_ENA SLIMTX6_ENA SLIMTX5_ENA SLIMTX4_ENA SLIMTX3_ENA SLIMTX2_ENA SLIMTX1_ENA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description SLIMbus RX Channel n Enable 0 = Disabled 1 = Enabled SLIMbus TX Channel n Enable 0 = Disabled 1 = Enabled 149 CS42L92 4.10 SLIMbus Interface Control Table 4-63. SLIMbus Signal Path Enable (Cont.) Register Address R1527 (0x05F7) SLIMbus_RX_ Port_Status R1528 (0x05F8) SLIMbus_TX_ Port_Status Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Label SLIMRX8_PORT_STS SLIMRX7_PORT_STS SLIMRX6_PORT_STS SLIMRX5_PORT_STS SLIMRX4_PORT_STS SLIMRX3_PORT_STS SLIMRX2_PORT_STS SLIMRX1_PORT_STS SLIMTX8_PORT_STS SLIMTX7_PORT_STS SLIMTX6_PORT_STS SLIMTX5_PORT_STS SLIMTX4_PORT_STS SLIMTX3_PORT_STS SLIMTX2_PORT_STS SLIMTX1_PORT_STS Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description SLIMbus RX Channel n Port Status (Read only) 0 = Disabled 1 = Configured and active SLIMbus TX Channel n Port Status (Read only) 0 = Disabled 1 = Configured and active 4.10.5 SLIMbus Control Register Access The SLIMbus interface supports read/write access to the CS42L92 control registers via the value map of the interface device. Full read/write access to all registers is possible, via the user value elements portion of the value map. Note that if multibyte transfers of more than 8 bytes are scheduled (see Section 4.10.5.3), system clocking constraints must be observed to ensure control interface limits are not exceeded. Full details of the applicable clocking requirements are provided in Section 4.16.7. 4.10.5.1 Control Register Write Register write operations are implemented using the CHANGE_VALUE message. A maximum of two messages may be required, depending on circumstances: the first CHANGE_VALUE message selects the register page (bits [23:8] of the control register address); the second message contains the data and bits [7:0] of the register address. The first message may be omitted if the register page is unchanged from the previous read or write operation. The required SLIMbus parameters are described in Table 4-64 and Table 4-65, for the generic case of writing the value 0xVVVV to control register address 0xYYYYZZ. Note that it is also possible to write blocks of up to 16 bytes (to consecutive register addresses), as described in Section 4.10.5.3. Table 4-64. Register Write Message (1)—CHANGE_VALUE Parameter Source Address 0xSS Value Destination Address 0xLL Access Mode Byte Address Slice Size Value Update 0b1 0x800 0b001 0xYYYY Description SS is the 8-bit logical address of the message source. This could be any active device on the bus, but is typically the manager device (0xFF). LL is the 8-bit logical address of the message destination (i.e., the CS42L92 SLIMbus interface device). The value is assigned by the SLIMbus manager device. Selects byte-based access mode. Identifies the user value element for selecting the control register page address. Selects 2-byte slice size YYYY is bits [23:8] of the applicable control register address. Table 4-65. Register Write Message (2)—CHANGE_VALUE Parameter Source Address 0xSS Destination Address 0xLL Access Mode 0b1 150 Value Description SS is the 8-bit logical address of the message source. This could be any active device on the bus, but is typically the manager device (0xFF). LL is the 8-bit logical address of the message destination (i.e., the CS42L92 SLIMbus interface device). The value is assigned by the SLIMbus manager device. Selects byte-based access mode. DS1162F1 CS42L92 4.10 SLIMbus Interface Control Table 4-65. Register Write Message (2)—CHANGE_VALUE (Cont.) Parameter Byte Address Value 0xUUU Slice Size Value Update 0b001 0xVVVV Note: Description Specifies the value map address, calculated as 0xA00 + (2 x 0xZZ), where ZZ is bits [7:0] of the applicable control register address. Selects 2-byte slice size VVVV is the 16-bit data to be written. The first message may be omitted if its contents are unchanged from the previous CHANGE_VALUE message sent to the CS42L92. 4.10.5.2 Control Register Read Register read operations are implemented using the CHANGE_VALUE and REQUEST_VALUE messages. A maximum of two messages may be required, depending on circumstances: the CHANGE_VALUE message selects the register page (bits [23:8] of the control register address); the REQUEST_VALUE message contains bits [7:0] of the register address. The first message may be omitted if the register page is unchanged from the previous read or write operation. The required SLIMbus parameters are described in Table 4-66 and Table 4-67, for the generic case of reading the contents of control register address 0xYYYYZZ. Note that it is also possible to read blocks of up to 8 bytes (to consecutive register addresses), as described in Section 4.10.5.3. Table 4-66. Register Read Message (1)—CHANGE_VALUE Parameter Source Address Value 0xSS Description SS is the 8-bit logical address of the message source. This could be any active device on the bus, but is typically the manager device (0xFF). Destination Address 0xLL LL is the 8-bit logical address of the message destination (i.e., the CS42L92 SLIMbus interface device). The value is assigned by the SLIMbus manager device. Access Mode 0b1 Selects byte-based access mode. Byte Address 0x800 Identifies the user value element for selecting the control register page address. Slice Size 0b001 Selects 2-byte slice size Value Update 0xYYYY YYYY is bits [23:8] of the applicable control register address. Table 4-67. Register Read Message (2)—REQUEST_VALUE Parameter Source Address Value Description 0xSS SS is the 8-bit logical address of the message source. This could be any active device on the bus, but is typically the manager device (0xFF). Destination Address 0xLL LL is the 8-bit logical address of the message destination (i.e., the CS42L92 SLIMbus interface device). The value is assigned by the SLIMbus manager device. Access Mode 0b1 Selects byte-based access mode. Byte Address 0xUUU Specifies the value map address, calculated as 0xA00 + (2 x 0xZZ), where ZZ is bits [7:0] of the applicable control register address. Slice Size 0b001 Selects 2-byte slice size Transaction ID 0xTTTT TTTT is the 16-bit transaction ID for the message. The value is assigned by the SLIMbus manager device. Note: The first message may be omitted if its contents are unchanged from the previous CHANGE_VALUE message sent to the CS42L92. The CS42L92 responds to the register read commands in accordance with the normal SLIMbus protocols. Note that the CS42L92 assumes that sufficient control space slots are available in which to provide its response before the next REQUEST_VALUE message is received. The CS42L92 response is made using a REPLY_VALUE message; the SLIMbus manager should wait until the REPLY_VALUE message has been received before sending the next REQUEST_ VALUE message. If additional REQUEST_VALUE messages are received before the CS42L92 response has been made, the earlier REQUEST_VALUE messages are ignored (i.e., only the last REQUEST_VALUE message is serviced). 4.10.5.3 Multibyte Control Register Access Register data transfers of up to 16 bytes can be configured using the slice size parameter in the second message of the applicable protocol (see Table 4-65 or Table 4-67). Additional value update words are appended to respective data message in this case, with the applicable data contents. DS1162F1 151 CS42L92 4.11 Output Signal Path Multibyte register read/write access is supported with slice size of 2, 4, 8, 12, or 16 bytes. Note that if multibyte transfers of more than 8 bytes are scheduled, system clocking constraints must be observed to ensure control interface limits are not exceeded. See Section 4.16.7. When a 2-byte transfer is selected, the register address 0xYYYYZZ is used (using the same naming conventions as above). When more than 2 bytes are transferred, the register address is automatically incremented as described in Table 4-68. Table 4-68. SLIMbus Register Read/Write Sequence—16-Bit Register Space (< 0x3000) Register Address (30 k, may also be indicated using these bits. Only valid when MICD1_ADC_MODE = 0. 0 Mic Detect 1 Data Valid 0 = Not Valid 1 = Valid 0 Mic Detect 1 Status 0 = Mic/accessory not detected 1 = Mic/accessory detected Mic/accessory detection is assured for load impedance up to 30 k. Only valid when MICD1_ADC_MODE = 0. 0x00 Mic Detect 1 ADC Level (Difference) Only valid when MICD1_ADC_MODE = 1. 0x00 15 MICD2_ADC_ MODE 0 7:4 MICD2_SENSE_ SEL[3:0] 0001 2:0 MICD2_GND_ SEL[2:0] 000 Mic Detect 1 ADC Level Only valid when MICD1_ADC_MODE = 1. Mic Detect 2 Measurement Mode 0 = Discrete Mode 1 = ADC Mode Mic Detect 2 Sense Select 1000 = MICDET5 0100 = HPDET1 0000 = MICDET1 1001 = JACKDET3 0101 = HPDET2 0001 = MICDET2 All other codes are 0110 = JACKDET1 0010 = MICDET3 reserved 0111 = JACKDET2 0011 = MICDET4 Mic Detect 2 Ground Select 000 = MICDET1/HPOUTFB1 011 = MICDET4/HPOUTFB4 001 = MICDET2/HPOUTFB2 100 = MICDET5/HPOUTFB5 010 = MICDET3/HPOUTFB3 All other codes are reserved DS1162F1 CS42L92 4.12 External Accessory Detection Table 4-87. Microphone Detect Control (Cont.) Register Address Bit Label R691 (0x02B3) 15:12 MICD2_BIAS_ STARTTIME[3:0] Mic_Detect_2_ Control_1 11:8 MICD2_ RATE[3:0] 7:4 MICD2_BIAS_ SRC[3:0] 1 MICD2_DBTIME 0 MICD2_ENA R692 (0x02B4) Mic_Detect_2_ Control_2 7:0 MICD2_LVL_ SEL[7:0] R693 (0x02B5) Mic_Detect_2_ Control_3 10:2 MICD2_LVL[8:0] R699 (0x02BB) Mic_Detect_2_ Control_4 1 MICD2_VALID 0 MICD2_STS 15:8 MICD2_ ADCVAL_ DIFF[7:0] 6:0 MICD2_ ADCVAL[6:0] Default Description 0001 Mic Detect 2 Bias Start-up Delay (Selects the delay time between enabling the MICBIASnx reference and performing the MICDET function.) 0000 = 0 ms (continuous) 0101 = 4 ms 1010 = 128 ms 0110 = 8 ms 1011 = 256 ms 0001 = 0.25 ms 0010 = 0.5 ms 0111 = 16 ms 1100 = 512 ms 0011 = 1 ms 1000 = 32 ms 1101 = 24 ms 0100 = 2 ms 1001 = 64 ms 1110 to 1111 = 512 ms 0001 Mic Detect 2 Rate (Selects the delay between successive MICDET measurements.) 0000 = 0 ms (continuous) 0101 = 4 ms 1010 = 128 ms 0001 = 0.25 ms 0110 = 8 ms 1011 = 256 ms 0010 = 0.5 ms 0111 = 16 ms 1100 = 512 ms 1000 = 32 ms 1101 = 24 ms 0011 = 1 ms 0100 = 2 ms 1001 = 64 ms 1110 to 1111 = 512 ms 0000 Mic Detect 2 Reference Select 0000 = MICBIAS1A 0011 = MICBIAS1D 1111 = MICVDD 0001 = MICBIAS1B 0100 = MICBIAS2A All other codes are reserved 0010 = MICBIAS1C 0101 = MICBIAS2B 1 Mic Detect 2 Debounce 0 = 2 measurements 1 = 4 measurements Only valid when MICD2_ADC_MODE = 0. 0 Mic Detect 2 Enable 0 = Disabled 1 = Enabled 1001_ Mic Detect 2 Level Select (enables mic/accessory detection in specific impedance ranges) 1111 [7] = Enable 1–30 k detection [3] = Not used [2] = Enable 360–680  detection [6] = Not used [5] = Not used [1] = Enable 210–290  detection [4] = Not used [0] = Enable 110–180  detection Only valid when MICD2_ADC_MODE = 0. 0_0000_ Mic Detect 2 Level (indicates the measured impedance) 0000 [8] = 1–30 k [3] = 360–680  [2] = 210–290  [7] = Not used [6] = Not used [1] = 110–180  [0] = 0–70  [5] = Not used [4] = Not used Accessory detection is assured within the specified impedance limits. Note that other impedance conditions, including loads >30 k, may also be indicated using these bits. Only valid when MICD2_ADC_MODE = 0. 0 Mic Detect 2 Data Valid 0 = Not Valid 1 = Valid 0 Mic Detect 2 Status 0 = Mic/accessory not detected 1 = Mic/accessory detected Mic/accessory detection is assured for load impedance up to 30 k. Only valid when MICD2_ADC_MODE = 0. 0x00 Mic Detect 2 ADC Level (Difference) Only valid when MICD2_ADC_MODE = 1. 0x00 Mic Detect 2 ADC Level Only valid when MICD2_ADC_MODE = 1. The external connections for the microphone detect circuit are shown in Fig. 4-61. In typical applications, it can be used to detect a microphone or button press. Note that, when using the microphone detect circuit, it is recommended to use the IN1ALx, IN1BLx, or IN1BR analog microphone input paths to ensure best immunity to electrical transients arising from the external accessory. DS1162F1 181 CS42L92 4.12 External Accessory Detection Note that the IN1ALx, IN1BLx, or IN1BR analog mic channels are recommended for use with the external accessory detect function. MICVDD If measuring the impedance on a MICBIAS-powered pin, one of the MICDETn inputs must always be used as the sense pin, as shown. MICBIAS1A MICBIAS1B MICBIAS1C MICBIAS1D LDO2 Regulator MICBIAS2A MICBIAS2B Accessory-detect reference supply selected by MICD1_BIAS_SRC (MICVDD or MICBIASnx) 2.2 k (±2%) External accessories C INnx Analog Input MICDETn HPDETn JACKDETn Sense pin selected by MICD1_SENSE_SEL Accessory / Button Detect MICDETn Button 2 Hookswitch / Button 1 Microphone Ground pin selected by MICD1_GND_SEL Figure 4-61. Microphone- and Accessory-Detect Interface 4.12.3.2 MICBIAS Reference Control The voltage reference for the microphone detection is configured using the MICDn_BIAS_SRC field, as described in Table 4-87. The microphone detection function automatically enables the applicable reference when required for impedance measurement. If the selected reference (MICBIASxy) is not already enabled, the microphone detect circuit automatically enables the respective MICBIAS output for short periods of time only, every time the impedance measurement is scheduled. To allow time for the associated circuitry to stabilize, a time delay is applied before the measurement is performed; this is configured using MICDn_BIAS_STARTTIME, as described in Table 4-87. If the measurement rate setting (MICDn_RATE) is greater than 0x0, the delay (MICDn_BIAS_STARTTIME) should be set to 0.25 ms or more. Note: The microphone detection automatically enables the applicable MICBIASxy output switch, every time the impedance measurement is scheduled. The respective MICBIAS generator (MICBIAS1 or MICBIAS2) is not controlled automatically—the applicable generators must be enabled using the MICB1_ENA and MICB2_ENA bits, as described in Table 4-124. The timing of the microphone detect function is shown in Fig. 4-62. Two different cases are shown, according to whether MICBIASxy is enabled periodically by the impedance measurement function, or is enabled at all times. If the selected reference (MICBIASxy) is not enabled continuously, the respective MICBIASxy discharge bits should be cleared. The MICBIAS control registers are described in Section 4.19. 182 DS1162F1 CS42L92 4.12 External Accessory Detection MICBx_ENA = 1, MICBxy_ENA = 0: MICBIASxy is enabled periodically for measurement function Measurement time (100 s to 500 s) time MICDn_BIAS_STARTTIME (0 ms to 512 ms; 0.25 ms default) MICDn_RATE (0 ms to 512 ms; 0.25 ms default) MICBx_ENA = 1, MICBxy_ENA = 1: MICBIASxy is enabled constantly Measurement time (100 s to 500 s) time MICDn_RATE (0 ms to 512 ms; 0.25 ms default) Figure 4-62. Microphone- and Accessory-Detect Timing 4.12.3.3 Measurement Range Control When the discrete measurement mode is selected (MICDn_ADC_MODE = 0), the MICDn_LVL_SEL[7:0] bits allow each impedance measurement level to be enabled or disabled independently. This allows the function to be tailored to the particular application requirements. If one or more bits within MICDn_LVL_SEL is cleared, the corresponding impedance level is disabled. Any measured impedance which lies in a disabled level is reported as the next lowest, enabled level. For example, the MICDn_LVL_SEL[2] bit enables the detection of a 360–680  impedance. If MICDn_LVL_SEL[2] = 0, an external impedance in this range is indicated in the next lowest detection range (210–290 ); this would be reported in the MICDn_LVL field as MICDn_LVL[2] = 1. With default register configuration, and all measurement levels enabled, the CS42L92 can detect the presence of a typical microphone and up to four push buttons. It is possible to configure the detection circuit for up to eight push buttons, by adjusting the impedance detection thresholds. However, adjustment of the detection thresholds is outside the scope of this data sheet—please contact your local Cirrus Logic representative for further information, if required. The measurement time varies between 100–500 s, depending on the impedance of the external load, and depending on how many impedance measurement levels are enabled. A high impedance is measured faster than a low impedance. 4.12.3.4 External Components The external connections for the microphone detect circuit are shown in Fig. 4-61. Examples of suitable external components are described in Section 5.1.7. The accuracy of the microphone detect function is assured whenever the connected load is within the applicable limits specified in Table 3-11. It is required that a 2.2-k (2%) resistor must also be connected between the measurement (SENSE) pin and the selected MICBIAS reference—different resistor values lead to inaccuracy in the impedance measurement. Note that, for typical headset detection, the choice of external resistance values must take into account the impedance of the microphone—the detected impedance corresponds to the combined parallel resistance of the microphone and any asserted push button. DS1162F1 183 CS42L92 4.12 External Accessory Detection 4.12.4 Headphone Detect The CS42L92 headphone detection circuit measures the impedance of an external headphone load. This feature can be used to set different gain levels or to apply other configuration settings according to the type of load connected. Separate monitor pins are provided for headphone detection on the left and right channels of HPOUTn. 4.12.4.1 Headphone Detection Control The headphone detection circuit measures the external impedance connected to the HPDETn pins. In typical usage, this provides measurement of the load impedance on one or more of the headphone outputs (HPOUT1–4). Note that impedance measurement is also possible via the MICDETn and JACKDETn pins, subject to some additional constraints. If the measurement (sense) pin is connected to one of the headphone outputs, then HPDET1, HPDET2, or JACKDET1 must always be used. The valid measurement range and the measurement accuracy are reduced, if using the MICDETn or JACKDETn pins. To configure the headphone detection circuit, the applicable pin connections for the intended measurement must be written to the HPD_SENSE_SEL and HPD_GND_SEL fields. The headphone detection circuit measures the external impedance between the pins selected by these two fields; the valid selections for each are defined in Table 4-90. When measuring the load impedance on one the HPOUTn output paths, the HPD_GND_SEL selection should be the same MICDETn/HPOUTFBn pin as the ground feedback pin for the applicable headphone output. See Section 4.11.8 to configure the ground feedback pin for the HPOUTn outputs. The HPD_FRC_SEL field must also be configured, to select where the measurement current is applied. As a general rule, this should be the same as the HPD_SENSE_SEL pin. Other configurations can be used if required—for example, to improve measurement accuracy in cases where the SENSE input path includes significant unwanted resistance. Note: There is no requirement for the SENSE and GND pin selections to be uniquely assigned between the microphone detect and headphone detect functions—the same pin may be used as a SENSE or GND connection for more than one of the detection functions. If multiple microphone/headphone detections are enabled, the respective measurements are automatically scheduled in isolation to each other. See Section 4.12.3 for details of the microphone detect function. Headphone detection is commanded by writing 1 to HPD_POLL. The impedance measurement range is configured using HPD_IMPEDANCE_RANGE. This field should be set in accordance with the expected load impedance. Note that a number of separate measurements are typically required to determine the load impedance; the recommended control requirements are described in Section 4.12.4.2. Note: Setting HPD_IMPEDANCE_RANGE is not required for detection on the MICDETn or JACKDETn pins. The impedance measurement range, and measurement accuracy, in these cases are different to the HPDET1 and HPDET2 measurements. If headphone detection is performed using a measurement pin connected to one of the headphone outputs, the respective output driver must be disabled before the measurement is commanded. The required settings are shown in Table 4-88. Table 4-88. Output Configuration for Headphone Detect Description Requirement HPOUT1L Impedance measurement HPD_OVD_ENA = 1, HPD_OUT_SEL = 000, HP1L_ENA = 0 HPOUT1R Impedance measurement HPD_OVD_ENA = 1, HPD_OUT_SEL = 001, HP1R_ENA = 0 HPOUT2L Impedance measurement HPD_OVD_ENA = 1, HPD_OUT_SEL = 010, HP2L_ENA = 0 HPOUT2R Impedance measurement HPD_OVD_ENA = 1, HPD_OUT_SEL = 011, HP2R_ENA = 0 HPOUT3L or HPOUT4L Impedance measurement HPD_OVD_ENA = 1, HPD_OUT_SEL = 100, HP3L_ENA = 0 HPOUT3R or HPOUT4R Impedance measurement HPD_OVD_ENA = 1, HPD_OUT_SEL = 101, HP3R_ENA = 0 Note: The applicable headphone outputs configuration must be maintained until after the headphone detection has completed. See Table 4-71 for details of the HPnx_ENA bits. If headphone detection is performed using a measurement pin that is not connected to one of the headphone outputs, the HPD_OVD_ENA bit should be cleared. 184 DS1162F1 CS42L92 4.12 External Accessory Detection If headphone detection is performed using a measurement pin that is also connected to one of the MICBIAS outputs, the respective MICBIAS output must be disabled and floating (MICBnx_ENA = 0, MICBnx_DISCH = 0). When headphone detection is commanded, the CS42L92 uses an adjustable current source to determine the connected impedance. A sweep of measurement currents is applied. The rate of this sweep can be adjusted using HPD_CLK_DIV and HPD_RATE. 4.12.4.2 Measurement Output The headphone detection process typically comprises a number of separate measurements (for different impedance ranges). Completion of each measurement is indicated by HPD_DONE. When this bit is set, the measurement result can be read from the HPD_DACVAL field, and decoded as described in Eq. 4-3. Impedance    C 0 +  C 1  Offset  - – C5 = -----------------------------------------------------------------------------------------------------------------------------------------------------------------HPD_DACVAL + 0.5  1 – ------------------------------------------------------C2 C 3  1 +  C 4  Gradient   Equation 4-3. Headphone Impedance Calculation The associated parameters for decoding the measurement result are defined Table 4-89. The applicable values are dependent on the HPD_IMPEDANCE_RANGE setting in each case. The Offset and Gradient values are derived from register fields that are factory-calibrated for each device. Table 4-89. Headphone Measurement Decode Parameters Parameter C0 C1 C2 C3 C4 C5 Offset Gradient HPD_IMPEDANCE_ RANGE = 00 1.007 –0.0072 4005 69.3 0.0055 0.6 HP_OFFSET_00 HP_GRADIENT_0X HPD_IMPEDANCE_ RANGE = 01 1.007 –0.0072 7975 69.6 0.0055 0.6 HP_OFFSET_01 HP_GRADIENT_0X HPD_IMPEDANCE_ RANGE = 10 9.744 –0.0795 7300 62.9 0.0055 0.6 HP_OFFSET_10 HP_GRADIENT_1X HPD_IMPEDANCE_ RANGE = 11 100.684 –0.9494 7300 63.2 0.0055 0.6 HP_OFFSET_11 HP_GRADIENT_1X Note that, to achieve the specified measurement accuracy, the above equation must be calculated to an accuracy of at least 5 decimal places throughout. The impedance measurement result is valid if 169  HPD_DACVAL  1019. (In case of any contradiction with the HPD_ IMPEDANCE_RANGE description, the HPD_DACVAL validity takes precedence.) If the external impedance is entirely unknown (i.e., it could lie in any of the HPD_IMPEDANCE_RANGE regions), it is recommended to test initially with HPD_IMPEDANCE_RANGE = 00. If the resultant HPD_DACVAL is < 169, the impedance is higher than the selected measurement range, so the test should be scheduled again, after incrementing HPD_IMPEDANCE_RANGE. Each measurement is triggered by writing 1 to HPD_POLL. Completion of each measurement is indicated by HPD_DONE. Note that, after HPD_DONE bit has been asserted, it remains asserted until the next measurement has been commanded. Note: A simpler, but less accurate, procedure for headphone impedance measurement is also supported, using the HPD_LVL field. When the HPD_DONE bit is set, indicating completion of a measurement, the impedance can be read directly from the HPD_LVL field, provided that the value lies within the range of the applicable HPD_ IMPEDANCE_RANGE setting. Note that, for detection using the MICDETn or JACKDETn pins, the HPD_LVL field is the only supported measurement output option. The HPD_IMPEDANCE_RANGE field is not valid for detection on the MICDETn or JACKDETn pins. See Table 4-90 for further description of the HPD_LVL field. The headphone detection function is an input to the interrupt control circuit and can be used to trigger an interrupt event on completion of the headphone detection; see Section 4.15. DS1162F1 185 CS42L92 4.12 External Accessory Detection The fields associated with headphone detection are described in Table 4-90. The external circuit configuration is shown Fig. 4-63. Note that 32-bit register addressing is used from R12888 (0x3000) upwards; 16-bit format is used otherwise. The registers noted in Table 4-90 contain a mixture of 16- and 32-bit register addresses. Table 4-90. Headphone Detect Control Register Address R665 (0x0299) Headphone_ Detect_0 Bit 15 Label HPD_OVD_ENA 14:12 HPD_OUT_SEL[2:0] 186 Default 0 000 11:8 HPD_FRC_SEL[3:0] 0000 7:4 HPD_SENSE_SEL[3:0] 0000 2:0 HPD_GND_SEL[2:0] 000 Description Headphone Detect Output Override Enable This bit, when set, causes the HPD_OUT_SEL headphone output channel to be automatically configured for headphone detection each time headphone detection is scheduled. Note that the respective output driver must also be disabled (HPnx_ENA = 0) for the duration of a headphone output impedance measurement. 0 = Disabled 1 = Enabled Headphone Detect Output Channel Select 000 = HPOUT1L 100 = HPOUT3L 001 = HPOUT1R 101 = HPOUT3R 010 = HPOUT2L All other codes are reserved 011 = HPOUT2R Headphone Detect Measurement Current Pin Select 0000 = MICDET1 0110 = JACKDET1 0001 = MICDET2 0111 = JACKDET2 0010 = MICDET3 1000 = MICDET5 0011 = MICDET4 1001 = JACKDET3 0100 = HPDET1 All other codes are reserved 0101 = HPDET2 Headphone Detect Sense Pin Select 0000 = MICDET1 0110 = JACKDET1 0111 = JACKDET2 0001 = MICDET2 0010 = MICDET3 1000 = MICDET5 0011 = MICDET4 1001 = JACKDET3 0100 = HPDET1 All other codes are reserved 0101 = HPDET2 Headphone Detect Ground Pin Select 000 = MICDET1/HPOUTFB1 011 = MICDET4/HPOUTFB4 001 = MICDET2/HPOUTFB2 100 = MICDET5/HPOUTFB5 010 = MICDET3/HPOUTFB3 All other codes are reserved DS1162F1 CS42L92 4.12 External Accessory Detection Table 4-90. Headphone Detect Control (Cont.) Register Address R667 (0x029B) Headphone_ Detect_1 R668 (0x029C) Headphone_ Detect_2 R669 (0x029D) Headphone_ Detect_3 DS1162F1 Bit Label 10:9 HPD_IMPEDANCE_ RANGE[1:0] Default 00 4:3 HPD_CLK_DIV[1:0] 00 2:1 HPD_RATE[1:0] 00 0 HPD_POLL 0 15 HPD_DONE 0 14:0 HPD_LVL[14:0] 0x0000 9:0 0x000 HPD_DACVAL[9:0] Description Headphone Detect Range 00 = 4  to 30  01 = 8  to 100  10 = 100  to 1 k 11 = 1 k to 10 k Only valid when HPD_SENSE_SEL = 0100 or 0101. Headphone Detect Clock Rate (Selects the clocking rate of the headphone detect adjustable current source. Decreasing the clock rate gives a slower measurement time.) 00 = 32 kHz 01 = 16 kHz 10 = 8 kHz 11 = 4 kHz Headphone Detect Sweep Rate (Selects the step size between successive measurements. Increasing the step size gives a faster measurement time.) 00 = 1 01 = 2 10 = 4 11 = Reserved Headphone Detect Enable Write 1 to start HP Detect function Headphone Detect Status 0 = HP Detect not complete 1 = HP Detect done Headphone Detect Level LSB = 0.5  8 = 4 or less 9 = 4.5  10 = 5  11 = 5.5  … 20,000 = 10 k or more For HPDET1 or HPDET2 measurement (HPD_SENSE_SEL = 0100 or 0101), HPD_LVL is valid from 4  to10 k, within the range selected by HPD_IMPEDANCE_RANGE. For other measurements, HPD_LVL is valid from 400  to 6 k only. If HPD_LVL reports a value outside the valid range, the range should be adjusted and the measurement repeated. A 0- result may be reported if the measurement is less than the minimum value for the selected range. Headphone Detect Level (Coded as integer, LSB = 1). See separate description for full decode information. 187 CS42L92 4.12 External Accessory Detection Table 4-90. Headphone Detect Control (Cont.) Register Address Bit Label R131076 31:24 HP_OFFSET_11[7:0] (0x20004) OTP_HPDET_Cal_ 1 23:16 HP_OFFSET_10[7:0] 15:8 HP_OFFSET_01[7:0] 7:0 R131078 (0x20006) OTP_HPDET_Cal_ 2 HP_OFFSET_00[7:0] 15:8 HP_GRADIENT_1X[7:0] 7:0 HP_GRADIENT_0X[7:0] Default Description See Headphone Detect Calibration field. Footnote 1 Signed number, LSB = 0.25. Range is –31.75 to +31.75. Default value is factory-set per device. See Headphone Detect Calibration field. Footnote 1 Signed number, LSB = 0.25. Range is –31.75 to +31.75. Default value is factory-set per device. See Headphone Detect Calibration field. Footnote 1 Signed number, LSB = 0.25. Range is –31.75 to +31.75. Default value is factory-set per device. See Headphone Detect Calibration field. Footnote 1 Signed number, LSB = 0.25. Range is –31.75 to +31.75. Default value is factory-set per device. See Headphone Detect Calibration field. Footnote 1 Signed number, LSB = 0.25. Range is –31.75 to +31.75. Default value is factory-set per device. See Headphone Detect Calibration field. Footnote 1 Signed number, LSB = 0.25. Range is –31.75 to +31.75. Default value is factory-set per device. 1. Default value is factory-set per device. The external connections for the headphone detect circuit are shown in Fig. 4-63. Note that the HPOUTFB ground connection should be close to headset jack. HPDETn MICDETn JACKDETn If measuring the impedance on a headphone output path, HPDET1, HPDET2, or JACKDET1 must be used as the sense pin. Sense pin selected by HPD_SENSE_SEL Measurement current pin selected by HPD_FRC_SEL (optional series resistors) HPOUT1L HPOUT1R MICDETn/HPOUTFBn Ground feedback pin selected by HP1_GND_SEL Ground measurement pin selected by HPD_GND_SEL Figure 4-63. Headphone Detect Interface Note that, where external resistors are connected in series with the headphone load, as shown, it is recommended that the HPDETn connection is to the headphone side of the resistors. If the HPDETn connection is made to the CS42L92 end of these resistors, this leads to a corresponding offset in the measured impedance. Under default conditions, the measurement time varies between 17–244 ms, depending on the impedance of the external load. A high impedance is measured faster than a low impedance. 188 DS1162F1 CS42L92 4.13 Low Power Sleep Configuration 4.13 Low Power Sleep Configuration The CS42L92 supports a low-power Sleep Mode, in which most functions are disabled and power consumption is minimized. The CS42L92 enters Sleep Mode when the DCVDD supply is removed. Note that the AVDD and DBVDD supplies must be present throughout the Sleep Mode duration. In Sleep Mode, the CS42L92 can generate an interrupt event in response to a change in voltage on the JACKDET1, JACKDET2, or JACKDET3 pins. This enables a jack insertion event (or other digital logic transition) to be used to trigger a wake-up of the CS42L92. In Sleep Mode, the CS42L92 can provide an unregulated voltage output on the MICBIAS1A pin. This can be used to power an external microphone during Sleep Mode—see Section 4.19. The system clocks (SYSCLK, ASYNCCLK, DSPCLK) should be disabled before selecting Sleep Mode. The external clock input (MCLKn) may also be stopped, if desired. The functionality and control fields associated with Sleep Mode are supported via an internal always-on supply domain. The always-on control registers are listed in Table 4-91. These fields are maintained (i.e., not reset) in Sleep Mode. Note that the control interface is not supported in Sleep Mode; read/write access to the always-on registers is not possible. Access to the register map using any of the control interfaces should be ceased before selecting Sleep Mode. Table 4-91. Sleep Mode Always-On Control Registers Register Address Label R710 (0x02C6) MICD_CLAMP2_OVD MICD_CLAMP2_MODE[2:0] MICD_CLAMP1_OVD MICD_CLAMP1_MODE[3:0] R723 (0x02D3) MICB1A_AOD_ENA JD3_ENA JD2_ENA JD1_ENA R6150 (0x1806) MICD_CLAMP2_FALL_EINT1 MICD_CLAMP2_RISE_EINT1 JD3_FALL_EINT1 JD3_RISE_EINT1 MICD_CLAMP1_FALL_EINT1 MICD_CLAMP1_RISE_EINT1 JD2_FALL_EINT1 JD2_RISE_EINT1 JD1_FALL_EINT1 JD1_RISE_EINT1 R6214 (0x1846) IM_MICD_CLAMP2_FALL_EINT1 IM_MICD_CLAMP2_RISE_EINT1 IM_JD3_FALL_EINT1 IM_JD3_RISE_EINT1 IM_MICD_CLAMP1_FALL_EINT1 IM_MICD_CLAMP1_RISE_EINT1 IM_JD2_FALL_EINT1 IM_JD2_RISE_EINT1 IM_JD1_FALL_EINT1 IM_JD1_RISE_EINT1 R6784 (0x1A80) IM_IRQ1 IRQ_POL IRQ_OP_CFG R6864 (0x1AD0) RESET_PU RESET_PD Reference See Section 4.12 See Section 4.19 See Section 4.12 See Section 4.15 See Section 4.23 The always-on digital I/O pins are listed in Table 4-92. All other digital input pins have no effect in Sleep Mode; all other digital output pins are undriven (floating). DS1162F1 189 CS42L92 4.14 General-Purpose I/O Note: The INnx/DMICx connections are isolated from the CS42L92 circuits in Sleep Mode. This enables a microphone that is connected to the CS42L92 to be used by another circuit while Sleep Mode is selected. The IRQ output is normally deasserted in Sleep Mode. In Sleep Mode, the IRQ output can be asserted only in response to the JACKDET1, JACKDET2, or JACKDET3 inputs. If the IRQ output is asserted in Sleep Mode, it can be deasserted only after a wake-up transition. Output drivers and bus keepers are disabled in Sleep Mode, for all pins not on the always-on domain; this means that the logic level on these pins is undefined. If a defined logic state is required during Sleep Mode (e.g., as input to another device), an external pull resistor may be required. If an external pull resistor is connected to a pin that also supports a bus keeper function, the pull resistance should be chosen carefully, taking into account the resistance of the bus keeper. See Section 4.14.1 for specific notes concerning the GPIO pins. Table 4-92. Sleep Mode Always-On Digital Input/Output Pins Pin Name Description Reference IRQ Interrupt Request output See Section 4.15 JACKDET1 Jack Detect input 1 See Section 4.12 JACKDET2 Jack Detect input 2 JACKDET3 Jack Detect input 3 RESET Digital Reset input (active low) See Section 4.23 The always-on functionality includes the JD1, JD2, and JD3 control signals, which provide support for the low-power Sleep Mode. The MICDET clamp status signal is also supported; this is controlled by a selectable logic function, derived from JD1, JD2, or JD3. The JD1, JD2, JD3, and MICDET clamp status signals are derived from the JACKDET1, JACKDET2, and JACKDET3 inputs, and can be used to trigger the interrupt controller. • The JD1, JD2, and JD3 signals are derived from the jack detect function (see Section 4.12). These inputs can be used to trigger a response to a jack insertion or jack removal detection. If these signals are enabled, the JD1, JD2, and JD3 signals indicate the status of the JACKDET1, JACKDET2, and JACKDET3 input pins respectively. See Table 4-84 for details of the associated control fields. • The MICDET clamp status is controlled by the JD1, JD2, or JD3 signals (see Section 4.12). The configurable logic provides flexibility in selecting the appropriate conditions for activating the MICDET clamp. The clamp status can be used to trigger a response to a jack insertion or jack removal detection. The MICDET clamp function is configured using MICD_CLAMP1_MODE and MICD_CLAMP2_MODE, as described in Table 4-85. Note that, due to control logic that is shared between the two clamps, the option to control both clamps in response to the JDn signals cannot be supported at the same time. It is assumed that a maximum of one clamp is active at any time—the MICDET clamp status provides an indication for the active clamp only. The interrupt functionality associated with these signals is part of the always-on functionality, enabling the CS42L92 to provide indication of jack insertion or jack removal to the host processor in Sleep Mode; see Section 4.15. Note that the JACKDETn inputs do not result in a wake-up transition directly; a wake-up transition only occurs by reapplication of DCVDD. In a typical application, the JACKDETn inputs provide a signal to the applications processor, via the IRQ output; if a wake-up transition is required, this is triggered by the applications processor enabling the DCVDD supply. 4.14 General-Purpose I/O The CS42L92 supports up to 16 GPIO pins, which can be assigned to application-specific functions. The GPIOs enable interfacing and detection of external hardware and can provide logic outputs to other devices. The GPIO input functions can be used to generate an interrupt (IRQ) event. 190 DS1162F1 CS42L92 4.14 General-Purpose I/O There are 2 dedicated GPIO pins; the remaining 14 GPIOs are implemented as alternate functions to a pin-specific capability. The GPIO and interrupt circuits support the following functions: • Pin-specific alternative functions for external interfaces (AIF, PDM) • Logic input/button detect (GPIO input) • Logic 1 and Logic 0 output (GPIO output) • Interrupt (IRQ) status output • Clock output • Frequency-locked loop (FLL) status output • FLL clock output • IEC-60958-3–compatible S/PDIF output • Pulse-width modulation (PWM) signal output • ASRC lock status • General-purpose timer status output • Event logger FIFO buffer status output • Alarm generator status output • Auxiliary PDM interface Logic input and output (GPIO) can be supported in two different ways on the CS42L92. The standard mechanism described in this section provides a comprehensive suite of options including input debounce, and selectable output drive configuration. The DSP GPIO circuit is tailored towards more advanced requirements typically demanded by DSP software features. The DSP GPIO functions are described in Section 4.5.4. The CS42L92 also incorporates two general-purpose switches; these are analog switches, described in Section 4.14.18. If the JTAG interface is enabled, the GPIO13–15 pins are configured as a JTAG interface that provides test and debug access to the CS42L92. The respective GPIO configuration registers have no effect in this case, and the GPIO pins cannot be assigned any other function. See Section 4.20 for details of the JTAG interface. 4.14.1 GPIO Control For each GPIO, the selected function is determined by the GPn_FN field, where n identifies the GPIO pin (1–16). The pin direction, set by GPn_DIR, must be set according to function selected by GPn_FN. If a pin is configured as a GPIO input (GPn_DIR = 1, GPn_FN = 0x001), the logic level at the pin can be read from the respective GPn_LVL bit. Note that GPn_LVL is not affected by the GPn_POL bit. A debounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled on each pin by setting the respective GPn_DB bit. The debounce circuit uses the 32-kHz clock, which must be enabled whenever input debounce functions are required. The debounce time is configurable using the GP_DBTIME field. See Section 4.16 for further details of the CS42L92 clocking configuration. Each GPIO pin is an input to the interrupt control circuit and can be used to trigger an interrupt event. An interrupt event is triggered on the rising and falling edges of the GPIO input. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See Section 4.15 for details of the interrupt event handling. Integrated pull-up and pull-down resistors are provided on each GPIO pin; these can be configured independently using the GPn_PU and GPn_PD fields. When the pull-up and pull-down control bits are both enabled, the CS42L92 provides a bus keeper function on the respective pin. The bus keeper function holds the logic level unchanged whenever the pin is undriven (e.g., if the signal is tristated). Note: The bus keeper is enabled by default on all GPIO pins and, if not actively driven, may result in either a Logic 0 or Logic 1 at the respective input on start-up. If an external pull resistor is connected (e.g., to control the logic level in Sleep Mode), the chosen resistance should take account of the bus keeper resistance (see Table 3-10). A strong pull resistor (e.g., 10 k) is required, if a specific start-up condition is to be forced by the external pull component. DS1162F1 191 CS42L92 4.14 General-Purpose I/O If a pin is configured as a GPIO output (GPn_DIR = 0, GPn_FN = 0x001), its level can be set to Logic 0 or Logic 1 using the GPn_LVL field. Note that the GPn_LVL bits are write-only when the respective GPIO pin is configured as an output. If a pin is configured as an output (GPn_DIR = 0), the polarity can be inverted using the GPn_POL bit. When GPn_ POL = 1, the selected output function is inverted. In the case of logic level output (GPn_FN = 0x001), the external output is the opposite logic level to GPn_LVL when GPn_POL = 1. Note that, if GPn_FN = 0x000 or 0x002, the GPn_POL bit has no effect on the respective GPIO pin. A GPIO output can be either CMOS driven or open drain. This is selected on each pin using the respective GPn_OP_CFG bit. Note that if GPn_FN = 0x000 the GPn_OP_CFG bit has no effect on the respective GPIO pin—see Table 4-93 for further details. If GPn_FN = 0x002, the respective pin output is CMOS. The register fields that control the GPIO pins are described in Table 4-93. Table 4-93. GPIO Control Register Address R5888 (0x1700) GPIO1_CTRL_1 to R5918 (0x171E) GPIO16_CTRL1 192 Bit 15 Label GPn_LVL 14 GPn_OP_CFG 13 GPn_DB 12 GPn_POL 9:0 GPn_FN[9:0] Default Description See GPIOn level. Write to this bit to set a GPIO output. Read from this bit to read GPIO Footnote 2 input level. For output functions only, if GPn_POL is set, the GPn_LVL bit is the opposite logic level to the external pin. Note that, if GPn_DIR = 0, the GPn_LVL bit is write-only. 0 GPIOn Output Configuration 0 = CMOS 1 = Open drain Note that, if GPn_FN = 0x000 or 0x002, this bit has no effect on the GPIOn output. If GPn_FN = 0x000, the pin configuration is set according to the applicable pin-specific function (see Table 4-95). If GPn_FN = 0x002, the pin configuration is CMOS. 1 GPIOn Input Debounce 0 = Disabled 1 = Enabled 0 GPIOn Output Polarity Select 0 = Noninverted (Active High) 1 = Inverted (Active Low) Note that, if GPn_FN = 0x000 or 0x002, this bit has no effect on the GPIOn output. 0x001 GPIOn Pin Function (see Table 4-94 for details) DS1162F1 CS42L92 4.14 General-Purpose I/O Table 4-93. GPIO Control (Cont.) Register Address R5889 (0x1701) GPIO1_CTRL_2 to R5919 (0x171F) GPIO16_CTRL2 Bit 15 Label GPn_DIR Default 1 Description GPIOn Pin Direction 0 = Output 1 = Input Note that, if GPn_FN = 0x000 or 0x002, this bit has no effect on the GPIOn pin. If GPn_FN = 0x000, the pin direction is set according to the applicable pin-specific function (see Table 4-95). If GPn_FN = 0x002, the pin direction is set according to the DSP GPIO configuration. 14 GPn_PU 1 GPIOn Pull-Up Enable 0 = Disabled 1 = Enabled Note: If GPn_PD and GPn_PU are both set, a bus keeper function is enabled on the respective GPIOn pin. 13 GPn_PD 1 GPIOn Pull-Down Enable 0 = Disabled 1 = Enabled Note: If GPn_PD and GPn_PU are both set, a bus keeper function is enabled on the respective GPIOn pin. R6848 (0x1AC0) 3:0 GP_DBTIME[3:0] 0x0 GPIO Input debounce time GPIO_Debounce_ 0x0 = 100 s Config 0x1 = 1.5 ms 0x2 = 3 ms 0x3 = 6 ms 0x4 = 12 ms 0x5 = 24 ms 0x6 = 48 ms 0x7 = 96 ms 0x8 = 192 ms 0x9 = 384 ms 0xA = 768 ms 0xB to 0xF = Reserved 1. n is a number (1–16) that identifies the individual GPIO. 2. The default value of GPn_LVL depends upon whether the pin is actively driven by another device. If the pin is actively driven, the bus keeper maintains this logic level. If the pin is not actively driven, the bus keeper may establish either a Logic 1 or Logic 0 as the initial input level. 4.14.2 GPIO Function Select The available GPIO functions are described in Table 4-94. The function of each GPIO is set using GPn_FN, where n identifies the GPIO pin (1–16). Note that the respective GPn_DIR must also be set according to whether the function is an input or output. Table 4-94. GPIO Function Select GPn_FN Valid On 0x000 GPIO3–16 only 0x001 All GPIOs (1–16) 0x002 0x003 All GPIOs (1–16) All GPIOs (1–16) 0x004 All GPIOs (1–16) 0x010 0x011 GPIO1–4 only GPIO1–4 only DS1162F1 Description Pin-specific alternate function Comments Alternate functions supporting digital microphone, digital audio interface, master control interface, and PDM output functions. Button-detect input/logic-level output GPn_DIR = 0: GPIO pin logic level is set by GPn_LVL. GPn_DIR = 1: Button detect or logic level input. DSP GPIO Low latency input/output for DSP functions. IRQ1 output Interrupt (IRQ1) output 0 = IRQ1 not asserted 1 = IRQ1 asserted IRQ2 output Interrupt (IRQ2) output 0 = IRQ2 not asserted 1 = IRQ2 asserted FLL1 clock Clock output from FLL1 FLL2 clock Clock output from FLL2 193 CS42L92 4.14 General-Purpose I/O Table 4-94. GPIO Function Select (Cont.) GPn_FN Valid On 0x018 GPIO1–4 only Description FLL1 lock 0x019 GPIO1–4 only FLL2 lock 0x040 0x041 0x048 0x049 0x04C 0x088 GPIO1–4 only GPIO1–4 only All GPIOs (1–16) All GPIOs (1–16) All GPIOs (1–16) GPIO1–4 only OPCLK clock output OPCLK async clock output PWM1 output PWM2 output S/PDIF output ASRC1 IN1 lock 0x089 GPIO1–4 only ASRC1 IN2 lock 0x140 All GPIOs (1–16) Timer 1 status 0x150 GPIO1–4 only Event Log 1 FIFO not-empty status 0x230 All GPIOs (1–16) Alarm 1 Channel 1 status 0x231 All GPIOs (1–16) Alarm 1 Channel 2 status 0x232 All GPIOs (1–16) Alarm 1 Channel 3 status 0x233 All GPIOs (1–16) Alarm 1 Channel 4 status 0x280 0x281 GPIO3 or GPIO10 GPIO4 or GPIO9 Auxiliary PDM clock input/output Auxiliary PDM data output Comments Indicates FLL1 lock status 0 = Not locked 1 = Locked Indicates FLL2 lock status 0 = Not locked 1 = Locked Configurable clock output derived from SYSCLK Configurable clock output derived from ASYNCCLK Configurable PWM output PWM1 Configurable PWM output PWM2 IEC-60958-3–compatible S/PDIF output Indicates ASRC1 IN1 Lock status (ASRC IN1 paths convert from the ASRC1_RATE1 sample rate to the ASRC1_RATE2 sample rate.) 0 = Not locked 1 = Locked Indicates ASRC1 IN2 Lock status (ASRC IN2 paths convert from the ASRC1_RATE2 sample rate to the ASRC1_RATE1 sample rate.) 0 = Not locked 1 = Locked Timer 1 Status A pulse is output after the respective timer reaches its final count value. Event Log 1 FIFO Not-Empty status 0 = FIFO Empty 1 = FIFO Not Empty Alarm 1 Channel 1 Status A pulse is output when the respective alarm-trigger conditions are met. The pulse duration is configurable. Alarm 1 Channel 2 Status A pulse is output when the respective alarm-trigger conditions are met. The pulse duration is configurable. Alarm 1 Channel 3 Status A pulse is output when the respective alarm-trigger conditions are met. The pulse duration is configurable. Alarm 1 Channel 4 Status A pulse is output when the respective alarm-trigger conditions are met. The pulse duration is configurable. Auxiliary PDM interface clock Auxiliary PDM interface data 4.14.3 Pin-Specific Alternate Function—GPn_FN = 0x000 The CS42L92 provides two dedicated GPIO pins (1–2). The remaining 14 GPIOs are multiplexed with the pin-specific functions listed in Table 4-95. The alternate functions are selected by setting the respective GPn_FN fields to 0x000, as described in Section 4.14.1. Note that each function is unique to the associated pin and can be supported only on that pin. If the alternate function is selected on a GPIO pin, the pin direction (input or output) and the output driver configuration (CMOS or open drain) are set automatically as described in Table 4-95. The respective GPn_DIR and GPn_OP_CFG bits have no effect in this case. Table 4-95. GPIO Alternate Functions Name AIF1BCLK/GPIO6 AIF1LRCLK/GPIO8 AIF1RXDAT/GPIO7 194 Condition GP6_FN = 0x000 GP8_FN = 0x000 GP7_FN = 0x000 Description Direction Audio Interface 1 bit clock Digital I/O Audio Interface 1 left/right clock Digital I/O Audio Interface 1 RX digital audio data Digital input Output Driver Configuration CMOS CMOS — DS1162F1 CS42L92 4.14 General-Purpose I/O Table 4-95. GPIO Alternate Functions (Cont.) Name AIF1TXDAT/GPIO5 AIF2BCLK/GPIO10 AIF2LRCLK/GPIO12 AIF2RXDAT/GPIO11 AIF2TXDAT/GPIO9 AIF3BCLK/GPIO14 AIF3LRCLK/GPIO16 AIF3RXDAT/GPIO15 AIF3TXDAT/GPIO13 SPKCLK/GPIO3 SPKDAT/GPIO4 Condition GP5_FN = 0x000 GP10_FN = 0x000 GP12_FN = 0x000 GP11_FN = 0x000 GP9_FN = 0x000 GP14_FN = 0x000 GP16_FN = 0x000 GP15_FN = 0x000 GP13_FN = 0x000 GP3_FN = 0x000 GP4_FN = 0x000 Description Audio Interface 1 TX digital audio data Audio Interface 2 bit clock Audio Interface 2 left/right clock Audio Interface 2 RX digital audio data Audio Interface 2 TX digital audio data Audio Interface 3 bit clock Audio Interface 3 left/right clock Audio Interface 3 RX digital audio data Audio Interface 3 TX digital audio data Digital speaker (PDM) clock Digital speaker (PDM) data Direction Digital output Digital I/O Digital I/O Digital input Digital output Digital I/O Digital I/O Digital input Digital output Digital output Digital output Output Driver Configuration CMOS CMOS CMOS — CMOS CMOS CMOS — CMOS CMOS CMOS Note that if the JTAG interface is enabled, the GPIO13–15 pins are configured as a JTAG interface. Under these conditions, the respective GPIO configuration registers have no effect, and the GPIO pins cannot be assigned any other function. See Section 4.20 for details of the JTAG interface. 4.14.4 Button Detect (GPIO Input)—GPn_FN = 0x001 Button-detect functionality can be selected on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. The same functionality can be used to support a jack-detect input function. It is recommended to enable the GPIO input debounce feature when using GPIOs as button input or jack-detect input. The GPn_LVL fields may be read to determine the logic levels on a GPIO input, after the selectable debounce controls. Note that GPn_LVL is not affected by the GPn_POL bit. The debounced GPIO signals are also inputs to the interrupt-control circuit. An interrupt event is triggered on the rising and falling edges of the GPIO input. The associated interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal. See Section 4.15 for details of the interrupt event handling. 4.14.5 Logic 1 and Logic 0 Output (GPIO Output)—GPn_FN = 0x001 The CS42L92 can be programmed to drive a logic high or logic low level on a GPIO pin by selecting the GPIO Output function as described in Section 4.14.1. The output logic level is selected using the respective GPn_LVL bit. Note that, if a GPIO pin is configured as an output, the respective GPn_LVL bits are write-only. The polarity of the GPIO output can be inverted using the GPn_POL bits. If GPn_POL = 1, the external output is the opposite logic level to GPn_LVL. 4.14.6 DSP GPIO (Low-Latency DSP Input/Output)—GPn_FN = 0x002 The DSP GPIO function provides an advanced I/O capability for signal-processing applications. The DSP GPIO pins are accessed using maskable sets of I/O control registers; this allows the selected combinations of GPIOs to be controlled with ease, regardless of how the allocation of GPIO pins has been implemented in hardware. The DSP GPIO function is selected by setting the respective GPIO fields as described in Section 4.14.1. A full description of the DSP GPIO function is provided in Section 4.5.4. Note that, if GPn_FN is set to 0x002, the respective pin direction (input or output) is set according to the DSP GPIO configuration for that pin—the GPn_DIR control bit has no effect in this case. DS1162F1 195 CS42L92 4.14 General-Purpose I/O 4.14.7 Interrupt (IRQ) Status Output—GPn_FN = 0x003, 0x004 The CS42L92 has an interrupt controller, which can be used to indicate when any selected interrupt events occur. Individual interrupts may be masked in order to configure the interrupt as required. See Section 4.15 for a full definition of all supported interrupt events. The interrupt controller supports two separate interrupt request (IRQ) outputs. The IRQ1 or IRQ2 status may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. Note that the IRQ1 status is output on the IRQ pin at all times. 4.14.8 Frequency-Locked Loop (FLL) Clock Output—GPn_FN = 0x010, 0x011 Clock outputs derived from the FLLs may be output on a GPIO pin. The GPIO output from each FLLn (FLL1 or FLL2) is controlled by the respective FLLn_GPCLK_DIV and FLLn_GPCLK_ENA fields, as described in Table 4-96. It is recommended to disable the clock output (FLLn_GPCLK_ENA = 0) before making any change to the respective FLLn_GPCLK_DIV field. Note that FLLn_GPCLK_DIV and FLLn_GPCLK_ENA affect the GPIO outputs only; they do not affect the FLL frequency. The maximum output frequency supported for GPIO output is noted in Table 3-10. The FLL clock outputs may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. See Section 4.16 for details of the CS42L92 system clocking and how to configure the FLLs. Table 4-96. FLL Clock Output Control Register Address R398 (0x018E) FLL1_GPIO_Clock R430 (0x01AE) FLL2_GPIO_Clock Bit 7:1 Label FLL1_GPCLK_ DIV[6:0] Default 0x02 0 FLL1_GPCLK_ ENA 0 7:1 FLL2_GPCLK_ DIV[6:0] 0x02 0 FLL2_GPCLK_ ENA 0 Description FLL1 GPIO Clock Divider 0x00 = Reserved 0x01 = Reserved 0x02 = Divide by 2 0x03 = Divide by 3 0x04 = Divide by 4 … 0x7F = Divide by 127 (FGPIO = FFLL/FLL1_GPCLK_DIV) FLL1 GPIO Clock Enable 0 = Disabled 1 = Enabled FLL2 GPIO Clock Divider 0x00 = Reserved 0x01 = Reserved 0x02 = Divide by 2 0x03 = Divide by 3 0x04 = Divide by 4 … 0x7F = Divide by 127 (FGPIO = FFLL/FLL2_GPCLK_DIV) FLL2 GPIO Clock Enable 0 = Disabled 1 = Enabled 4.14.9 Frequency-Locked Loop (FLL) Status Output—GPn_FN = 0x018, 0x019 The CS42L92 provides FLL status flags, which may be used to control other events. The FLL lock signals indicate whether FLL lock has been achieved. See Section 4.16.8 for details of the FLLs. The FLL lock signals may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. 196 DS1162F1 CS42L92 4.14 General-Purpose I/O The FLL lock signals are inputs to the interrupt controller circuit. An interrupt event is triggered on the rising and falling edges of these signals. The associated interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal. See Section 4.15 for details of the interrupt event handling. 4.14.10 OPCLK and OPCLK_ASYNC Clock Output—GPn_FN = 0x040, 0x041 A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. The OPCLK frequency is controlled by OPCLK_DIV and OPCLK_SEL. The OPCLK output is enabled by setting OPCLK_ENA, as described in Table 4-97. A clock output (OPCLK_ASYNC) derived from ASYNCCLK can be output on a GPIO pin. The OPCLK_ASYNC frequency is controlled by OPCLK_ASYNC_DIV and OPCLK_ASYNC_SEL. The OPCLK_ASYNC output is enabled by setting OPCLK_ASYNC_ENA. It is recommended to disable the clock output (OPCLK_ENA = 0 or OPCLK_ASYNC_ENA = 0) before making any change to the respective OPCLK_DIV, OPCLK_SEL, OPCLK_ASYNC_DIV, or OPCLK_ASYNC_SEL fields. The OPCLK or OPCLK_ASYNC clock can be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. Note that the OPCLK source frequency cannot be higher than the SYSCLK frequency. The OPCLK_ASYNC source frequency cannot be higher than the ASYNCCLK frequency. The maximum output frequency supported for GPIO output is noted in Table 3-10. See Section 4.16 for details of the system clocks (SYSCLK and ASYNCCLK). Table 4-97. OPCLK Control Register Address Bit Label R329 (0x0149) 15 OPCLK_ENA Output_system_ clock 7:3 OPCLK_DIV[4:0] 2:0 OPCLK_SEL[2:0] DS1162F1 Default Description 0 OPCLK Enable 0 = Disabled 1 = Enabled 0x00 OPCLK Divider 0x02 = Divide by 2 0x04 = Divide by 4 0x06 = Divide by 6 … (even numbers only) 0x1E = Divide by 30 Note that only even numbered divisions (2, 4, 6, etc.) are valid selections. All other codes are reserved when the OPCLK signal is enabled. 000 OPCLK Source Frequency 000 = 6.144 MHz (5.6448 MHz) 001 = 12.288 MHz (11.2896 MHz) 010 = 24.576 MHz (22.5792 MHz) 011 = 49.152 MHz (45.1584 MHz) All other codes are reserved The frequencies in brackets apply for 44.1 kHz–related SYSCLK rates only (i.e., SAMPLE_RATE_n = 01XXX). The OPCLK Source Frequency must be less than or equal to the SYSCLK frequency. 197 CS42L92 4.14 General-Purpose I/O Table 4-97. OPCLK Control (Cont.) Register Address Bit Label R330 (0x014A) 15 OPCLK_ASYNC_ ENA Output_async_ lock 7:3 OPCLK_ASYNC_ DIV[4:0] 2:0 OPCLK_ASYNC_ SEL[2:0] Default Description 0 OPCLK_ASYNC Enable 0 = Disabled 1 = Enabled 0x00 OPCLK_ASYNC Divider 0x02 = Divide by 2 0x04 = Divide by 4 0x06 = Divide by 6 … (even numbers only) 0x1E = Divide by 30 Note that only even numbered divisions (2, 4, 6, etc.) are valid selections. All other codes are reserved when the OPCLK_ASYNC signal is enabled. 000 OPCLK_ASYNC Source Frequency 000 = 6.144 MHz (5.6448 MHz) 001 = 12.288 MHz (11.2896 MHz) 010 = 24.576 MHz (22.5792 MHz) 011 = 49.152 MHz (45.1584 MHz) All other codes are reserved The frequencies in brackets apply for 44.1 kHz–related ASYNCCLK rates only (i.e., ASYNC_SAMPLE_RATE_n = 01XXX). The OPCLK_ASYNC Source Frequency must be less than or equal to the ASYNCCLK frequency. 4.14.11 Pulse-Width Modulation (PWM) Signal Output—GPn_FN = 0x048, 0x049 The CS42L92 incorporates two PWM signal generators, which can be enabled as GPIO outputs. The duty cycle of each PWM signal can be modulated by an audio source, or can be set to a fixed value using a control register setting. The PWM outputs may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. See Section 4.3.12 for details of how to configure the PWM signal generators. 4.14.12 S/PDIF Audio Output—GPn_FN = 0x04C The CS42L92 incorporates an IEC-60958-3–compatible S/PDIF transmitter, which can be selected as a GPIO output. The S/PDIF transmitter supports stereo audio channels and allows full control over the S/PDIF validity bits and channel status information. The S/PDIF signal may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. See Section 4.3.8 for details of how to configure the S/PDIF output generator. 4.14.13 ASRC Lock Status Output—GPn_FN = 0x088, 0x089 The CS42L92 provides ASRC status flags, which may be used to control other events. The ASRC-lock signals indicate whether ASRC lock has been achieved. See Section 4.3.15 for details of the ASRCs. The ASRC lock signals may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. The ASRC lock signals are inputs to the interrupt control circuit. An interrupt event is triggered on the rising and falling edges of the ASRC lock signals. The associated interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal. See Section 4.15 for details of the interrupt event handling. 198 DS1162F1 CS42L92 4.14 General-Purpose I/O 4.14.14 General-Purpose Timer Status Output—GPn_FN = 0x140 The general-purpose timer can count up or down, and supports continuous or single count modes. A status output, indicating the progress of the timer, is provided. See Section 4.5.3 for details of the general-purpose timer. A logic signal from the general-purpose timer may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. This logic signal is pulsed high whenever the timer reaches its final count value. The general-purpose timer also provides input to the interrupt control circuit. An interrupt event is triggered whenever the timer reaches its final count value. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See Section 4.15 for details of the interrupt event handling. 4.14.15 Event Logger FIFO Buffer Status Output—GPn_FN = 0x150 The event logger incorporates a 16-stage FIFO buffer, in which any detected events (signal transitions) are recorded. A status output for the FIFO buffer is provided. See Section 4.5.1 for details of the event logger. A logic signal from the event logger may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. This logic signal is set high whenever the FIFO not-empty condition is true. The event logger also provides input to the interrupt control circuit. An interrupt event is triggered whenever the FIFO condition occurs. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See Section 4.15 for details of the interrupt event handling. 4.14.16 Alarm Generator Status Output—GPn_FN = 0x230, 0x231, 0x232, 0x233 The CS42L92 incorporates four alarm-generator circuits that are associated with the general-purpose timer. A status output is provided by each alarm; these can be used to indicate one-off events, or can be configured for cyclic (repeated) triggers. See Section 4.5.2 for details of the alarm-control circuits. The alarm status may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. The alarm status is asserted when the respective alarm-trigger conditions are met. The signal is asserted for a duration that is configurable as described in Section 4.5.2.1. The alarm generators also provide input to the interrupt control circuit. An interrupt event is triggered whenever the alarm-trigger conditions are met. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See Section 4.15 for details of the interrupt event handling. 4.14.17 Auxiliary PDM Interface—GPn_FN = 0x280, 0x281 The CS42L92 provides an auxiliary PDM interface that can be used to provide an audio path between an analog microphone connected to the CS42L92 and a digital input to an external audio processor. The external connections to the auxiliary PDM interface are supported on GPIO pins as follows: • In Master Mode (AUXPDM1_MSTR = 1), the CLK output can be configured on the GPIO3 or GPIO10 pins. The DAT output can be configured on GPIO4 or GPIO9. • In Slave Mode (AUXPDM1_MSTR = 0), the CLK input is supported on GPIO10 only. The DAT output is supported on GPIO9 only. The applicable GPIO pins are configured by setting the respective GPIO fields as described in Section 4.14.1. See Section 4.2.10 for details of how to configure the auxiliary PDM interface. 4.14.18 General-Purpose Switch The CS42L92 provides two general-purpose switches, which can be used as controllable analog switches for external functions. The switches support bidirectional analog operation, offering flexibility in the potential circuit applications. Refer to Table 3-2 and Table 3-10 for further details. Note that this feature is entirely independent of the GPIOn pins. • The GP1 switch is implemented between the GPSW1P and GPSW1N pins; it is configured using SW1_MODE. • The GP2 switch is implemented between the GPSW2P and GPSW2N pins; it is configured using SW2_MODE. DS1162F1 199 CS42L92 4.15 Interrupts The SWn_MODE fields allow the switches to be disabled, enabled, or synchronized to the MICDET clamp status, as described in Table 4-98. The switches can be used in conjunction with the MICDET clamp function to suppress pops and clicks associated with jack insertion and removal. An example circuit is shown in Fig. 4-60 within Section 4.12.2. Note that the MICDET clamp function must also be configured appropriately when using this method of pop suppression. Table 4-98. General-Purpose Switch Control Register Address R712 (0x02C8) GP_Switch_1 Bit 3:2 Label SW2_MODE[1:0] Default 00 1:0 SW1_MODE[1:0] 00 Description General-purpose Switch 2 control 00 = Disabled (switch open) 01 = Enabled (switch closed) 10 = Enabled if MICDET clamp status is set 11 = Enabled if MICDET clamp status is clear General-purpose Switch 1 control 00 = Disabled (switch open) 01 = Enabled (switch closed) 10 = Enabled if MICDET clamp status is set 11 = Enabled if MICDET clamp status is clear 4.15 Interrupts The interrupt controller has multiple inputs. These include the jack detect and GPIO input pins, DSP_IRQn flags, headphone/accessory detection, FLL/ASRC lock detection, and status flags from DSP peripheral functions. See Table 4-99 and Table 4-100 for a full definition of the interrupt controller inputs. Any combination of these inputs can be used to trigger an interrupt request event. The interrupt controller supports two sets of interrupt registers. This allows two separate interrupt request (IRQ) outputs to be generated, and for each IRQ to report a different set of input or status conditions. For each interrupt request (IRQ1 and IRQ2) output, there is an interrupt register field associated with each interrupt input. These fields are asserted whenever a logic edge is detected on the respective input. Some inputs are triggered on rising edges only; some are triggered on both edges. Separate rising and falling interrupt bits are provided for the JD1 and JD2 signals. The interrupt register fields for IRQ1 are described in Table 4-99. The interrupt register fields for IRQ2 are described in Table 4-100. The interrupt flags can be polled at any time or in response to the interrupt request output being signaled via the IRQ pin or a GPIO pin. All interrupts are edge triggered, as noted above. Many are triggered on both the rising and falling edges and, therefore, the interrupt bits cannot indicate which edge has been detected. The raw status fields described in Table 4-99 and Table 4-100 indicate the current value of the corresponding inputs to the interrupt controller. Note that the raw status bits associated with IRQ1 and IRQ2 provide the same information. The status of any GPIO (or DSP GPIO) inputs can also be read using the GPIO (or DSP GPIO) control fields, as described in Table 4-93 and Table 4-41. Individual mask bits can enable or disable different functions from the interrupt controller. The mask bits are described in Table 4-99 (for IRQ1) and Table 4-100 (for IRQ2). Note that a masked interrupt input does not assert the corresponding interrupt register field and does not cause the associated interrupt request output to be asserted. The interrupt request outputs represent the logical OR of the associated interrupt registers. IRQ1 is derived from the x_ EINT1 registers; IRQ2 is derived from the x_EINT2 registers. The interrupt register fields are latching fields and, once they are set, they are not reset until a 1 is written to the respective bits. The interrupt request outputs are not reset until each of the associated interrupts has been reset. A debounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled on each pin using the fields described in Table 4-93. The GPIO debounce circuit uses the 32-kHz clock, which must be enabled whenever the GPIO debounce function is required. A debounce circuit is always enabled on the FLL status inputs—either the 32-kHz clock or the SYSCLK signal must be enabled to trigger an interrupt from the FLL status inputs. Note that the raw status fields (described in Table 4-99 and Table 4-100) are valid without clocking; these fields can be used to provide FLL status readback if system clocks are not available. 200 DS1162F1 CS42L92 4.15 Interrupts The IRQ outputs can be globally masked using the IM_IRQ1 and IM_IRQ2 bits. When not masked, the IRQ status can be read from IRQ1_STS and IRQ2_STS for the respective IRQ outputs. The IRQ1 output is provided externally on the IRQ pin. Under default conditions, this output is active low. The polarity can be inverted using IRQ_POL. The IRQ output can be either CMOS driven or open drain; this is selected using the IRQ_ OP_CFG bit. The IRQ output is active low and is referenced to the DBVDD power domain. The IRQ2 status can be used to trigger DSP firmware execution; see Section 4.4. This allows the DSP firmware execution to be linked to external events (e.g., jack detection, or GPIO input), or to any of the status conditions flagged by the interrupt registers. The IRQ1 and IRQ2 signals may be output on a GPIO pin; see Section 4.14. The CS42L92 interrupt controller circuit is shown in Fig. 4-64. (Note that not all interrupt inputs are shown.) The control fields associated with IRQ1 and IRQ2 are described in Table 4-99 and Table 4-100 respectively. The global interrupt mask bits, status bits, and output configuration fields are described Table 4-101. xxx_STSn xxx_STSn GP1_STSn FLL1_LOCK_STSn DRC1_SIG_DET_STSn INPUTS_SIG_DET_STSn De-bouncing & Edge detection Note that, under default register conditions, the boot done status is the only unmasked interrupt source; a falling edge on the IRQ pin indicates completion of the boot sequence. xxx_EINT1 IM_xxx_EINT1 xxx_EINT1 IM_xxx_EINT1 GP1_EINT1 IM_GP1_EINT1 IRQ1_STS FLL1_LOCK_EINT1 IM_IRQ1 IM_FLL1_LOCK_EINT1 DRC1_SIG_DET_EINT1 IM_DRC1_SIG_DET_EINT1 INPUTS_SIG_DET_EINT1 IM_INPUTS_SIG_DET_EINT1 xxx_EINT2 IM_xxx_EINT2 xxx_EINT2 IM_xxx_EINT2 GP1_EINT2 IM_GP1_EINT2 IRQ2_STS FLL1_LOCK_EINT2 IM_IRQ2 IM_FLL1_LOCK_EINT2 DRC1_SIG_DET_EINT2 IM_DRC1_SIG_DET_EINT2 INPUTS_SIG_DET_EINT2 IM_INPUTS_SIG_DET_EINT2 Note: not all available interrupt sources are shown Figure 4-64. Interrupt Controller DS1162F1 201 CS42L92 4.15 Interrupts The IRQ1 interrupt, mask, and status control registers are described in Table 4-99. Table 4-99. Interrupt 1 Control Registers Register Address R6144 (0x1800) IRQ1_Status_1 R6145 (0x1801) IRQ1_Status_2 R6149 (0x1805) IRQ1_Status_6 R6150 (0x1806) IRQ1_Status_7 202 Bit 12 Label CTRLIF_ERR_EINT1 Default 0 9 SYSCLK_FAIL_EINT1 0 7 BOOT_DONE_EINT1 0 14 DSPCLK_ERR_EINT1 0 13 ASYNCCLK_ERR_EINT1 0 12 SYSCLK_ERR_EINT1 0 9 FLL2_LOCK_EINT1 0 8 FLL1_LOCK_EINT1 0 6 FLL2_REF_LOST_EINT1 0 5 FLL1_REF_LOST_EINT1 0 9 MICDET2_EINT1 0 8 MICDET1_EINT1 0 0 HPDET_EINT1 0 11 MICD_CLAMP2_FALL_EINT1 0 10 MICD_CLAMP2_RISE_EINT1 0 9 JD3_FALL_EINT1 0 8 JD3_RISE_EINT1 0 5 MICD_CLAMP1_FALL_EINT1 0 4 MICD_CLAMP1_RISE_EINT1 0 3 JD2_FALL_EINT1 0 2 JD2_RISE_EINT1 0 1 JD1_FALL_EINT1 0 0 JD1_RISE_EINT1 0 Description Control Interface Error Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. SYSCLK Fail Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Boot Done Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSPCLK Error Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. ASYNCCLK Error Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. SYSCLK Error Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. FLL2 Lock Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. FLL1 Lock Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. FLL2 Reference Lost Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. FLL1 Reference Lost Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Mic/Accessory Detect 2 Interrupt (Detection event triggered) Note: Cleared when a 1 is written. Mic/Accessory Detect 1 Interrupt (Detection event triggered) Note: Cleared when a 1 is written. Headphone Detect Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. MICDET Clamp 2 Interrupt (Falling edge triggered) Note: Cleared when a 1 is written. MICDET Clamp 2 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. JD3 Interrupt (Falling edge triggered) Note: Cleared when a 1 is written. JD3 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. MICDET Clamp 1 Interrupt (Falling edge triggered) Note: Cleared when a 1 is written. MICDET Clamp 1 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. JD2 Interrupt (Falling edge triggered) Note: Cleared when a 1 is written. JD2 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. JD1 Interrupt (Falling edge triggered) Note: Cleared when a 1 is written. JD1 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DS1162F1 CS42L92 4.15 Interrupts Table 4-99. Interrupt 1 Control Registers (Cont.) Register Address R6152 (0x1808) IRQ1_Status_9 R6154 (0x180A) IRQ1_Status_11 DS1162F1 Bit 9 Label ASRC1_IN2_LOCK_EINT1 Default 0 8 ASRC1_IN1_LOCK_EINT1 0 2 INPUTS_SIG_DET_EINT1 0 1 DRC2_SIG_DET_EINT1 0 0 DRC1_SIG_DET_EINT1 0 15 DSP_IRQ16_EINT1 0 14 DSP_IRQ15_EINT1 0 13 DSP_IRQ14_EINT1 0 12 DSP_IRQ13_EINT1 0 11 DSP_IRQ12_EINT1 0 10 DSP_IRQ11_EINT1 0 9 DSP_IRQ10_EINT1 0 8 DSP_IRQ9_EINT1 0 7 DSP_IRQ8_EINT1 0 6 DSP_IRQ7_EINT1 0 5 DSP_IRQ6_EINT1 0 4 DSP_IRQ5_EINT1 0 3 DSP_IRQ4_EINT1 0 2 DSP_IRQ3_EINT1 0 1 DSP_IRQ2_EINT1 0 0 DSP_IRQ1_EINT1 0 Description ASRC1 IN2 Lock Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. ASRC1 IN1 Lock Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. Input Path Signal-Detect Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. DRC2 Signal-Detect Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. DRC1 Signal-Detect Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. DSP IRQ16 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ15 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ14 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ13 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ12 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ11 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ10 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ9 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ8 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ7 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ6 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ5 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ4 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ3 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ2 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ1 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. 203 CS42L92 4.15 Interrupts Table 4-99. Interrupt 1 Control Registers (Cont.) Register Address R6155 (0x180B) IRQ1_Status_12 R6156 (0x180C) IRQ1_Status_13 R6157 (0x180D) IRQ1_Status_14 R6158 (0x180E) IRQ1_Status_15 204 Bit 9 Label HP4R_SC_EINT1 Default 0 8 HP4L_SC_EINT1 0 5 HP3R_SC_EINT1 0 4 HP3L_SC_EINT1 0 3 HP2R_SC_EINT1 0 2 HP2L_SC_EINT1 0 1 HP1R_SC_EINT1 0 0 HP1L_SC_EINT1 0 5 HP3R_ENABLE_DONE_EINT1 0 4 HP3L_ENABLE_DONE_EINT1 0 3 HP2R_ENABLE_DONE_EINT1 0 2 HP2L_ENABLE_DONE_EINT1 0 1 HP1R_ENABLE_DONE_EINT1 0 0 HP1L_ENABLE_DONE_EINT1 0 5 HP3R_DISABLE_DONE_EINT1 0 4 HP3L_DISABLE_DONE_EINT1 0 3 HP2R_DISABLE_DONE_EINT1 0 2 HP2L_DISABLE_DONE_EINT1 0 1 HP1R_DISABLE_DONE_EINT1 0 0 HP1L_DISABLE_DONE_EINT1 0 12 DFC_SATURATE_EINT1 0 Description HPOUT4R Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT4L Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT3R Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT3L Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT2R Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT2L Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT1R Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT1L Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT3R/HPOUT4R Enable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT3L/HPOUT4L Enable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT2R Enable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT2L Enable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT1R Enable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT1L Enable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT3R/HPOUT4R Disable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT3L/HPOUT4L Disable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT2R Disable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT2L Disable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT1R Disable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT1L Disable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DFC Saturate Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DS1162F1 CS42L92 4.15 Interrupts Table 4-99. Interrupt 1 Control Registers (Cont.) Register Address R6160 (0x1810) IRQ1_Status_17 Bit 15 GP16_EINT1 Default 0 14 GP15_EINT1 0 13 GP14_EINT1 0 12 GP13_EINT1 0 11 GP12_EINT1 0 10 GP11_EINT1 0 9 GP10_EINT1 0 8 GP9_EINT1 0 7 GP8_EINT1 0 6 GP7_EINT1 0 5 GP6_EINT1 0 4 GP5_EINT1 0 3 GP4_EINT1 0 2 GP3_EINT1 0 1 GP2_EINT1 0 0 GP1_EINT1 0 R6164 (0x1814) 0 TIMER1_EINT1 0 IRQ1_Status_21 R6165 (0x1815) 0 EVENT1_NOT_EMPTY_EINT1 0 IRQ1_Status_22 R6166 (0x1816) 0 EVENT1_FULL_EINT1 0 IRQ1_Status_23 R6167 (0x1817) 0 EVENT1_WMARK_EINT1 0 IRQ1_Status_24 R6168 (0x1818) 0 DSP1_DMA_EINT1 0 IRQ1_Status_25 R6170 (0x181A) 0 DSP1_START1_EINT1 0 IRQ1_Status_27 R6171 (0x181B) 0 DSP1_START2_EINT1 0 IRQ1_Status_28 R6173 (0x181D) 0 DSP1_BUSY_EINT1 0 0 DSP1_BUS_ERR_EINT1 0 IRQ1_Status_30 R6176 (0x1820) IRQ1_Status_33 DS1162F1 Label Description GPIO16 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO15 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO14 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO13 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO12 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO11 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO10 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO9 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO8 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO7 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO6 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO5 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO4 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO3 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO2 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO1 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. Timer 1 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Event Log 1 FIFO Not Empty Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Event Log 1 FIFO Full Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Event Log 1 FIFO Watermark Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP1 DMA Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP1 Start 1 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP1 Start 2 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP1 Busy Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP1 Bus Error Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. 205 CS42L92 4.15 Interrupts Table 4-99. Interrupt 1 Control Registers (Cont.) Register Address R6179 (0x1823) IRQ1_Status_36 Bit 3 Label TIMER_ALM1_CH4_EINT1 2 TIMER_ALM1_CH3_EINT1 1 TIMER_ALM1_CH2_EINT1 0 TIMER_ALM1_CH1_EINT1 R6208 (0x1840) to R6243 (0x1863) R6272 (0x1880) IRQ1_Raw_ Status_1 R6273 (0x1881) IRQ1_Raw_ Status_2 206 IM_* 12 CTRLIF_ERR_STS1 7 BOOT_DONE_STS1 14 DSPCLK_ERR_STS1 13 ASYNCCLK_ERR_STS1 12 SYSCLK_ERR_STS1 9 FLL2_LOCK_STS1 8 FLL1_LOCK_STS1 6 FLL2_REF_LOST_STS1 5 FLL1_REF_LOST_STS1 Default 0 Description Alarm 1 Channel 4 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. 0 Alarm 1 Channel 3 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. 0 Alarm 1 Channel 2 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. 0 Alarm 1 Channel 1 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. See For each x_EINT1 interrupt bit in R6144 to R6179, a Footnote 1 corresponding mask bit (IM_*) is provided in R6208 to R6243. The mask bits are coded as follows: 0 = Do not mask interrupt 1 = Mask interrupt 0 Control Interface Error Status 0 = Normal 1 = Control Interface Error 0 Boot Status 0 = Busy (boot sequence in progress) 1 = Idle (boot sequence completed) Control register writes should not be attempted until Boot Sequence has completed. 0 DSPCLK Error Interrupt Status 0 = Normal 1 = Insufficient DSPCLK cycles for one or more of the requested DSP1 clock frequencies 0 ASYNCCLK Error Interrupt Status 0 = Normal 1 = Insufficient ASYNCCLK cycles for the requested signal path functionality 0 SYSCLK Error Interrupt Status 0 = Normal 1 = Insufficient SYSCLK cycles for the requested signal path functionality 0 FLL2 Lock Status 0 = Not locked 1 = Locked 0 FLL1 Lock Status 0 = Not locked 1 = Locked 0 FLL2 Reference Lost Status 0 = Normal 1 = Reference Lost 0 FLL1 Reference Lost Status 0 = Normal 1 = Reference Lost DS1162F1 CS42L92 4.15 Interrupts Table 4-99. Interrupt 1 Control Registers (Cont.) Register Address R6278 (0x1886) IRQ1_Raw_ Status_7 R6280 (0x1888) IRQ1_Raw_ Status_9 DS1162F1 Bit 8 Label JD3_STS1 Default 0 4 MICD_CLAMP_STS1 0 2 JD2_STS1 0 0 JD1_STS1 0 9 ASRC1_IN2_LOCK_STS1 0 8 ASRC1_IN1_LOCK_STS1 0 2 INPUTS_SIG_DET_STS1 0 1 DRC2_SIG_DET_STS1 0 0 DRC1_SIG_DET_STS1 0 Description JACKDET3 input status 0 = Jack not detected 1 = Jack is detected (Assumes the JACKDET3 pin is pulled low on jack insertion.) MICDET Clamp status 0 = Clamp disabled 1 = Clamp enabled Separate _STS bits are not provided for each clamp—it is assumed that a maximum of one clamp is active at any time. The clamp override condition (MICD_CLAMPn_OVD = 1) is not indicated. JACKDET2 input status 0 = Jack not detected 1 = Jack is detected (Assumes the JACKDET2 pin is pulled low on jack insertion.) JACKDET1 input status 0 = Jack not detected 1 = Jack is detected (Assumes the JACKDET1 pin is pulled low on jack insertion.) ASRC1 IN2 Lock Status 0 = Not locked 1 = Locked ASRC1 IN1 Lock Status 0 = Not locked 1 = Locked Input Path Signal-Detect Status 0 = Normal 1 = Signal detected DRC2 Signal-Detect Status 0 = Normal 1 = Signal detected DRC1 Signal-Detect Status 0 = Normal 1 = Signal detected 207 CS42L92 4.15 Interrupts Table 4-99. Interrupt 1 Control Registers (Cont.) Register Address R6283 (0x188B) IRQ1_Raw_ Status_12 R6284 (0x188C) IRQ1_Raw_ Status_13 208 Bit 9 Label HP4R_SC_STS1 Default 0 8 HP4L_SC_STS1 0 5 HP3R_SC_STS1 0 4 HP3L_SC_STS1 0 3 HP2R_SC_STS1 0 2 HP2L_SC_STS1 0 1 HP1R_SC_STS1 0 0 HP1L_SC_STS1 0 5 HP3R_ENABLE_DONE_STS1 0 4 HP3L_ENABLE_DONE_STS1 0 3 HP2R_ENABLE_DONE_STS1 0 2 HP2L_ENABLE_DONE_STS1 0 1 HP1R_ENABLE_DONE_STS1 0 0 HP1L_ENABLE_DONE_STS1 0 Description HPOUT4R Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT4L Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT3R Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT3L Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT2R Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT2L Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT1R Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT1L Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT3R/HPOUT4R Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT3L/HPOUT4L Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT2R Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT2L Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT1R Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT1L Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) DS1162F1 CS42L92 4.15 Interrupts Table 4-99. Interrupt 1 Control Registers (Cont.) Register Address R6285 (0x188D) IRQ1_Raw_ Status_14 Bit 5 Label HP3R_DISABLE_DONE_STS1 Default 0 4 HP3L_DISABLE_DONE_STS1 0 3 HP2R_DISABLE_DONE_STS1 0 2 HP2L_DISABLE_DONE_STS1 0 1 HP1R_DISABLE_DONE_STS1 0 0 HP1L_DISABLE_DONE_STS1 0 R6293 (0x1895) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 GP16_STS1 GP15_STS1 GP14_STS1 GP13_STS1 GP12_STS1 GP11_STS1 GP10_STS1 GP9_STS1 GP8_STS1 GP7_STS1 GP6_STS1 GP5_STS1 GP4_STS1 GP3_STS1 GP2_STS1 GP1_STS1 EVENT1_NOT_EMPTY_STS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ1_Raw_ Status_22 R6294 (0x1896) 0 EVENT1_FULL_STS1 0 IRQ1_Raw_ Status_23 R6295 (0x1897) 0 EVENT1_WMARK_STS1 0 IRQ1_Raw_ Status_24 R6296 (0x1898) 0 DSP1_DMA_STS1 0 0 DSP1_BUSY_STS1 0 R6288 (0x1890) IRQ1_Raw_ Status_17 IRQ1_Raw_ Status_25 R6301 (0x189D) IRQ1_Raw_ Status_30 DS1162F1 Description HPOUT3R/HPOUT4R Disable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT3L/HPOUT4L Disable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT2R Disable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT2L Disable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT1R Disable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT1L Disable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) GPIOn Input status. Reads back the logic level of GPIOn. Only valid for pins configured as GPIO input (does not include DSPGPIO inputs). Event Log 1 FIFO Not-Empty status 0 = FIFO Empty 1 = FIFO Not Empty Event Log 1 FIFO Full status 0 = FIFO Not Full 1 = FIFO Full Event Log 1 FIFO Watermark status 0 = FIFO Watermark not reached 1 = FIFO Watermark reached DSP1 DMA status 0 = Normal 1 = All enabled WDMA buffers filled, and all enabled RDMA buffers emptied DSP1 Busy status 0 = DSP Idle 1 = DSP Busy 209 CS42L92 4.15 Interrupts Table 4-99. Interrupt 1 Control Registers (Cont.) Register Address R6307 (0x18A3) IRQ1_Raw_ Status_36 Bit 3 Label TIMER_ALM1_CH4_STS1 Default 0 2 TIMER_ALM1_CH3_STS1 0 1 TIMER_ALM1_CH2_STS1 0 0 TIMER_ALM1_CH1_STS1 0 Description Alarm 1 Channel 4 status 0 = Alarm idle 1 = Alarm output asserted Alarm 1 Channel 3 status 0 = Alarm idle 1 = Alarm output asserted Alarm 1 Channel 2 status 0 = Alarm idle 1 = Alarm output asserted Alarm 1 Channel 1 status 0 = Alarm idle 1 = Alarm output asserted 1.The BOOT_DONE_EINT1 interrupt is 0 (unmasked) by default; all other interrupts are 1 (masked) by default. The IRQ2 interrupt, mask, and status control registers are described in Table 4-100. Table 4-100. Interrupt 2 Control Registers Register Address R6400 (0x1900) IRQ2_Status_1 R6401 (0x1901) IRQ2_Status_2 R6405 (0x1905) IRQ2_Status_6 210 Bit 12 Label CTRLIF_ERR_EINT2 Default 0 9 SYSCLK_FAIL_EINT2 0 7 BOOT_DONE_EINT2 0 14 DSPCLK_ERR_EINT2 0 13 ASYNCCLK_ERR_EINT2 0 12 SYSCLK_ERR_EINT2 0 9 FLL2_LOCK_EINT2 0 8 FLL1_LOCK_EINT2 0 6 FLL2_REF_LOST_EINT2 0 5 FLL1_REF_LOST_EINT2 0 9 MICDET2_EINT2 0 8 MICDET1_EINT2 0 0 HPDET_EINT2 0 Description Control Interface Error Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. SYSCLK Fail Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Boot Done Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSPCLK Error Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. ASYNCCLK Error Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. SYSCLK Error Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. FLL2 Lock Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. FLL1 Lock Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. FLL2 Reference Lost Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. FLL1 Reference Lost Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Mic/Accessory Detect 2 Interrupt (Detection event triggered) Note: Cleared when a 1 is written. Mic/Accessory Detect 1 Interrupt (Detection event triggered) Note: Cleared when a 1 is written. Headphone Detect Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DS1162F1 CS42L92 4.15 Interrupts Table 4-100. Interrupt 2 Control Registers (Cont.) Register Address R6406 (0x1906) IRQ2_Status_7 R6408 (0x1908) IRQ2_Status_9 DS1162F1 Bit 3 Label JD3_FALL_EINT2 Default 0 2 JD3_RISE_EINT2 0 5 MICD_CLAMP_FALL_EINT2 0 4 MICD_CLAMP_RISE_EINT2 0 3 JD2_FALL_EINT2 0 2 JD2_RISE_EINT2 0 1 JD1_FALL_EINT2 0 0 JD1_RISE_EINT2 0 9 ASRC1_IN2_LOCK_EINT2 0 8 ASRC1_IN1_LOCK_EINT2 0 2 INPUTS_SIG_DET_EINT2 0 1 DRC2_SIG_DET_EINT2 0 0 DRC1_SIG_DET_EINT2 0 Description JD3 Interrupt (Falling edge triggered) Note: Cleared when a 1 is written. JD3 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. MICDET Clamp Interrupt (Falling edge triggered) Indicates a falling edge transition on MICDET Clamp 1 or MICDET Clamp 2. Separate x_EINT2 bits are not provided—it is assumed that a maximum of one clamp is active at any time. Note: Cleared when a 1 is written. MICDET Clamp Interrupt (Rising edge triggered) Indicates a rising edge transition on MICDET Clamp 1 or MICDET Clamp 2. Separate x_EINT2 bits are not provided—it is assumed that a maximum of one clamp is active at any time. Note: Cleared when a 1 is written. JD2 Interrupt (Falling edge triggered) Note: Cleared when a 1 is written. JD2 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. JD1 Interrupt (Falling edge triggered) Note: Cleared when a 1 is written. JD1 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. ASRC1 IN2 Lock Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. ASRC1 IN1 Lock Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. Input Path Signal-Detect Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. DRC2 Signal-Detect Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. DRC1 Signal-Detect Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. 211 CS42L92 4.15 Interrupts Table 4-100. Interrupt 2 Control Registers (Cont.) Register Address R6410 (0x190A) IRQ2_Status_11 R6411 (0x190B) IRQ2_Status_12 212 Bit 15 Label DSP_IRQ16_EINT2 Default 0 14 DSP_IRQ15_EINT2 0 13 DSP_IRQ14_EINT2 0 12 DSP_IRQ13_EINT2 0 11 DSP_IRQ12_EINT2 0 10 DSP_IRQ11_EINT2 0 9 DSP_IRQ10_EINT2 0 8 DSP_IRQ9_EINT2 0 7 DSP_IRQ8_EINT2 0 6 DSP_IRQ7_EINT2 0 5 DSP_IRQ6_EINT2 0 4 DSP_IRQ5_EINT2 0 3 DSP_IRQ4_EINT2 0 2 DSP_IRQ3_EINT2 0 1 DSP_IRQ2_EINT2 0 0 DSP_IRQ1_EINT2 0 9 HP4R_SC_EINT2 0 8 HP4L_SC_EINT2 0 5 HP3R_SC_EINT2 0 4 HP3L_SC_EINT2 0 3 HP2R_SC_EINT2 0 2 HP2L_SC_EINT2 0 1 HP1R_SC_EINT2 0 0 HP1L_SC_EINT2 0 Description DSP IRQ16 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ15 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ14 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ13 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ12 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ11 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ10 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ9 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ8 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ7 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ6 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ5 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ4 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ3 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ2 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP IRQ1 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT4R Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT4L Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT3R Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT3L Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT2R Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT2L Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT1R Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT1L Short Circuit Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DS1162F1 CS42L92 4.15 Interrupts Table 4-100. Interrupt 2 Control Registers (Cont.) Register Address R6412 (0x190C) IRQ2_Status_13 R6413 (0x190D) IRQ2_Status_14 R6414 (0x190E) IRQ2_Status_15 DS1162F1 Bit 5 Label HP3R_ENABLE_DONE_EINT2 Default 0 4 HP3L_ENABLE_DONE_EINT2 0 3 HP2R_ENABLE_DONE_EINT2 0 2 HP2L_ENABLE_DONE_EINT2 0 1 HP1R_ENABLE_DONE_EINT2 0 0 HP1L_ENABLE_DONE_EINT2 0 5 HP3R_DISABLE_DONE_EINT2 0 4 HP3L_DISABLE_DONE_EINT2 0 3 HP2R_DISABLE_DONE_EINT2 0 2 HP2L_DISABLE_DONE_EINT2 0 1 HP1R_DISABLE_DONE_EINT2 0 0 HP1L_DISABLE_DONE_EINT2 0 12 DFC_SATURATE_EINT2 0 Description HPOUT3R/HPOUT4R Enable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT3L/HPOUT4L Enable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT2R Enable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT2L Enable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT1R Enable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT1L Enable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT3R/HPOUT4R Disable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT3L/HPOUT4L Disable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT2R Disable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT2L Disable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT1R Disable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. HPOUT1L Disable Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DFC Saturate Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. 213 CS42L92 4.15 Interrupts Table 4-100. Interrupt 2 Control Registers (Cont.) Register Address R6416 (0x1910) IRQ2_Status_17 Bit 15 GP16_EINT2 Default 0 14 GP15_EINT2 0 13 GP14_EINT2 0 12 GP13_EINT2 0 11 GP12_EINT2 0 10 GP11_EINT2 0 9 GP10_EINT2 0 8 GP9_EINT2 0 7 GP8_EINT2 0 6 GP7_EINT2 0 5 GP6_EINT2 0 4 GP5_EINT2 0 3 GP4_EINT2 0 2 GP3_EINT2 0 1 GP2_EINT2 0 0 GP1_EINT2 0 R6420 (0x1914) 0 TIMER1_EINT2 0 IRQ2_Status_21 R6421 (0x1915) 0 EVENT1_NOT_EMPTY_EINT2 0 IRQ2_Status_22 R6422 (0x1916) 0 EVENT1_FULL_EINT2 0 IRQ2_Status_23 R6423 (0x1917) 0 EVENT1_WMARK_EINT2 0 IRQ2_Status_24 R6424 (0x1918) 0 DSP1_DMA_EINT2 0 IRQ2_Status_25 R6426 (0x191A) 0 DSP1_START1_EINT2 0 IRQ2_Status_27 R6427 (0x191B) 0 DSP1_START2_EINT2 0 IRQ2_Status_28 R6429 (0x191D) 0 DSP1_BUSY_EINT2 0 0 DSP1_BUS_ERR_EINT2 0 IRQ2_Status_30 R6432 (0x1920) IRQ2_Status_33 214 Label Description GPIO16 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO15 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO14 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO13 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO12 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO11 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO10 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO9 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO8 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO7 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO6 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO5 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO4 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO3 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO2 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. GPIO1 Interrupt (Rising and falling edge triggered) Note: Cleared when a 1 is written. Timer 1 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Event Log 1 FIFO Not Empty Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Event Log 1 FIFO Full Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Event Log 1 FIFO Watermark Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP1 DMA Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP1 Start 1 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP1 Start 2 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP1 Busy Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DSP1 Bus Error Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. DS1162F1 CS42L92 4.15 Interrupts Table 4-100. Interrupt 2 Control Registers (Cont.) Register Address R6435 (0x1923) IRQ2_Status_36 Bit 3 Label TIMER_ALM1_CH4_EINT2 Default 0 2 TIMER_ALM1_CH3_EINT2 0 1 TIMER_ALM1_CH2_EINT2 0 0 TIMER_ALM1_CH1_EINT2 0 IM_* 1 12 CTRLIF_ERR_STS2 0 7 BOOT_DONE_STS2 0 14 DSPCLK_ERR_STS2 0 13 ASYNCCLK_ERR_STS2 0 12 SYSCLK_ERR_STS2 0 9 FLL2_LOCK_STS2 0 8 FLL1_LOCK_STS2 0 6 FLL2_REF_LOST_STS2 0 5 FLL1_REF_LOST_STS2 0 R6464 (0x1940) to R6499 (0x1963) R6528 (0x1980) IRQ2_Raw_ Status_1 R6529 (0x1981) IRQ2_Raw_ Status_2 DS1162F1 Description Alarm 1 Channel 4 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Alarm 1 Channel 3 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Alarm 1 Channel 2 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. Alarm 1 Channel 1 Interrupt (Rising edge triggered) Note: Cleared when a 1 is written. For each x_EINT2 interrupt bit in R6400 to R6435, a corresponding mask bit (IM_*) is provided in R6464 to R6499. The mask bits are coded as follows: 0 = Do not mask interrupt 1 = Mask interrupt Control Interface Error Status 0 = Normal 1 = Control Interface Error Boot Status 0 = Busy (boot sequence in progress) 1 = Idle (boot sequence completed) Control register writes should not be attempted until Boot Sequence has completed. DSPCLK Error Interrupt Status 0 = Normal 1 = Insufficient DSPCLK cycles for one or more of the requested DSP1 clock frequencies ASYNCCLK Error Interrupt Status 0 = Normal 1 = Insufficient ASYNCCLK cycles for the requested signal path functionality SYSCLK Error Interrupt Status 0 = Normal 1 = Insufficient SYSCLK cycles for the requested signal path functionality FLL2 Lock Status 0 = Not locked 1 = Locked FLL1 Lock Status 0 = Not locked 1 = Locked FLL2 Reference Lost Status 0 = Normal 1 = Reference Lost FLL1 Reference Lost Status 0 = Normal 1 = Reference Lost 215 CS42L92 4.15 Interrupts Table 4-100. Interrupt 2 Control Registers (Cont.) Register Address R6534 (0x1986) IRQ2_Raw_ Status_7 R6536 (0x1988) IRQ2_Raw_ Status_9 216 Bit 8 Label JD3_STS2 Default 0 4 MICD_CLAMP_STS2 0 2 JD2_STS2 0 0 JD1_STS2 0 9 ASRC1_IN2_LOCK_STS2 0 8 ASRC1_IN1_LOCK_STS2 0 2 INPUTS_SIG_DET_STS2 0 1 DRC2_SIG_DET_STS2 0 0 DRC1_SIG_DET_STS2 0 Description JACKDET3 input status 0 = Jack not detected 1 = Jack is detected (Assumes the JACKDET3 pin is pulled low on jack insertion.) MICDET Clamp status 0 = Clamp disabled 1 = Clamp enabled 0 = Clamp disabled 1 = Clamp enabled Separate _STS bits are not provided for each clamp—it is assumed that a maximum of one clamp is active at any time. The clamp override condition (MICD_CLAMPn_OVD = 1) is not indicated. JACKDET2 input status 0 = Jack not detected 1 = Jack is detected (Assumes the JACKDET2 pin is pulled low on jack insertion.) JACKDET1 input status 0 = Jack not detected 1 = Jack is detected (Assumes the JACKDET1 pin is pulled low on jack insertion.) ASRC1 IN2 Lock Status 0 = Not locked 1 = Locked ASRC1 IN1 Lock Status 0 = Not locked 1 = Locked Input Path Signal-Detect Status 0 = Normal 1 = Signal detected DRC2 Signal-Detect Status 0 = Normal 1 = Signal detected DRC1 Signal-Detect Status 0 = Normal 1 = Signal detected DS1162F1 CS42L92 4.15 Interrupts Table 4-100. Interrupt 2 Control Registers (Cont.) Register Address R6539 (0x198B) IRQ2_Raw_ Status_12 R6540 (0x198C) IRQ2_Raw_ Status_13 DS1162F1 Bit 9 Label HP4R_SC_STS2 Default 0 8 HP4L_SC_STS2 0 5 HP3R_SC_STS2 0 4 HP3L_SC_STS2 0 3 HP2R_SC_STS2 0 2 HP2L_SC_STS2 0 1 HP1R_SC_STS2 0 0 HP1L_SC_STS2 0 5 HP3R_ENABLE_DONE_STS2 0 4 HP3L_ENABLE_DONE_STS2 0 3 HP2R_ENABLE_DONE_STS2 0 2 HP2L_ENABLE_DONE_STS2 0 1 HP1R_ENABLE_DONE_STS2 0 0 HP1L_ENABLE_DONE_STS2 0 Description HPOUT4R Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT4L Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT3R Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT3L Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT2R Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT2L Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT1R Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT1L Short Circuit Status 0 = Normal 1 = Short Circuit detected HPOUT3R/HPOUT4R Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT3L/HPOUT4L Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT2R Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT2L Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT1R Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT1L Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) 217 CS42L92 4.15 Interrupts Table 4-100. Interrupt 2 Control Registers (Cont.) Register Address R6541 (0x198D) IRQ2_Raw_ Status_14 Bit 5 Label HP3R_DISABLE_DONE_STS2 Default 0 4 HP3L_DISABLE_DONE_STS2 0 3 HP2R_DISABLE_DONE_STS2 0 2 HP2L_DISABLE_DONE_STS2 0 1 HP1R_DISABLE_DONE_STS2 0 0 HP1L_DISABLE_DONE_STS2 0 R6549 (0x1995) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 GP16_STS2 GP15_STS2 GP14_STS2 GP13_STS2 GP12_STS2 GP11_STS2 GP10_STS2 GP9_STS2 GP8_STS2 GP7_STS2 GP6_STS2 GP5_STS2 GP4_STS2 GP3_STS2 GP2_STS2 GP1_STS2 EVENT1_NOT_EMPTY_STS2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ2_Raw_ Status_22 R6550 (0x1996) 0 EVENT1_FULL_STS2 0 IRQ2_Raw_ Status_23 R6551 (0x1997) 0 EVENT1_WMARK_STS2 0 IRQ2_Raw_ Status_24 R6552 (0x1998) 0 DSP1_DMA_STS2 0 0 DSP1_BUSY_STS2 0 R6544 (0x1990) IRQ2_Raw_ Status_17 IRQ2_Raw_ Status_25 R6557 (0x199D) IRQ2_Raw_ Status_30 218 Description HPOUT3R/HPOUT4R Disable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT3L/HPOUT4L Disable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT2R Disable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT2L Disable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT1R Disable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) HPOUT1L Disable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) GPIOn Input status Reads back the logic level of GPIOn. Only valid for pins configured as GPIO input (does not include DSPGPIO inputs). Event Log 1 FIFO Not-Empty status 0 = FIFO Empty 1 = FIFO Not Empty Event Log n FIFO Full status 0 = FIFO Not Full 1 = FIFO Full Event Log 1 FIFO Watermark status 0 = FIFO Watermark not reached 1 = FIFO Watermark reached DSP1 DMA status 0 = Normal 1 = All enabled WDMA buffers filled, and all enabled RDMA buffers emptied DSP1 Busy status 0 = DSP Idle 1 = DSP Busy DS1162F1 CS42L92 4.16 Clocking and Sample Rates Table 4-100. Interrupt 2 Control Registers (Cont.) Register Address R6563 (0x19A3) IRQ2_Raw_ Status_36 Bit 3 Label TIMER_ALM1_CH4_STS2 Default 0 2 TIMER_ALM1_CH3_STS2 0 1 TIMER_ALM1_CH2_STS2 0 0 TIMER_ALM1_CH1_STS2 0 Description Alarm 1 Channel 4 status 0 = Alarm idle 1 = Alarm output asserted Alarm 1 Channel 3 status 0 = Alarm idle 1 = Alarm output asserted Alarm 1 Channel 2 status 0 = Alarm idle 1 = Alarm output asserted Alarm 1 Channel 1 status 0 = Alarm idle 1 = Alarm output asserted The IRQ output and polarity control registers are described in Table 4-101. Table 4-101. Interrupt Control Registers Register Address R6784 (0x1A80) IRQ1_CTRL Bit 11 Label IM_IRQ1 Default 0 10 IRQ_POL 1 9 IRQ_OP_CFG 0 R6786 (0x1A82) IRQ2_CTRL 11 IM_IRQ2 0 R6816 (0x1AA0) Interrupt_Raw_ Status_1 1 IRQ2_STS 0 0 IRQ1_STS 0 Description IRQ1 Output Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. IRQ Output Polarity Select 0 = Noninverted (Active High) 1 = Inverted (Active Low) IRQ Output Configuration 0 = CMOS 1 = Open drain IRQ2 Output Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. IRQ2 Status. IRQ2_STS is the logical OR of all unmasked x_EINT2 interrupts. 0 = Not asserted 1 = Asserted IRQ1 Status. IRQ1_STS is the logical OR of all unmasked x_EINT1 interrupts. 0 = Not asserted 1 = Asserted 4.16 Clocking and Sample Rates The CS42L92 requires a clock reference for its internal functions and also for the input (ADC) paths, output (DAC) paths, and digital audio interfaces. Under typical clocking configurations, all commonly used audio sample rates can be derived directly from the external reference; for additional flexibility, the CS42L92 incorporates two FLL circuits to perform frequency conversion and filtering. External clock signals may be connected via the MCLK1, MCLK2, and MCLK3 input pins. In AIF Slave Modes, the BCLK signals may be used as a reference for the system clocks. The SLIMbus interface can provide the clock reference, when used as the input to one of the FLLs. To avoid audible glitches, all clock configurations must be set up before enabling playback. 4.16.1 System Clocking Overview The CS42L92 supports three primary clock domains—SYSCLK, ASYNCCLK, and DSPCLK. The SYSCLK and ASYNCCLK clock domains are the reference clocks for all the audio signal paths on the CS42L92. Up to five different sample rates may be independently selected for specific audio interfaces and other input/output signal paths; each selected sample rate must be synchronized either to SYSCLK or to ASYNCCLK, as described in Section 4.16.2. DS1162F1 219 CS42L92 4.16 Clocking and Sample Rates The SYSCLK and ASYNCCLK clock domains are independent (i.e., not synchronized). Stereo full-duplex sample-rate conversion is supported, allowing asynchronous audio data to be mixed and to be routed between independent interfaces. See Section 4.3 for further details. The DSPCLK clock domain is the reference clock for the programmable DSP core on the CS42L92. A wide range of DSPCLK frequencies can be supported, and a programmable clock divider is provided for the DSP core, allowing the DSP clocking (and power consumption) to be optimized according to the applicable processing requirements. See Section 4.3 for further details. Note that there is no requirement for DSPCLK to be synchronized to SYSCLK or ASYNCCLK. The DSPCLK controls the software execution in the DSP core; audio outputs from the DSP are synchronized either to SYSCLK or ASYNCCLK, regardless of the applicable DSPCLK rate. Excluding the DSP core, each subsystem within the CS42L92 digital core is clocked at a dynamically controlled rate, limited by the SYSCLK (or ASYNCCLK) frequency, as applicable. For maximum signal mixing and processing capacity, it is recommended that the highest possible SYSCLK and ASYNCCLK frequencies are configured. The DSP core is clocked at the DSPCLK rate (or supported divisions of the DSPCLK frequency). The DSPCLK configuration must ensure that sufficient clock cycles are available for the processing requirements of the DSP core. The requirements vary, according to the particular software that is in use. 4.16.2 Sample-Rate Control The CS42L92 supports two independent clock domains for the audio signal paths, referenced to SYSCLK and ASYNCCLK respectively. Different sample rates may be selected for each of the audio interfaces (AIF1, AIF2, AIF3, SLIMbus), and for the input (ADC) and output (DAC) paths. Each of these must be referenced either to SYSCLK or to ASYNCCLK. (Note that the SLIMbus interface supports multiple sample rates, selected independently for each input or output channel.) Up to three different sample rates can be selected using SAMPLE_RATE_1, SAMPLE_RATE_2 and SAMPLE_RATE_3. These must each be numerically related to each other and to the SYSCLK frequency (further details of these requirements are provided in Table 4-102 and the accompanying text). The remaining two sample rates can be selected using ASYNC_SAMPLE_RATE_1 and ASYNC_SAMPLE_RATE_2. These sample rates must be numerically related to each other and to the ASYNCCLK frequency (further details of these requirements are provided in Table 4-103 and the accompanying text), Each of the audio interfaces, input paths, and output paths is associated with one of the sample rates selected by the SAMPLE_RATE_n or ASYNC_SAMPLE_RATE_n fields. Note that if any two interfaces are operating at the same sample rate, but are not synchronized, one of these must be referenced to the ASYNCCLK domain, and the other to the SYSCLK domain. When any of the SAMPLE_RATE_n or ASYNC_SAMPLE_RATE_n fields is written to, the activation of the new setting is automatically synchronized by the CS42L92 to ensure continuity of all active signal paths. The SAMPLE_RATE_n_STS and ASYNC_SAMPLE_RATE_n_STS bits provide indication of the sample rate selections that have been implemented. 220 DS1162F1 CS42L92 4.16 Clocking and Sample Rates The following restrictions must be observed regarding the sample-rate control configuration: • Unless otherwise noted, the sample rate selection for all functions is valid from 8–192 kHz. • The input (ADC/DMIC) signal paths must always be associated with the SYSCLK clocking domain. • If 384- or 768-kHz DMICCLK clock rate is selected, the supported sample rate for the respective input paths is restricted as described in Table 4-1. The sample rate for the input signal paths can be set globally, or can be configured independently for each input channel—see Section 4.2.5. • The S/PDIF sample rate is valid from 32–192 kHz. The output (DAC), digital audio interface (AIF), DSP core, and SLIMbus input/output sample rates are valid from 8–384 kHz. • The asynchronous sample-rate converter (ASRC) supports sample rates 8–192 kHz. The ratio of the two sample rates must not exceed 6. • The isochronous sample-rate converters (ISRCs) support sample rates 8–384 kHz. For each ISRC, the ratio of the applicable SAMPLE_RATE_n or ASYNC_SAMPLE_RATE_n fields must not exceed 24. The sample-rate conversion ratio must be an integer (1–24) or equal to 1.5. • All external clock references (MCLK input or Slave Mode AIF input) must be within 1% of the applicable register field settings. 4.16.3 Automatic Sample-Rate Detection The CS42L92 supports automatic sample-rate detection on the digital audio interfaces (AIF1–AIF3). Note that this is only possible when the respective interface is operating in Slave Mode (i.e., when LRCLK and BCLK are inputs to the CS42L92). Automatic sample-rate detection is enabled by setting RATE_EST_ENA. The LRCLK input pin selected for sample-rate detection is set using LRCLK_SRC. As many as four audio sample rates can be configured for automatic detection; these sample rates are selected using the SAMPLE_RATE_DETECT_n fields. Note that the function only detects sample rates that match one of the SAMPLE_ RATE_DETECT_n fields. If one of the selected audio sample rates is detected on the selected LRCLK input, the control-write sequencer is triggered. A unique sequence of actions may be programmed for each detected sample rate. Note that the applicable control sequences must be programmed by the user for each detection outcome; see Section 4.18. The TRIG_ON_STARTUP bit controls whether the sample-rate detection circuit responds to the initial detection of the applicable interface (i.e., when the AIFn interface starts up). • If TRIG_ON_STARTUP = 0, the detection circuit only responds (i.e., trigger the control-write sequencer) to a change in the detected sample rate—the initial sample-rate detection is ignored. (Note that the initial sample-rate detection is the first detection of a sample rate that matches one of the SAMPLE_RATE_DETECT_n fields.) • If TRIG_ON_STARTUP = 1, the detection circuit triggers the control-write sequencer whenever a selected sample rate is detected, including when the AIF interface starts up, or when the sample-rate detection is first enabled. As described above, setting TRIG_ON_STARTUP = 0 is designed to inhibit any response to the initial detection of a sample rate that matches one of the SAMPLE_RATE_DETECT_n fields. Note that, if the LRCLK_SRC setting is changed, or if the detection function is disabled and reenabled, a subsequent detection of a matching sample rate may trigger the control-write sequencer, regardless of the TRIG_ON_STARTUP setting. There are some restrictions to be observed regarding the automatic sample-rate detection configuration, as noted in the following: • The same sample rate must not be selected on more than one of the SAMPLE_RATE_DETECT_n fields. • Sample rates 384 kHz and 352.8 kHz must not be selected concurrently. • Sample rates 192 kHz and 176.4 kHz must not be selected concurrently. • Sample rates 96 kHz and 88.2 kHz must not be selected concurrently. The control registers associated with the automatic sample-rate detection function are described in Table 4-104. DS1162F1 221 CS42L92 4.16 Clocking and Sample Rates 4.16.4 System Clock Configuration The system clocks (SYSCLK, ASYNCCLK and DSPCLK) may be provided directly from external inputs (MCLK, or Slave Mode BCLK inputs). Alternatively, these clocks can be derived using the integrated FLLs, with MCLK, BCLK, LRCLK or SLIMCLK as a reference. Each clock is configured independently, as described in the following sections. The SYSCLK (and ASYNCCLK, when applicable) clocks must be configured and enabled before any audio path is enabled. The DSPCLK clock must be configured and enabled, if running firmware applications on the DSP core. 4.16.4.1 SYSCLK Configuration The required SYSCLK frequency is dependent on the SAMPLE_RATE_n fields. Table 4-102 illustrates the valid SYSCLK frequencies for every supported sample rate. The SYSCLK frequency must be valid for all of the SAMPLE_RATE_n fields. It follows that all of the SAMPLE_RATE_n fields must select numerically-related values, that is, all from the same group of sample rates as represented in Table 4-102. Table 4-102. SYSCLK Frequency Selection SYSCLK Frequency (MHz) 6.144 12.288 24.576 49.152 98.304 SYSCLK_FREQ 000 001 010 011 100 SYSCLK_FRAC 0 Sample Rate (kHz) SAMPLE_RATE_n 12 0x01 24 0x02 48 0x03 96 0x04 192 0x05 384 0x06 8 0x11 16 0x12 32 0x13 5.6448 000 1 11.025 0x09 11.2896 001 22.05 0x0A 22.5792 010 44.1 0x0B 45.1584 011 88.2 0x0C 90.3168 100 176.4 0x0D 352.8 0x0E Note: The SAMPLE_RATE_n fields must each be set to a value from the same group of sample rates, and from the same group as the SYSCLK frequency. SYSCLK_SRC is used to select the SYSCLK source, as described in Table 4-104. The source may be MCLKn, AIFnBCLK, or FLLn. If an FLL circuit is selected as the source, the relevant FLL must be enabled and configured, as described in Section 4.16.8. Notes: If FLL1 is selected as SYSCLK source, two different clock frequencies are available. Typical use cases should select a SYSCLK frequency equal to FFLL1 × 2 (i.e., in the range 90–100 MHz). A lower frequency selection, equal to FFLL1, is provided to support low-power always-on use cases. If FLL2 is selected as SYSCLK source, the SYSCLK frequency is FFLL2 × 2 (i.e., 90–100 MHz). SYSCLK_FREQ and SYSCLK_FRAC must be set according to the frequency of the selected SYSCLK source. The SYSCLK-referenced circuits within the digital core are clocked at a dynamically controlled rate this is limited by the SYSCLK frequency. For maximum signal mixing and processing capacity, the highest possible SYSCLK frequency should be used. The SAMPLE_RATE_n fields are set according to the sample rates that are required by one or more of the CS42L92 audio interfaces. The CS42L92 supports sample rates ranging from 8–384 kHz. See Section 4.16.2 for further details of the supported sample rates for each of the digital-core functions. The SYSCLK signal is enabled by setting SYSCLK_ENA. The applicable clock source (MCLKn, AIFnBCLK, or FLLn) must be enabled before setting SYSCLK_ENA. This bit should be cleared before stopping or removing the applicable clock source. 222 DS1162F1 CS42L92 4.16 Clocking and Sample Rates The CS42L92 supports seamless switching between clock sources. To change the SYSCLK configuration while SYSCLK is enabled, the SYSCLK_FRAC, SYSCLK_FREQ, and SYSCLK_SRC fields must be updated together in one register write operation. Note that, if changing the frequency only (not the source), SYSCLK_ENA should be cleared before the clock frequency is updated. The current SYSCLK frequency and source can be read from the SYSCLK_FREQ_STS and SYSCLK_SRC_STS fields respectively. The CS42L92 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded signal paths and processing functions. If the frequency is too low, an attempt to enable a signal path or processing function fails. Note that active signal paths are not affected under such circumstances. The SYSCLK frequency check provides input to the interrupt-control circuit and can be used to trigger an interrupt event if the frequency is not high enough to support the commanded functionality; see Section 4.15. 4.16.4.2 ASYNCCLK Configuration The required ASYNCCLK frequency is dependent on the ASYNC_SAMPLE_RATE_n fields. Table 4-103 illustrates the valid ASYNCCLK frequencies for every supported sample rate. Note that, if all the sample rates in the system are synchronized to SYSCLK, the ASYNCCLK should be disabled (see Table 4-104). The associated register field values are not important in this case. Table 4-103. ASYNCCLK Frequency Selection ASYNCCLK Frequency (MHz) 6.144 12.288 24.576 49.152 98.304 ASYNC_CLK_FREQ 000 001 010 011 100 Sample Rate (kHz) ASYNC_SAMPLE_RATE_n 12 0x01 24 0x02 48 0x03 96 0x04 192 0x05 384 0x06 8 0x11 16 0x12 32 0x13 5.6448 000 11.025 0x09 11.2896 001 22.05 0x0A 22.5792 010 44.1 0x0B 45.1584 011 88.2 0x0C 90.3168 100 176.4 0x0D 352.8 0x0E Note: The ASYNC_SAMPLE_RATE_n fields must each be set to a value from the same group of sample rates, and from the same group as the ASYNCCLK frequency. ASYNC_CLK_SRC is used to select the ASYNCCLK source, as described in Table 4-104. The source may be MCLKn, AIFnBCLK, or FLLn. If an FLL circuit is selected as the source, the relevant FLL must be enabled and configured, as described in Section 4.16.8. Notes: If FLL1 is selected as ASYNCCLK source, two different clock frequencies are available. Typical use cases should select a SYSCLK frequency equal to FFLL1 × 2 (i.e., in the range 90–100 MHz). A lower frequency selection, equal to FFLL1, is provided to support low-power always-on use cases. If FLL2 is selected as ASYNCCLK source, the ASYNCCLK frequency is FFLL2 × 2 (i.e., 90–100 MHz). ASYNC_CLK_FREQ is set according to the frequency of the selected ASYNCCLK source. The ASYNCCLK-referenced circuits within the digital core are clocked at a dynamically controlled rate that is limited by the ASYNCCLK frequency. For maximum signal mixing and processing capacity, the highest possible ASYNCCLK frequency should be used. The ASYNC_SAMPLE_RATE_n fields are set according to the sample rates of any audio interface that is not synchronized to the SYSCLK clock domain. DS1162F1 223 CS42L92 4.16 Clocking and Sample Rates The ASYNCCLK signal is enabled by setting ASYNC_CLK_ENA. The applicable clock source (MCLKn, AIFnBCLK, or FLLn) must be enabled before setting ASYNC_CLK_ENA. This bit should be cleared before stopping or removing the applicable clock source. The CS42L92 supports seamless switching between clock sources. To change the ASYNCCLK configuration while ASYNCCLK is enabled, the ASYNC_CLK_FREQ and ASYNC_CLK_SRC fields must be updated together in one register write operation. Note that, if changing the frequency only (not the source), ASYNC_CLK_ENA should be cleared before the clock frequency is updated. The current ASYNCCLK frequency and source can be read from the ASYNC_CLK_ FREQ_STS and ASYNC_CLK_SRC_STS fields respectively. The CS42L92 performs automatic checks to confirm that the ASYNCCLK frequency is high enough to support the commanded signal paths and processing functions. If the frequency is too low, an attempt to enable a signal path or processing function fails. Note that active signal paths are not affected under such circumstances. The ASYNCCLK frequency check provides input to the interrupt-control circuit and can be used to trigger an interrupt event if the frequency is not high enough to support the commanded functionality; see Section 4.15. 4.16.4.3 DSPCLK Configuration The required DSPCLK frequency depends on the requirements of firmware loaded on the DSP core. The DSP is clocked at the DSPCLK rate or at supported divisions of the DSPCLK frequency; the DSPCLK configuration must ensure that sufficient clock cycles are available for the processing requirements. The requirements vary, according to the particular firmware that is in use. A configurable clock divider is provided for the DSP core, allowing the DSP clocking (and power consumption) to be optimized according to the applicable processing requirements; see Section 4.4 for details. DSP_CLK_FREQ must be configured for the applicable DSPCLK frequency. This field is coded in LSB units of 1/64 MHz. Note that, if the field coding cannot represent the DSPCLK frequency exactly, the DSPCLK frequency must be rounded down in the DSP_CLK_FREQ field. The suggested method for calculating DSP_CLK_FREQ is to multiply the DSPCLK frequency by 64, round down to the nearest integer, and use the resulting integer as DSP_CLK_FREQ (LSB = 1). DSP_CLK_SRC is used to select the DSPCLK source, as described in Table 4-104. The source may be MCLKn, AIFnBCLK, or FLLn. If an FLL circuit is selected as the source, the relevant FLL must be enabled and configured, as described in Section 4.16.8. Notes: If FLL1 is selected as DSPCLK source, two different clock frequencies are available. Typical use cases should select a DSPCLK frequency equal to FFLL1 × 3 (i.e., in the range 135–150 MHz). A lower frequency selection, equal to FFLL1, is provided to support low-power always-on use cases. If FLL2 is selected as DSPCLK source, the DSPCLK frequency is FFLL2 × 3 (i.e., 135–150 MHz). The DSPCLK signal is enabled by setting DSP_CLK_ENA. The applicable clock source (MCLKn, AIFnBCLK, or FLLn) must be enabled before setting DSP_CLK_ENA. This bit should be cleared when reconfiguring the clock sources. The CS42L92 supports seamless switching between clock sources. To change the DSPCLK configuration while DSPCLK is enabled, the DSP_CLK_FREQ field must be updated before DSP_CLK_SRC. The new configuration becomes effective when the DSP_CLK_SRC field is written. Note that, if changing the frequency only (not the source), the DSP_CLK_ENA bit should be cleared before the clock frequency is updated. The current DSPCLK frequency and source can be read from the DSP_CLK_FREQ_STS and DSP_CLK_SRC_STS fields respectively. In a typical application, DSPCLK and SYSCLK are derived from a single FLL source. Note that there is no requirement for DSPCLK to be synchronized to SYSCLK or ASYNCCLK. The DSPCLK controls the software execution in the DSP core; audio outputs from the DSP core are synchronized either to SYSCLK or ASYNCCLK, regardless of the applicable DSPCLK rate. 224 DS1162F1 CS42L92 4.16 Clocking and Sample Rates 4.16.5 Miscellaneous Clock Controls The CS42L92 incorporates a 32-kHz clock circuit, which is required for input signal debounce, microphone/accessory detect, and for the Charge Pump 2 (CP2) circuits. The 32-kHz clock must be configured and enabled whenever any of these features are used. The 32-kHz clock can be generated automatically from SYSCLK, or may be provided externally via the MCLK1 or MCLK2 input pins. The 32-kHz clock source is selected using CLK_32K_SRC. The 32-kHz clock is enabled by setting CLK_32K_ ENA. A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. A clock output (OPCLK_ASYNC) derived from ASYNCCLK can be output on a GPIO pin. See Section 4.14 for details on configuring a GPIO pin for these functions. The CS42L92 provides integrated pull-down resistors on the MCLK1, MCLK2, and MCLK3 pins. This provides a flexible capability for interfacing with other devices. The clocking scheme for the CS42L92 is shown in Fig. 4-65. DS1162F1 225 CS42L92 4.16 Clocking and Sample Rates 32k Clock CLK_32K_ENA p. 227 CLK_32K_SRC[1:0] p. 227 Divider (Auto) OPCLK OPCLK_ENA p. 231 MCLK1 MCLK2 MCLK3 Divider OPCLK_SEL[2:0] p. 231 OPCLK_DIV[4:0] p. 231 AIF1BCLK AIF2BCLK AIF3BCLK SYSCLK SYSCLK_ENA p. 227 x2 x2 OPCLK_ ASYNC SYSCLK_SRC[3:0] p. 227 OPCLK_ASYNC_ENA p. 231 Divider OPCLK_ASYNC_SEL[2:0] p. 231 OPCLK_ASYNC_DIV[4:0] p. 231 ASYNCCLK ASYNC_CLK_ENA p. 229 x2 x2 ASYNC_CLK_SRC[3:0] p. 229 DSPCLK DSP_CLK_ENA p. 230 x3 x3 DSP_CLK_SRC[3:0] p. 230 FLL1 GPIO Divider FLL1_GPCLK_ENA p. 196 FLL1_REFCLK_SRC[3:0] p. 239 FLL1_GPCLK_DIV[6:0] p. 196 (see note ) FLL2 GPIO Divider FLL2_GPCLK_ENA p. 196 FLL2_REFCLK_SRC[3:0] p. 241 FLL2_GPCLK_DIV[6:0] p. 196 (see note ) Automatic Clocking Control Note: AIFnLRCLK and SLIMCLK can also be selected as FLLn input reference . SYSCLK_FREQ[2:0] p. 227 SYSCLK_FRAC p. 227 ASYNC_CLK_FREQ[2:0] p. 229 DSP_CLK_FREQ[15:0] p. 230 SAMPLE_RATE_1[4:0] p. 228 SAMPLE_RATE_2[4:0] p. 228 SAMPLE_RATE_3[4:0] p. 228 ASYNC_SAMPLE_RATE_1[4:0] p. 229 ASYNC_SAMPLE_RATE_2[4:0] p. 229 Figure 4-65. System Clocking 226 DS1162F1 CS42L92 4.16 Clocking and Sample Rates The CS42L92 clocking control registers are described in Table 4-104. Table 4-104. Clocking Control Register Address R256 (0x0100) Clock_32k_1 R257 (0x0101) System_Clock_1 Bit 6 Label CLK_32K_ENA 1:0 CLK_32K_ SRC[1:0] 10 15 SYSCLK_FRAC 0 10:8 SYSCLK_ FREQ[2:0] 6 3:0 DS1162F1 SYSCLK_ENA SYSCLK_ SRC[3:0] Default 0 100 0 0100 Description 32kHz Clock Enable 0 = Disabled 1 = Enabled 32kHz Clock Source 00 = MCLK1 (direct) 01 = MCLK2 (direct) 10 = SYSCLK (automatically divided) 11 = Reserved SYSCLK Frequency 0 = SYSCLK is a multiple of 6.144MHz 1 = SYSCLK is a multiple of 5.6448MHz SYSCLK Frequency 000 = 6.144 MHz (5.6448 MHz) 001 = 12.288 MHz (11.2896 MHz) 010 = 24.576 MHz (22.5792 MHz) 011 = 49.152 MHz (45.1584 MHz) 100 = 98.304 MHz (90.3168 MHz) All other codes are reserved The frequencies in brackets apply for 44.1 kHz–related sample rates only (i.e., SAMPLE_RATE_n = 01XXX). SYSCLK Control 0 = Disabled 1 = Enabled SYSCLK should only be enabled after the applicable clock source has been configured and enabled. Clear this bit before stopping the reference clock or changing the reference clock frequency. Note that the SYSCLK frequency can be changed without disabling, provided the clock source is also changed at the same time. SYSCLK Source 0000 = MCLK1 0001 = MCLK2 0010 = MCLK3 0100 = FLL1 × 2 0101 = FLL2 × 2 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1111 = FLL1 All other codes are reserved 227 CS42L92 4.16 Clocking and Sample Rates Table 4-104. Clocking Control (Cont.) Register Address R258 (0x0102) Sample_rate_1 Bit 4:0 Label SAMPLE_RATE_ 1[4:0] Default 0x11 R259 (0x0103) Sample_rate_2 R260 (0x0104) Sample_rate_3 R266 (0x010A) Sample_rate_1_ status R267 (0x010B) Sample_rate_2_ status R268 (0x010C) Sample_rate_3_ status 4:0 SAMPLE_RATE_ 2[4:0] 0x11 4:0 SAMPLE_RATE_ 3[4:0] 0x11 4:0 SAMPLE_RATE_ 1_STS[4:0] 0x00 4:0 SAMPLE_RATE_ 2_STS[4:0] 0x00 Sample Rate 2 Status (Read only) Field coding is same as SAMPLE_RATE_1. 4:0 SAMPLE_RATE_ 3_STS[4:0] 0x00 Sample Rate 3 Status (Read only) Field coding is same as SAMPLE_RATE_1. 228 Description Sample Rate 1 Select 0x00 = None 0x01 = 12 kHz 0x02 = 24 kHz 0x03 = 48 kHz 0x04 = 96 kHz 0x05 = 192 kHz 0x06 = 384 kHz 0x09 = 11.025 kHz 0x0A = 22.05 kHz 0x0B = 44.1 kHz 0x0C = 88.2 kHz 0x0D = 176.4 kHz 0x0E = 352.8 kHz 0x11 = 8 kHz 0x12 = 16 kHz 0x13 = 32 kHz All other codes are reserved Sample Rate 2 Select Field coding is same as SAMPLE_RATE_1. Sample Rate 3 Select Field coding is same as SAMPLE_RATE_1. Sample Rate 1 Status (Read only) Field coding is same as SAMPLE_RATE_1. DS1162F1 CS42L92 4.16 Clocking and Sample Rates Table 4-104. Clocking Control (Cont.) Register Address Bit Label R274 (0x0112) 10:8 ASYNC_CLK_ FREQ[2:0] Async_clock_1 Default 011 Description ASYNCCLK Frequency 000 = 6.144 MHz (5.6448 MHz) 001 = 12.288 MHz (11.2896 MHz) 010 = 24.576 MHz (22.5792 MHz) 011 = 49.152 MHz (45.1584 MHz) 100 = 98.304 MHz (90.3168 MHz) All other codes are reserved The frequencies in brackets apply for 44.1 kHz–related sample rates only (i.e., ASYNC_SAMPLE_RATE_n = 01XXX). ASYNCCLK Control 0 = Disabled 1 = Enabled ASYNCCLK should only be enabled after the applicable clock source has been configured and enabled. Clear this bit before stopping the reference clock or changing the reference clock frequency. Note that the ASYNCCLK frequency can be changed without disabling, provided the clock source is also changed at the same time. ASYNCCLK Source 0000 = MCLK1 0001 = MCLK2 0010 = MCLK3 0100 = FLL1 × 2 0101 = FLL2 × 2 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1111 = FLL1 All other codes are reserved ASYNC Sample Rate 1 Select 0x00 = None 0x01 = 12 kHz 0x02 = 24 kHz 0x03 = 48 kHz 0x04 = 96 kHz 0x05 = 192 kHz 0x06 = 384 kHz 0x09 = 11.025 kHz 0x0A = 22.05 kHz 0x0B = 44.1 kHz 0x0C = 88.2 kHz 0x0D = 176.4 kHz 0x0E = 352.8 kHz 0x11 = 8 kHz 0x12 = 16 kHz 0x13 = 32 kHz All other codes are reserved ASYNC Sample Rate 2 Select Field coding is same as ASYNC_SAMPLE_RATE_1. 6 ASYNC_CLK_ ENA 0 3:0 ASYNC_CLK_ SRC[3:0] 0101 R275 (0x0113) Async_sample_ rate_1 4:0 ASYNC_ SAMPLE_RATE_ 1[4:0] 0x11 R276 (0x0114) Async_sample_ rate_2 R283 (0x011B) Async_sample_ rate_1_status R284 (0x011C) Async_sample_ rate_2_status 4:0 ASYNC_ SAMPLE_RATE_ 2[4:0] 0x11 4:0 ASYNC_ SAMPLE_RATE_ 1_STS[4:0] 0x00 ASYNC Sample Rate 1 Status (Read only) Field coding is same as ASYNC_SAMPLE_RATE_1. 4:0 ASYNC_ SAMPLE_RATE_ 2_STS[4:0] 0x00 ASYNC Sample Rate 2 Status (Read only) Field coding is same as ASYNC_SAMPLE_RATE_1. DS1162F1 229 CS42L92 4.16 Clocking and Sample Rates Table 4-104. Clocking Control (Cont.) Register Address R288 (0x0120) DSP_Clock_1 Bit 6 Label DSP_CLK_ENA 3:0 DSP_CLK_ SRC[3:0] Default 0 0101 R290 (0x0122) DSP_Clock_2 15:0 DSP_CLK_ FREQ[15:0] 0x0000 R294 (0x0126) DSP_Clock_4 R295 (0x0127) DSP_Clock_5 15:0 DSP_CLK_ FREQ_STS[15:0] 0x0000 230 3:0 DSP_CLK_SRC_ STS[3:0] 0101 Description DSPCLK Control 0 = Disabled 1 = Enabled DSPCLK should only be enabled after the applicable clock source has been configured and enabled. Clear this bit before stopping the reference clock or changing the reference clock frequency. Note that the DSPCLK frequency can be changed without disabling, provided the clock source is also changed at the same time. DSPCLK Source 0000 = MCLK1 0001 = MCLK2 0010 = MCLK3 0100 = FLL1 × 3 0101 = FLL2 × 3 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1111 = FLL1 All other codes are reserved DSPCLK Frequency Coded as LSB = 1/64 MHz, Valid from 5.6 MHz to 148 MHz. Note that, if this field is written while DSPCLK is enabled, the new frequency does not become effective until DSP_CLK_SRC is updated. To reconfigure DSPCLK while DSPCLK is enabled, the DSP_CLK_FREQ field must be updated before DSP_CLK_SRC. DSPCLK Frequency (Read only) Coded as LSB = 1/64 MHz. DSPCLK Source (Read only) 0000 = MCLK1 0001 = MCLK2 0010 = MCLK3 0100 = FLL1 × 3 0101 = FLL2 × 3 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1111 = FLL1 All other codes are reserved DS1162F1 CS42L92 4.16 Clocking and Sample Rates Table 4-104. Clocking Control (Cont.) Register Address R329 (0x0149) Output_system_ clock R330 (0x014A) Output_async_ clock R334 (0x014E) Clock_Gen_Pad_ Ctrl DS1162F1 Bit 15 Label OPCLK_ENA Default 0 7:3 OPCLK_DIV[4:0] 0x00 2:0 OPCLK_SEL[2:0] 000 15 OPCLK_ASYNC_ ENA 0 7:3 OPCLK_ASYNC_ DIV[4:0] 0x00 2:0 OPCLK_ASYNC_ SEL[2:0] 000 9 MCLK3_PD 0 8 MCLK2_PD 0 7 MCLK1_PD 0 Description OPCLK Enable 0 = Disabled 1 = Enabled OPCLK Divider 0x02 = Divide by 2 0x04 = Divide by 4 0x06 = Divide by 6 … (even numbers only) 0x1E = Divide by 30 Note that only even numbered divisions (2, 4, 6, etc.) are valid selections. All other codes are reserved when the OPCLK signal is enabled. OPCLK Source Frequency 000 = 6.144 MHz (5.6448 MHz) 001 = 12.288 MHz (11.2896 MHz) 010 = 24.576 MHz (22.5792 MHz) 011 = 49.152 MHz (45.1584 MHz) All other codes are reserved The frequencies in brackets apply for 44.1 kHz–related SYSCLK rates only (i.e., SAMPLE_RATE_n = 01XXX). The OPCLK Source Frequency must be less than or equal to the SYSCLK frequency. OPCLK_ASYNC Enable 0 = Disabled 1 = Enabled OPCLK_ASYNC Divider 0x02 = Divide by 2 0x04 = Divide by 4 0x06 = Divide by 6 … (even numbers only) 0x1E = Divide by 30 Note that only even numbered divisions (2, 4, 6, etc.) are valid selections. All other codes are reserved when the OPCLK_ASYNC signal is enabled. OPCLK_ASYNC Source Frequency 000 = 6.144 MHz (5.6448 MHz) 001 = 12.288 MHz (11.2896 MHz) 010 = 24.576 MHz (22.5792 MHz) 011 = 49.152 MHz (45.1584 MHz) All other codes are reserved The frequencies in brackets apply for 44.1 kHz–related ASYNCCLK rates only (i.e., ASYNC_SAMPLE_RATE_n = 01XXX). The OPCLK_ASYNC Source Frequency must be less than or equal to the ASYNCCLK frequency. MCLK3 Pull-Down Control 0 = Disabled 1 = Enabled MCLK2 Pull-Down Control 0 = Disabled 1 = Enabled MCLK1 Pull-Down Control 0 = Disabled 1 = Enabled 231 CS42L92 4.16 Clocking and Sample Rates Table 4-104. Clocking Control (Cont.) Register Address R338 (0x0152) Rate_Estimator_1 Bit 4 Label TRIG_ON_ STARTUP 3:1 LRCLK_SRC[2:0] 000 0 RATE_EST_ENA 0 R339 (0x0153) Rate_Estimator_2 4:0 SAMPLE_RATE_ DETECT_A[4:0] 0x00 R340 (0x0154) Rate_Estimator_3 4:0 SAMPLE_RATE_ DETECT_B[4:0] 0x00 R341 (0x0155) Rate_Estimator_4 4:0 SAMPLE_RATE_ DETECT_C[4:0] 0x00 R342 (0x0156) Rate_Estimator_5 4:0 SAMPLE_RATE_ DETECT_D[4:0] 0x00 232 Default 0 Description Automatic Sample-Rate Detection Start-Up select 0 = Do not trigger Write Sequencer on initial detection 1 = Always trigger the Write Sequencer on sample-rate detection Automatic Sample-Rate Detection source 000 = AIF1LRCLK 010 = AIF2LRCLK 100 = AIF3LRCLK All other codes are reserved Automatic Sample-Rate Detection control 0 = Disabled 1 = Enabled Automatic Detection Sample Rate A (Up to four different sample rates can be configured for automatic detection.) Field coding is same as SAMPLE_RATE_n. Automatic Detection Sample Rate B (Up to four different sample rates can be configured for automatic detection.) Field coding is same as SAMPLE_RATE_n. Automatic Detection Sample Rate C (Up to four different sample rates can be configured for automatic detection.) Field coding is same as SAMPLE_RATE_n. Automatic Detection Sample Rate D (Up to four different sample rates can be configured for automatic detection.) Field coding is same as SAMPLE_RATE_n. DS1162F1 CS42L92 4.16 Clocking and Sample Rates Table 4-104. Clocking Control (Cont.) Register Address Bit Label R352 (0x0160) 15:13 ASYNC_CLK_ FREQ_STS[2:0] Clocking_debug_5 Default 000 12:9 ASYNC_CLK_ SRC_STS[3:0] 0000 6:4 SYSCLK_FREQ_ STS[2:0] 000 3:0 SYSCLK_SRC_ STS[3:0] 0000 Description ASYNCCLK Frequency (Read only) 000 = 6.144 MHz (5.6448 MHz) 001 = 12.288 MHz (11.2896 MHz) 010 = 24.576 MHz (22.5792 MHz) 011 = 49.152 MHz (45.1584 MHz) 100 = 98.304 MHz (90.3168 MHz) All other codes are reserved The frequencies in brackets apply for 44.1 kHz–related sample rates only (i.e., ASYNC_SAMPLE_RATE_n = 01XXX). ASYNCCLK Source (Read only) 0000 = MCLK1 0001 = MCLK2 0010 = MCLK3 0100 = FLL1 × 2 0101 = FLL2 × 2 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1111 = FLL1 All other codes are reserved SYSCLK Frequency (Read only) 000 = 6.144 MHz (5.6448 MHz) 001 = 12.288 MHz (11.2896 MHz) 010 = 24.576 MHz (22.5792 MHz) 011 = 49.152 MHz (45.1584 MHz) 100 = 98.304 MHz (90.3168 MHz) All other codes are reserved The frequencies in brackets apply for 44.1 kHz–related sample rates only (i.e., SAMPLE_RATE_n = 01XXX). SYSCLK Source (Read only) 0000 = MCLK1 0001 = MCLK2 0010 = MCLK3 0100 = FLL1 × 2 0101 = FLL2 × 2 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1111 = FLL1 All other codes are reserved In AIF Slave Modes, it is important to ensure that the applicable clock domain (SYSCLK or ASYNCCLK) is synchronized with the associated external LRCLK. This can be achieved by selecting an MCLKn input that is derived from the same reference as the LRCLK, or can be achieved by selecting the external BCLK or LRCLK signal as a reference input to one of the FLLs, as a source for SYSCLK or ASYNCCLK. If the AIF clock domain is not synchronized with the LRCLK, clicks arising from dropped or repeated audio samples occur, due to the inherent tolerances of multiple, asynchronous, system clocks. See Section 5.4 for further details on valid clocking configurations. 4.16.6 BCLK and LRCLK Control The digital audio interfaces (AIF1–AIF3) use BCLK and LRCLK signals for synchronization. In Master Mode, these are output signals, generated by the CS42L92. In Slave Mode, these are input signals to the CS42L92. It is also possible to support mixed master/slave operation. DS1162F1 233 CS42L92 4.16 Clocking and Sample Rates The BCLK and LRCLK signals are controlled as shown in Fig. 4-66. See Section 4.7 for details of the associated control fields. Note that the BCLK and LRCLK signals are synchronized to SYSCLK or ASYNCCLK, depending upon the applicable clock domain for the respective interface. See Section 4.3.14 for further details. SYSCLK AIF1_BCLK_MSTR p. 131 AIF1_LRCLK_MSTR p. 132 AIF1_BCLK_FREQ[4:0] p. 135 ASYNCCLK AIF1_BCPF[12:0] p. 135 f/N Master Mode Clock Outputs f/N (see note) AIF1BCLK AIF1LRCLK AIF2_BCLK_MSTR p. 132 AIF2_LRCLK_MSTR p. 132 AIF2_BCLK_FREQ[4:0] p. 136 AIF2_BCPF[12:0] p. 136 f/N Master Mode Clock Outputs f/N (see note) AIF2BCLK AIF2LRCLK AIF3_BCLK_MSTR p. 132 AIF3_LRCLK_MSTR p. 133 AIF3_BCLK_FREQ[4:0] p. 136 AIF3_BCPF[12:0] p. 136 f/N f/N (see note) Master Mode Clock Outputs AIF3BCLK AIF3LRCLK Note: The clock reference for each AIF is SYSCLK or ASYNCCLK AIFn is clocked from SYSCLK if AIFn_RATE < 1000 AIFn is clocked from ASYNCCLK if AIFn_RATE >= 1000 Figure 4-66. BCLK and LRCLK Control 4.16.7 Control Interface Clocking Register map access is possible with or without a system clock—there is no requirement for SYSCLK, or any other system clock, to be enabled when accessing the register map. See Section 4.17 for details of control register access. Timing specifications for each of the control interfaces are provided in Table 3-19–Table 3-21. In some applications, additional system-wide constraints must be observed to ensure control interface limits are not exceeded. These constraints need to be considered if any of the following conditions is true. • SYSCLK is enabled and is < 22.5792 MHz • Control-register access is scheduled at register address 0x8_0000 or above • Control-register access is scheduled on more than one of the control interfaces simultaneously The control interface limits vary depending on the system clock (SYSCLK or DSPCLK) configuration, the address of the control register access, and on which control interfaces are being used. 234 DS1162F1 CS42L92 4.16 Clocking and Sample Rates Table 4-105 describes valid system conditions for accessing the codec registers (below 0x8_0000). The control interfaces must operate within the limits represented by one of the permitted configurations shown, in accordance with the applicable SYSCLK frequency. Table 4-105. Maximum SPI/SLIMbus Clock Speeds—Codec Register Access SYSCLK Condition SYSCLK is disabled, or SYSCLK  22.5792 MHz SYSCLK = 12.288 MHz SYSCLK = 11.2896 MHz SYSCLK < 11.2896 MHz SPI 26 MHz SLIMbus 27 MHz 26 MHz — 13 MHz 12 MHz 26 MHz — 12 MHz 9 MHz 13 MHz — — 27 MHz 24.576 MHz 27 MHz — 27 MHz 22.5792 MHz 27 MHz — 27 MHz Description Full concurrent SPI/SLIMbus capability for codec register access. SPI and SLIMbus operating in isolation. SPI and SLIMbus operating concurrently. SPI and SLIMbus operating in isolation. SPI and SLIMbus operating concurrently. SPI and SLIMbus operating in isolation. Notes: • If SYSCLK < 11.2896 MHz, simultaneous register access via SPI/SLIMbus control interfaces should not be attempted. • If SYSCLK is disabled, full concurrent SPI/SLIMbus capability for codec register access is supported. • The SPI interface limits noted above are only applicable if the SPI interface is accessing codec registers. Options shown with “—” in the SPI column represent use cases where the SPI interface is either unused, or is being used to access the DSP registers. • The SLIMbus interface limits noted above are only applicable if multibyte burst transfers of more than 8 bytes are scheduled. Options shown with “—” in the SLIMbus column represent use cases where SLIMbus is either unused, or is configured to support any combination of audio channels, and burst transfers  8 bytes. • Register access via the I2C interface is supported at all times, regardless of the SLIMbus loading. Table 4-106 describes valid system conditions for accessing the DSP firmware registers (0x8_0000 and above). The control interfaces must operate within the limits represented by one of the permitted configurations shown, in accordance with the applicable DSPCLK frequency. Table 4-106. Maximum SPI/SLIMbus Clock Speeds—DSP Firmware Register Access DSPCLK Condition DSPCLK is disabled, or DSPCLK  45 MHz 24.576 MHz  DSPCLK < 45 MHz 12.288 MHz  DSPCLK < 24.576 MHz SPI 26 MHz — 26 MHz 21 MHz 26 MHz — 13 MHz — SLIMbus — 27 MHz 24.576 MHz 27 MHz — 24.576 MHz — 12.288 MHz Description One high speed interface. SPI and SLIMbus operating concurrently. SPI and SLIMbus operating in isolation. SPI and SLIMbus operating in isolation. Notes: • If DSPCLK < 24.576MHz, simultaneous register access via SPI/SLIMbus control interfaces should not be attempted. • If DSPCLK is disabled, the valid configurations are the same as for DSPCLK  45MHz. • The SPI interface limits noted above are only applicable if the SPI interface is accessing DSP registers. Options shown with “—” in the SPI column represent use cases where the SPI interface is either unused, or is being used to access the codec registers. • The SLIMbus interface limits noted above are only applicable if multibyte burst transfers of more than 8 bytes are scheduled. Options shown with “—” in the SLIMbus column represent use cases where SLIMbus is either unused, or is configured to support any combination of audio channels, and burst transfers  8 bytes. • Register access via the I2C interface is supported at all times, regardless of the SLIMbus loading. 4.16.8 Frequency-Locked Loop (FLL1, FLL2) Two integrated FLLs are provided to support the clocking requirements of the CS42L92. These can be configured according to the available reference clocks and the application requirements. The reference clock may use a high frequency (e.g., 12.288 MHz) or low frequency (e.g., 32.768 kHz). The FLL is tolerant of jitter and may be used to generate a stable output clock from a less stable input reference. DS1162F1 235 CS42L92 4.16 Clocking and Sample Rates 4.16.8.1 Overview The FLL characteristics are summarized in Table 3-11. In normal operation, the FLL output is frequency locked to an input clock reference. The FLL can be used to generate a free-running clock in the absence of any external reference, as described in Section 4.16.8.6. 4.16.8.2 FLL Enable The FLL is enabled by setting FLLn_ENA (where n = 1 or 2 for the corresponding FLL). Note that the other FLL fields should be configured before enabling the FLL; the FLLn_ENA bit should be set as the final step of the FLLn enable sequence. The FLL supports configurable free-running operation in FLL Hold Mode, using the FLLn_HOLD bit described in Section 4.16.8.6. If the FLL is enabled and FLL Hold Mode is selected, the configured output frequency is maintained without any input reference required. Note that, once the FLL output has been established, the FLL is always free running if the input reference clock is stopped, regardless of the FLLn_HOLD bit. Note that, to disable the FLL while the input reference clock has stopped, FLLn_HOLD must be set before clearing FLLn_ ENA. When changing FLL settings, it is recommended to disable the FLL by clearing FLLn_ENA before updating the other register fields. It is possible to configure the FLL while the FLL is enabled, as described in Section 4.16.8.4. As a general rule, however, it is recommended to configure the FLL before setting FLLn_ENA. The procedure for configuring the FLL is described in the following subsections. The description is applicable to FLL1 and FLL2; the associated control fields are described in Table 4-108 and Table 4-109 respectively. 4.16.8.3 Input Frequency Control The main input reference is selected using FLLn_REFCLK_SRC. The available options are MCLKn, SLIMCLK, AIFnBCLK, or AIFnLRCLK. The SLIMCLK reference is controlled by an adaptive divider on the external SLIMCLK input. The divider automatically adapts to the SLIMbus clock gear, to provide a constant reference frequency for the FLL—see Section 4.10.3. The FLLn_REFCLK_DIV field controls a programmable divider on the input reference. The input can be divided by 1, 2, 4 or 8. The divider should be configured to bring each reference down to 13 MHz or below. For best performance, it is recommended that the highest possible frequency—within the 13 MHz limit—should be selected. The FLL incorporates a reference-detection circuit for the main input clock. This ensures best FLL performance in the event of the main input clock being interrupted. If there is a possibility of the main input being interrupted while the FLL is enabled, then the reference-detection circuit must be enabled by setting FLLn_REFDET. The reference detection also provides input to the interrupt control circuit and can be used to trigger an interrupt event when the input reference is stopped—see Section 4.15. 4.16.8.4 Output Frequency Control The FLL output frequency, FFLL, relative to the main input reference FREF, is a function of: • The frequency ratio set by FLLn_FB_DIV • The real number represented by N.K. (N = integer; K = fractional portion, i.e., < 1) The output frequency must be in the range 45–50 MHz. If the FLL is selected as SYSCLK or ASYNCCLK source, the respective FFLL frequency must be exactly 49.152 MHz (for 48 kHz–related sample rates) or 45.1584 MHz (for 44.1 kHz–related sample rates). • If FLL2 is selected as SYSCLK or ASYNCCLK source, the respective clock frequency is equal to FFLL × 2. • If FLL1 is selected as SYSCLK or ASYNCCLK source, two different frequencies are available. Typical use cases should select the higher frequency (FFLL × 2); a lower frequency (FFLL) is available to support low-power always-on use cases. 236 DS1162F1 CS42L92 4.16 Clocking and Sample Rates If the FLL is selected as DSPCLK source, the following frequency options are supported: • If FLL2 is selected as DSPCLK source, the DSPCLK frequency is in the range 135–150 MHz. The frequency is equal to FFLL × 3. • If FLL1 is selected as DSPCLK source, two different frequencies are available. Typical use cases should select the higher frequency (FFLL × 3); a lower frequency (FFLL) is available to support low-power always-on use cases. • Note that the DSPCLK can be divided to lower frequencies for clocking the DSP core. The FLL clock can be configured as a GPIO output; a programmable divider supports division ratios in the range 2 through 127, enabling a wide range of GPIO clock output frequencies. Note: The chosen FFLL frequency can be used to support multiple outputs simultaneously (e.g., SYSCLK, DSPCLK, and GPIO). To configure the FLL output frequency, it must be determined whether Integer Mode or Fractional Mode is required. • If the ratio FFLL / FREF is an integer, then Integer Mode applies • If the ratio FFLL / FREF is not an integer, then Fractional Mode applies The input reference must be identified in one of three frequency ranges. • If FREF < 192 kHz, this is low clock frequency • If FREF  192 kHz and FREF < 1.152 MHz, this is mid clock frequency • If FREF  1.152 MHz, this is high clock frequency Note: FREF is the input frequency, after division by FLLn_REFCLK_DIV, where applicable. The FLL oscillator frequency, FOSC, is set according to the applicable mode and input reference frequency. • If Fractional Mode is used and FREF is high frequency, then FOSC = FFLL × 6 • Otherwise, FOSC = FFLL The FLL oscillator frequency, FOSC, is set according to the following equation: FOSC = (FREF × N.K × FLLn_FB_DIV) The FLLn_FB_DIV value should be configured according to the applicable mode and input reference frequency. • If Integer Mode is used and FREF is low frequency, then FLLn_FB_DIV should be set to 4 • If Fractional Mode is used and FREF is low frequency, then FLLn_FB_DIV should be set to 256 • Otherwise, FLLn_FB_DIV should be set to 1 The value of N.K can be determined as follows: N.K = FOSC / (FLLn_FB_DIV × FREF) The calculated value of N must lie within a valid range, according to the applicable mode. • If Integer Mode is used, N is valid in the range 1–1023 • If Fractional Mode is used, N is valid in the range 4–255 If the calculated value of N is too high, a higher FLLn_FB_DIV is required. If the calculated value of N is too low, a lower FLLn_FB_DIV is required. It is recommended to adjust the FLLn_FB_DIV value by multiplying or dividing by 2 until a valid N is achieved. The value of N is held in FLLn_N. The value of K is determined by the ratio FLLn_THETA / FLLn_LAMBDA. In Fractional Mode, the FLLn_THETA and FLLn_LAMBDA fields can be derived as described in Section 4.16.8.5. The FLLn_N, FLLn_THETA, and FLLn_LAMBDA fields are all coded as integers (LSB = 1). DS1162F1 237 CS42L92 4.16 Clocking and Sample Rates When changing FLL settings, it is recommended to disable the FLL by clearing FLLn_ENA before updating the other register fields. If the FLL settings or input reference are changed without disabling the FLL, the FLL Hold Mode must be selected before writing to any other FLL control fields. FLL Hold Mode is selected by setting FLLn_HOLD. If the FLL control fields are written while the FLL is enabled (FLLn_ENA = 1), the new values are only effective when a 1 is written to FLLn_CTRL_UPD. This makes it possible to update the FLL configuration fields simultaneously, without disabling the FLL. To change FLL settings without disabling the FLL, the recommended control sequence is: • Select FLL Hold Mode (FLLn_HOLD = 1) • Write to the FLL control fields • Update the FLL control registers (write 1 to FLLn_CTRL_UPD) • Disable FLL Hold Mode (FLLn_HOLD = 0) Note that, if the FLL is disabled, the FLL control fields can be updated without writing to FLLn_CTRL_UPD. The FLLn_PD_GAIN_FINE, FLLn_PD_GAIN_COARSE, FLLn_FD_GAIN_FINE, FLLn_FD_GAIN_COARSE, FLLn_HP, and FLLn_CLK_VCO_FAST_SRC fields should be configured as described in Table 4-107. Note: When writing to the FLLn_CLK_VCO_FAST_SRC or FLLn_HP fields, take care not to change other nonzero bits that are configured at the same register address. Table 4-107. FLLn Control Field Settings Condition Low clock frequency Mid clock frequency High clock frequency Integer Mode Fractional Mode, Low clock frequency Fractional Mode, Mid clock frequency Fractional Mode, High clock frequency Integer Mode Fractional Mode 0x2 0x2 0x2 — FLLn_PD_ GAIN_ COARSE 0x3 0x2 0x1 — — — FLLn_PD_ GAIN_FINE 0xF 0xF 0xF — FLLn_FD_ GAIN_ COARSE 0x0 0x2 0x0 — — — FLLn_FD_ GAIN_FINE FLLn_ FLLn_CLK_ LOCKDET_ VCO_ THR FAST_SRC 0x2 — 0x8 0x8 — 0x0 0x0 0x0 0x3 — — FLLn_HP — — 0x0 0x3 4.16.8.5 Calculation of Theta and Lambda In Fractional Mode, FLLn_THETA and FLLn_LAMBDA are calculated with the following steps: 1. Calculate GCD(FLL) using the Greatest Common Denominator function: GCD(FLL) = GCD(FLLn_FB_DIV × FREF, FOSC), where GCD(x, y) is the greatest common denominator of x and y. FREF is the input frequency, after division by FLLn_REFCLK_DIV, where applicable. 2. Calculate FLLn_THETA and FLLn_LAMBDA using the following equations: FLLn_THETA = (FOSC – (FLL_N × FLLn_FB_DIV × FREF)) / GCD(FLL) FLLn_LAMBDA = (FLLn_FB_DIV × FREF) / GCD(FLL) Notes: The values of GCD(FLL), FLLn_THETA, and FLLn_LAMBDA should be calculated using the applicable frequency values in Hz (i.e., not kHz or MHz). In Fractional Mode, the values of FLLn_THETA and FLLn_LAMBDA must be coprime (i.e., not divisible by any common integer). The calculation above ensures that the values are coprime. The value of K must be less than 1 (i.e., FLLn_THETA must be less than FLLn_LAMBDA). 238 DS1162F1 CS42L92 4.16 Clocking and Sample Rates 4.16.8.6 FLL Hold Mode FLL Hold Mode enables the FLL to generate a clock signal even if no external reference is available, such as when the normal input reference has been interrupted during a standby or start-up period. FLL Hold Mode is selected by setting FLLn_HOLD. If the FLL is enabled and FLL Hold Mode is selected, the normal feedback mechanism of the FLL is halted and the FLL oscillates independently of the external input references—the FLL output frequency remains unchanged if FLL Hold Mode is enabled. If the FLL is enabled and the input reference clock is stopped, the loop always runs freely, regardless of the FLLn_HOLD setting. If FLLn_HOLD = 0, the FLL relocks to the input reference whenever it is available. If the FLL configuration or input reference are changed without disabling the FLL, the FLL Hold Mode must be selected before writing to any other FLL control fields—see Section 4.16.8.4. The free-running FLL clock may be selected as the SYSCLK, ASYNCCLK, or DSPCLK source, as shown in Fig. 4-65. 4.16.8.7 FLL Control Registers The FLL1 control registers are described in Table 4-108. Example settings for a variety of reference frequencies and output frequencies are shown in Section 4.16.8.10. Table 4-108. FLL1 Register Map Register Address R369 (0x0171) FLL1_Control_1 R370 (0x0172) FLL1_Control_2 R371 (0x0173) FLL1_Control_3 R372 (0x0174) FLL1_Control_4 R373 (0x0175) FLL1_Control_5 R374 (0x0176) FLL1_Control_6 DS1162F1 Bit 3:0 Label FLL1_REFCLK_ SRC[3:0] Default Description 0000 FLL1 Clock source 0000 = MCLK1 1000 = AIF1BCLK 1101 = AIF2LRCLK 0001 = MCLK2 1001 = AIF2BCLK 1110 = AIF3LRCLK 0010 = MCLK3 1010 = AIF3BCLK All other codes are reserved 0011 = SLIMCLK 1100 = AIF1LRCLK 2 FLL1_HOLD 1 FLL1 Hold Mode Enable 0 = Disabled 1 = Enabled The FLL feedback mechanism is halted in FLL Hold Mode, and the latest integrator setting is maintained. 0 FLL1_ENA 0 FLL1 Enable 0 = Disabled 1 = Enabled This should be set as the final step of the FLL1 enable sequence. 15 FLL1_CTRL_UPD 0 FLL1 Control Update Write 1 to apply the FLL1 configuration field settings. (Only valid if FLL1_ENA = 1) 9:0 FLL1_N[9:0] 0x004 FLL1 Integer multiply for FREF Coded as LSB = 1. 15:0 FLL1_ 0x0000 FLL1 Fractional multiply for FREF. THETA[15:0] Sets the numerator (multiply) part of the FLL1_THETA/FLL1_LAMBDA ratio. Coded as LSB = 1. 15:0 FLL1_ 0x0000 FLL1 Fractional multiply for FREF. LAMBDA[15:0] Sets the denominator (dividing) part of the FLL1_THETA/FLL1_LAMBDA ratio. Coded as LSB = 1. 9:0 FLL1_FB_DIV[9:0] 0x0001 FLL1 Clock Feedback ratio Coded as LSB = 1. 15 FLL1_REFDET 1 FLL1 Reference Detect control 0 = Disabled 1 = Enabled 7:6 FLL1_REFCLK_ 00 FLL1 Clock Reference divider DIV[1:0] 00 = 1 10 = 4 01 = 2 11 = 8 MCLK (or other input reference) must be divided down to  13 MHz. 239 CS42L92 4.16 Clocking and Sample Rates Table 4-108. FLL1 Register Map (Cont.) Register Address Bit Label R376 (0x0178) 15:12 FLL1_PD_GAIN_ FINE[3:0] FLL1_Control_8 R378 (0x017A) FLL1_Control_10 R379 (0x017B) FLL1_Control_11 R381 (0x017D) FLL1_Digital_ Test_1 240 Default Description 0x2 FLL1 Phase Detector Gain 2 Gain is 2–X, where X is FLL1_PD_GAIN_FINE in 2’s complement coding. 0110 = 2–6 0000 = 1 1100 = 16 0001 = 0.5 0111 = 2–7 1101 = 8 0010 = 0.25 1000 = 256 1110 = 4 0011 = 0.125 1001 = 128 1111 = 2 0100 = 2–4 1010 = 64 1011 = 32 0101 = 2–5 11:8 FLL1_PD_GAIN_ 0x1 FLL1 Phase Detector Gain 1 COARSE[3:0] Gain is 2–X, where X is FLL1_PD_GAIN_COARSE in 2’s complement coding. 0000 = 1 0110 = 2–6 1100 = 16 0001 = 0.5 0111 = 2–7 1101 = 8 0010 = 0.25 1000 = 256 1110 = 4 0011 = 0.125 1001 = 128 1111 = 2 0100 = 2–4 1010 = 64 1011 = 32 0101 = 2–5 7:4 FLL1_FD_GAIN_ 0xF FLL1 Frequency Detector Gain 2 FINE[3:0] Gain is 2–X, where X is FLL1_FD_GAIN_FINE in integer coding. 1110 = 2–14 0000 = 1 0011 = 0.125 0001 = 0.5 ... 1111 = Reserved 0010 = 0.25 1101 = 2–13 3:0 FLL1_FD_GAIN_ 0x0 FLL1 Frequency Detector Gain 1 COARSE[3:0] Gain is 2–X, where X is FLL1_FD_GAIN_COARSE in 2’s complement coding. 0000 = 1 0110 = 2–6 1100 = 16 0001 = 0.5 0111 = 2–7 1101 = 8 0010 = 0.25 1000 = 256 1110 = 4 0011 = 0.125 1111 = 2 1001 = 128 0100 = 2–4 1010 = 64 1011 = 32 0101 = 2–5 15:14 FLL1_HP[1:0] 00 FLL1 Fractional Mode control 00 = Integer mode 10 = Reserved 01 = Reserved 11 = Fractional Mode 4:1 FLL1_LOCKDET_ 0x8 FLL1 Lock Detect threshold THR[3:0] Valid from 0x0 (low threshold) to 0xF (high threshold) 0 FLL1_LOCKDET 1 FLL1 Lock Detect enabled 0 = Disabled 1 = Enabled 1:0 FLL1_CLK_VCO_ 0x0 FLL1 Oscillator Frequency Control FAST_SRC[1:0] 00 = 45–50 MHz 10 = Reserved 01 = Reserved 11 = 270–300 MHz DS1162F1 CS42L92 4.16 Clocking and Sample Rates The FLL2 control registers are described in Table 4-109. Table 4-109. FLL2 Register Map Register Address R401 (0x0191) FLL2_Control_1 R402 (0x0192) FLL2_Control_2 R403 (0x0193) FLL2_Control_3 R404 (0x0194) FLL2_Control_4 R405 (0x0195) FLL2_Control_5 R406 (0x0196) FLL2_Control_6 DS1162F1 Bit 3:0 Label FLL2_REFCLK_ SRC[3:0] Default Description 0111 FLL2 Clock source 1000 = AIF1BCLK 1101 = AIF2LRCLK 0000 = MCLK1 0001 = MCLK2 1001 = AIF2BCLK 1110 = AIF3LRCLK 0010 = MCLK3 1010 = AIF3BCLK All other codes are reserved 0011 = SLIMCLK 1100 = AIF1LRCLK 2 FLL2_HOLD 1 FLL2 Hold Mode Enable 0 = Disabled 1 = Enabled The FLL feedback mechanism is halted in FLL Hold Mode, and the latest integrator setting is maintained. 0 FLL2_ENA 0 FLL2 Enable 0 = Disabled 1 = Enabled This should be set as the final step of the FLL2 enable sequence. 15 FLL2_CTRL_UPD 0 FLL2 Control Update Write 1 to apply the FLL2 configuration field settings. (Only valid if FLL2_ENA = 1) 9:0 FLL2_N[9:0] 0x004 FLL2 Integer multiply for FREF Coded as LSB = 1. 15:0 FLL2_ 0x0000 FLL2 Fractional multiply for FREF. THETA[15:0] Sets the numerator (multiply) part of the FLL2_THETA/FLL2_LAMBDA ratio. Coded as LSB = 1. 15:0 FLL2_ 0x0000 FLL2 Fractional multiply for FREF. LAMBDA[15:0] Sets the denominator (dividing) part of the FLL2_THETA/FLL2_LAMBDA ratio. Coded as LSB = 1. 9:0 FLL2_FB_DIV[9:0] 0x0001 FLL2 Clock Feedback ratio Coded as LSB = 1. 15 FLL2_REFDET 1 FLL2 Reference Detect control 0 = Disabled 1 = Enabled 7:6 FLL2_REFCLK_ 00 FLL2 Clock Reference divider DIV[1:0] 00 = 1 10 = 4 01 = 2 11 = 8 MCLK (or other input reference) must be divided down to  13 MHz. 241 CS42L92 4.16 Clocking and Sample Rates Table 4-109. FLL2 Register Map (Cont.) Register Address Bit Label R408 (0x0198) 15:12 FLL2_PD_GAIN_ FINE[3:0] FLL2_Control_8 R410 (0x019A) FLL2_Control_10 R411 (0x019B) FLL2_Control_11 R413 (0x019D) FLL2_Digital_ Test_1 Default Description 0x2 FLL2 Phase Detector Gain 2 Gain is 2–X, where X is FLL2_PD_GAIN_FINE in 2’s complement coding. 0110 = 2–6 0000 = 1 1100 = 16 0001 = 0.5 0111 = 2–7 1101 = 8 0010 = 0.25 1000 = 256 1110 = 4 0011 = 0.125 1001 = 128 1111 = 2 0100 = 2–4 1010 = 64 1011 = 32 0101 = 2–5 11:8 FLL2_PD_GAIN_ 0x1 FLL2 Phase Detector Gain 1 COARSE[3:0] Gain is 2–X, where X is FLL2_PD_GAIN_COARSE in 2’s complement coding. 0000 = 1 0110 = 2–6 1100 = 16 0001 = 0.5 0111 = 2–7 1101 = 8 0010 = 0.25 1000 = 256 1110 = 4 0011 = 0.125 1001 = 128 1111 = 2 0100 = 2–4 1010 = 64 1011 = 32 0101 = 2–5 7:4 FLL2_FD_GAIN_ 0xF FLL2 Frequency Detector Gain 2 FINE[3:0] Gain is 2–X, where X is FLL2_FD_GAIN_FINE in integer coding. 1110 = 2–14 0000 = 1 0011 = 0.125 0001 = 0.5 ... 1111 = Reserved 0010 = 0.25 1101 = 2–13 3:0 FLL2_FD_GAIN_ 0x0 FLL2 Frequency Detector Gain 1 COARSE[3:0] Gain is 2–X, where X is FLL2_FD_GAIN_COARSE in 2’s complement coding. 0000 = 1 0110 = 2–6 1100 = 16 0001 = 0.5 0111 = 2–7 1101 = 8 0010 = 0.25 1000 = 256 1110 = 4 0011 = 0.125 1111 = 2 1001 = 128 0100 = 2–4 1010 = 64 1011 = 32 0101 = 2–5 15:14 FLL2_HP[1:0] 00 FLL2 Fractional Mode control 00 = Integer mode 10 = Reserved 01 = Reserved 11 = Fractional Mode 4:1 FLL2_LOCKDET_ 0x8 FLL2 Lock Detect threshold THR[3:0] Valid from 0x0 (low threshold) to 0xF (high threshold) 0 FLL2_LOCKDET 1 FLL2 Lock Detect enabled 0 = Disabled 1 = Enabled 1:0 FLL2_CLK_VCO_ 0x0 FLL2 Oscillator Frequency Control FAST_SRC[1:0] 00 = 45–50 MHz 10 = Reserved 01 = Reserved 11 = 270–300 MHz 4.16.8.8 FLL Interrupts and GPIO Output For each FLL, the CS42L92 provides status signals that indicate whether the input reference is present and whether FLL lock has been achieved (i.e., the FLL is locked to the input reference signal). To enable the FLL lock indication, the FLLn_LOCKDET bit must be set. The FLL lock condition is measured with respect to a configurable threshold that is set using FLLn_LOCKDET_THR. Note that the FLLn_LOCKDET_THR field controls the lock indication only—it does not control the behavior of the FLL. To enable the FLL input reference indication, the FLLn_REFDET bit must be set. The FLL status signals are inputs to the interrupt control circuit and can be used to trigger an interrupt event when the input reference is stopped or when the FLL lock status changes. See Section 4.15. Note that these interrupt signals are debounced and require clocking to be present in order to assert the respective interrupt—either the 32-kHz clock or the SYSCLK signal must be enabled to trigger an interrupt from the FLL signals. 242 DS1162F1 CS42L92 4.16 Clocking and Sample Rates The FLL lock signal can be output directly on a GPIO pin as an external indication of the FLL status. See Section 4.14 to configure a GPIO pin for these functions. (These GPIO outputs are not debounced and do not require clocking to be present.) Clock output signals derived from the FLL can be output on a GPIO pin. See Section 4.14 to configure a GPIO pin for this function. 4.16.8.9 Example FLL Calculation The following example illustrates how to derive the FLL1 register fields to generate an FLL output frequency (FFLL) of 49.152 MHz from a 12.000-MHz reference clock (FREF). This is suitable for generating SYSCLK at 98.304 MHz and DSPCLK at 147.456 MHz. 1. Set FLL1_REFCLK_DIV to generate FREF  13 MHz: FLL1_REFCLK_DIV = 00 (divide by 1) 2. Determine if Integer Mode or Fractional Mode is required: FFLL / FREF is 4.096. Therefore, Fractional Mode applies. 3. Identify the input clock frequency range: FREF  1.152 MHz. This is high clock frequency. 4. Calculate the FLL oscillator frequency, FOSC: In Fractional Mode, with high clock frequency input, FOSC = FFLL × 6 = 294.912 MHz 5. Select the required value of FLL1_FB_DIV: In Fractional Mode, with high clock frequency input, FLL1_FB_DIV = 1 6. Calculate N.K as given by N.K = FOSC / (FLL1_FB_DIV × FREF): N.K = 294912000 / (1 × 12000000) = 24.576 7. Confirm that the calculated value of N is within the valid range for fractional mode (4–255). 8. Determine FLL1_N from the integer portion of N.K: FLL1_N = 24 (0x018) 9. Determine GCD(FLL), as given by GCD(FLL) = GCD(FLL1_FB_DIV × FREF, FOSC): GCD(FLL) = GCD(1 × 12000000, 294912000) = 96000 10.Determine FLL1_THETA, as given by FLL1_THETA = (FOSC – (FLL1_N × FLL1_FB_DIV × FREF)) / GCD(FLL): FLL1_THETA = (294912000 – (24 × 1 × 12000000)) / 96000 FLL1_THETA = 72 (0x0048) 11. Determine FLL1_LAMBDA, as given by FLL1_LAMBDA = (FLL1_FB_DIV x FREF) / GCD(FLL): FLL1_LAMBDA = (1 × 12000000) / 96000 FLL1_LAMBDA = 125 (0x007D) 12.Determine other FLL settings as specified in Table 4-107 for Fractional Mode and high clock frequency input: FLL1_PD_GAIN_FINE = 0x2 FLL1_PD_GAIN_COARSE = 0x1 FLL1_FD_GAIN_FINE = 0xF FLL1_FD_GAIN_COARSE = 0x0 FLL1_CLK_VCO_FAST_SRC = 0x3 FLL1_HP = 0x3 DS1162F1 243 CS42L92 4.17 Control Interface 4.16.8.10 Example FLL Settings Table 4-110 shows FLL settings for generating an output frequency (FFLL) of 49.152 MHz from a variety of low- and high-frequency reference inputs. This is suitable for generating SYSCLK at 98.304 MHz and DSPCLK at 147.456 MHz. Table 4-110. Example FLL Settings FSOURCE FFLL (MHz) FREF Divider1 FB_DIV1 N.K 2 FLLn_N 32.000 kHz 32.768 kHz 44.100 kHz 48 kHz 128 kHz 9.6 MHz 10 MHz 11.2896 MHz 12.000 MHz 12.288 MHz 13.000 MHz 19.200 MHz 22.5792 MHz 24 MHz 24.576 MHz 26 MHz 49.152 49.152 49.152 49.152 49.152 49.152 49.152 49.152 49.152 49.152 49.152 49.152 49.152 49.152 49.152 49.152 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 4 4 256 4 4 1 1 1 1 1 1 1 1 1 1 1 384 375 4.3537415 256 96 30.72 29.4912 26.12245 24.576 4 22.68554 30.72 26.12245 24.576 4 22.68554 0x180 0x177 0x004 0x100 0x060 0x01E 0x01D 0x01A 0x018 0x004 0x016 0x01E 0x01A 0x018 0x004 0x016 FLLn_ THETA 0x0000 0x0000 0x0034 0x0000 0x0000 0x0012 0x0133 0x0006 0x0048 0x0000 0x045A 0x0012 0x0006 0x0048 0x0000 0x045A FLLn_ LAMBDA 0x0001 0x0001 0x0093 0x0001 0x0001 0x0019 0x0271 0x0031 0x007D 0x0001 0x0659 0x0019 0x0031 0x007D 0x0001 0x0659 1.See Table 4-108 and Table 4-109 for the coding of the FLLn_REFCLK_DIV and FLLn_FB_DIV fields. 2.N.K values are represented in the FLLn_N, FLLn_THETA, and FLLn_LAMBDA fields. 4.17 Control Interface The CS42L92 is controlled by read/write access to its control registers. The control interface supports 2-wire (I2C) and 4-wire (SPI) modes. Note that the SLIMbus interface also supports read/write access to the CS42L92 control registers; see Section 4.10. The CS42L92 executes a boot sequence following power-on reset, hardware reset, software reset, or wake-up from Sleep Mode. Note that control register writes should not be attempted until the boot sequence has completed. See Section 4.22 for further details. The control interface function can be supported with or without system clocking—there is no requirement for SYSCLK, or any other system clock, to be enabled when accessing the register map. Timing specifications for each of the control interfaces are provided in Table 3-19–Table 3-21. In some applications, additional system-wide constraints must be observed to ensure control interface limits are not exceeded. Full details of these requirements are provided in Section 4.16.7. These constraints need to be considered if any of the following conditions is true. • SYSCLK is enabled and is < 22.5792 MHz • Control-register access is scheduled at register address 0x80000 or above • Control-register access is scheduled on more than one of the control interfaces simultaneously The control interface can be configured as a 2-wire (I2C) or 4-wire (SPI) interface. The mode is determined by the logic level on the CIFMODE pin, as described in Table 4-111. 244 DS1162F1 CS42L92 4.17 Control Interface Table 4-111. CS42L92 Control Interface Summary CIFMODE Logic 1 Interface Mode Four-wire (SPI) interface Pin Functions CIFMISO—Data output CIFMOSI—Data input CIFSCLK—Interface clock input CIFSS—Slave select input Logic 0 Two-wire (I2C) interface CIFSCLK—Interface clock input CIFSDA—Data input/output Note: The CIFMOSI and CIFSDA functions are multiplexed on a dual-function pin. An integrated pull-down resistor is provided on the CIF1MISO pin. This provides a flexible capability for interfacing with other devices. The pull-down is configured using the CIF1MISO_PD bit, as described in Table 4-112. Table 4-112. Control Interface Pull-Down Register Address R8 (0x0008) Ctrl_IF_CFG_1 Bit 7 Label CIF1MISO_PD Default 0 Description CIFMISO Pull-Down Control 0 = Disabled 1 = Enabled A detailed description of the I2C and SPI interface modes is provided in the following sections. 4.17.1 Four-Wire (SPI) Control Mode The SPI control interface mode is supported using the CIFSS, CIFSCLK, CIFMOSI, and CIFMISO pins. In write operations (R/W = 0), the MOSI pin input is driven by the controlling device. In read operations (R/W = 1), the MOSI pin is ignored following receipt of the valid register address. If SS is asserted (Logic 0), the MISO output is actively driven when outputting data and is high impedance at other times. If SS is not asserted, the MISO output is high impedance. The high-impedance state of the MISO output allows the pin to be shared with other slaves. An internal pull-down resistor can be enabled on the MISO pin, as described in Table 4-112. Data transfers on the SPI interface must use the applicable message format, according to the register address space that is being accessed: • When accessing register addresses below R12288 (0x3000), the applicable SPI protocol comprises a 31-bit register address and 16-bit data words. • When accessing register addresses from R12888 (0x3000) upwards, the applicable SPI protocol comprises a 31-bit register address and 32-bit data words. • Note that, in all cases, the complete SPI message protocol also includes a read/write bit and a 16-bit padding phase (see Fig. 4-67 and Fig. 4-68 below). Continuous read and write modes enable multiple register operations to be scheduled faster than is possible with single register operations. In these modes, the CS42L92 automatically increments the register address at the end of each data word, for as long as SS is held low and SCLK is toggled. Successive data words can be input/output every 16 (or 32) clock cycles (depending on the applicable register address space). The SPI protocol is shown in Fig. 4-67 and Fig. 4-68. Note that 16-bit data words are shown, but the equivalent protocol also applies to 32-bit data words. DS1162F1 245 CS42L92 4.17 Control Interface Fig. 4-67 shows a single register write to a specified address. SS SCLK MOSI R/W A30 A29 A1 A0 X X 31-bit register address X X B15 B14 16-bit padding B1 B0 16-bit data word Figure 4-67. Control Interface SPI Register Write (16-Bit Data Words) Fig. 4-68 shows a single register read from a specified address. SS SCLK MOSI R/W A30 A29 A1 A0 X X X MISO X X X B15 B14 31-bit register address 16-bit padding X X B1 B0 16-bit data word Figure 4-68. Control Interface SPI Register Read (16-Bit Data Words) 4.17.2 Two-Wire (I2C) Control Mode The I2C control interface mode is supported using the CIFSCLK and CIFSDA pins. In I2C Mode, the CS42L92 is a slave device on the control interface; SCLK is a clock input, while SDA is a bidirectional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the CS42L92 transmits Logic 1 by tristating the SDA pin, rather than pulling it high. An external pull-up resistor is required to pull the SDA line high so that the Logic 1 can be recognized by the master. In order to allow many devices to share a single two-wire control bus, every device on the bus has a unique 8-bit device ID (this is not the same as the address of each register in the CS42L92). The CS42L92 device ID is 0011_0100 (0x34). Note that the LSB of the device ID is the read/write bit; this bit is set to Logic 1 for read and Logic 0 for write. The CS42L92 operates as a slave device only. The controller indicates the start of data transfer with a high-to-low transition on SDA while SCLK remains high. This indicates that a device ID and subsequent address/data bytes follow. The CS42L92 responds to the start condition and shifts in the next 8 bits on SDA (8-bit device ID, including read/write bit, MSB first). If the device ID received matches the device ID of the CS42L92, the CS42L92 responds by pulling SDA low on the next clock pulse (ACK). If the device ID is not recognized or the R/W bit is set incorrectly, the CS42L92 returns to the idle condition and waits for a new start condition. If the device ID matches the device ID of the CS42L92, the data transfer continues. The controller indicates the end of data transfer with a low-to-high transition on SDA while SCLK remains high. After receiving a complete address and data sequence the CS42L92 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e., SDA changes while SCLK is high), the device returns to the idle condition. 246 DS1162F1 CS42L92 4.17 Control Interface Data transfers on the I2C interface must use the applicable message format, according to the register address space that is being accessed: • When accessing register addresses below R12288 (0x3000), the applicable I2C protocol comprises a 32-bit register address and 16-bit data words. • When accessing register addresses from R12888 (0x3000) upwards, the applicable I2C protocol comprises a 32-bit register address and 32-bit data words. • Note that, in all cases, the complete I2C message protocol also includes a device ID, a read/write bit, and other signaling bits (see Fig. 4-69 and Fig. 4-70). The CS42L92 supports the following read and write operations: • Single write • Single read • Multiple write • Multiple read Continuous (multiple) read and write modes allow register operations to be scheduled faster than is possible with single register operations. In these modes, the CS42L92 automatically increments the register address after each data word. Successive data words can be input/output every 2 (or 4) data bytes, depending on the applicable register address space. The I2C protocol for a single, 16-bit register write operation is shown in Fig. 4-69. SCLK D7 SDA D1 R/W A31 A25 A24 A 23 A 17 A16 A15 device ID (Write) ACK register address A31 –A24 ACK register address A23–A 16 ACK START A1 A8 A7 register address A15–A8 ACK A0 register address A7 –A0 A9 B15 ACK B9 B8 B7 ACK data bits B15–B 8 B1 B0 data bits B7– B0 ACK STOP Note: The SDA pin is used as input for the control register address and data; SDA is pulled low by the receiving device to provide the acknowledge(ACK ) response Figure 4-69. Control Interface I2C Register Write (16-Bit Data Words) The I2C protocol for a single, 16-bit register read operation is shown in Fig. 4-70. SCLK D7 SDA START D1 R/W A31 A25 A24 device ID (Write) ACK register address A31 –A24 A1 A0 register address A7–A0 A 23 Rpt START A15 A16 register address A23–A 16 ACK D7 ACK A 17 D1 R/W device ID (Read) ACK A9 A8 A7 register address A15–A8 ACK B15 B9 data bits B 15–B8 B8 B7 ACK B1 data bits B7 –B0 B0 ACK STOP Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses Figure 4-70. Control Interface I2C Register Read (16-Bit Data Words) The control interface also supports other register operations; the interface protocol for these operations is shown in Fig. 4-71 through Fig. 4-74. The terminology used in the following figures is detailed in Table 4-113. DS1162F1 247 CS42L92 4.17 Control Interface Note that 16-bit data words are shown in these illustrations. The equivalent protocol is also applicable to 32-bit words, with 4 data bytes transmitted (or received) instead of 2. Table 4-113. Control Interface (I2C) Terminology Terminology S Sr A Description Start condition Repeated start Acknowledge (SDA low) Not acknowledge (SDA high) A P Stop condition Read/not write 0 = Write; 1 = Read Data flow from bus master to CS42L92 Data flow from CS42L92 to bus master R/W [White field] [Gray field] Fig. 4-71 shows a single register write to a specified address. 8-Bit Device ID S Device ID 8 bits R/W A (0) 8 bits Address Byte [3] A 8 bits Address Byte [2] A 8 bits Address Byte [1] A (Most Significant Byte) Address Byte [0] (Least Significant Byte ) 8 bits A 8 bits MSByte Data A LSByte Data A P A P A P Figure 4-71. Single-Register Write to Specified Address Fig. 4-72 shows a single register read from a specified address. S Device ID R/W A (0) Address Byte [3] A Address Byte [2] A Address Byte [1] A (Most Significant Byte) Address Byte [0] (Least Significant Byte ) A Sr Device ID R/W A MSByte Data A LSByte Data (1) Figure 4-72. Single-Register Read from Specified Address Fig. 4-73 shows a multiple register write to a specified address. S Device ID R/W A Address Byte [3] A Address Byte [2] A Address Byte [1] A Address Byte [0] (0) Written to Register Address A MSByte Data 0 A Written to Register Address + 1 LSByte Data 0 A MSByte Data 1 Written to Register Address + N - 1 A MSByte Data N-1 A LSByte Data N-1 A LSByte Data 1 A Written to Register Address + N A MSByte Data N A LSByte Data N Figure 4-73. Multiple-Register Write to Specified Address 248 DS1162F1 CS42L92 4.18 Control-Write Sequencer Fig. 4-74 shows a multiple register read from a specified address. S Device ID R/W A Address Byte [3] A Address Byte [2] A Address Byte [1] A Address Byte [0] (0) Read from Register Address A Sr Device ID R/W A MSByte Data 0 A LSByte Data 0 A (1) Read from Register Address + N - 1 A MSByte Data N-1 A LSByte Data N-1 Read from Register Address + N A MSByte Data N A LSByte Data N A P Figure 4-74. Multiple-Register Read from Specified Address 4.18 Control-Write Sequencer The control-write sequencer is a programmable unit that forms part of the CS42L92 control interface logic. It provides the ability to perform a sequence of register-write operations with the minimum of demands on the host processor—the sequence may be initiated by a single operation from the host processor and then left to execute independently. Default sequences for pop-suppressed start-up and shutdown of each headphone/earpiece output driver are provided (these are scheduled automatically when the respective output paths are enabled or disabled). Other control sequences can be programmed, and may be associated with sample-rate detection, DRC, MICDET clamp, or event logger status; these sequences are automatically scheduled whenever a corresponding event is detected. When a sequence is initiated, the sequencer performs a series of predefined register writes. The start index of a control sequence within the sequencer’s memory may be commanded directly by the host processor. The applicable start index for each of the sequences associated with sample-rate detection, DRC, MICDET clamp, or event logger status is held in a user-programmed control register. The control-write sequencer may be triggered by a number of different events. Multiple sequences are queued if necessary, and each is scheduled in turn. The control-write sequencer can be supported with or without system clocking—there is no requirement for SYSCLK or for any other system clock to be enabled when using the control-write sequencer. The timing accuracy of the sequencer operation is improved when SYSCLK is present, but the general functionality is supported with or without SYSCLK. 4.18.1 Initiating a Sequence The fields associated with running the control-write sequencer are described in Table 4-114. The CS42L92 provides 16 general-purpose trigger bits for the write sequencer to allow easy triggering of the associated control sequences. Writing 1 to the trigger bit initiates a control sequence, starting at the respective index position within the control-write sequencer memory. The WSEQ_TRG1_INDEX field defines the sequencer start index corresponding to the WSEQ_TRG1 trigger control bit. Equivalent start index fields are provided for each trigger control bit, as described in Table 4-114. Note that a sequencer start index of 0x1FF causes the respective sequence to be aborted. The general-purpose control sequences are undefined following power-on reset, a hardware reset, or a Sleep Mode transition. The general-purpose control sequences must be reconfigured by the host processor following any of these events. Note that all control sequences are maintained in the sequencer memory through software reset. The write sequencer can also be commanded using control bits in register R22 (0x16). In this case, the write sequencer is enabled using the WSEQ_ENA bit and the index location of the first command in the sequence is held in the WSEQ_ START_INDEX field. Writing 1 to the WSEQ_START bit commands the sequencer to execute a control sequence, starting at the specified index position. Note that, if the sequencer is already running, the WSEQ_START command is queued and executed when the sequencer becomes available. DS1162F1 249 CS42L92 4.18 Control-Write Sequencer Note: The mechanism for queuing multiple sequence requests has limitations when the WSEQ_START bit is used to trigger the write sequencer. If a sequence is initiated using the WSEQ_START bit, no other control sequences should be triggered until the sequence completes. The WSEQ_BUSY bit (described in Table 4-120) provides an indication of the sequencer status and can be used to confirm the sequence has completed. Multiple control sequences triggered by any other method are queued if necessary, and scheduled in turn. The write sequencer can be interrupted by writing 1 to the WSEQ_ABORT bit. Note that this command only aborts a sequence that is currently running; if other sequence commands are pending and not yet started, these sequences are not aborted by writing to the WSEQ_ABORT bit. The write sequencer stores up to 508 register-write commands. These are defined in registers R12288 (0x3000) through R13302 (0x33F6). See Table 4-121 for a description of these registers. Table 4-114. Write Sequencer Control—Initiating a Sequence Register Address R22 (0x0016) Write_Sequencer_ Ctrl_0 Bit 11 10 9 8:0 R66 (0x0042) Spare_Triggers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 250 Label Default Description WSEQ_ABORT 0 Writing 1 to this bit aborts the current sequence. WSEQ_START 0 Writing 1 to this bit starts the write sequencer at the index location selected by WSEQ_ START_INDEX. At the end of the sequence, this bit is reset by the write sequencer. WSEQ_ENA 0 Write Sequencer Enable 0 = Disabled 1 = Enabled Only applies to sequences triggered using the WSEQ_START bit. WSEQ_ 0x000 Sequence Start Index. Contains the index location in the sequencer memory of the first START_ command in the selected sequence. INDEX[8:0] Only applies to sequences triggered using the WSEQ_START bit. Valid from 0 to 507 (0x1FB). WSEQ_TRG16 0 Write Sequence Trigger 16 Write 1 to trigger WSEQ_TRG15 0 Write Sequence Trigger 15 Write 1 to trigger WSEQ_TRG14 0 Write Sequence Trigger 14 Write 1 to trigger WSEQ_TRG13 0 Write Sequence Trigger 13 Write 1 to trigger WSEQ_TRG12 0 Write Sequence Trigger 12 Write 1 to trigger WSEQ_TRG11 0 Write Sequence Trigger 11 Write 1 to trigger WSEQ_TRG10 0 Write Sequence Trigger 10 Write 1 to trigger WSEQ_TRG9 0 Write Sequence Trigger 9 Write 1 to trigger WSEQ_TRG8 0 Write Sequence Trigger 8 Write 1 to trigger WSEQ_TRG7 0 Write Sequence Trigger 7 Write 1 to trigger WSEQ_TRG6 0 Write Sequence Trigger 6 Write 1 to trigger WSEQ_TRG5 0 Write Sequence Trigger 5 Write 1 to trigger WSEQ_TRG4 0 Write Sequence Trigger 4 Write 1 to trigger WSEQ_TRG3 0 Write Sequence Trigger 3 Write 1 to trigger WSEQ_TRG2 0 Write Sequence Trigger 2 Write 1 to trigger WSEQ_TRG1 0 Write Sequence Trigger 1 Write 1 to trigger DS1162F1 CS42L92 4.18 Control-Write Sequencer Table 4-114. Write Sequencer Control—Initiating a Sequence (Cont.) Register Address R75 (0x004B) Spare_Sequence_ Select_1 R76 (0x004C) Spare_Sequence_ Select_2 R77 (0x004D) Spare_Sequence_ Select_3 R78 (0x004E) Spare_Sequence_ Select_4 R79 (0x004F) Spare_Sequence_ Select_5 R80 (0x0050) Spare_Sequence_ Select_6 R89 (0x0059) Spare_Sequence_ Select_7 R90 (0x005A) Spare_Sequence_ Select_8 R91 (0x005B) Spare_Sequence_ Select_9 R92 (0x005C) Spare_Sequence_ Select_10 Bit 8:0 R93 (0x005D) Spare_Sequence_ Select_11 8:0 R94 (0x005E) Spare_Sequence_ Select_12 8:0 R104 (0x0068) Spare_Sequence_ Select_13 8:0 R105 (0x0069) Spare_Sequence_ Select_14 8:0 R106 (0x006A) Spare_Sequence_ Select_15 8:0 R107 (0x006B) Spare_Sequence_ Select_16 8:0 8:0 8:0 8:0 8:0 8:0 8:0 8:0 8:0 8:0 Label Default Description WSEQ_TRG1_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer INDEX[8:0] memory of the first command in the sequence associated with the WSEQ_TRG1 trigger. Valid from 0 to 507 (0x1FB). WSEQ_TRG2_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer INDEX[8:0] memory of the first command in the sequence associated with the WSEQ_TRG2 trigger. Valid from 0 to 507 (0x1FB). WSEQ_TRG3_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer INDEX[8:0] memory of the first command in the sequence associated with the WSEQ_TRG3 trigger. Valid from 0 to 507 (0x1FB). WSEQ_TRG4_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer INDEX[8:0] memory of the first command in the sequence associated with the WSEQ_TRG4 trigger. Valid from 0 to 507 (0x1FB). WSEQ_TRG5_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer INDEX[8:0] memory of the first command in the sequence associated with the WSEQ_TRG5 trigger. Valid from 0 to 507 (0x1FB). WSEQ_TRG6_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer INDEX[8:0] memory of the first command in the sequence associated with the WSEQ_TRG6 trigger. Valid from 0 to 507 (0x1FB). WSEQ_TRG7_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer INDEX[8:0] memory of the first command in the sequence associated with the WSEQ_TRG7 trigger. Valid from 0 to 507 (0x1FB). WSEQ_TRG8_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer INDEX[8:0] memory of the first command in the sequence associated with the WSEQ_TRG8 trigger. Valid from 0 to 507 (0x1FB). WSEQ_TRG9_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer INDEX[8:0] memory of the first command in the sequence associated with the WSEQ_TRG9 trigger. Valid from 0 to 507 (0x1FB). WSEQ_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer TRG10_ memory of the first command in the sequence associated with the WSEQ_TRG10 INDEX[8:0] trigger. Valid from 0 to 507 (0x1FB). 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer WSEQ_ TRG11_ memory of the first command in the sequence associated with the WSEQ_TRG11 INDEX[8:0] trigger. Valid from 0 to 507 (0x1FB). WSEQ_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer TRG12_ memory of the first command in the sequence associated with the WSEQ_TRG12 INDEX[8:0] trigger. Valid from 0 to 507 (0x1FB). WSEQ_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer TRG13_ memory of the first command in the sequence associated with the WSEQ_TRG13 INDEX[8:0] trigger. Valid from 0 to 507 (0x1FB). WSEQ_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer TRG14_ memory of the first command in the sequence associated with the WSEQ_TRG14 INDEX[8:0] trigger. Valid from 0 to 507 (0x1FB). WSEQ_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer TRG15_ memory of the first command in the sequence associated with the WSEQ_TRG15 INDEX[8:0] trigger. Valid from 0 to 507 (0x1FB). WSEQ_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer TRG16_ memory of the first command in the sequence associated with the WSEQ_TRG16 INDEX[8:0] trigger. Valid from 0 to 507 (0x1FB). 4.18.2 Automatic Sample-Rate Detection Sequences The CS42L92 supports automatic sample-rate detection on the digital audio interfaces (AIF1–AIF3) when operating in AIF Slave Mode. Automatic sample-rate detection is enabled by setting RATE_EST_ENA—see Table 4-104. DS1162F1 251 CS42L92 4.18 Control-Write Sequencer As many as four audio sample rates can be configured for automatic detection; these sample rates are selected using the SAMPLE_RATE_DETECT_n fields. If a selected audio sample rate is detected, the control-write sequencer is triggered. The applicable start index location within the sequencer memory is separately configurable for each detected sample rate. The WSEQ_SAMPLE_RATE_DETECT_A_INDEX field defines the sequencer start index corresponding to the SAMPLE_ RATE_DETECT_A sample rate. Equivalent start index fields are defined for the other sample rates, as described in Table 4-115. Note that a sequencer start index of 0x1FF causes the respective sequence to be aborted. The automatic sample-rate detection control sequences are undefined following power-on reset, a hardware reset, or a Sleep Mode transition. The automatic sample-rate detection control sequences must be reconfigured by the host processor following any of these events. Note that all control sequences are maintained in the sequencer memory through software reset. See Section 4.16 for further details of the automatic sample-rate detection function. Table 4-115. Write Sequence Control—Automatic Sample-Rate Detection Register Address R97 (0x0061) Sample_Rate_ Sequence_Select_1 Bit 8:0 R98 (0x0062) Sample_Rate_ Sequence_Select_2 8:0 R99 (0x0063) Sample_Rate_ Sequence_Select_3 8:0 R100 (0x0064) Sample_Rate_ Sequence_Select_4 8:0 Label Default Description WSEQ_SAMPLE_ 0x1FF Sample Rate A Write Sequence start index. Contains the index location in the RATE_DETECT_ sequencer memory of the first command in the sequence associated with Sample A_INDEX[8:0] Rate A detection. Valid from 0 to 507 (0x1FB). WSEQ_SAMPLE_ 0x1FF Sample Rate B Write Sequence start index. Contains the index location in the RATE_DETECT_ sequencer memory of the first command in the sequence associated with Sample B_INDEX[8:0] Rate B detection. Valid from 0 to 507 (0x1FB). WSEQ_SAMPLE_ 0x1FF Sample Rate C Write Sequence start index. Contains the index location in the RATE_DETECT_ sequencer memory of the first command in the sequence associated with Sample C_INDEX[8:0] Rate C detection. Valid from 0 to 507 (0x1FB). WSEQ_SAMPLE_ 0x1FF Sample Rate D Write Sequence start index. Contains the index location in the RATE_DETECT_ sequencer memory of the first command in the sequence associated with Sample D_INDEX[8:0] Rate D detection. Valid from 0 to 507 (0x1FB). 4.18.3 DRC Signal-Detect Sequences The DRC function within the CS42L92 digital core provides a configurable signal-detect function. This allows the signal level at the DRC input to be monitored and used to trigger other events. The DRC signal-detect functions are enabled and configured using the fields described in Table 4-17 and Table 4-18 for DRC1 and DRC2 respectively. A control-write sequence can be associated with a rising edge and/or a falling edge of the DRC1 signal-detect output. This is enabled by setting DRC1_WSEQ_SIG_DET_ENA, as described in Table 4-17. Note that signal detection is supported on DRC1 and DRC2, but the triggering of the control-write sequencer is available on DRC1 only. When the DRC signal-detect sequence is enabled, the control-write sequencer is triggered whenever the DRC1 signal-detect output transitions (high or low). The applicable start index location within the sequencer memory is separately configurable for each logic condition. The WSEQ_DRC1_SIG_DET_RISE_SEQ_INDEX field defines the sequencer start index corresponding to a DRC1 signal-detect rising edge event, as described in Table 4-116. The WSEQ_DRC1_SIG_DET_FALL_SEQ_INDEX field defines the sequencer start index corresponding to a DRC1 signal-detect falling edge event. Note that a sequencer start index of 0x1FF causes the respective sequence to be aborted. The DRC signal-detect sequences cannot be independently enabled for rising and falling edges. Instead, a start index of 0x1FF can be used to disable the sequence for either edge, if required. 252 DS1162F1 CS42L92 4.18 Control-Write Sequencer The DRC signal-detect control sequences are undefined following power-on reset, a hardware reset, or a Sleep Mode transition. The DRC signal-detect control sequences must be reconfigured by the host processor following any of these events. Note that all control sequences are maintained in the sequencer memory through software reset. See Section 4.3.5 for further details of the DRC function. Table 4-116. Write Sequencer Control—DRC Signal-Detect Register Address Bit Label R110 (0x006E) 8:0 WSEQ_DRC1_ SIG_DET_RISE_ Trigger_ INDEX[8:0] Sequence_ Select_32 R111 (0x006F) 8:0 WSEQ_DRC1_ SIG_DET_FALL_ Trigger_ INDEX[8:0] Sequence_ Select_33 Default Description 0x1FF DRC1 Signal-Detect (Rising) Write Sequence start index. Contains the index location in the sequencer memory of the first command in the sequence associated with DRC1 Signal-Detect (Rising) detection. Valid from 0 to 507 (0x1FB). 0x1FF DRC1 Signal-Detect (Falling) Write Sequence start index. Contains the index location in the sequencer memory of the first command in the sequence associated with DRC1 Signal-Detect (Falling) detection. Valid from 0 to 507 (0x1FB). 4.18.4 MICDET Clamp Sequences The CS42L92 supports external accessory detection functions, including the MICDET clamp circuits. The MICDET clamp status can be used to trigger the control-write sequencer. The MICDET clamps can be controlled using selectable logic conditions in respect of the JDn signals, as described in Table 4-85. A control-write sequence can be associated with a rising edge and/or a falling edge of the MICDET clamp status. This is configured using the WSEQ_ENA_MICD_CLAMP_RISE and WSEQ_ENA_MICD_CLAMP_FALL bits, as described in Table 4-85. If one of the selected JDn logic conditions is detected, the control-write sequencer is triggered. Note that these control-sequencer events are only valid if the clamp status changed in response to the JDn signals. The applicable start index location within the sequencer memory is separately configurable for the rising and falling edge conditions. Note that, due to control logic that is shared between the two MICDET clamps, the option to control both clamps in response to the JDn signals cannot be supported at the same time. It is assumed that a maximum of one clamp is active at any time. Accordingly, only the active clamp is capable of triggering the control-write sequencer. The WSEQ_MICD_CLAMP_RISE_INDEX field defines the sequencer start index corresponding to a MICDET clamp rising edge (clamp active) event, as described in Table 4-117. The WSEQ_MICD_CLAMP_FALL_INDEX field defines the sequencer start index corresponding to a MICDET clamp falling edge event. Note that a sequencer start index of 0x1FF causes the respective sequence to be aborted. The MICDET clamp control sequences are undefined following power-on reset, a hardware reset, or a Sleep Mode transition. The MICDET clamp control sequences must be reconfigured by the host processor following any of these events. Note that all control sequences are maintained in the sequencer memory through software reset. See Section 4.12 for further details of the MICDET clamp status signals. Table 4-117. Write Sequencer Control—MICDET Clamp Register Address R102 (0x0066) Always_On_Triggers_ Sequence_Select_1 Bit Label 8:0 WSEQ_MICD_ CLAMP_RISE_ INDEX[8:0] R103 (0x0067) Always_On_Triggers_ Sequence_Select_2 8:0 WSEQ_MICD_ CLAMP_FALL_ INDEX[8:0] Default Description 0x1FF MICDET Clamp (Rising) Write Sequence start index. Contains the index location in the sequencer memory of the first command in the sequence associated with MICDET clamp (Rising) detection. Valid from 0 to 507 (0x1FB). 0x1FF MICDET Clamp (Falling) Write Sequence start index. Contains the index location in the sequencer memory of the first command in the sequence associated with MICDET clamp (Falling) detection. Valid from 0 to 507 (0x1FB). 4.18.5 Event Logger Sequences The CS42L92 provides an event log function, for monitoring and recording internal or external signals. The logged events are held in a FIFO buffer, from which the application software can read details of the detected logic transitions. DS1162F1 253 CS42L92 4.18 Control-Write Sequencer The control-write sequencer is automatically triggered whenever the NOT_EMPTY status of the event log buffer is asserted. The WSEQ_EVENTLOG1_INDEX field defines the sequencer start index corresponding to the event logger, as described in Table 4-118. Note that a sequencer start index of 0x1FF causes the respective sequence to be aborted. The event logger control sequence is undefined following power-on reset, a hardware reset, or a Sleep Mode transition. The event logger control sequence must be reconfigured by the host processor following any of these events. Note that all control sequences are maintained in the sequencer memory through software reset. See Section 4.5.1 for further details of the event logger. Table 4-118. Write Sequencer Control—Event Logger Register Address Bit Label R120 (0x0078) 8:0 WSEQ_ EVENTLOG1_ Eventlog_ INDEX[8:0] Sequence_ Select_1 Default Description 0x1FF Event Log 1 Write Sequence start index. Contains the index location in the sequencer memory of the first command in the sequence associated with Event Log 1 FIFO Not-Empty detection. Valid from 0 to 507 (0x1FB). 4.18.6 Boot Sequence The CS42L92 executes a boot sequence following power-on reset, hardware reset, software reset, or wake-up from Sleep Mode. The boot sequence configures the CS42L92 with factory-set trim (calibration) data. See Section 4.22 and Section 4.23 for further details. The start index location of the boot sequence is 384 (0x180). See Table 4-123 for details of the write sequencer memory allocation. The boot sequence can be commanded at any time by writing 1 to the WSEQ_BOOT_START bit. Table 4-119. Write Sequencer Control—Boot Sequence Register Address R24 (0x0018) Write_Sequencer_ Ctrl_2 Bit 1 Label WSEQ_BOOT_ START Default 0 Description Writing 1 to this bit starts the write sequencer at the index location configured for the Boot Sequence. The Boot Sequence start index is 384 (0x180). 4.18.7 Sequencer Status Indication The status of the write sequencer can be read using WSEQ_BUSY and WSEQ_CURRENT_INDEX, as described in Table 4-120. When the WSEQ_BUSY bit is asserted, this indicates that the write sequencer is busy. The index address of the most recent write sequencer command can be read from the WSEQ_CURRENT_INDEX field. This can be used to provide a precise indication of the write sequencer progress. Table 4-120. Write Sequencer Control—Status Indication Register Address Bit Label R23 (0x0017) 9 WSEQ_BUSY Write_Sequencer_ (read only) Ctrl_1 8:0 WSEQ_CURRENT_ INDEX[8:0] (read only) Default Description 0 Sequencer Busy flag (Read Only). 0 = Sequencer idle 1 = Sequencer busy 0x000 Sequence Current Index. This indicates the memory location of the most recently accessed command in the write sequencer memory. Coding is the same as WSEQ_START_INDEX. 4.18.8 Programming a Sequence A control-write sequence comprises a series of write operations to data bits within the control register map. Standard write operations are defined by five fields, contained within a single 32-bit register. An extended instruction set is also defined; the associated actions make use of alternate definitions of the 32-bit registers. 254 DS1162F1 CS42L92 4.18 Control-Write Sequencer The sequencer instruction fields are replicated 508 times, defining each of the sequencer’s 508 possible index addresses. Many sequences can be stored in the sequencer memory at the same time, with each assigned a unique range of index addresses. The WSEQ_DELAYn field is used to identify the end-of-sequence position, as described below. The general definition of the sequencer instruction fields is described as follows, where n denotes the sequencer index address (valid from 0 to 507): • WSEQ_DATA_WIDTHn is a 3-bit field that identifies the width of the data block to be written. Note that the maximum value of this field selects a width of 8 bits; writes to fields that are larger than 8 bits wide must be performed using two separate operations of the write sequencer. • WSEQ_ADDRn is a 12-bit field containing the register address in which the data should be written. The applicable register address is referenced to the base address currently configured for the sequencer—it is calculated as: (base address * 512) + WSEQ_ADDRn. Note that the base address is configured using the sequencer’s extended instruction set. • WSEQ_DELAYn is a 4-bit field that controls the waiting time between the current step and the next step in the sequence (i.e., the delay occurs after the write in which it was called). The total delay time per step (including execution) is defined below, giving a useful range of execution/delay times from 3.3 s up to 1 s per step. If WSEQ_DELAYn = 0x0 or 0xF, the step execution time is 3.3 s For all other values, the step execution time is 61.44 s x ((2 WSEQ_DELAY) – 1) Setting this field to 0xF identifies the step as the last in the sequence • WSEQ_DATA_STARTn is a 4-bit field that identifies the LSB position within the selected control register to which the data should be written. For example, setting WSEQ_DATA_STARTn = 0100 selects bit [4] as the LSB position of the data to be written. • WSEQ_DATAn is an 8-bit field that contains the data to be written to the selected control register. The WSEQ_ DATA_WIDTHn field determines how many of these bits are written to the selected control register; the most significant bits (above the number indicated by WSEQ_DATA_WIDTHn) are ignored. The extended instruction set for the write sequencer is accessed by setting WSEQ_MODEn (bit [28]) in the respective sequencer definition register. The extended instruction set comprises the following functions: • If bits [31:24] = 0x11, the register base address is set equal to the value contained in bits [23:0]. • If bits [31:16] = 0x12FF, the sequencer performs an unconditional jump to the index location defined in bits [15:0]. The index location is valid in the range 0 to 507 (0x1FB). • All other settings within the extended instruction set are reserved. The control field definitions for Step 0 are described in Table 4-121. The equivalent definitions also apply to Step 1 through Step 507, in the subsequent register address locations. DS1162F1 255 CS42L92 4.18 Control-Write Sequencer Table 4-121. Write Sequencer Control—Programming a Sequence Register Address Bit Label R12288 (0x3000) 31:29 WSEQ_DATA_ WIDTH0[2:0] WSEQ_ Sequence_1 Default Description 000 Width of the data block written in this sequence step. 000 = 1 bit 011 = 4 bits 110 = 7 bits 001 = 2 bits 100 = 5 bits 111 = 8 bits 010 = 3 bits 101 = 6 bits 28 WSEQ_MODE0 0 Extended Sequencer Instruction select 0 = Basic instruction set 1 = Extended instruction set 27:16 WSEQ_ADDR0[11:0] 0x000 Control Register Address to be written to in this sequence step. The register address is calculated as: (Base Address * 512) + WSEQ_ADDRn. Base Address is 0x00_0000 by default, and is configured using the sequencer’s extended instruction set. 15:12 WSEQ_DELAY0[3:0] 0000 Time delay after executing this step. 0x0 = 3.3 s 0x1 to 0xE = 61.44 s x ((2WSEQ_DELAY)–1) 0xF = End of sequence marker 11:8 WSEQ_DATA_ 0000 Bit position of the LSB of the data block written in this sequence step. START0[3:0] 0000 = Bit 0 … 1111 = Bit 15 7:0 WSEQ_DATA0[7:0] 0x00 Data to be written in this sequence step. When the data width is less than 8 bits, one or more of the MSBs of WSEQ_DATAn are ignored. It is recommended that unused bits be cleared. 4.18.9 Sequencer Memory Definition The write sequencer memory defines up to 508 write operations; these are indexed as 0 to 507 in the sequencer memory map. The write sequencer memory reverts to its default contents following power-on reset, a hardware reset, or a Sleep Mode transition. In these cases, the sequence memory contains the boot sequence and the OUT1–OUT3 signal path enable/ disable sequences; the remainder of the sequence memory is undefined. User-defined sequences can be programmed after power-up. The user-defined control sequences must be reconfigured by the host processor following power-on reset, a hardware reset, or a Sleep Mode transition. Note that all control sequences are maintained in the sequencer memory through software reset. See Section 5.2 for a summary of the CS42L92 memory reset conditions. The default control sequences can be overwritten in the sequencer memory, if required. Note that the headphone/earpiece output path enable bits (HPnx_ENA) always trigger the write sequencer (at the predetermined start index addresses). Writing 1 to the WSEQ_LOAD_MEM bit clears the sequencer memory to the power-on reset state. Table 4-122. Write Sequencer Control—Load Memory Control Register Address R24 (0x0018) Write_Sequencer_Ctrl_2 Bit 0 Label WSEQ_LOAD_ MEM Default 0 Description Writing 1 to this bit resets the sequencer memory to the power-on reset state. The sequencer memory is summarized in Table 4-123. User-defined sequences should be assigned space within the allocated portion (user space) of the write sequencer memory. The start index for the user-defined sequences is configured using the fields described in Table 4-114 through Table 4-118. 256 DS1162F1 CS42L92 4.19 Charge Pumps, Regulators, and Voltage Reference Table 4-123. Write Sequencer Memory Allocation Description Default Sequences User Space Boot Sequence Sequence Index Range 0 to 302 303 to 383 384 to 507 4.19 Charge Pumps, Regulators, and Voltage Reference The CS42L92 incorporates two charge-pump circuits and an LDO-regulator circuit to generate supply rails for internal functions and to support external microphone requirements. The CS42L92 also provides two MICBIAS generators (with six switchable outputs), which provide low noise reference voltages suitable for biasing ECM-type microphones or powering digital microphones. In Sleep Mode, the CS42L92 can provide an unregulated voltage output that can be used to power an external microphone. See Section 4.13 for details of Sleep Mode. The CPVDD domain (1.8 V) powers the Charge Pump 1 and Charge Pump 2 circuits. The CPVDD2 power domain (1.2 V) is an additional supply used by Charge Pump 1 only. Refer to Section 5.1 for recommended external components. 4.19.1 Charge Pump 1 Charge Pump 1 (CP1) is used to generate the positive and negative supply rails for the analog output drivers. CP1 is enabled automatically by the CS42L92 when required by the output drivers. The Charge Pump 1 circuit is shown in Fig. 4-75. 4.19.2 Charge Pump 2 and LDO2 Regulator Charge Pump 2 (CP2) powers LDO2, which provides the supply rail for analog input circuits and for the MICBIAS generators. CP2 and LDO2 are enabled by setting CP2_ENA. If CP2 and LDO2 are enabled, the MICVDD voltage is selected using the LDO2_VSEL field. Note that, when one or more of the MICBIAS generators is operating in normal (regulator) mode, the MICVDD voltage must be at least 200 mV greater than the highest selected MICBIASn output voltages. If CP2 and LDO2 are enabled, an internal bypass path may be selected, connecting the MICVDD pin directly to the CPVDD supply. This path is controlled using the CP2_BYPASS bit. Note that the bypass path is only supported when CP2 is enabled. Note: The 32-kHz clock must be configured and enabled if CP2 is enabled in its normal operating mode. The 32-kHz clock is not required in bypass mode (CP2_BYPASS = 1). See Section 4.16 for details of the system clocks. If CP2 is disabled, the CP2VOUT pin can be either floating or actively discharged. The behavior is configured using the CP2_DISCH bit. If LDO2 is disabled, the MICVDD pin can be either floating or actively discharged. The behavior is configured using the LDO2_DISCH bit. The MICVDD pin is connected to the output of LDO2. Note that the MICVDD does not support direct connection to an external supply; MICVDD is always powered internally to the CS42L92. The Charge Pump 2 and LDO2 Regulator circuits are shown in Fig. 4-75. The associated control bits are described in Table 4-124. Note that decoupling capacitors and flyback capacitors are required for these circuits. Refer to Section 5.1 for recommended external components. DS1162F1 257 CS42L92 4.19 Charge Pumps, Regulators, and Voltage Reference 4.19.3 Microphone Bias (MICBIAS) Control There are two MICBIAS generators, which provide low-noise reference voltages suitable for biasing ECM-type microphones or powering digital microphones. Refer to Section 5.1.3 for recommended external components. The MICBIAS generators are powered from MICVDD, which is generated by an internal charge pump and LDO, as shown in Fig. 4-75. Switchable outputs from the MICBIAS generators allow six separate reference/supply outputs to be independently controlled. The MICBIAS regulators are enabled using the MICB1_ENA and MICB2_ENA bits. The MICBIAS output switches are enabled using the MICB1x_ENA and MICB2x_ENA (where x is A, B, C, or D). The MICBIAS1 generator supports four switchable outputs (MICBIAS1A–MICBIAS1D). The MICBIAS2 generator supports two switchable outputs (MICBIAS2A–MICBIAS2B). Note that, to enable any of the MICBIASnx outputs, both the output switch and the respective regulator must be enabled. When a MICBIAS output is disabled, it can be configured to be floating or to be actively discharged. This is configured using the MICBn_DISCH bits (for the MICBIAS regulators), and the MICBnx_DISCH bits (for the switched outputs). Each discharge path is only effective when the respective regulator, or switched output, is disabled. The MICBIAS generators can each operate in Regulator Mode or in Bypass Mode. The applicable mode is selected using the MICBn_BYPASS bits. In Regulator Mode (MICBn_BYPASS = 0), the output voltage is selected using the MICBn_LVL fields. In this mode, MICVDD must be at least 200 mV greater than the required MICBIAS output voltages. The MICBIAS outputs are powered from the MICVDD pin and use the internal band-gap circuit as a reference. In Regulator Mode, the MICBIAS regulators are designed to operate without external decoupling capacitors. The regulators can be configured to support a capacitive load if required, using the MICBn_EXT_CAP bits. (This may be appropriate for a DMIC supply.) It is important that the external capacitance is compatible with the applicable MICBn_EXT_ CAP setting. The compatible load conditions are detailed in Table 3-11. In Bypass Mode (MICBn_BYPASS = 1), the respective outputs (MICBIASnx), when enabled, are connected directly to MICVDD. This enables a low power operating state. Note that the MICBn_EXT_CAP settings are not applicable in Bypass Mode—there are no restrictions on the external MICBIAS capacitance in Bypass Mode. The MICBIAS generators incorporate a pop-free control circuit to ensure smooth transitions when the MICBIAS outputs are enabled or disabled in Bypass Mode; this feature is enabled using the MICBn_RATE bits. The MICBIAS generators are shown in Fig. 4-75. The MICBIAS control fields are described in Table 4-124. The maximum output current for each MICBIAS regulator is noted in Table 3-11. This limit must be observed for each set of MICBIASnx outputs, especially if more than one microphone is connected to a single regulator. Note that the maximum output current differs between Regulator Mode and Bypass Mode. 4.19.3.1 MICBIAS output in Sleep Mode The CS42L92 supports a low-power Sleep Mode, in which most functions are disabled and power consumption is minimized. The CS42L92 can maintain an unregulated voltage output in Sleep Mode, suitable for powering an external microphone in always-on applications. The INnx/DMICx connections are isolated from the CS42L92 circuits in Sleep Mode, to allow any connected microphone to be used by another circuit while Sleep Mode is selected. If the MICB1A_AOD_ENA bit is set, the normal register-field configuration of CP2, LDO2, and MICBIAS1 are overridden. Under these conditions, the CP2, LDO2 and MICBIAS1 circuits are bypassed and the MICBIAS1A output is connected directly to the CPVDD supply. The unregulated MICBIAS1A output can be maintained in Sleep Mode by setting MICB1A_AOD_ENA before the DCVDD supply is removed. 258 DS1162F1 CS42L92 4.19 Charge Pumps, Regulators, and Voltage Reference To minimize any transient effects during the Sleep Mode transition, the MICBIAS1A should be configured in bypass mode before Sleep Mode is enabled. The following control sequence is recommended: • CP_BYPASS = 1 • MICB1_BYPASS = 1 • MICB1A_AOD_ENA = 1 • Remove DCVDD To minimize any transient effects following a wake-up transition, the MICBIAS1A should be configured in bypass mode before clearing MICB1A_AOD_ENA. The following control sequence is recommended: • Apply DCVDD • LDO2_VSEL = (set as required) • CP2_BYPASS = 0 • MICB1_LVL = (set as required) • MICB1_BYPASS = 0 • MICB1_ENA = 1 • MICB1A_ENA = 1 • MICB1A_AOD_ENA = 0 4.19.4 Voltage-Reference Circuit The CS42L92 incorporates a voltage-reference circuit, powered by AVDD. This circuit ensures the accuracy of the LDO-regulator and MICBIAS voltage settings. 4.19.5 Block Diagram and Control Registers The charge-pump and regulator circuits are shown in Fig. 4-75. Note that decoupling capacitors and flyback capacitors are required for these circuits. Refer to Section 5.1 for recommended external components. DS1162F1 259 CS42L92 CPVDD CP1C1A CP1C1B CP1C2A CP1C2B CP1VOUT1P CP1VOUT1N CP1VOUT2P CP1VOUT2N CPVDD2 4.19 Charge Pumps, Regulators, and Voltage Reference Charge Pump 1 CPGND CP2CA CP2CB CP2_ENA p. 260 CP2_BYPASS p. 260 CP2_DISCH p. 260 Charge Pump 2 CP2VOUT Analog Output Supply MICBIAS1A MICB1_ENA p. 261 MICB1_BYPASS p. 261 MICB1_LVL[3:0] p. 261 MICB1_RATE p. 261 MICB1_DISCH p. 261 MICB1_EXT_CAP p. 261 LDO2_VSEL[5:0] p. 261 LDO2_DISCH p. 261 LDO2 MICB1A_ENA p. 262 MICB1A_DISCH p. 262 MICBIAS1B MICB1B_ENA p. 262 MICB1B_DISCH p. 262 MICBIAS1C MICB1C_ENA p. 262 MICB1C_DISCH p. 262 MICBIAS1D MICVDD MICB1D_ENA p. 262 MICB1D_DISCH p. 262 Analog Input Supply Analog Supply AVDD AGND Voltage Reference AVDD MICBIAS2A MICB2_ENA p. 261 MICB2_BYPASS p. 261 MICB2_LVL[3:0] p. 261 MICB2_RATE p. 261 MICB2_DISCH p. 261 MICB2_EXT_CAP p. 261 MICB2A_ENA p. 262 MICB2A_DISCH p. 262 MICBIAS2B MICB2B_ENA p. 262 MICB2B_DISCH p. 262 Analog Reference Figure 4-75. Charge Pumps and Regulators The charge-pump and regulator control registers are described in Table 4-124. Table 4-124. Charge-Pump and LDO Control Registers Register Address Bit Label R512 (0x0200) 2 CP2_DISCH Mic_Charge_ Pump_1 260 1 CP2_BYPASS 0 CP2_ENA Default Description 1 Charge Pump 2 Discharge 0 = CP2VOUT floating when disabled 1 = CP2VOUT discharged when disabled 1 Charge Pump 2 and LDO2 Bypass Mode 0 = Normal 1 = Bypass Mode In Bypass Mode, CPVDD is connected directly to MICVDD. Note that CP2_ENA must also be set. 1 Charge Pump 2 and LDO2 Control (Provides analog input and MICVDD supplies) 0 = Disabled 1 = Enabled DS1162F1 CS42L92 4.19 Charge Pumps, Regulators, and Voltage Reference Table 4-124. Charge-Pump and LDO Control Registers (Cont.) Register Address Bit Label R531 (0x0213) 10:5 LDO2_VSEL[5:0] LDO2_Control_1 R536 (0x0218) Mic_Bias_Ctrl_1 R537 (0x0219) Mic_Bias_Ctrl_2 DS1162F1 Default Description 0x1F LDO2 Output Voltage Select 1 0x00 = 0.900 V 0x13 = 1.375 V … (100-mV steps) 0x01 = 0.925 V 0x14 = 1.400 V 0x26 = 3.200 V 0x02 = 0.950 V 0x15 = 1.500 V 0x27 to 0x3F = 3.300 V … (25-mV steps) 0x16 = 1.600 V 2 LDO2_DISCH 1 LDO2 Discharge 0 = MICVDD floating when disabled 1 = MICVDD discharged when disabled 15 MICB1_EXT_CAP 0 Microphone Bias 1 External Capacitor (when MICB1_BYPASS = 0). Configures the MICBIAS1 regulator according to the specified capacitance connected to the MICBIAS1x outputs. 0 = No external capacitor 1 = External capacitor connected 8:5 MICB1_LVL[3:0] 0x7 Microphone Bias 1 Voltage Control (when MICB1_BYPASS = 0) 0x0 = 1.5 V … (0.1-V steps) 0xD to 0xF = 2.8 V 0x1 = 1.6 V 0xC = 2.7 V 3 MICB1_RATE 0 Microphone Bias 1 Rate (Bypass Mode) 0 = Fast start-up/shutdown 1 = Pop-free start-up/shutdown 2 MICB1_DISCH 1 Microphone Bias 1 Discharge 0 = MICBIAS1 floating when disabled 1 = MICBIAS1 discharged when disabled 1 MICB1_BYPASS 1 Microphone Bias 1 Mode 0 = Regulator Mode 1 = Bypass Mode 0 MICB1_ENA 0 Microphone Bias 1 Enable 0 = Disabled 1 = Enabled 15 MICB2_EXT_CAP 0 Microphone Bias 2 External Capacitor (when MICB2_BYPASS = 0). Configures the MICBIAS2 regulator according to the specified capacitance connected to the MICBIAS2x outputs. 0 = No external capacitor 1 = External capacitor connected 8:5 MICB2_LVL[3:0] 0x7 Microphone Bias 2 Voltage Control (when MICB2_BYPASS = 0) 0x0 = 1.5 V … (0.1-V steps) 0xD to 0xF = 2.8 V 0x1 = 1.6 V 0xC = 2.7 V 3 MICB2_RATE 0 Microphone Bias 2 Rate (Bypass Mode) 0 = Fast start-up/shutdown 1 = Pop-free start-up/shutdown 2 MICB2_DISCH 1 Microphone Bias 2 Discharge 0 = MICBIAS2 floating when disabled 1 = MICBIAS2 discharged when disabled 1 MICB2_BYPASS 1 Microphone Bias 2 Mode 0 = Regulator Mode 1 = Bypass Mode 0 MICB2_ENA 0 Microphone Bias 2 Enable 0 = Disabled 1 = Enabled 261 CS42L92 4.19 Charge Pumps, Regulators, and Voltage Reference Table 4-124. Charge-Pump and LDO Control Registers (Cont.) Register Address Bit Label R540 (0x021C) 13 MICB1D_DISCH Mic_Bias_Ctrl_5 12 MICB1D_ENA R542 (0x021E) Mic_Bias_Ctrl_6 R723 (0x02D3) Jack_detect_ analogue 9 MICB1C_DISCH 8 MICB1C_ENA 5 MICB1B_DISCH 4 MICB1B_ENA 1 MICB1A_DISCH 0 MICB1A_ENA 5 MICB2B_DISCH 4 MICB2B_ENA 1 MICB2A_DISCH 0 MICB2A_ENA 14 MICB1A_AOD_ ENA Default Description 1 Microphone Bias 1D Discharge 0 = MICBIAS1D floating when disabled 1 = MICBIAS1D discharged when disabled 0 Microphone Bias 1D Enable 0 = Disabled 1 = Enabled 1 Microphone Bias 1C Discharge 0 = MICBIAS1C floating when disabled 1 = MICBIAS1C discharged when disabled 0 Microphone Bias 1C Enable 0 = Disabled 1 = Enabled 1 Microphone Bias 1B Discharge 0 = MICBIAS1B floating when disabled 1 = MICBIAS1B discharged when disabled 0 Microphone Bias 1B Enable 0 = Disabled 1 = Enabled 1 Microphone Bias 1A Discharge 0 = MICBIAS1A floating when disabled 1 = MICBIAS1A discharged when disabled 0 Microphone Bias 1A Enable 0 = Disabled 1 = Enabled 1 Microphone Bias 2B Discharge 0 = MICBIAS2B floating when disabled 1 = MICBIAS2B discharged when disabled 0 Microphone Bias 2B Enable 0 = Disabled 1 = Enabled 1 Microphone Bias 2A Discharge 0 = MICBIAS2A floating when disabled 1 = MICBIAS2A discharged when disabled 0 Microphone Bias 2A Enable 0 = Disabled 1 = Enabled 0 Microphone Bias 1A Always-On Enable 0 = Disabled 1 = Enabled 1.See Table 4-125 for LDO2 output voltage definition. Table 4-125 lists the LDO2 voltage control settings. Table 4-125. LDO2 Voltage Control LDO2_VSEL[5:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 262 LDO Output 0.900 V 0.925 V 0.950 V 0.975 V 1.000 V 1.025 V 1.050 V 1.075 V 1.100 V 1.125 V 1.150 V LDO2_VSEL[5:0] 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F LDO Output 1.500 V 1.600 V 1.700 V 1.800 V 1.900 V 2.000 V 2.100 V 2.200 V 2.300 V 2.400V 2.500 V DS1162F1 CS42L92 4.20 JTAG Interface Table 4-125. LDO2 Voltage Control (Cont.) LDO2_VSEL[5:0] 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 LDO Output 1.175 V 1.200 V 1.225 V 1.250 V 1.275 V 1.300 V 1.325 V 1.350 V 1.375 V 1.400 V LDO2_VSEL[5:0] 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 to 0x3F LDO Output 2.600 V 2.700 V 2.800 V 2.900 V 3.000 V 3.100 V 3.200 V 3.300 V 3.300 V 4.20 JTAG Interface The JTAG interface provides test and debug access to the CS42L92. The interface comprises five connections, some of which are multiplexed with the GPIO13–GPIO15 pins, as noted in Table 4-126. Table 4-126. JTAG Interface Connections Pin No N8 R8 F7 J8 D7 Pin Name AIF3BCLK/GPIO14 AIF3RXDAT/GPIO15 TDO AIF3TXDAT/GPIO13 TRST JTAG Function TCK TDI TDO TMS TRST JTAG Description Clock input Data input Data output Mode select input Test access port reset input (active low) The JTAG interface is supported whenever the GPIO13–GPIO15 are configured as GPIO inputs. To allow JTAG operation, the following conditions must be met: • GPn_FN = 0x001 (n = 13–15) • GPn_DIR = 0x1 (n = 13–15) The GPn_FN and GPn_DIR fields are defined in Table 4-93. Note that the above conditions are also the default values of these control fields. For normal operation (test and debug access disabled), the JTAG interface should be held in reset. An internal pull-down resistor holds the TRST pin low (i.e., JTAG interface is held in reset) when not actively driven. It is recommended to connect the TRST pin to DGND, if the JTAG interface function is not required. Integrated pull-up and pull-down resistors can be enabled on the TCK, TDI, and TMS pins. This is provided as part of the GPIO functionality, and provides a flexible capability for interfacing with other devices. The pull-up and pull-down resistors can be configured independently using the fields described in Table 4-93. If the JTAG interface is enabled (TRST deasserted and TCK active) at the time of any reset, a software reset must be scheduled, with the TCK input stopped or TRST asserted (Logic 0), before using the JTAG interface. It is recommended to always schedule a software reset before starting the JTAG clock or deasserting the JTAG reset. In this event, the JTAG interface should be held in its reset state until the software reset has completed, and the BOOT_ DONE_STSx bits have been set. See Section 4.23 for further details of the CS42L92 software reset. 4.21 Short-Circuit Protection The CS42L92 provides short-circuit protection on the headphone output drivers. The short-circuit protection function for the headphone output paths operates continuously if the respective output driver is enabled. If a short circuit is detected on the headphone output, current limiting is applied to protect the respective output driver. Note that the driver continues to operate, but the output is current-limited. DS1162F1 263 CS42L92 4.22 Power-On Reset (POR) The headphone short-circuit protection function provides input to the interrupt control circuit and can be used to trigger an interrupt event when a short-circuit condition is detected; see Section 4.15. 4.22 Power-On Reset (POR) The CS42L92 remains in the reset state until AVDD, DBVDD, and DCVDD are above their respective reset thresholds. Note that specified device performance is not assured outside the voltage ranges defined in Table 3-3. After the initial power-up, the POR is rescheduled following an interruption to the DBVDD or AVDD supplies. If the CS42L92 SLIMbus component is in its operational state, it must be reset before scheduling a POR. See Section 4.10 for details of the SLIMbus reset control messages. 4.22.1 Boot Sequence Following power-on reset, a boot sequence is executed. The BOOT_DONE_STSx bits are asserted on completion of the boot sequence, as described in Table 4-127. Control-register writes should not be attempted until BOOT_DONE_STSx has been asserted. Note that the BOOT_DONE_STS1 and BOOT_DONE_STS2 bits provide the same information. The BOOT_DONE_STSx signal is an input to the interrupt control circuit and can be used to trigger an interrupt event on completion of the boot sequence; see Section 4.15. Under default register conditions, a falling edge on the IRQ pin indicates completion of the boot sequence. For details of the boot sequence, see Section 4.18. Table 4-127. Device Boot-Up Status Register Address Bit Label R6272 (0x1880) 7 BOOT_DONE_ STS1 IRQ1_Raw_ Status_1 R6528 (0x1980) IRQ2_Raw_ Status_1 7 BOOT_DONE_ STS2 Default Description 0 Boot Status 0 = Busy (boot sequence in progress) 1 = Idle (boot sequence completed) Control register writes should not be attempted until Boot Sequence has completed. 0 Boot Status 0 = Busy (boot sequence in progress) 1 = Idle (boot sequence completed) Control register writes should not be attempted until Boot Sequence has completed. 4.22.2 Digital I/O Status in Reset Table 1-1 describes the default status of the CS42L92 digital I/O pins on completion of power-on reset, prior to any register writes. The same default conditions are also applicable on completion of a hardware reset or software reset (see Section 4.23). The same default conditions are applicable following a wake-up transition, except for the IRQ and RESET pins. These are always-on pins whose configuration is unchanged in Sleep Mode and during a wake-up transition. Note that the default conditions described in Table 1-1 are not valid if modified by the boot sequence or by a wake-up control sequence. See Section 4.18 for details of these functions. 4.23 Hardware Reset, Software Reset, Wake-Up, and Device ID The CS42L92 supports hardware- and software-controlled reset functions. The reset functions, and the Sleep/Wake-Up state transitions, provide similar (but not identical) functionality. Each of these is described in the following subsections. The CS42L92 device ID can be read from the Software_Reset (R0) control register, as described in Section 4.23.7. 264 DS1162F1 CS42L92 4.23 Hardware Reset, Software Reset, Wake-Up, and Device ID 4.23.1 Hardware Reset The CS42L92 provides a hardware reset function, which is executed whenever the RESET input is asserted (Logic 0). The RESET input is active low and is referenced to the DBVDD power domain. A hardware reset causes all of the CS42L92 control registers to be reset to their default states. An internal pull-up resistor is enabled by default on the RESET pin; this can be configured using the RESET_PU bit. A pull-down resistor is also available, as described in Table 4-128. When the pull-up and pull-down resistors are both enabled, the CS42L92 provides a bus keeper function on the RESET pin. The bus keeper function holds the input logic level unchanged whenever the external circuit removes the drive (e.g., if the signal is tristated). If the CS42L92 SLIMbus component is in its operational state, it must be reset prior to scheduling a hardware reset. See Section 4.10 for details of the SLIMbus reset control messages. Table 4-128. Reset Pull-Up/Pull-Down Configuration Register Address R6864 (0x1AD0) AOD_Pad_Ctrl Bit Label Default Description 1 RESET_PU 1 RESET Pull-up enable 0 = Disabled 1 = Enabled Note: If RESET_PD and RESET_PU are both set, a bus keeper function is enabled on the RESET pin. 0 RESET_PD 0 RESET Pull-down enable 0 = Disabled 1 = Enabled Note: If RESET_PD and RESET_PU are both set, a bus keeper function is enabled on the RESET pin. 4.23.2 Software Reset A software reset is executed by writing any value to register R0. A software reset causes most of the CS42L92 control registers to be reset to their default states. Note that the control-write sequencer memory is retained during software reset. Note that the first register read/write operation following a software reset may be unsuccessful, if the register access is attempted via a different control interface to the one that commanded the software reset. Note that only the first register read/write is affected, and only when using more than one control interface. 4.23.3 Wake-Up The CS42L92 is in Sleep Mode when AVDD and DBVDD are present, and DCVDD is below its reset threshold. (Note that specific control requirements are also applicable for entering Sleep Mode, as described in Section 4.13.) In Sleep Mode, most of the digital core (and control registers) are held in reset; selected functions and control registers are maintained via an always-on internal supply domain. See Section 4.13 for details of the always-on functions. A wake-up transition (from Sleep Mode) is similar to a software reset, but selected functions and control registers are maintained via an always-on internal supply domain—the always-on registers are not reset during wake-up. See Section 4.13 for details of the always-on functions. 4.23.4 Write Sequencer and DSP Firmware Memory Control in Reset and Wake-Up The control-write sequencer memory contents reverts to its default contents following power-on reset, a hardware reset, or a Sleep Mode transition. The control sequences (including any user-defined sequences) are maintained in the sequencer memory through software reset. The DSP firmware memory contents are cleared following power-on reset, a hardware reset, or a Sleep Mode transition. The firmware memory contents are not affected by software reset, provided DCVDD is held above its reset threshold. See Section 5.2 for a summary of the CS42L92 memory reset conditions. DS1162F1 265 CS42L92 4.23 Hardware Reset, Software Reset, Wake-Up, and Device ID 4.23.5 Boot Sequence Following hardware reset, software reset, or wake-up from Sleep Mode, a boot sequence is executed. The BOOT_DONE_ STSx bits (see Table 4-127) are deasserted during hardware reset and software reset, and also in Sleep Mode. The BOOT_DONE_STSx bits are asserted on completion of the boot sequence. Control register writes should not be attempted until BOOT_DONE_STSx has been asserted. The BOOT_DONE_STSx status is an input to the interrupt control circuit and can be used to trigger an interrupt event; see Section 4.15. Note that the BOOT_DONE_STS1 and BOOT_DONE_STS2 bits provide the same information. For details of the boot sequence, see Section 4.18. 4.23.6 Digital I/O Status in Reset The status of the CS42L92 digital I/O pins following hardware reset, software reset, or wake-up is described in Section 4.22.2. 4.23.7 Device ID The device ID can be read from Register R0. The hardware revision can be read from Register R1. The software revision can be read from Register R2. The software revision code is incremented if software driver compatibility or software feature support is changed. Table 4-129. Device Reset and ID Register Address Bit Label Default Description R0 (0x0000) 15:0 SW_RST_DEV_ 0x6371 Writing to this register resets all registers to their default state. ID[15:0] Software_Reset Reading from this register indicates Device ID 0x6371. R1 (0x0001) 7:0 HW_ — Hardware Device revision. REVISION[7:0] Hardware_ This field is incremented for every new revision of the device. Revision R2 (0x0002) 7:0 SW_ — Software Device revision. REVISION[7:0] Software_Revision This field is incremented if software driver compatibility or software feature support is changed. 266 DS1162F1 CS42L92 5 Applications 5 Applications 5.1 Recommended External Components This section provides information on the recommended external components for use with the CS42L92. 5.1.1 Analog Input Paths The CS42L92 supports up to eight analog audio input connections. Each input is biased to the internal DC reference, VREF. (Note that this reference voltage is present on the VREFC pin.) A DC-blocking capacitor is required for each analog input pin used in the target application. The choice of capacitor is determined by the filter that is formed between that capacitor and the impedance of the input pin. The circuit is shown in Fig. 5-1. Fc = VREF Input + PGA – C R 1 2  RC Fc = High-pass 3 dB cut-off frequency Figure 5-1. Audio Input Path DC-Blocking Capacitor In accordance with the CS42L92 input pin resistance (see Table 3-5), a 1-F capacitance for all input connections gives good results in most cases, with a 3-dB cut-off frequency around 13 Hz. Ceramic capacitors are suitable, but take care to ensure the desired capacitance is maintained at the AVDD operating voltage. Also, ceramic capacitors may show microphonic effects, where vibrations and mechanical conditions give rise to electrical signals. This is particularly problematic for microphone input paths where a large signal gain is required. A single capacitor is required for a single-ended line or microphone input connection. For a differential input connection, a DC-blocking capacitor is required on both input pins. The external connections for single-ended and differential microphones, incorporating the CS42L92 microphone bias circuit, are shown in Fig. 5-2. 5.1.2 DMIC Input Paths The CS42L92 supports up to eight channels of DMIC input; two channels of audio data can be multiplexed on each DMICDATn pin. Each stereo pair is clocked using the respective DMICCLKn pin. The external connections for digital microphones, incorporating the CS42L92 microphone bias circuit, are shown in Fig. 5-4. Ceramic decoupling capacitors for the digital microphones may be required—refer to the specific recommendations for the application microphones. If two microphones are connected to a single DMICDAT pin, the microphones must be configured to ensure that the Left mic transmits a data bit when DMICCLK is high, and the Right mic transmits a data bit when DMICCLK is low. The CS42L92 samples the DMIC data at the end of each DMICCLK phase. Each microphone must tristate its data output when the other microphone is transmitting. Integrated pull-down resistors can be enabled on the DMICDAT pins if required. The voltage reference for each DMIC interface is selectable. It is important that the selected reference for the CS42L92 interface is compatible with the applicable configuration of the external microphone. DS1162F1 267 CS42L92 5.1 Recommended External Components 5.1.3 Microphone Bias Circuit The CS42L92 is designed to interface easily with analog or digital microphones. Each microphone requires a bias current (electret condenser microphones) or voltage supply (silicon microphones); these can be provided by the MICBIAS regulators on the CS42L92. Two MICBIAS generators are available; switchable outputs allow six separate reference/supply outputs to be independently controlled. Note that the MICVDD pin can also be used (instead of MICBIASnx) as a reference or power supply for external microphones. The MICBIAS outputs are recommended, as these offer better noise performance and independent enable/ disable control. Analog microphones may be connected in single-ended or differential configurations, as shown in Fig. 5-2. The differential configuration provides better performance due to its rejection of common-mode noise; the single-ended method provides a reduction in external component count. A bias resistor is required when using an ECM. The bias resistor should be chosen according to the minimum operating impedance of the microphone and MICBIAS voltage so that the maximum bias current of the CS42L92 is not exceeded. A 2.2-k bias resistor is recommended; this provides compatibility with a wide range of microphone components. MICBIAS MICBIAS INnAxP, INnBLP, INnBx INnAxN, IN1BLN ECM INnAxP, INnBLP, INnBx + PGA – To ADC ECM + PGA – INnAxN, IN1BLN To ADC GND VREF VREF GND Figure 5-2. Single-Ended and Differential Analog Microphone Connections Analog MEMS microphones can be connected to the CS42L92 as shown in Fig. 5-3. In this configuration, the MICBIAS generators provide a low-noise supply for the microphones; a bias resistor is not required. MICBIAS VDD MEMS Mic OUT INnAxP, INnBLP, INnBx GND INnAxN, IN1BLN GND VREF MICBIAS + PGA – To ADC MEMS Mic VDD OUT-P OUT-N GND GND INnAxP, INnBLP, INnBx INnAxN, IN1BLN + PGA – To ADC VREF Figure 5-3. Single-Ended and Differential Analog Microphone Connections DMIC connection to the CS42L92 is shown in Fig. 5-4. Note that ceramic decoupling capacitors at the DMIC power supply pins may be required—refer to the specific recommendations for the application microphones. 268 DS1162F1 CS42L92 5.1 Recommended External Components MICVDD or MICBIASnx DMICCLKn DMICDATn VDD VDD CLK DATA Digital Mic CHAN VDD Digital Microphone Interface The DMIC inputs are referenced to MICVDD, MICBIAS1, or MICBIAS2. CLK DATA Digital Mic The supply for each digital microphone should provide the same voltage as the applicable reference. CHAN AGND Figure 5-4. DMIC Connection Each MICBIAS generator can operate in Regulator Mode or in Bypass Mode. See Section 4.19 for details of the MICBIAS generators. In Regulator Mode, the MICBIAS regulators are designed to operate without external decoupling capacitors. The regulators can be configured to support a capacitive load if required (e.g., for DMIC supply decoupling). The compatible load conditions are detailed in Table 3-11. If the capacitive load on MICBIAS1 or MICBIAS2 exceeds the specified conditions for Regulator Mode (e.g., due to a decoupling capacitor or long PCB trace), the respective generator must be configured in Bypass Mode. The maximum output current for each MICBIAS regulator is noted in Table 3-11. This limit must be observed for each set of MICBIASnx outputs, especially if more than one microphone is connected to a single regulator. Note that the maximum output current differs between Regulator Mode and Bypass Mode. The MICBIAS output voltage can be adjusted using register control in Regulator Mode. 5.1.4 Headphone Driver Output Path The CS42L92 provides four stereo headphone output drivers. These outputs are all ground referenced, allowing direct connection to the external loads. There is no requirement for DC-blocking capacitors. In single-ended (default) configuration, the headphone outputs comprise eight independently controlled output channels, for up to four stereo headphone or line outputs. In mono (BTL) mode, the headphone drivers support up to four differential outputs, suitable for a mono earpiece or hearing coil load. Note that the OUT3 signal path is common to the HPOUT3 and HPOUT4 drivers—only one of these stereo drivers may be enabled at any time. The headphone outputs incorporate a common mode, or ground loop, feedback path that provides rejection of system-related ground noise. The feedback pins must be connected to ground for normal operation of the headphone outputs. Five feedback pins are provided (HPOUTFB1–HPOUTFB5). The ground feedback path for each HPOUT path is selected using the HPn_GND_SEL bits as follows: • The ground feedback path for HPOUT1 and HPOUT2 headphone outputs is selected using the HP1_GND_SEL and HP2_GND_SEL register fields respectively—see Table 4-81. • The ground feedback path for HPOUT3 and HPOUT4 headphone outputs is selected using the HP3_GND_SEL field. DS1162F1 269 CS42L92 5.1 Recommended External Components The selected feedback pin should be connected to GND as close as possible to the respective headphone jack ground pin, as shown in Fig. 5-5. In mono (differential) mode, the feedback pins should be connected to the ground plane that is closest to the earpiece output PCB tracks. It is recommended to ensure that the electrical characteristics of the PCB traces for each output pair are closely matched. This is particularly important to matching the two traces of a differential (BTL) output. Typical headphone and earpiece connections are shown in Fig. 5-5. CS42L92 HPOUT1L HPOUT1R HPOUTFB1 HPOUTFB2 The HPOUT outputs can use any of the HPOUTFBn pins for ground feedback. The feedback pins are configured using HP1_GND_SEL, HP2_GND_SEL and HP2_GND_SEL. NC HPOUT2L HPOUT2R HPOUTFB3 HPOUTFB4 NC HPOUT3L HPOUT3R Line Output (Aux/Dock) HPOUT4L HPOUT4R Earpiece HPOUTFB5 Each headphone output can support stereo (single-ended) or mono (differential) output. The illustration shows the configuration for a typical application . Figure 5-5. Headphone and Earpiece Connection It is common for ESD diodes to be wired to pins that link to external connectors. This provides protection from potentially harmful ESD effects. In a typical application, ESD diodes would be recommended if the headphone paths (HPOUT1–HPOUT4) are used for external headphone or line output. The HPOUTn outputs are ground-referenced, and the respective voltages may swing between +1.8V and –1.8V. The ESD diode configuration must be carefully chosen. The recommended ESD diode configuration for these ground-referenced outputs is shown in Fig. 5-6. The back-to-back arrangement prevents clipping and distortion of the output signal. Note that similar care is required when connecting the CS42L92 outputs to external circuits that provide input path ESD protection; the configuration on those input circuits must be correctly designed to accommodate ground-referenced signals. 270 DS1162F1 CS42L92 5.1 Recommended External Components CS42L92 HPOUTnL External Headphone/Line Output Connection HPOUTnR External Headphone/Line Output Connection ESD Protection Diodes Figure 5-6. ESD Diode Configuration for External Output Connections 5.1.5 Power Supply/Reference Decoupling Electrical coupling exists particularly in digital logic systems where switching in one subsystem causes fluctuations on the power supply. This effect occurs because the inductance of the power supply acts in opposition to the changes in current flow that are caused by the logic switching. The resultant variations (spikes) in the power-supply voltage can cause malfunctions and unintentional behavior in other components. A decoupling (bypass) capacitor can be used as an energy storage component that provides power to the decoupled circuit for the duration of these power-supply variations, protecting it from malfunctions that could otherwise arise. Coupling also occurs in a lower frequency form when ripple is present on the power supply rail caused by changes in the load current or by limitations of the power-supply regulation method. In audio components such as the CS42L92, these variations can alter the performance of the signal path, leading to degradation in signal quality. A decoupling capacitor can be used to filter these effects by presenting the ripple voltage with a low-impedance path that does not affect the circuit to be decoupled. These coupling effects are addressed by placing a capacitor between the supply rail and the corresponding ground reference. In the case of systems comprising multiple power supply rails, decoupling should be provided on each rail. PCB layout is also a contributory factor for coupling effects. If multiple power supply rails are connected to a single supply source, it is recommended to provide separate PCB tracks connecting each rail to the supply. See Section 5.5 for PCB-layout recommendations. The recommended power-supply decoupling capacitors for CS42L92 are detailed in Table 5-1. Table 5-1. Power Supply Decoupling Capacitors Power Supply AVDD1, AVDD2 CPVDD1 CPVDD2 DBVDD DCVDD FLLVDD MICVDD VREFC Decoupling Capacitor 2 x 1.0 F ceramic—one capacitor on each AVDDn pin 4.7 F ceramic 4.7 F ceramic 1 x 0.1 F ceramic 1 2 x 1.0 F ceramic—one capacitor on each DCVDD pin 4.7 F ceramic 4.7 F ceramic 2.2 F ceramic 1.Total capacitance of 4.7 F is required for the DBVDD domain. This can be provided by dedicated DBVDD decoupling or by other capacitors on the same power rail. DS1162F1 271 CS42L92 5.1 Recommended External Components All decoupling capacitors should be placed as close as possible to the CS42L92 device. The connection between AGND, the AVDD decoupling capacitor, and the main system ground should be made at a single point as close as possible to the AGND balls of the CS42L92. Due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacitance across the required temperature and voltage ranges in the intended application. For most application the use of ceramic capacitors with capacitor dielectric X7R is recommended. 5.1.6 Charge-Pump Components The CS42L92 incorporates two charge-pump circuits (CP1 and CP2). CP1 generates the CP1VOUTnx supply rails for the ground-referenced headphone drivers; CP2 generates the CP2VOUT supply rail for the microphone bias (MICBIAS) regulators. Decoupling capacitors are required on each of the charge-pump outputs. Two fly-back capacitors are required for CP1; a single fly-back capacitor is required for CP2. The recommended charge-pump capacitors for CS42L92 are detailed in Table 5-2. Table 5-2. Charge-Pump External Capacitors Description CP1VOUT1P decoupling CP1VOUT1N decoupling CP1 fly-back 1 (connect between CP1C1A and CP1C1B) CP1VOUT2P decoupling CP1VOUT2N decoupling CP1 fly-back 2 (connect between CP1C2A and CP1C2B) CP2VOUT decoupling CP2 fly-back (connect between CP2CA and CP2CB) Capacitor Required capacitance is 2.0 F at 2 V. Suitable component typically 4.7 F. Required capacitance is 2.0 F at 2 V. Suitable component typically 4.7 F. Required capacitance is 1.0 F at 2 V. Suitable component typically 2.2 F. Required capacitance is 2.0 F at 2 V. Suitable component typically 4.7 F. Required capacitance is 2.0 F at 2 V. Suitable component typically 4.7 F. Required capacitance is 1.0 F at 2 V. Suitable component typically 2.2 F. Required capacitance is 1.0 F at 3.6 V. Suitable component typically 4.7 F. Required capacitance is 220 nF at 2 V. Suitable component typically 470 nF. Ceramic capacitors are recommended for these charge-pump requirements. Note that, due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacitance across the required temperature and voltage ranges in the intended application. Ceramic capacitors with X7R dielectric are recommended. The positioning of the charge-pump capacitors is important. These capacitors (particularly the fly-back capacitors) must be placed as close as possible to the CS42L92. The component choice and positioning of the CP1 components are more critical than those of CP2, due to the higher output power requirements of CP1. 5.1.7 External Accessory Detection Components The external accessory detection circuit measures jack insertion using the JACKDETn pins. The insertion switch status is detected using an internal pull-up resistor circuit on the respective pin. Note that the logic thresholds associated with the JACKDETn pins differ from each other, as described in Table 3-11—this provides support for different jack switch configurations. Microphone detection and key-button press detection is supported using the MICDETn pins. The applicable pin should be connected to one of the MICBIASnx outputs, via a 2.2-k bias resistor, as described in Section 5.1.3. Note that, when using the external accessory detection function, the MICBIASnx resistor must be 2.2 k ±2%. A recommended circuit configuration, including headphone output on HPOUT1 and microphone connections, is shown in Fig. 5-7. See Section 5.1.1 for details of the DC-blocking microphone input capacitor selection. 272 DS1162F1 CS42L92 5.1 Recommended External Components The recommended external components and connections for microphone/push-button detection are shown in Fig. 5-7. Note that, when using the microphone detect circuit, it is recommended to use the IN1ALx, IN1BLx, or IN1BR analog microphone input paths to ensure best immunity to electrical transients arising from the external accessory. CS42L92 2.2 k(±2%) MICBIASnx * IN1ALx, IN1BLx, IN1BR C MICDET1 HPOUT1L HPOUT1R HPOUTFB2 (jack insertion switch ) JACKDETn * Note that the IN1ALx, IN1BLx, or IN1BR analog mic channels are recommended with the external accessory detect function Note: The illustrated circuit assumes the jack insertion switch contacts are closed when the jack is inserted. Figure 5-7. External Accessory Detection The accessory detection circuit measures the impedance of an external load connected to one of the MICDET pins. The microphone-detection circuit uses MICVDD, or any one of the MICBIASnx sources, as a reference. The applicable source is configured using MICDn_BIAS_SRC. With default register configuration, the CS42L92 can detect the presence of a typical microphone and up to four push buttons, using the components shown in Fig. 5-8. When the microphone detection circuit is enabled, each of the push buttons shown causes a different bit in the MICDn_LVL field to be set. The choice of external resistor values must take into account the impedance of the microphone—the detected impedance corresponds to the combined parallel resistance of the microphone and any asserted push button. The components shown in Fig. 5-8 are examples only, assuming default impedance measurement ranges and a microphone impedance of 1 k or higher. DS1162F1 273 CS42L92 5.2 Resets Summary The measured impedance is reported using the MICDm_STS and MICDm_LVL bits. If no accessory or push button is detected, the MICDm_STS bit is cleared. MICBIAS If MICDm_STS = 1, one of the MICDm_LVL bits is set to indicate the measured impedance. The applicable MICDm_LVL bit for each push button is noted below. 2.2 k (±2%) Detection of the microphone alone (no push buttons closed) is indicated in MICDm_LVL[8]. Analog Input Rmic 1 k MICDETn HPDETn JACKDETn MICDm_LVL[8] – Microphone detect R1 = 0  MICDm_LVL[0] R2 = 150  MICDm_LVL[1] R3 = 270  MICDm_LVL[2] MICDm_LVL[3] R4 = 620  C 4 x Push Buttons Sense pin selected by MICDm_SENSE_SEL MICDETn Ground pin selected by MICDm_GND_SEL Microphone Figure 5-8. External Accessory Detect Components 5.2 Resets Summary Table 5-3 summarizes the CS42L92 registers and other programmable memory under different reset conditions. The associated events and conditions are listed as follows: • A power-on reset occurs when AVDD or DBVDD is below its respective reset threshold. Note that DCVDD is also required for initial start-up; subsequent interruption to DCVDD should only be permitted as part of a control sequence for entering Sleep Mode. • A hardware reset occurs when the RESET input is asserted (Logic 0). • A software reset occurs when register R0 is written to. • Sleep Mode is selected when DCVDD is removed. Note that the AVDD and DBVDD supplies must be present throughout the Sleep Mode duration. Table 5-3. Memory Reset Summary Reset Type Power-on reset Hardware reset Software reset Sleep Mode Always-On Registers 1 Other Registers Reset Reset Reset Retained Reset Reset Reset Reset Control-Write Sequencer Memory Reset Reset Retained Reset DSP Firmware Memory Reset Reset Retained 2 Reset 1.See Section 4.13 for details of Sleep Mode and the always-on registers. 2.To retain the DSP firmware memory contents during software reset, it must be ensured that DCVDD is held above its reset threshold. 5.3 Output-Signal Drive-Strength Control The CS42L92 supports configurable drive-strength control for the digital output pins. This can be used to assist system-level integration and design considerations. The drive-strength control bits are described in Table 5-4. Note that, in the case of bidirectional pins (e.g., GPIOn), the drive-strength control bits are only applicable if the pin is configured as an output. 274 DS1162F1 CS42L92 5.3 Output-Signal Drive-Strength Control Table 5-4. Output Drive-Strength and Slew-Rate Control Register Address R8 (0x0008) Ctrl_IF_CFG_1 Bit 8 Label CIF1MISO_DRV_ STR Default 1 R1520 (0x05F0) Slimbus_Pad_Ctrl 1 SLIMDAT2_DRV_ STR 1 1 SLIMDAT1_DRV_ STR 1 0 SLIMCLK_DRV_ STR 1 R5889 (0x1701) GPIO1_CTRL2 12 GP1_DRV_STR 1 R5891 (0x1703) GPIO2_CTRL2 12 GP2_DRV_STR 1 R5893 (0x1705) GPIO3_CTRL2 12 GP3_DRV_STR 1 R5895 (0x1707) GPIO4_CTRL2 12 GP4_DRV_STR 1 R5897 (0x1709) GPIO5_CTRL2 12 GP5_DRV_STR 1 R5899 (0x170B) GPIO6_CTRL2 12 GP6_DRV_STR 1 R5901 (0x170D) GPIO7_CTRL2 12 GP7_DRV_STR 1 R5903 (0x170F) GPIO8_CTRL2 12 GP8_DRV_STR 1 R5905 (0x1711) GPIO9_CTRL2 12 GP9_DRV_STR 1 R5907 (0x1713) GPIO10_CTRL2 12 GP10_DRV_STR 1 R5909 (0x1715) GPIO11_CTRL2 12 GP11_DRV_STR 1 R5911 (0x1717) GPIO12_CTRL2 12 GP12_DRV_STR 1 R5913 (0x1719) GPIO13_CTRL2 12 GP13_DRV_STR 1 DS1162F1 Description CIF1MISO output drive strength 0 = 4 mA 1 = 8 mA SLIMDAT2 output drive strength 0 = 8 mA 1 = 12 mA SLIMDAT1 output drive strength 0 = 8 mA 1 = 12 mA SLIMCLK output drive strength 0 = 2 mA 1 = 4 mA GPIO1 output drive strength 0 = 4 mA 1 = 8 mA GPIO2 output drive strength 0 = 4 mA 1 = 8 mA SPKCLK/GPIO3 output drive strength 0 = 4 mA 1 = 8 mA SPKDAT/GPIO4 output drive strength 0 = 4 mA 1 = 8 mA AIF1TXDAT/GPIO5 output drive strength 0 = 4 mA 1 = 8 mA AIF1BCLK/GPIO6 output drive strength 0 = 4 mA 1 = 8 mA AIF1RXDAT/GPIO7 output drive strength 0 = 4 mA 1 = 8 mA AIF1LRCLK/GPIO8 output drive strength 0 = 4 mA 1 = 8 mA AIF2TXDAT/GPIO9 output drive strength 0 = 4 mA 1 = 8 mA AIF2BCLK/GPIO10 output drive strength 0 = 4 mA 1 = 8 mA AIF2RXDAT/GPIO11 output drive strength 0 = 4 mA 1 = 8 mA AIF2LRCLK/GPIO12 output drive strength 0 = 4 mA 1 = 8 mA AIF3TXDAT/GPIO13 output drive strength 0 = 4 mA 1 = 8 mA 275 CS42L92 5.4 Digital Audio Interface Clocking Configurations Table 5-4. Output Drive-Strength and Slew-Rate Control (Cont.) Register Address R5915 (0x171B) GPIO14_CTRL2 Bit 12 Label GP14_DRV_STR Default 1 R5917 (0x171D) GPIO15_CTRL2 12 GP15_DRV_STR 1 R5919 (0x171F) GPIO16_CTRL2 12 GP16_DRV_STR 1 Description AIF3BCLK/GPIO14 output drive strength 0 = 4 mA 1 = 8 mA AIF3RXDAT/GPIO15 output drive strength 0 = 4 mA 1 = 8 mA AIF3LRCLK/GPIO16 output drive strength 0 = 4 mA 1 = 8 mA 5.4 Digital Audio Interface Clocking Configurations The digital audio interfaces (AIF1–AIF3) can be configured in master or slave modes. In all applications, it is important that the system clocking configuration is correctly designed. Incorrect clock configurations lead to audible clicks arising from dropped or repeated audio samples; this is caused by the inherent tolerances of multiple asynchronous system clocks. To ensure reliable clocking of the audio interface functions, the external interface clocks (e.g., BCLK, LRCLK) must be derived from the same clock source as SYSCLK (or ASYNCCLK, where applicable). In AIF Master Mode, the external BCLK and LRCLK signals are generated by the CS42L92 and synchronization of these signals with SYSCLK (or ASYNCCLK) is ensured. In this case, clocking of the AIF is typically derived from the MCLKn inputs, either directly or via one of the FLL circuits. Alternatively, an AIFn or SLIMbus interface can be used to provide the reference clock to which the AIF master can be synchronized. In AIF Slave Mode, the external BCLK and LRCLK signals are generated by another device, as inputs to the CS42L92. In this case, the system clock (SYSCLK or ASYNCCLK) must be generated from a source that is synchronized to the external BCLK and LRCLK inputs. In a typical Slave Mode application, the BCLK input is selected as the clock reference, using the FLL to perform frequency shifting. The MCLK1, MCLK2, or MCLK3 inputs can also be used, but only if the selected clock is synchronized externally to the BCLK and LRCLK inputs. The SLIMbus interface can also provide the clock reference, via one of the FLLs, provided that the BCLK and LRCLK signals are externally synchronized with the SLIMCLK input. The valid AIF clocking configurations are listed in Table 5-5 for AIF Master and AIF Slave Modes. The applicable system clock (SYSCLK or ASYNCCLK) depends on the AIFn_RATE setting for the relevant digital audio interface; if AIFn_RATE < 1000, SYSCLK is applicable; if AIFn_RATE  1000, ASYNCCLK is applicable. Table 5-5. AIF Clocking Configurations AIF Mode AIF Master Mode AIF Slave Mode Clocking Configuration SYSCLK_SRC (ASYNCCLK_SRC) selects MCLK1, MCLK2, or MCLK3 as SYSCLK (ASYNCCLK) source. SYSCLK_SRC (ASYNCCLK_SRC) selects FLLn as SYSCLK (ASYNCCLK) source; FLLn_REFCLK_SRC selects MCLK1, MCLK2, or MCLK3 as FLLn source. SYSCLK_SRC (ASYNCCLK_SRC) selects FLLn as SYSCLK (ASYNCCLK) source; FLLn_REFCLK_SRC selects a different interface (BCLK, LRCLK, SLIMCLK) as FLLn source. SYSCLK_SRC (ASYNCCLK_SRC) selects FLLn as SYSCLK (ASYNCCLK) source; FLLn_REFCLK_SRC selects BCLK as FLLn source. SYSCLK_SRC (ASYNCCLK_SRC) selects MCLK1, MCLK2, or MCLK3 as SYSCLK (ASYNCCLK) source, provided MCLK is externally synchronized to the BCLK input. SYSCLK_SRC (ASYNCCLK_SRC) selects FLLn as SYSCLK (ASYNCCLK) source; FLLn_REFCLK_SRC selects MCLK1, MCLK2, or MCLK3 as FLLn source, provided MCLK is externally synchronized to the BCLK input. SYSCLK_SRC (ASYNCCLK_SRC) selects FLLn as SYSCLK (ASYNCCLK) source; FLLn_REFCLK_SRC selects a different interface (e.g., SLIMCLK) as FLLn source, provided the other interface is externally synchronized to the BCLK input. In each case, the SYSCLK (ASYNCCLK) frequency must be a valid ratio to the LRCLK frequency; the supported clocking rates are defined by the SYSCLK_FREQ (ASYNC_CLK_FREQ) and SAMPLE_RATE_n (ASYNC_SAMPLE_RATE_n) fields. 276 DS1162F1 CS42L92 5.4 Digital Audio Interface Clocking Configurations The valid AIF clocking configurations are shown in Fig. 5-9 to Fig. 5-15. Note that, where MCLK1 is shown as the clock source, it is equally possible to select MCLK2 or MCLK3 as the clock source. Similarly, in cases where FLL1 is shown, it is equally possible to select FLL2. Fig. 5-9 shows AIF Master Mode operation, using MCLK as the clock reference. CS42L92 Processor AIFnBCLK MCLK3 MCLK2 MCLK1 FLLn AIFnBCLK SLIMCLK SYSCLK (or ASYNCCLK) AIFn (Master Mode) SYSCLK_SRC (or ASYNC_CLK_SRC) AIFnLRCLK AIFnRXDAT AIFnTXDAT Oscillator Figure 5-9. AIF Master Mode, Using MCLK as Reference Fig. 5-10 shows AIF Master Mode operation, using MCLK as the clock reference. In this example, the FLL is used to generate the system clock, with MCLK as the reference. CS42L92 Processor AIFnBCLK AIFnLRCLK SLIMCLK FLL1 MCLK3 MCLK2 MCLK1 FLL1_REFCLK _SRC AIFnBCLK AIFnBCLK SLIMCLK MCLK1 MCLK2 MCLK3 SYSCLK (or ASYNCCLK) AIFn (Master Mode) AIFnLRCLK AIFnRXDAT AIFnTXDAT SYSCLK_SRC (or ASYNC_CLK_SRC) Oscillator Figure 5-10. AIF Master Mode, Using MCLK and FLL as Reference DS1162F1 277 CS42L92 5.4 Digital Audio Interface Clocking Configurations Fig. 5-11 shows AIF Master Mode operation, using a separate interface as the clock reference. In this example, the FLL is used to generate the system clock, with SLIMCLK as the reference. CS42L92 Processor FLL1 FLL1_REFCLK _SRC AIFnBCLK AIFnLRCLK SLIMCLK MCLK1 MCLK2 MCLK3 AIFnBCLK AIFnBCLK SLIMCLK MCLK1 MCLK2 MCLK3 SYSCLK (or ASYNCCLK) AIFn (Master Mode) AIFnLRCLK AIFnRXDAT AIFnTXDAT SYSCLK_SRC (or ASYNC_CLK_SRC) Processor AIFnBCLK AIFn (Slave Mode) AIFnLRCLK AIFnRXDAT AIFnTXDAT Automatic Divider FRAMER_REF_GEAR Processor SLIMbus Interface SLIMCLK SLIMDAT Figure 5-11. AIF Master Mode, Using Another Interface as Reference Fig. 5-12 shows AIF Slave Mode operation, using BCLK as the clock reference. In this example, the FLL is used to generate the system clock, with BCLK as the reference. CS42L92 AIFnBCLK AIFnLRCLK SLIMCLK MCLK1 MCLK2 MCLK3 FLL1_REFCLK_SRC Processor FLL1 AIFnBCLK AIFnBCLK SLIMCLK MCLK1 MCLK2 MCLK3 SYSCLK (or ASYNCCLK) AIFn (Slave Mode) AIFnLRCLK AIFnRXDAT AIFnTXDAT SYSCLK_SRC (or ASYNC_CLK_SRC) Figure 5-12. AIF Slave Mode, Using BCLK and FLL as Reference 278 DS1162F1 CS42L92 5.4 Digital Audio Interface Clocking Configurations Fig. 5-13 shows AIF Slave Mode operation, using MCLK as the clock reference. For correct operation, the MCLK input must be fully synchronized to the audio interface. CS42L92 Processor MCLK3 MCLK2 MCLK1 FLLn AIFnBCLK SLIMCLK AIFnBCLK SYSCLK (or ASYNCCLK) AIFn (Slave Mode) AIFnLRCLK AIFnRXDAT AIFnTXDAT SYSCLK_SRC (or ASYNC_CLK_SRC) Synchronous Clock Generator Figure 5-13. AIF Slave Mode, Using MCLK as Reference Fig. 5-14 shows AIF Slave Mode operation, using MCLK as the clock reference. For correct operation, the MCLK input must be fully synchronized to the audio interface. In this example, the FLL is used to generate the system clock, with MCLK as the reference. CS42L92 Processor AIFnBCLK AIFnLRCLK SLIMCLK MCLK3 MCLK2 MCLK1 FLL1_REFCLK _SRC FLL1 AIFnBCLK AIFnBCLK SLIMCLK MCLK1 MCLK2 MCLK3 SYSCLK (or ASYNCCLK) AIFn (Slave Mode) AIFnLRCLK AIFnRXDAT AIFnTXDAT SYSCLK_SRC (or ASYNC_CLK_SRC) Synchronous Clock Generator Figure 5-14. AIF Slave Mode, Using MCLK and FLL as Reference DS1162F1 279 CS42L92 5.5 PCB Layout Considerations Fig. 5-15 shows AIF Slave Mode operation, using a separate interface as the clock reference. In this example, the FLL is used to generate the system clock, with SLIMCLK as the reference. For correct operation, the SLIMCLK input must be fully synchronized to the other audio interfaces. Processor MCLK1 MCLK2 MCLK3 FLL1 FLL1_REFCLK _SRC AIFnBCLK AIFnLRCLK SLIMCLK CS42L92 AIFnBCLK SLIMCLK MCLK1 MCLK2 MCLK3 AIFnBCLK SYSCLK (or ASYNCCLK) AIFn (Slave Mode) AIFnLRCLK AIFnRXDAT AIFnTXDAT SYSCLK_SRC (or ASYNC_CLK_SRC) Synchronous Clock Generator Processor AIFnBCLK AIFn (Slave Mode) AIFnLRCLK AIFnRXDAT AIFnTXDAT Automatic Divider FRAMER_REF_GEAR Processor SLIMbus Interface SLIMCLK SLIMDAT Figure 5-15. AIF Slave Mode, Using Another Interface as Reference 5.5 PCB Layout Considerations PCB layout should be carefully considered, to ensure optimum performance of the CS42L92. Poor PCB layout degrades the performance and is a contributory factor in EMI, ground bounce, and resistive voltage losses. All external components should be placed close to the CS42L92, with current loop areas kept as small as possible. The following specific considerations should be noted: • Placement of the charge pump capacitors is a high priority requirement—these capacitors (particularly the fly-back capacitors) must be placed as close as possible to the CS42L92. The component choice and positioning of the CP1 components are more critical than those of CP2, due to the higher output power requirements of CP1. • Decoupling capacitors should be placed as close as possible to the CS42L92. The connection between AGND, the AVDD decoupling capacitor, and the main system ground should be made at a single point as close as possible to the AGND balls of the CS42L92. • The VREFC capacitor should be placed as close as possible to the CS42L92. The ground connection to the VREFC capacitor should be as close as possible to the AGND1 ball of the CS42L92. • If multiple power supply rails are connected to a single supply source, it is recommended to provide separate PCB tracks connecting each rail to the supply. This configuration is also known as star connection. • If power supply rails are routed between different layers of the PCB, it is recommended to use several track vias, in order to minimize resistive voltage losses. • Differential input signal tracks should be routed as a pair, ensuring similar length/width dimensions on each track. Input signal paths should be kept away from high frequency digital signals. 280 DS1162F1 CS42L92 6 Register Map • Differential output signal tracks should be routed as a pair, ensuring similar length/width dimensions on each track. The tracks should provide a low resistance path from the device output pin to the load (< 1% of the minimum load). • The headphone output ground-feedback pins should be connected to GND as close as possible to the respective headphone jack ground pin. The ground-feedback PCB track should follow the same route as the respective output signal paths. 6 Register Map The CS42L92 control registers are listed in the following tables. Note that only the register addresses described here should be accessed; writing to other addresses may result in undefined behavior. Register bits that are not documented should not be changed from the default values. The CS42L92 register map is defined in two regions: • The register space below 0x3000 is defined in 16-bit word format • The register space from 0x3000 upwards is defined in 32-bit word format It is important to ensure that all control interface register operations use the applicable data word format, in accordance with the applicable register addresses. The 16-bit codec register space is described in Table 6-1. Table 6-1. Register Map Definition—16-bit region Register R0 (0h) R1 (1h) R2 (2h) R8 (8h) R22 (16h) R23 (17h) R24 (18h) R32 (20h) R33 (21h) R34 (22h) R35 (23h) R36 (24h) R48 (30h) R49 (31h) R50 (32h) R66 (42h)R65 (41h) R75 (4Bh) R76 (4Ch) R77 (4Dh) R78 (4Eh) R79 (4Fh) R80 (50h) Name Software_Reset 15 14 13 12 11 10 9 Hardware_Revision 0 0 0 0 0 0 0 0 HW_REVISION [7:0] 0001h Software_Revision 0 0 0 0 0 0 0 0 SW_REVISION [7:0] 0000h Ctrl_IF_CFG_1 0 0 0 0 0 0 1 Write_Sequencer_Ctrl_0 0 0 0 0 WSEQ_ ABORT WSEQ_ START WSEQ_ ENA WSEQ_START_INDEX [8:0] 0000h Write_Sequencer_Ctrl_1 0 0 0 0 0 0 WSEQ_ BUSY WSEQ_CURRENT_INDEX [8:0] 0000h Write_Sequencer_Ctrl_2 0 0 0 0 0 0 0 Tone_Generator_1 TONE_RATE [4:0] 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 TONE2_ TONE1_ OVD OVD 1 0 0 0 0 0 0 0 WSEQ_ WSEQ_ BOOT_ LOAD_ START MEM TONE2_ TONE1_ ENA ENA 0 0 0 0 0 0 0 0 0 PWM_Drive_1 0 0 0 PWM_RATE [4:0] 0 0 0000h 0000h TONE2_LVL [7:0] 0 0000h 1000h 0 PWM_CLK_SEL [2:0] 0308h 0000h TONE1_LVL [7:0] TONE2_LVL [23:8] 0 Default 6371h 1000h TONE1_LVL [23:8] Tone_Generator_4 Tone_Generator_5 7 CIF1MISO CIF1MISO _DRV_ _PD STR TONE_OFFSET [1:0] Tone_Generator_2 Tone_Generator_3 8 SW_RST_DEV_ID [15:0] 0 PWM2_ OVD PWM1_ OVD 0 0 PWM2_ ENA PWM1_ ENA 0000h PWM_Drive_2 0 0 0 0 0 0 PWM1_LVL [9:0] 0100h PWM_Drive_3 0 0 0 0 0 0 PWM2_LVL [9:0] 0100h Spare_Triggers WSEQ_ TRG16 WSEQ_ TRG15 WSEQ_ TRG14 WSEQ_ TRG13 WSEQ_ TRG12 WSEQ_ TRG11 WSEQ_ TRG10 0 0 0 0 0 0 0 WSEQ_TRG1_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG2_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG3_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG4_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG5_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG6_INDEX [8:0] 01FFh Spare_Sequence_ Select_1 Spare_Sequence_ Select_2 Spare_Sequence_ Select_3 Spare_Sequence_ Select_4 Spare_Sequence_ Select_5 Spare_Sequence_ Select_6 DS1162F1 WSEQ_ TRG9 WSEQ_ TRG8 WSEQ_ TRG7 WSEQ_ TRG6 WSEQ_ TRG5 WSEQ_ TRG4 WSEQ_ TRG3 WSEQ_ TRG2 WSEQ_ TRG1 0000h 281 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R89 (59h) R90 (5Ah) R91 (5Bh) R92 (5Ch) R93 (5Dh) R94 (5Eh) R97 (61h) R98 (62h) R99 (63h) R100 (64h) R102 (66h) R103 (67h) R104 (68h) R105 (69h) R106 (6Ah) R107 (6Bh) R110 (6Eh) R111 (6Fh) R120 (78h) R144 (90h) R145 (91h) R146 (92h) R147 (93h) R148 (94h) R149 (95h) R150 (96h) R151 (97h) R152 (98h) R160 (A0h) R256 (100h) R257 (101h) R258 (102h) R259 (103h) R260 (104h) R266 (10Ah) R267 (10Bh) R268 (10Ch) R274 (112h) 282 Name Spare_Sequence_ Select_7 Spare_Sequence_ Select_8 Spare_Sequence_ Select_9 Spare_Sequence_ Select_10 Spare_Sequence_ Select_11 Spare_Sequence_ Select_12 Sample_Rate_ Sequence_Select_1 Sample_Rate_ Sequence_Select_2 Sample_Rate_ Sequence_Select_3 Sample_Rate_ Sequence_Select_4 Always_On_Triggers_ Sequence_Select_1 Always_On_Triggers_ Sequence_Select_2 Spare_Sequence_ Select_13 Spare_Sequence_ Select_14 Spare_Sequence_ Select_15 Spare_Sequence_ Select_16 Trigger_Sequence_ Select_32 Trigger_Sequence_ Select_33 Eventlog_Sequence_ Select_1 Haptics_Control_1 15 14 13 12 11 10 9 0 0 0 0 0 0 0 WSEQ_TRG7_INDEX [8:0] Default 01FFh 0 0 0 0 0 0 0 WSEQ_TRG8_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG9_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG10_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG11_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG12_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_SAMPLE_RATE_DETECT_A_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_SAMPLE_RATE_DETECT_B_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_SAMPLE_RATE_DETECT_C_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_SAMPLE_RATE_DETECT_D_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_MICD_CLAMP_RISE_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_MICD_CLAMP_FALL_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG13_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG14_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG15_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_TRG16_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_DRC1_SIG_DET_RISE_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_DRC1_SIG_DET_FALL_INDEX [8:0] 01FFh 0 0 0 0 0 0 0 WSEQ_EVENTLOG1_INDEX [8:0] 01FFh 0 0 Haptics_Control_2 0 Haptics_phase_1_ intensity Haptics_phase_1_ duration Haptics_phase_2_ intensity Haptics_phase_2_ duration Haptics_phase_3_ intensity Haptics_phase_3_ duration Haptics_Status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOISE_ GEN_ENA 0 0 0 0 CLK_32K_ ENA 0 0 0 SYSCLK_ ENA 0 0 Comfort_Noise_ Generator Clock_32k_1 HAP_RATE [4:0] 8 0 7 6 0 5 0 4 0 ONESHOT _TRIG 3 2 HAP_CTRL [1:0] 1 0 HAP_ACT 0 7FFFh LRA_FREQ [14:0] NOISE_GEN_RATE [4:0] 0000h 0 0000h PHASE1_INTENSITY [7:0] 0000h PHASE1_DURATION [8:0] 0 0000h PHASE2_INTENSITY [7:0] 0000h PHASE2_DURATION [10:0] 0 0000h PHASE3_INTENSITY [7:0] 0000h PHASE3_DURATION [8:0] 0 0 0 0 ONESHOT _STS 0000h NOISE_GEN_GAIN [4:0] 0000h 0 0002h 0 0 0 0 0 SYSCLK_ FRAC 0 0 0 0 Sample_rate_1 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_1 [4:0] 0011h Sample_rate_2 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_2 [4:0] 0011h Sample_rate_3 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_3 [4:0] 0011h Sample_rate_1_status 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_1_STS [4:0] 0000h Sample_rate_2_status 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_2_STS [4:0] 0000h Sample_rate_3_status 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_3_STS [4:0] 0000h Async_clock_1 0 0 0 0 0 0 ASYNC_ CLK_ENA 0 System_Clock_1 SYSCLK_FREQ [2:0] ASYNC_CLK_FREQ [2:0] 0 0 CLK_32K_SRC [1:0] SYSCLK_SRC [3:0] ASYNC_CLK_SRC [3:0] 0404h 0305h DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R275 (113h) R276 (114h) R283 (11Bh) R284 (11Ch) R329 (149h) R330 (14Ah) Name Async_sample_rate_1 15 14 13 12 11 10 9 8 7 6 5 0 0 0 0 0 0 0 0 0 0 0 ASYNC_SAMPLE_RATE_1 [4:0] Default 0011h Async_sample_rate_2 0 0 0 0 0 0 0 0 0 0 0 ASYNC_SAMPLE_RATE_2 [4:0] 0011h Async_sample_rate_1_ status Async_sample_rate_2_ status Output_system_clock 0 0 0 0 0 0 0 0 0 0 0 ASYNC_SAMPLE_RATE_1_STS [4:0] 0000h 0 0 0 0 0 0 0 0 0 0 0 ASYNC_SAMPLE_RATE_2_STS [4:0] 0000h OPCLK_ ENA 0 0 0 0 0 0 0 OPCLK_DIV [4:0] OPCLK_SEL [2:0] 0000h 0 0 0 0 0 0 0 OPCLK_ASYNC_DIV [4:0] OPCLK_ASYNC_SEL [2:0] 0000h R334 (14Eh) R338 (152h) R339 (153h) R340 (154h) R341 (155h) R342 (156h) R352 (160h) R369 (171h) R370 (172h) Clock_Gen_Pad_Ctrl OPCLK_ ASYNC_ ENA 0 0 0 0 0 0 Rate_Estimator_1 0 0 0 0 0 0 0 0 Rate_Estimator_2 0 0 0 0 0 0 0 Rate_Estimator_3 0 0 0 0 0 0 Rate_Estimator_4 0 0 0 0 0 Rate_Estimator_5 0 0 0 0 0 R371 (173h) R372 (174h) R373 (175h) R374 (176h) R376 (178h) R378 (17Ah) R379 (17Bh) R381 (17Dh) R398 (18Eh) FLL1_Control_3 FLL1_THETA [15:0] 0000h FLL1_Control_4 FLL1_LAMBDA [15:0] 0000h R401 (191h) R402 (192h) FLL2_Control_1 R403 (193h) R404 (194h) R405 (195h) R406 (196h) R408 (198h) R410 (19Ah) R411 (19Bh) R413 (19Dh) R430 (1AEh) FLL2_Control_3 FLL2_THETA [15:0] 0000h FLL2_Control_4 FLL2_LAMBDA [15:0] 0000h R512 (200h) R531 (213h) Output_async_clock Clocking_debug_5 ASYNC_CLK_FREQ_STS [2:0] FLL1_Control_1 FLL1_Control_2 0 0 0 0 0 0 SAMPLE_RATE_DETECT_A [4:0] 0000h 0 0 0 0 0 SAMPLE_RATE_DETECT_B [4:0] 0000h 0 0 0 0 0 0 SAMPLE_RATE_DETECT_C [4:0] 0000h 0 0 0 0 0 0 SAMPLE_RATE_DETECT_D [4:0] 0000h 0 0 0 0 0 0 0 0 0 FLL1_Control_6 FLL1_ REFDET 0 0 0 0 0 0 0 0 0 FLL1_REFCLK_DIV [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLL1_Digital_Test_1 0 0 1 1 0 0 1 1 0 1 1 FLL1_GPIO_Clock 0 0 0 0 0 0 0 0 FLL2_ CTRL_ UPD 0 0 0 0 0 FLL2_Control_5 0 0 0 0 0 0 FLL2_Control_6 FLL2_ REFDET 0 0 0 0 0 FLL2_Control_8 FLL2_Control_10 FLL2_PD_GAIN_FINE [3:0] FLL2_HP [1:0] 0 0 0 FLL1_ENA 0 0 FLL2_REFCLK_DIV [1:0] 0 0 0001h 0 0 0 0 0 0 0 1 1 0 0 0 0 1000h FLL1_ LOCKDET 0011h 0 FLL1_LOCKDET_THR [3:0] FLL1_CLK_VCO_ FAST_SRC[1:0] FLL2_ HOLD 0 FLL1_ GPCLK_ ENA FLL2_ENA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLL2_Digital_Test_1 0 0 1 1 0 0 1 1 0 1 1 0 FLL2_GPIO_Clock 0 0 0 0 0 0 Mic_Charge_Pump_1 0 0 0 0 0 0 0 LDO2_Control_1 0 0 0 0 0 0 0 0 0 0 FLL2_LOCKDET_THR [3:0] 1 1 0 LDO2_VSEL [5:0] 0 0 0 7000h 0 0 CP2_ DISCH CP2_ BYPASS 0 0 LDO2_ DISCH 0 8000h 21F0h 0 1000h FLL2_ LOCKDET 0011h FLL2_CLK_VCO_ FAST_SRC[1:0] FLL2_GPCLK_DIV [6:0] 0 0C04h 0001h FLL2_FD_GAIN_COARSE [3:0] 0 33E8h 0004h FLL2_FD_GAIN_FINE [3:0] 1 8000h 21F0h FLL1_FD_GAIN_COARSE [3:0] 0 7004h 0004h FLL2_FB_DIV [9:0] FLL2_Control_11 DS1162F1 0 FLL2_N [9:0] 0 0 FLL1_ HOLD FLL1_GPCLK_DIV [6:0] FLL2_PD_GAIN_COARSE [3:0] FLL2_GPDIV_SRC [1:0] 0 FLL1_FD_GAIN_FINE [3:0] 1 0 0 FLL1_FB_DIV [9:0] 0 0 0000h SYSCLK_SRC_STS [3:0] FLL1_N [9:0] FLL1_PD_GAIN_COARSE [3:0] FLL1_GPDIV_SRC [1:0] 0 LRCLK_SRC [2:0] SYSCLK_FREQ_STS [2:0] FLL1_Control_11 FLL2_Control_2 0000h 0 0 FLL2_REFCLK_SRC [3:0] RATE_ EST_ENA TRIG_ON_ STARTUP 0 FLL1_HP [1:0] 0000h 0 0 FLL1_Control_10 0 0 0 0 0 0 0 FLL1_PD_GAIN_FINE [3:0] 1 0 0 0 2 0 FLL1_Control_5 FLL1_Control_8 3 0 ASYNC_CLK_SRC_STS [3:0] FLL1_REFCLK_SRC [3:0] FLL1_ CTRL_ UPD MCLK3_ MCLK2_ MCLK1_ PD PD PD 4 33E8h FLL2_ GPCLK_ ENA CP2_ENA 0C04h 0 03E4h 0006h 283 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R536 (218h) R537 (219h) R540 (21Ch) R542 (21Eh) R665 (299h) R667 (29Bh) R668 (29Ch) R669 (29Dh) R674 (2A2h) Name Mic_Bias_Ctrl_1 15 14 13 12 11 10 9 4 3 2 1 0 MICB1_ EXT_CAP 0 0 0 0 0 0 MICB1_LVL [3:0] 0 MICB1_ RATE MICB1_ DISCH MICB1_ BYPASS MICB1_ ENA Mic_Bias_Ctrl_2 MICB2_ EXT_CAP 0 0 0 0 0 0 MICB2_LVL [3:0] 0 MICB2_ RATE MICB2_ DISCH MICB2_ BYPASS MICB2_ ENA 00E6h Mic_Bias_Ctrl_5 0 0 0 0 Mic_Bias_Ctrl_6 0 0 0 0 Headphone_Detect_0 HPD_ OVD_ENA Headphone_Detect_1 0 Headphone_Detect_2 HPD_ DONE Headphone_Detect_3 0 MICB1D_ MICB1D_ DISCH ENA 0 0 HPD_OUT_SEL [2:0] 0 0 7 MICB1C_ MICB1C_ DISCH ENA 0 0 0 0 HPD_IMPEDANCE_ RANGE [1:0] 0 0 0 0 0 0 ADC_ MODE MICD1_BIAS_STARTTIME [3:0] 0 0 0 0 MICB1B_ MICB1B_ DISCH ENA 0 0 MICB1A_ MICB1A_ DISCH ENA 2222h 0 0 MICB2B_ MICB2B_ DISCH ENA 0 0 MICB2A_ MICB2A_ DISCH ENA 0022h HPD_SENSE_SEL [3:0] 0 0 0 R691 (2B3h) R692 (2B4h) R693 (2B5h) R699 (2BBh) R710 (2C6h) Mic_Detect_2_Control_1 Micd_Clamp_control 0 0 0 0 0 0 R712 (2C8h) R723 (2D3h) R768 (300h) R769 (301h) R776 (308h) R777 (309h) R780 (30Ch) R784 (310h) R785 (311h) R786 (312h) R787 (313h) R788 (314h) R789 (315h) R790 (316h) GP_Switch_1 0 0 0 0 0 0 MICD_ CLAMP2_ OVD 0 Jack_detect_analogue 0 MICB1A_ AOD_ENA 0 0 0 0 Input_Enables 0 0 0 0 0 Input_Enables_Status 0 0 0 0 0 R791 (317h) R792 (318h) R793 (319h) R794 (31Ah) IN1R_Rate_Control 0 0 0 0 0 Mic_Detect_1_Control_3 0 0 0 0 0 Mic_Detect_1_Control_4 0 MICD1_RATE [3:0] Mic_Detect_1_Control_2 0 0 Mic_Detect_2_Control_0 MICD2_ 0 0 0 ADC_ MODE MICD2_BIAS_STARTTIME [3:0] 0 0 0 0 Mic_Detect_2_Control_3 0 0 0 0 0 Mic_Detect_2_Control_4 IN_RATE [4:0] 0 0 0 0 0 0000h MICD2_ADCVAL [6:0] 0 0000h 0210h MICD_CLAMP1_MODE [3:0] SW2_MODE [1:0] SW1_MODE [1:0] 0000h 0 IN4L_ IN4R_ IN3L_ IN3R_ IN2L_ IN2R_ IN1L_ IN1R_ ENA_STS ENA_STS ENA_STS ENA_STS ENA_STS ENA_STS ENA_STS ENA_STS 0000h IN_RATE_ MODE 0 0 0 0 0 0 IN_VU IN1L_ MUTE IN1_OSR [2:0] 0 0 0 0 0 0 IN_VD_RAMP [2:0] 0 0 0 0 0 0 0 0 0400h 0 IN_VI_RAMP [2:0] 0022h 0 IN_HPF_CUT [2:0] 0002h IN1L_PGA_VOL [6:0] 0 0080h 0180h IN1L_VOL [7:0] 0 0 0 0 0 0 0 0 0500h 0 0 0 0 0 0 0 0 0000h 0 0080h 0 0 0 0 0 0 IN1R_LP_ MODE 0 IN_VU IN1R_ MUTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h IN1R_RATE [4:0] 0 0 0 0 0 0 0 0 0 0 0 0000h 0 IN2_ MODE 0 0 0 0080h 0 IN_VU IN2L_ MUTE IN1R_SRC [1:0] 0 IN2L_SRC [1:0] 0 MICD2_ STS 0 IN1_ MODE IN2L_SIG_ DET_ENA 009Fh MICD2_ VALID 0 0 DMIC2L_Control MICD2_ ENA 0000h 0 0 1102h MICD2_ DBTIME IN4L_ENA IN4R_ENA IN3L_ENA IN3R_ENA IN2L_ENA IN2R_ENA IN1L_ENA IN1R_ENA IN1L_HPF ADC_Digital_Volume_2L 0 0 IN1L_Control 0 0 0 0 IN2L_HPF MICD2_BIAS_SRC [3:0] 0 0 IN2L_Control 0010h 0000h 0 0 MICD2_GND_SEL [2:0] JD3_ENA JD2_ENA JD1_ENA 0 IN1R_ SIG_DET_ ENA 0000h 0 0 0 DMIC1R_Control MICD1_ STS MICD2_SENSE_SEL [3:0] 0 0 0 009Fh 0000h 0 0 0 MICD1_ ENA MICD1_ADCVAL [6:0] 0 0 IN1L_RATE [4:0] MICD1_ DBTIME MICD1_ VALID 0 0 IN1L_Rate_Control 1102h 0 HPF_Control 0 0 0 0 0 0 0 0 0 MICD1_BIAS_SRC [3:0] 0 0 0 0010h 0 0 IN1L_LP_ MODE MICD1_GND_SEL [2:0] MICD_ CLAMP1_ OVD 0 0 0 0 MICD_CLAMP2_MODE [2:0] 0 IN1L_SRC [1:0] MICD1_SENSE_SEL [3:0] 0 0 IN1_DMIC_SUP [1:0] 0000h 0000h MICD2_LVL [8:0] 0 0 HPD_ POLL (M) MICD2_LVL_SEL [7:0] 0 ADC_Digital_Volume_1R HPD_RATE [1:0] 0000h 0 Input_Volume_Ramp IN1R_HPF HPD_CLK_DIV [1:0] 0 MICD2_ADCVAL_DIFF [7:0] Input_Rate IN1R_Control 0000h HPD_GND_SEL [2:0] MICD1_LVL_SEL [7:0] MICD2_RATE [3:0] 0 IN1L_SIG_ DET_ENA 0 0 MICD1_LVL [8:0] 0 Mic_Detect_2_Control_2 DMIC1L_Control 0 0 MICD1_ADCVAL_DIFF [7:0] Default 00E6h 0 HPD_DACVAL [9:0] Mic_Detect_1_Control_1 0 5 HPD_LVL [14:0] Mic_Detect_1_Control_0 MICD1_ ADC_Digital_Volume_1L 6 0 HPD_FRC_SEL [3:0] R675 (2A3h) R676 (2A4h) R677 (2A5h) R683 (2ABh) R690 (2B2h) 284 8 0 IN2_DMIC_SUP [1:0] 0 IN2L_LP_ MODE 0 0 IN2_OSR [2:0] IN1R_PGA_VOL [6:0] 0180h IN1R_VOL [7:0] IN2L_PGA_VOL [6:0] 0180h IN2L_VOL [7:0] 0 0 0 0 0 0 0 0 0500h DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R795 (31Bh) R796 (31Ch) R797 (31Dh) R798 (31Eh) Name IN2L_Rate_Control R799 (31Fh) R800 (320h) R801 (321h) R802 (322h) R803 (323h) R804 (324h) R805 (325h) R806 (326h) IN2R_Rate_Control R807 (327h) R808 (328h) R809 (329h) R810 (32Ah) R811 (32Bh) R812 (32Ch) R813 (32Dh) R814 (32Eh) IN3R_Rate_Control R815 (32Fh) R832 (340h) R840 (348h) R1024 (400h) R1025 (401h) R1030 (406h) R1032 (408h) R1033 (409h) R1040 (410h) R1041 (411h) R1042 (412h) R1043 (413h) R1044 (414h) R1045 (415h) R1047 (417h) R1048 (418h) R1049 (419h) R1050 (41Ah) IN4R_Rate_Control IN2R_Control ADC_Digital_Volume_2R DMIC2R_Control IN3L_Control ADC_Digital_Volume_3L DMIC3L_Control 15 14 IN2R_HPF 0 IN2R_ SIG_DET_ ENA 0 ADC_Digital_Volume_3R DMIC3R_Control IN4L_Control ADC_Digital_Volume_4L DMIC4L_Control ADC_Digital_Volume_4R DMIC4R_Control 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 Default 0000h 0 0080h 0 0 0 0 0 0 IN2R_LP_ MODE 0 IN_VU IN2R_ MUTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h IN2R_RATE [4:0] 0 0 0 0 0 0 0 0 0 0 0 0000h 0 0 0 0 0 0 0 0 0 0 0 0000h 0 IN_VU IN3L_ MUTE 0 0 IN3L_HPF 0 0 0 0 0 0 0 IN3L_SIG_ DET_ENA 0 0 0 0 IN3_DMIC_SUP [1:0] IN3L_RATE [4:0] IN3_OSR [2:0] IN2R_PGA_VOL [6:0] 0180h IN3L_VOL [7:0] 0 0 0 0 0 0 0 0 0500h 0 0 0 0 0 0 0 0 0 0 0 0000h 0 0 0 0 0 0 0 0 0000h 0 0 0 0 0 0 0 0 0 0 0 0 0 IN_VU IN3R_ MUTE IN3R_ SIG_DET_ ENA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h IN3R_RATE [4:0] 0 0 0 0 0 0 0 0 0 0 0 0000h 0 0 0 0 0 0 0 0 0 0 0 0000h 0 IN_VU IN4L_ MUTE IN4L_HPF 0 0 IN4_DMIC_SUP [1:0] 0 0 0 0 0 IN4L_SIG_ DET_ENA 0 0 0 0 IN4L_RATE [4:0] IN4_OSR [2:0] 0180h IN3R_VOL [7:0] 0180h IN4L_VOL [7:0] 0 0 0 0 0 0 0 0 0500h 0 0 0 0 0 0 0 0 0 0 0 0000h 0 0 0 0 0 0 0 0 0000h IN4R_HPF 0 0 0 0 0 0 0 0 0 0 0 0 0 IN_VU IN4R_ MUTE IN4R_ SIG_DET_ ENA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 0 0 0 0 0 0 0 0 0 0 0 0000h IN4R_RATE [4:0] Signal_Detect_Globals 0 0 0 0 0 0 0 Dig_Mic_Pad_Ctrl 0 0 0 0 0 0 0 Output_Enables_1 EP_SEL 0 0 0 0 0 Output_Status_1 0 0 0 0 0 0 Raw_Output_Status_1 0 0 0 0 0 0 0 0 Output_Rate_1 OUT_RATE [4:0] IN_SIG_DET_HOLD [3:0] 0001h DMICDAT4DMICDAT3DMICDAT2DMICDAT1 _PD _PD _PD _PD 0000h IN_SIG_DET_THR [4:0] 0 0180h IN4R_VOL [7:0] 0 0 0 0 OUT5L_ OUT5R_ ENA ENA 0 0 HP3L_ ENA HP3R_ ENA HP2L_ ENA HP2R_ ENA HP1L_ ENA HP1R_ ENA 0000h OUT5L_ OUT5R_ ENA_STS ENA_STS 0 0 0 0 0 0 0 0 0000h 0 0 0 0 0 0 CP_DAC_ OUT_EXT_CLK_DIV MODE [1:0] 0 OUT_CLK_SRC [2:0] 0040h OUT_VD_RAMP [2:0] 0 OUT_VI_RAMP [2:0] 0022h Output_Volume_Ramp 0 0 0 0 0 0 0 0 0 Output_Path_Config_1L 0 OUT1L_ HIFI 0 OUT1_ MONO 0 0 0 0 1 DAC_Digital_Volume_1L 0 0 0 0 0 0 Output_Path_Config_1 0 0 0 0 0 0 Noise_Gate_Select_1L 0 0 0 0 Output_Path_Config_1R 0 OUT1R_ HIFI 0 0 0 0 DAC_Digital_Volume_1R 0 0 0 0 0 0 Noise_Gate_Select_1R 0 0 0 0 Output_Path_Config_2L 0 OUT2L_ HIFI 0 OUT2_ MONO 0 0 DAC_Digital_Volume_2L 0 0 0 0 0 0 Output_Path_Config_2 0 0 0 0 0 0 DS1162F1 0180h IN2R_VOL [7:0] IN3R_HPF IN4L_Rate_Control IN4R_Control 12 IN2R_SRC [1:0] IN3L_Rate_Control IN3R_Control 13 IN2L_RATE [4:0] 0 OUT3L_ OUT3R_ OUT2L_ OUT2R_ OUT1L_ OUT1R_ ENA_STS ENA_STS ENA_STS ENA_STS ENA_STS ENA_STS 0 OUT_VU OUT1L_ MUTE 0 0 0 0 0 0 0 0 0 0 0 0000h HP1_GND_SEL [2:0] 0001h OUT1L_NGATE_SRC [11:0] 0 0 1 0 0 OUT_VU OUT1R_ MUTE 0 0 0 0 0 0 1 0 0 OUT_VU OUT2L_ MUTE 0 0 0002h 0 0 0 0 0 0 0 0 0 0080h 0180h OUT2L_VOL [7:0] 0 0080h 0180h OUT1R_VOL [7:0] OUT1R_NGATE_SRC [11:0] 0 0080h 0180h OUT1L_VOL [7:0] 0 0000h HP2_GND_SEL [2:0] 0002h 285 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R1051 (41Bh) R1052 (41Ch) R1053 (41Dh) R1055 (41Fh) R1056 (420h) R1057 (421h) R1058 (422h) R1059 (423h) R1060 (424h) R1061 (425h) R1063 (427h) R1072 (430h) R1073 (431h) R1075 (433h) R1076 (434h) R1077 (435h) R1079 (437h) R1102 (44Eh) R1104 (450h) Name Noise_Gate_Select_2L 15 14 13 12 0 0 0 0 Output_Path_Config_2R 0 OUT2R_ HIFI 0 0 0 0 DAC_Digital_Volume_2R 0 0 0 0 0 0 Noise_Gate_Select_2R 0 0 0 0 Output_Path_Config_3L 0 OUT3L_ HIFI 0 OUT3_ MONO 0 0 DAC_Digital_Volume_3L 0 0 0 0 0 0 Output_Path_Config_3 0 0 0 0 0 0 Noise_Gate_Select_3L 0 0 0 0 Output_Path_Config_3R 0 OUT3R_ HIFI 0 0 0 0 DAC_Digital_Volume_3R 0 0 0 0 0 0 Noise_Gate_Select_3R 0 0 0 0 Output_Path_Config_5L 0 OUT5L_ HIFI OUT5_ OSR 0 0 0 DAC_Digital_Volume_5L 0 0 0 0 0 0 Noise_Gate_Select_5L 0 0 0 0 Output_Path_Config_5R 0 OUT5R_ HIFI 0 0 0 0 DAC_Digital_Volume_5R 0 0 0 0 0 0 Noise_Gate_Select_5R 0 0 0 0 Filter_Control 0 0 0 0 0 0 0 0 0 0 DAC_AEC_Control_1 0 0 0 0 0 0 0 0 0 0 R1105 (451h) DAC_AEC_Control_2 0 0 0 0 0 0 0 0 0 0 R1112 (458h) R1168 (490h) Noise_Gate_Control 0 0 0 0 0 0 0 0 0 0 PDM_SPK1_CTRL_1 0 0 SPK1R_ MUTE SPK1L_ MUTE 0 0 0 R1169 (491h) R1280 (500h) PDM_SPK1_CTRL_2 0 0 0 0 0 0 0 SPK1_ MUTE_ ENDIAN 0 AIF1_BCLK_Ctrl 0 0 0 0 0 0 0 0 R1281 (501h) R1282 (502h) AIF1_Tx_Pin_Ctrl 0 0 0 0 0 0 0 0 AIF1_Rx_Pin_Ctrl 0 0 0 0 0 0 0 0 0 0 0 R1283 (503h) R1284 (504h) R1286 (506h) R1287 (507h) R1288 (508h) R1289 (509h) R1290 (50Ah) R1291 (50Bh) R1292 (50Ch) R1293 (50Dh) R1294 (50Eh) AIF1_Rate_Ctrl 0 0 0 0 AIF1_TRI 0 0 0 0 0 286 11 10 9 8 7 6 5 4 3 2 1 0 Default 0004h 0 0 0 0 0 0080h OUT2L_NGATE_SRC [11:0] 0 0 1 0 0 OUT_VU OUT2R_ MUTE 0180h OUT2R_VOL [7:0] 0008h OUT2R_NGATE_SRC [11:0] 0 0 1 0 0 0 OUT_VU OUT3L_ MUTE 0 0 0 0 0 0 0180h OUT3L_VOL [7:0] 0 0 0 0 0 0002h HP3_GND_SEL [2:0] 0010h OUT3L_NGATE_SRC [11:0] 0 0 1 0 0 0 OUT_VU OUT3R_ MUTE 0 0 0 0 0 0 0 0 0020h 0 OUT_VU OUT5L_ MUTE 0 0 0 0 0 0 0 0 0100h 0 OUT_VU OUT5R_ MUTE 0 0 0 0 0200h OUT5R_NGATE_SRC [11:0] AIF1_RATE [4:0] 0 0000h HIFI_FIR_TYPE [3:0] AEC1_LOOPBACK_SRC [3:0] AEC1_ AEC1_ ENA_STS LOOPBAC K_ENA AEC2_LOOPBACK_SRC [3:0] AEC2_ AEC2_ ENA_STS LOOPBAC K_ENA NGATE_HOLD [1:0] NGATE_THR [2:0] NGATE_ ENA 0 AIF1_ AIF1_ BCLK_INV BCLK_ FRC 0 0 0 0 AIF1_ BCLK_ MSTR AIF1TX_ DAT_TRI 0 0000h 0000h 0000h 0069h SPK1_MUTE_SEQ [7:0] 0 0000h 0180h OUT5R_VOL [7:0] 0 0000h 0180h OUT5L_VOL [7:0] OUT5L_NGATE_SRC [11:0] 0 0080h 0180h OUT3R_VOL [7:0] OUT3R_NGATE_SRC [11:0] 0 0080h 0 0 SPK1_ FMT 0000h 000Ch AIF1_BCLK_FREQ [4:0] 0 0 0 0 0 0000h 0 0 AIF1_ LRCLK_ INV 0 AIF1_ LRCLK_ FRC 0 AIF1_ LRCLK_ MSTR 0 0000h 0 AIF1_ LRCLK_ MODE 0 0 0 0 0000h AIF1_Format 0 0 0 AIF1_Rx_BCLK_Rate 0 0 0 AIF1_Frame_Ctrl_1 0 0 AIF1TX_WL [5:0] AIF1TX_SLOT_LEN [7:0] 1818h AIF1_Frame_Ctrl_2 0 0 AIF1RX_WL [5:0] AIF1RX_SLOT_LEN [7:0] 1818h AIF1_Frame_Ctrl_3 0 0 0 0 0 0 0 0 0 0 AIF1TX1_SLOT [5:0] 0000h AIF1_Frame_Ctrl_4 0 0 0 0 0 0 0 0 0 0 AIF1TX2_SLOT [5:0] 0001h AIF1_Frame_Ctrl_5 0 0 0 0 0 0 0 0 0 0 AIF1TX3_SLOT [5:0] 0002h AIF1_Frame_Ctrl_6 0 0 0 0 0 0 0 0 0 0 AIF1TX4_SLOT [5:0] 0003h AIF1_Frame_Ctrl_7 0 0 0 0 0 0 0 0 0 0 AIF1TX5_SLOT [5:0] 0004h AIF1_Frame_Ctrl_8 0 0 0 0 0 0 0 0 0 0 AIF1TX6_SLOT [5:0] 0005h 0 0 AIF1_FMT [2:0] 0000h 0040h AIF1_BCPF [12:0] DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R1295 (50Fh) R1296 (510h) R1297 (511h) R1298 (512h) R1299 (513h) R1300 (514h) R1301 (515h) R1302 (516h) R1303 (517h) R1304 (518h) R1305 (519h) R1306 (51Ah) R1344 (540h) Name AIF1_Frame_Ctrl_9 15 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 AIF1TX7_SLOT [5:0] Default 0006h AIF1_Frame_Ctrl_10 0 0 0 0 0 0 0 0 0 0 AIF1TX8_SLOT [5:0] 0007h AIF1_Frame_Ctrl_11 0 0 0 0 0 0 0 0 0 0 AIF1RX1_SLOT [5:0] 0000h AIF1_Frame_Ctrl_12 0 0 0 0 0 0 0 0 0 0 AIF1RX2_SLOT [5:0] 0001h AIF1_Frame_Ctrl_13 0 0 0 0 0 0 0 0 0 0 AIF1RX3_SLOT [5:0] 0002h AIF1_Frame_Ctrl_14 0 0 0 0 0 0 0 0 0 0 AIF1RX4_SLOT [5:0] 0003h AIF1_Frame_Ctrl_15 0 0 0 0 0 0 0 0 0 0 AIF1RX5_SLOT [5:0] 0004h AIF1_Frame_Ctrl_16 0 0 0 0 0 0 0 0 0 0 AIF1RX6_SLOT [5:0] 0005h AIF1_Frame_Ctrl_17 0 0 0 0 0 0 0 0 0 0 AIF1RX7_SLOT [5:0] 0006h AIF1_Frame_Ctrl_18 0 0 0 0 0 0 0 0 0 0 AIF1RX8_SLOT [5:0] 0007h AIF1_Tx_Enables 0 0 0 0 0 0 0 0 AIF1TX8_ AIF1TX7_ AIF1TX6_ AIF1TX5_ AIF1TX4_ AIF1TX3_ AIF1TX2_ AIF1TX1_ ENA ENA ENA ENA ENA ENA ENA ENA 0000h AIF1_Rx_Enables 0 0 0 0 0 0 0 0 AIF1RX8_ AIF1RX7_ AIF1RX6_ AIF1RX5_ AIF1RX4_ AIF1RX3_ AIF1RX2_ AIF1RX1_ ENA ENA ENA ENA ENA ENA ENA ENA 0000h AIF2_BCLK_Ctrl 0 0 0 0 0 0 0 0 000Ch R1345 (541h) R1346 (542h) AIF2_Tx_Pin_Ctrl 0 0 0 0 0 0 0 0 AIF2_ AIF2_ BCLK_INV BCLK_ FRC 0 0 AIF2_Rx_Pin_Ctrl 0 0 0 0 0 0 0 0 0 0 0 R1347 (543h) R1348 (544h) R1350 (546h) R1351 (547h) R1352 (548h) R1353 (549h) R1354 (54Ah) R1355 (54Bh) R1356 (54Ch) R1357 (54Dh) R1358 (54Eh) R1359 (54Fh) R1360 (550h) R1361 (551h) R1362 (552h) R1363 (553h) R1364 (554h) R1365 (555h) R1366 (556h) R1367 (557h) R1368 (558h) R1369 (559h) R1370 (55Ah) AIF2_Rate_Ctrl 0 0 0 0 AIF2_TRI 0 0 0 0 0 AIF2_RATE [4:0] 5 4 AIF2_ BCLK_ MSTR AIF2TX_ DAT_TRI 3 2 1 0 AIF2_BCLK_FREQ [4:0] 0 0 0 0 0 0000h 0 0 AIF2_ LRCLK_ INV 0 AIF2_ LRCLK_ FRC 0 AIF2_ LRCLK_ MSTR 0 0000h 0 AIF2_ LRCLK_ MODE 0 0 0 0 0000h AIF2_Format 0 0 0 AIF2_Rx_BCLK_Rate 0 0 0 AIF2_Frame_Ctrl_1 0 0 AIF2TX_WL [5:0] AIF2TX_SLOT_LEN [7:0] 1818h AIF2_Frame_Ctrl_2 0 0 AIF2RX_WL [5:0] AIF2RX_SLOT_LEN [7:0] 1818h AIF2_Frame_Ctrl_3 0 0 0 0 0 0 0 0 0 0 AIF2TX1_SLOT [5:0] 0000h AIF2_Frame_Ctrl_4 0 0 0 0 0 0 0 0 0 0 AIF2TX2_SLOT [5:0] 0001h AIF2_Frame_Ctrl_5 0 0 0 0 0 0 0 0 0 0 AIF2TX3_SLOT [5:0] 0002h AIF2_Frame_Ctrl_6 0 0 0 0 0 0 0 0 0 0 AIF2TX4_SLOT [5:0] 0003h AIF2_Frame_Ctrl_7 0 0 0 0 0 0 0 0 0 0 AIF2TX5_SLOT [5:0] 0004h AIF2_Frame_Ctrl_8 0 0 0 0 0 0 0 0 0 0 AIF2TX6_SLOT [5:0] 0005h AIF2_Frame_Ctrl_9 0 0 0 0 0 0 0 0 0 0 AIF2TX7_SLOT [5:0] 0006h AIF2_Frame_Ctrl_10 0 0 0 0 0 0 0 0 0 0 AIF2TX8_SLOT [5:0] 0007h AIF2_Frame_Ctrl_11 0 0 0 0 0 0 0 0 0 0 AIF2RX1_SLOT [5:0] 0000h AIF2_Frame_Ctrl_12 0 0 0 0 0 0 0 0 0 0 AIF2RX2_SLOT [5:0] 0001h AIF2_Frame_Ctrl_13 0 0 0 0 0 0 0 0 0 0 AIF2RX3_SLOT [5:0] 0002h AIF2_Frame_Ctrl_14 0 0 0 0 0 0 0 0 0 0 AIF2RX4_SLOT [5:0] 0003h AIF2_Frame_Ctrl_15 0 0 0 0 0 0 0 0 0 0 AIF2RX5_SLOT [5:0] 0004h AIF2_Frame_Ctrl_16 0 0 0 0 0 0 0 0 0 0 AIF2RX6_SLOT [5:0] 0005h AIF2_Frame_Ctrl_17 0 0 0 0 0 0 0 0 0 0 AIF2RX7_SLOT [5:0] 0006h AIF2_Frame_Ctrl_18 0 0 0 0 0 0 0 0 0 0 AIF2RX8_SLOT [5:0] 0007h AIF2_Tx_Enables 0 0 0 0 0 0 0 0 AIF2TX8_ AIF2TX7_ AIF2TX6_ AIF2TX5_ AIF2TX4_ AIF2TX3_ AIF2TX2_ AIF2TX1_ ENA ENA ENA ENA ENA ENA ENA ENA 0000h AIF2_Rx_Enables 0 0 0 0 0 0 0 0 AIF2RX8_ AIF2RX7_ AIF2RX6_ AIF2RX5_ AIF2RX4_ AIF2RX3_ AIF2RX2_ AIF2RX1_ ENA ENA ENA ENA ENA ENA ENA ENA 0000h DS1162F1 0 0 AIF2_FMT [2:0] 0000h 0040h AIF2_BCPF [12:0] 287 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register Name R1408 AIF3_BCLK_Ctrl (580h) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 AIF3_ AIF3_ BCLK_INV BCLK_ FRC 0 0 5 R1409 (581h) R1410 (582h) AIF3_Tx_Pin_Ctrl 0 0 0 0 0 0 0 0 AIF3_Rx_Pin_Ctrl 0 0 0 0 0 0 0 0 0 0 0 R1411 (583h) R1412 (584h) R1414 (586h) R1415 (587h) R1416 (588h) R1417 (589h) R1418 (58Ah) R1419 (58Bh) R1420 (58Ch) R1421 (58Dh) R1422 (58Eh) R1423 (58Fh) R1424 (590h) R1425 (591h) R1426 (592h) R1427 (593h) R1428 (594h) R1429 (595h) R1430 (596h) R1431 (597h) R1432 (598h) R1433 (599h) R1434 (59Ah) R1474 (5C2h) R1475 (5C3h) R1476 (5C4h) R1477 (5C5h) R1490 (5D2h) R1491 (5D3h) R1492 (5D4h) R1493 (5D5h) R1494 (5D6h) R1495 (5D7h) R1496 (5D8h) R1497 (5D9h) AIF3_Rate_Ctrl 0 0 0 0 AIF3_TRI 0 0 0 0 0 288 AIF3_RATE [4:0] 4 AIF3_ BCLK_ MSTR AIF3TX_ DAT_TRI 3 2 1 0 Default 000Ch AIF3_BCLK_FREQ [4:0] 0 0 0 0 0 0000h 0 0 AIF3_ LRCLK_ INV 0 AIF3_ LRCLK_ FRC 0 AIF3_ LRCLK_ MSTR 0 0000h 0 AIF3_ LRCLK_ MODE 0 0 0 0 0000h AIF3_Format 0 0 0 AIF3_Rx_BCLK_Rate 0 0 0 AIF3_Frame_Ctrl_1 0 0 AIF3TX_WL [5:0] AIF3TX_SLOT_LEN [7:0] 1818h AIF3_Frame_Ctrl_2 0 0 AIF3RX_WL [5:0] AIF3RX_SLOT_LEN [7:0] 1818h AIF3_Frame_Ctrl_3 0 0 0 0 0 0 0 0 0 0 AIF3TX1_SLOT [5:0] 0000h AIF3_Frame_Ctrl_4 0 0 0 0 0 0 0 0 0 0 AIF3TX2_SLOT [5:0] 0001h AIF3_Frame_Ctrl_5 0 0 0 0 0 0 0 0 0 0 AIF3TX3_SLOT [5:0] 0002h AIF3_Frame_Ctrl_6 0 0 0 0 0 0 0 0 0 0 AIF3TX4_SLOT [5:0] 0003h AIF3_Frame_Ctrl_7 0 0 0 0 0 0 0 0 0 0 AIF3TX5_SLOT [5:0] 0004h AIF3_Frame_Ctrl_8 0 0 0 0 0 0 0 0 0 0 AIF3TX6_SLOT [5:0] 0005h AIF3_Frame_Ctrl_9 0 0 0 0 0 0 0 0 0 0 AIF3TX7_SLOT [5:0] 0006h AIF3_Frame_Ctrl_10 0 0 0 0 0 0 0 0 0 0 AIF3TX8_SLOT [5:0] 0007h AIF3_Frame_Ctrl_11 0 0 0 0 0 0 0 0 0 0 AIF3RX1_SLOT [5:0] 0000h AIF3_Frame_Ctrl_12 0 0 0 0 0 0 0 0 0 0 AIF3RX2_SLOT [5:0] 0001h AIF3_Frame_Ctrl_13 0 0 0 0 0 0 0 0 0 0 AIF3RX3_SLOT [5:0] 0002h AIF3_Frame_Ctrl_14 0 0 0 0 0 0 0 0 0 0 AIF3RX4_SLOT [5:0] 0003h AIF3_Frame_Ctrl_15 0 0 0 0 0 0 0 0 0 0 AIF3RX5_SLOT [5:0] 0004h AIF3_Frame_Ctrl_16 0 0 0 0 0 0 0 0 0 0 AIF3RX6_SLOT [5:0] 0005h AIF3_Frame_Ctrl_17 0 0 0 0 0 0 0 0 0 0 AIF3RX7_SLOT [5:0] 0006h AIF3_Frame_Ctrl_18 0 0 0 0 0 0 0 0 0 0 AIF3RX8_SLOT [5:0] 0007h AIF3_Tx_Enables 0 0 0 0 0 0 0 0 AIF3TX8_ AIF3TX7_ AIF3TX6_ AIF3TX5_ AIF3TX4_ AIF3TX3_ AIF3TX2_ AIF3TX1_ ENA ENA ENA ENA ENA ENA ENA ENA 0000h AIF3_Rx_Enables 0 0 0 0 0 0 0 0 AIF3RX8_ AIF3RX7_ AIF3RX6_ AIF3RX5_ AIF3RX4_ AIF3RX3_ AIF3RX2_ AIF3RX1_ ENA ENA ENA ENA ENA ENA ENA ENA 0000h SPD1_TX_Control 0 0 SPD1_ VAL2 SPD1_ VAL1 0 0 0 SPD1_TX_Channel_ Status_1 SPD1_TX_Channel_ Status_2 SPD1_TX_Channel_ Status_3 SLIMbus_RX_Ports0 0 0 SPD1_FREQ [3:0] 0 0 0040h AIF3_BCPF [12:0] SPD1_CATCODE [7:0] 0 0000h AIF3_FMT [2:0] SPD1_CHSTMODE [1:0] SPD1_CHNUM2 [3:0] 0 SPD1_RATE [4:0] SPD1_ORGSAMP [3:0] SPD1_PREEMPH [2:0] SPD1_CHNUM1 [3:0] SPD1_TXWL [2:0] SPD1_ ENA 0000h SPD1_ SPD1_ SPD1_ NOCOPY NOAUDIO PRO 0000h SPD1_SRCNUM [3:0] 0001h 0 0 0 SPD1_ SPD1_CS31_30 [1:0] SPD1_CLKACU [1:0] MAXWL 0000h SLIMRX2_PORT_ADDR [7:0] SLIMRX1_PORT_ADDR [7:0] 0100h SLIMbus_RX_Ports1 SLIMRX4_PORT_ADDR [7:0] SLIMRX3_PORT_ADDR [7:0] 0302h SLIMbus_RX_Ports2 SLIMRX6_PORT_ADDR [7:0] SLIMRX5_PORT_ADDR [7:0] 0504h SLIMbus_RX_Ports3 SLIMRX8_PORT_ADDR [7:0] SLIMRX7_PORT_ADDR [7:0] 0706h SLIMbus_TX_Ports0 SLIMTX2_PORT_ADDR [7:0] SLIMTX1_PORT_ADDR [7:0] 0908h SLIMbus_TX_Ports1 SLIMTX4_PORT_ADDR [7:0] SLIMTX3_PORT_ADDR [7:0] 0B0Ah SLIMbus_TX_Ports2 SLIMTX6_PORT_ADDR [7:0] SLIMTX5_PORT_ADDR [7:0] 0D0Ch SLIMbus_TX_Ports3 SLIMTX8_PORT_ADDR [7:0] SLIMTX7_PORT_ADDR [7:0] 0F0Eh DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R1507 (5E3h) R1509 (5E5h) R1510 (5E6h) R1511 (5E7h) R1512 (5E8h) R1513 (5E9h) R1514 (5EAh) R1515 (5EBh) R1516 (5ECh) R1520 (5F0h) Name SLIMbus_Framer_Ref_ Gear SLIMbus_Rates_1 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 SLIMCLK_ SRC Slimbus_Pad_Ctrl 0 0 0 0 R1525 (5F5h) R1526 (5F6h) R1527 (5F7h) SLIMbus_RX_Channel_ Enable SLIMbus_TX_Channel_ Enable SLIMbus_RX_Port_ Status 0 0 0 0 0 0 R1528 (5F8h) SLIMbus_TX_Port_ Status R1600 (640h) R1601 (641h) R1602 (642h) R1603 (643h) R1604 (644h) R1605 (645h) R1606 (646h) R1607 (647h) R1608 (648h) R1609 (649h) R1610 (64Ah) R1611 (64Bh) R1612 (64Ch) R1613 (64Dh) R1614 (64Eh) R1615 (64Fh) R1664 (680h) R1665 (681h) R1666 (682h) R1667 (683h) R1668 (684h) R1669 (685h) R1670 (686h) R1671 (687h) PWM1MIX_Input_1_ Source PWM1MIX_Input_1_ Volume PWM1MIX_Input_2_ Source PWM1MIX_Input_2_ Volume PWM1MIX_Input_3_ Source PWM1MIX_Input_3_ Volume PWM1MIX_Input_4_ Source PWM1MIX_Input_4_ Volume PWM2MIX_Input_1_ Source PWM2MIX_Input_1_ Volume PWM2MIX_Input_2_ Source PWM2MIX_Input_2_ Volume PWM2MIX_Input_3_ Source PWM2MIX_Input_3_ Volume PWM2MIX_Input_4_ Source PWM2MIX_Input_4_ Volume OUT1LMIX_Input_1_ Source OUT1LMIX_Input_1_ Volume OUT1LMIX_Input_2_ Source OUT1LMIX_Input_2_ Volume OUT1LMIX_Input_3_ Source OUT1LMIX_Input_3_ Volume OUT1LMIX_Input_4_ Source OUT1LMIX_Input_4_ Volume SLIMRX2_RATE [4:0] 0 0 0 SLIMRX1_RATE [4:0] 0 SLIMbus_Rates_2 SLIMRX4_RATE [4:0] 0 0 0 SLIMRX3_RATE [4:0] SLIMbus_Rates_3 SLIMRX6_RATE [4:0] 0 0 0 SLIMbus_Rates_4 SLIMRX8_RATE [4:0] 0 0 SLIMbus_Rates_5 SLIMTX2_RATE [4:0] 0 SLIMbus_Rates_6 SLIMTX4_RATE [4:0] SLIMbus_Rates_7 SLIMbus_Rates_8 DS1162F1 3 2 1 0 Default 0000h 0 0 0000h 0 0 0 0000h SLIMRX5_RATE [4:0] 0 0 0 0000h 0 SLIMRX7_RATE [4:0] 0 0 0 0000h 0 0 SLIMTX1_RATE [4:0] 0 0 0 0000h 0 0 0 SLIMTX3_RATE [4:0] 0 0 0 0000h SLIMTX6_RATE [4:0] 0 0 0 SLIMTX5_RATE [4:0] 0 0 0 0000h SLIMTX8_RATE [4:0] 0 0 0 SLIMTX7_RATE [4:0] 0 0 0 0000h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM1MIX _STS 0 0 0 0 0 0 PWM1MIX _STS 0 0 SLIMCLK_REF_GEAR [3:0] SLIMDAT2 SLIMDAT1 SLIMCLK_ _DRV_ _DRV_ DRV_STR STR STR SLIMRX8_ SLIMRX7_ SLIMRX6_ SLIMRX5_ SLIMRX4_ SLIMRX3_ SLIMRX2_ SLIMRX1_ ENA ENA ENA ENA ENA ENA ENA ENA 0007h 0 SLIMTX8_ SLIMTX7_ SLIMTX6_ SLIMTX5_ SLIMTX4_ SLIMTX3_ SLIMTX2_ SLIMTX1_ ENA ENA ENA ENA ENA ENA ENA ENA 0000h 0 0 0000h 0 0 0 0 0 0 0 SLIMRX8_ SLIMRX7_ SLIMRX6_ SLIMRX5_ SLIMRX4_ SLIMRX3_ SLIMRX2_ SLIMRX1_ PORT_ PORT_ PORT_ PORT_ PORT_ PORT_ PORT_ PORT_ STS STS STS STS STS STS STS STS SLIMTX8_ SLIMTX7_ SLIMTX6_ SLIMTX5_ SLIMTX4_ SLIMTX3_ SLIMTX2_ SLIMTX1_ PORT_ PORT_ PORT_ PORT_ PORT_ PORT_ PORT_ PORT_ STS STS STS STS STS STS STS STS PWM1MIX_SRC1 [7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM1MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM1MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM2MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM2MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM2MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM2MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT1LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT1LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT1LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT1LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM1MIX_VOL1 [6:0] 0 0 0 0 0 0 0 0 0 0 0 0080h 0080h 0080h 0000h OUT1LMIX_SRC4 [7:0] OUT1LMIX_VOL4 [6:0] 0080h 0000h OUT1LMIX_SRC3 [7:0] OUT1LMIX_VOL3 [6:0] 0080h 0000h OUT1LMIX_SRC2 [7:0] OUT1LMIX_VOL2 [6:0] 0080h 0000h OUT1LMIX_SRC1 [7:0] OUT1LMIX_VOL1 [6:0] 0080h 0000h PWM2MIX_SRC4 [7:0] PWM2MIX_VOL4 [6:0] 0080h 0000h PWM2MIX_SRC3 [7:0] PWM2MIX_VOL3 [6:0] 0080h 0000h PWM2MIX_SRC2 [7:0] PWM2MIX_VOL2 [6:0] 0080h 0000h PWM2MIX_SRC1 [7:0] PWM2MIX_VOL1 [6:0] 0080h 0000h PWM1MIX_SRC4 [7:0] PWM1MIX_VOL4 [6:0] 0000h 0000h PWM1MIX_SRC3 [7:0] PWM1MIX_VOL3 [6:0] 0000h 0000h PWM1MIX_SRC2 [7:0] PWM1MIX_VOL2 [6:0] 0000h 0 0080h 289 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R1672 (688h) R1673 (689h) R1674 (68Ah) R1675 (68Bh) R1676 (68Ch) R1677 (68Dh) R1678 (68Eh) R1679 (68Fh) R1680 (690h) R1681 (691h) R1682 (692h) R1683 (693h) R1684 (694h) R1685 (695h) R1686 (696h) R1687 (697h) R1688 (698h) R1689 (699h) R1690 (69Ah) R1691 (69Bh) R1692 (69Ch) R1693 (69Dh) R1694 (69Eh) R1695 (69Fh) R1696 (6A0h) R1697 (6A1h) R1698 (6A2h) R1699 (6A3h) R1700 (6A4h) R1701 (6A5h) R1702 (6A6h) R1703 (6A7h) R1704 (6A8h) R1705 (6A9h) R1706 (6AAh) R1707 (6ABh) R1708 (6ACh) R1709 (6ADh) 290 Name OUT1RMIX_Input_1_ Source OUT1RMIX_Input_1_ Volume OUT1RMIX_Input_2_ Source OUT1RMIX_Input_2_ Volume OUT1RMIX_Input_3_ Source OUT1RMIX_Input_3_ Volume OUT1RMIX_Input_4_ Source OUT1RMIX_Input_4_ Volume OUT2LMIX_Input_1_ Source OUT2LMIX_Input_1_ Volume OUT2LMIX_Input_2_ Source OUT2LMIX_Input_2_ Volume OUT2LMIX_Input_3_ Source OUT2LMIX_Input_3_ Volume OUT2LMIX_Input_4_ Source OUT2LMIX_Input_4_ Volume OUT2RMIX_Input_1_ Source OUT2RMIX_Input_1_ Volume OUT2RMIX_Input_2_ Source OUT2RMIX_Input_2_ Volume OUT2RMIX_Input_3_ Source OUT2RMIX_Input_3_ Volume OUT2RMIX_Input_4_ Source OUT2RMIX_Input_4_ Volume OUT3LMIX_Input_1_ Source OUT3LMIX_Input_1_ Volume OUT3LMIX_Input_2_ Source OUT3LMIX_Input_2_ Volume OUT3LMIX_Input_3_ Source OUT3LMIX_Input_3_ Volume OUT3LMIX_Input_4_ Source OUT3LMIX_Input_4_ Volume OUT3RMIX_Input_1_ Source OUT3RMIX_Input_1_ Volume OUT3RMIX_Input_2_ Source OUT3RMIX_Input_2_ Volume OUT3RMIX_Input_3_ Source OUT3RMIX_Input_3_ Volume 15 14 13 12 11 10 9 8 OUT1RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT1RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT1RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT1RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT2LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT2LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT2LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT2LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT2RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT2RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT2RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT2RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT3LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT3LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT3LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT3LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT3RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT3RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT3RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Default 0000h 0 0080h OUT1RMIX_SRC1 [7:0] OUT1RMIX_VOL1 [6:0] 0000h OUT1RMIX_SRC2 [7:0] OUT1RMIX_VOL2 [6:0] 0 0000h OUT1RMIX_SRC3 [7:0] OUT1RMIX_VOL3 [6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0080h 0000h OUT3RMIX_SRC3 [7:0] OUT3RMIX_VOL3 [6:0] 0080h 0000h OUT3RMIX_SRC2 [7:0] OUT3RMIX_VOL2 [6:0] 0080h 0000h OUT3RMIX_SRC1 [7:0] OUT3RMIX_VOL1 [6:0] 0080h 0000h OUT3LMIX_SRC4 [7:0] OUT3LMIX_VOL4 [6:0] 0080h 0000h OUT3LMIX_SRC3 [7:0] OUT3LMIX_VOL3 [6:0] 0080h 0000h OUT3LMIX_SRC2 [7:0] OUT3LMIX_VOL2 [6:0] 0080h 0000h OUT3LMIX_SRC1 [7:0] OUT3LMIX_VOL1 [6:0] 0080h 0000h OUT2RMIX_SRC4 [7:0] OUT2RMIX_VOL4 [6:0] 0080h 0000h OUT2RMIX_SRC3 [7:0] OUT2RMIX_VOL3 [6:0] 0080h 0000h OUT2RMIX_SRC2 [7:0] OUT2RMIX_VOL2 [6:0] 0080h 0000h OUT2RMIX_SRC1 [7:0] OUT2RMIX_VOL1 [6:0] 0080h 0000h OUT2LMIX_SRC4 [7:0] OUT2LMIX_VOL4 [6:0] 0080h 0000h OUT2LMIX_SRC3 [7:0] OUT2LMIX_VOL3 [6:0] 0080h 0000h OUT2LMIX_SRC2 [7:0] OUT2LMIX_VOL2 [6:0] 0080h 0000h OUT2LMIX_SRC1 [7:0] OUT2LMIX_VOL1 [6:0] 0080h 0000h OUT1RMIX_SRC4 [7:0] OUT1RMIX_VOL4 [6:0] 0080h 0 0080h DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R1710 (6AEh) R1711 (6AFh) R1728 (6C0h) R1729 (6C1h) R1730 (6C2h) R1731 (6C3h) R1732 (6C4h) R1733 (6C5h) R1734 (6C6h) R1735 (6C7h) R1736 (6C8h) R1737 (6C9h) R1738 (6CAh) R1739 (6CBh) R1740 (6CCh) R1741 (6CDh) R1742 (6CEh) R1743 (6CFh) R1792 (700h) R1793 (701h) R1794 (702h) R1795 (703h) R1796 (704h) R1797 (705h) R1798 (706h) R1799 (707h) R1800 (708h) R1801 (709h) R1802 (70Ah) R1803 (70Bh) R1804 (70Ch) R1805 (70Dh) R1806 (70Eh) R1807 (70Fh) R1808 (710h) R1809 (711h) R1810 (712h) R1811 (713h) Name OUT3RMIX_Input_4_ Source OUT3RMIX_Input_4_ Volume OUT5LMIX_Input_1_ Source OUT5LMIX_Input_1_ Volume OUT5LMIX_Input_2_ Source OUT5LMIX_Input_2_ Volume OUT5LMIX_Input_3_ Source OUT5LMIX_Input_3_ Volume OUT5LMIX_Input_4_ Source OUT5LMIX_Input_4_ Volume OUT5RMIX_Input_1_ Source OUT5RMIX_Input_1_ Volume OUT5RMIX_Input_2_ Source OUT5RMIX_Input_2_ Volume OUT5RMIX_Input_3_ Source OUT5RMIX_Input_3_ Volume OUT5RMIX_Input_4_ Source OUT5RMIX_Input_4_ Volume AIF1TX1MIX_Input_1_ Source AIF1TX1MIX_Input_1_ Volume AIF1TX1MIX_Input_2_ Source AIF1TX1MIX_Input_2_ Volume AIF1TX1MIX_Input_3_ Source AIF1TX1MIX_Input_3_ Volume AIF1TX1MIX_Input_4_ Source AIF1TX1MIX_Input_4_ Volume AIF1TX2MIX_Input_1_ Source AIF1TX2MIX_Input_1_ Volume AIF1TX2MIX_Input_2_ Source AIF1TX2MIX_Input_2_ Volume AIF1TX2MIX_Input_3_ Source AIF1TX2MIX_Input_3_ Volume AIF1TX2MIX_Input_4_ Source AIF1TX2MIX_Input_4_ Volume AIF1TX3MIX_Input_1_ Source AIF1TX3MIX_Input_1_ Volume AIF1TX3MIX_Input_2_ Source AIF1TX3MIX_Input_2_ Volume DS1162F1 15 14 13 12 11 10 9 8 OUT3RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT5LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT5LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT5LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT5LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT5RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT5RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT5RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT5RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX1MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX1MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX1MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX1MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX2MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX2MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX2MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX2MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX3MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX3MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Default 0000h 0 0080h OUT3RMIX_SRC4 [7:0] OUT3RMIX_VOL4 [6:0] 0000h OUT5LMIX_SRC1 [7:0] OUT5LMIX_VOL1 [6:0] 0 0000h OUT5LMIX_SRC2 [7:0] OUT5LMIX_VOL2 [6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0080h 0000h AIF1TX3MIX_SRC2 [7:0] AIF1TX3MIX_VOL2 [6:0] 0080h 0000h AIF1TX3MIX_SRC1 [7:0] AIF1TX3MIX_VOL1 [6:0] 0080h 0000h AIF1TX2MIX_SRC4 [7:0] AIF1TX2MIX_VOL4 [6:0] 0080h 0000h AIF1TX2MIX_SRC3 [7:0] AIF1TX2MIX_VOL3 [6:0] 0080h 0000h AIF1TX2MIX_SRC2 [7:0] AIF1TX2MIX_VOL2 [6:0] 0080h 0000h AIF1TX2MIX_SRC1 [7:0] AIF1TX2MIX_VOL1 [6:0] 0080h 0000h AIF1TX1MIX_SRC4 [7:0] AIF1TX1MIX_VOL4 [6:0] 0080h 0000h AIF1TX1MIX_SRC3 [7:0] AIF1TX1MIX_VOL3 [6:0] 0080h 0000h AIF1TX1MIX_SRC2 [7:0] AIF1TX1MIX_VOL2 [6:0] 0080h 0000h AIF1TX1MIX_SRC1 [7:0] AIF1TX1MIX_VOL1 [6:0] 0080h 0000h OUT5RMIX_SRC4 [7:0] OUT5RMIX_VOL4 [6:0] 0080h 0000h OUT5RMIX_SRC3 [7:0] OUT5RMIX_VOL3 [6:0] 0080h 0000h OUT5RMIX_SRC2 [7:0] OUT5RMIX_VOL2 [6:0] 0080h 0000h OUT5RMIX_SRC1 [7:0] OUT5RMIX_VOL1 [6:0] 0080h 0000h OUT5LMIX_SRC4 [7:0] OUT5LMIX_VOL4 [6:0] 0080h 0000h OUT5LMIX_SRC3 [7:0] OUT5LMIX_VOL3 [6:0] 0080h 0 0080h 291 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R1812 (714h) R1813 (715h) R1814 (716h) R1815 (717h) R1816 (718h) R1817 (719h) R1818 (71Ah) R1819 (71Bh) R1820 (71Ch) R1821 (71Dh) R1822 (71Eh) R1823 (71Fh) R1824 (720h) R1825 (721h) R1826 (722h) R1827 (723h) R1828 (724h) R1829 (725h) R1830 (726h) R1831 (727h) R1832 (728h) R1833 (729h) R1834 (72Ah) R1835 (72Bh) R1836 (72Ch) R1837 (72Dh) R1838 (72Eh) R1839 (72Fh) R1840 (730h) R1841 (731h) R1842 (732h) R1843 (733h) R1844 (734h) R1845 (735h) R1846 (736h) R1847 (737h) R1848 (738h) R1849 (739h) 292 Name AIF1TX3MIX_Input_3_ Source AIF1TX3MIX_Input_3_ Volume AIF1TX3MIX_Input_4_ Source AIF1TX3MIX_Input_4_ Volume AIF1TX4MIX_Input_1_ Source AIF1TX4MIX_Input_1_ Volume AIF1TX4MIX_Input_2_ Source AIF1TX4MIX_Input_2_ Volume AIF1TX4MIX_Input_3_ Source AIF1TX4MIX_Input_3_ Volume AIF1TX4MIX_Input_4_ Source AIF1TX4MIX_Input_4_ Volume AIF1TX5MIX_Input_1_ Source AIF1TX5MIX_Input_1_ Volume AIF1TX5MIX_Input_2_ Source AIF1TX5MIX_Input_2_ Volume AIF1TX5MIX_Input_3_ Source AIF1TX5MIX_Input_3_ Volume AIF1TX5MIX_Input_4_ Source AIF1TX5MIX_Input_4_ Volume AIF1TX6MIX_Input_1_ Source AIF1TX6MIX_Input_1_ Volume AIF1TX6MIX_Input_2_ Source AIF1TX6MIX_Input_2_ Volume AIF1TX6MIX_Input_3_ Source AIF1TX6MIX_Input_3_ Volume AIF1TX6MIX_Input_4_ Source AIF1TX6MIX_Input_4_ Volume AIF1TX7MIX_Input_1_ Source AIF1TX7MIX_Input_1_ Volume AIF1TX7MIX_Input_2_ Source AIF1TX7MIX_Input_2_ Volume AIF1TX7MIX_Input_3_ Source AIF1TX7MIX_Input_3_ Volume AIF1TX7MIX_Input_4_ Source AIF1TX7MIX_Input_4_ Volume AIF1TX8MIX_Input_1_ Source AIF1TX8MIX_Input_1_ Volume 15 14 13 12 11 10 9 8 AIF1TX3MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX3MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX4MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX4MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX4MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX4MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX5MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX5MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX5MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX5MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX6MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX6MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX6MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX6MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX7MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX7MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX7MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX7MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX8MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Default 0000h 0 0080h AIF1TX3MIX_SRC3 [7:0] AIF1TX3MIX_VOL3 [6:0] 0000h AIF1TX3MIX_SRC4 [7:0] AIF1TX3MIX_VOL4 [6:0] 0 0000h AIF1TX4MIX_SRC1 [7:0] AIF1TX4MIX_VOL1 [6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0080h 0000h AIF1TX8MIX_SRC1 [7:0] AIF1TX8MIX_VOL1 [6:0] 0080h 0000h AIF1TX7MIX_SRC4 [7:0] AIF1TX7MIX_VOL4 [6:0] 0080h 0000h AIF1TX7MIX_SRC3 [7:0] AIF1TX7MIX_VOL3 [6:0] 0080h 0000h AIF1TX7MIX_SRC2 [7:0] AIF1TX7MIX_VOL2 [6:0] 0080h 0000h AIF1TX7MIX_SRC1 [7:0] AIF1TX7MIX_VOL1 [6:0] 0080h 0000h AIF1TX6MIX_SRC4 [7:0] AIF1TX6MIX_VOL4 [6:0] 0080h 0000h AIF1TX6MIX_SRC3 [7:0] AIF1TX6MIX_VOL3 [6:0] 0080h 0000h AIF1TX6MIX_SRC2 [7:0] AIF1TX6MIX_VOL2 [6:0] 0080h 0000h AIF1TX6MIX_SRC1 [7:0] AIF1TX6MIX_VOL1 [6:0] 0080h 0000h AIF1TX5MIX_SRC4 [7:0] AIF1TX5MIX_VOL4 [6:0] 0080h 0000h AIF1TX5MIX_SRC3 [7:0] AIF1TX5MIX_VOL3 [6:0] 0080h 0000h AIF1TX5MIX_SRC2 [7:0] AIF1TX5MIX_VOL2 [6:0] 0080h 0000h AIF1TX5MIX_SRC1 [7:0] AIF1TX5MIX_VOL1 [6:0] 0080h 0000h AIF1TX4MIX_SRC4 [7:0] AIF1TX4MIX_VOL4 [6:0] 0080h 0000h AIF1TX4MIX_SRC3 [7:0] AIF1TX4MIX_VOL3 [6:0] 0080h 0000h AIF1TX4MIX_SRC2 [7:0] AIF1TX4MIX_VOL2 [6:0] 0080h 0 0080h DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R1850 (73Ah) R1851 (73Bh) R1852 (73Ch) R1853 (73Dh) R1854 (73Eh) R1855 (73Fh) R1856 (740h) R1857 (741h) R1858 (742h) R1859 (743h) R1860 (744h) R1861 (745h) R1862 (746h) R1863 (747h) R1864 (748h) R1865 (749h) R1866 (74Ah) R1867 (74Bh) R1868 (74Ch) R1869 (74Dh) R1870 (74Eh) R1871 (74Fh) R1872 (750h) R1873 (751h) R1874 (752h) R1875 (753h) R1876 (754h) R1877 (755h) R1878 (756h) R1879 (757h) R1880 (758h) R1881 (759h) R1882 (75Ah) R1883 (75Bh) R1884 (75Ch) R1885 (75Dh) R1886 (75Eh) R1887 (75Fh) Name AIF1TX8MIX_Input_2_ Source AIF1TX8MIX_Input_2_ Volume AIF1TX8MIX_Input_3_ Source AIF1TX8MIX_Input_3_ Volume AIF1TX8MIX_Input_4_ Source AIF1TX8MIX_Input_4_ Volume AIF2TX1MIX_Input_1_ Source AIF2TX1MIX_Input_1_ Volume AIF2TX1MIX_Input_2_ Source AIF2TX1MIX_Input_2_ Volume AIF2TX1MIX_Input_3_ Source AIF2TX1MIX_Input_3_ Volume AIF2TX1MIX_Input_4_ Source AIF2TX1MIX_Input_4_ Volume AIF2TX2MIX_Input_1_ Source AIF2TX2MIX_Input_1_ Volume AIF2TX2MIX_Input_2_ Source AIF2TX2MIX_Input_2_ Volume AIF2TX2MIX_Input_3_ Source AIF2TX2MIX_Input_3_ Volume AIF2TX2MIX_Input_4_ Source AIF2TX2MIX_Input_4_ Volume AIF2TX3MIX_Input_1_ Source AIF2TX3MIX_Input_1_ Volume AIF2TX3MIX_Input_2_ Source AIF2TX3MIX_Input_2_ Volume AIF2TX3MIX_Input_3_ Source AIF2TX3MIX_Input_3_ Volume AIF2TX3MIX_Input_4_ Source AIF2TX3MIX_Input_4_ Volume AIF2TX4MIX_Input_1_ Source AIF2TX4MIX_Input_1_ Volume AIF2TX4MIX_Input_2_ Source AIF2TX4MIX_Input_2_ Volume AIF2TX4MIX_Input_3_ Source AIF2TX4MIX_Input_3_ Volume AIF2TX4MIX_Input_4_ Source AIF2TX4MIX_Input_4_ Volume DS1162F1 15 14 13 12 11 10 9 8 AIF1TX8MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX8MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1TX8MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX1MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX1MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX1MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX1MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX2MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX2MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX2MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX2MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX3MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX3MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX3MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX3MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX4MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX4MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX4MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX4MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Default 0000h 0 0080h AIF1TX8MIX_SRC2 [7:0] AIF1TX8MIX_VOL2 [6:0] 0000h AIF1TX8MIX_SRC3 [7:0] AIF1TX8MIX_VOL3 [6:0] 0 0000h AIF1TX8MIX_SRC4 [7:0] AIF1TX8MIX_VOL4 [6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0080h 0000h AIF2TX4MIX_SRC4 [7:0] AIF2TX4MIX_VOL4 [6:0] 0080h 0000h AIF2TX4MIX_SRC3 [7:0] AIF2TX4MIX_VOL3 [6:0] 0080h 0000h AIF2TX4MIX_SRC2 [7:0] AIF2TX4MIX_VOL2 [6:0] 0080h 0000h AIF2TX4MIX_SRC1 [7:0] AIF2TX4MIX_VOL1 [6:0] 0080h 0000h AIF2TX3MIX_SRC4 [7:0] AIF2TX3MIX_VOL4 [6:0] 0080h 0000h AIF2TX3MIX_SRC3 [7:0] AIF2TX3MIX_VOL3 [6:0] 0080h 0000h AIF2TX3MIX_SRC2 [7:0] AIF2TX3MIX_VOL2 [6:0] 0080h 0000h AIF2TX3MIX_SRC1 [7:0] AIF2TX3MIX_VOL1 [6:0] 0080h 0000h AIF2TX2MIX_SRC4 [7:0] AIF2TX2MIX_VOL4 [6:0] 0080h 0000h AIF2TX2MIX_SRC3 [7:0] AIF2TX2MIX_VOL3 [6:0] 0080h 0000h AIF2TX2MIX_SRC2 [7:0] AIF2TX2MIX_VOL2 [6:0] 0080h 0000h AIF2TX2MIX_SRC1 [7:0] AIF2TX2MIX_VOL1 [6:0] 0080h 0000h AIF2TX1MIX_SRC4 [7:0] AIF2TX1MIX_VOL4 [6:0] 0080h 0000h AIF2TX1MIX_SRC3 [7:0] AIF2TX1MIX_VOL3 [6:0] 0080h 0000h AIF2TX1MIX_SRC2 [7:0] AIF2TX1MIX_VOL2 [6:0] 0080h 0000h AIF2TX1MIX_SRC1 [7:0] AIF2TX1MIX_VOL1 [6:0] 0080h 0 0080h 293 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R1888 (760h) R1889 (761h) R1890 (762h) R1891 (763h) R1892 (764h) R1893 (765h) R1894 (766h) R1895 (767h) R1896 (768h) R1897 (769h) R1898 (76Ah) R1899 (76Bh) R1900 (76Ch) R1901 (76Dh) R1902 (76Eh) R1903 (76Fh) R1904 (770h) R1905 (771h) R1906 (772h) R1907 (773h) R1908 (774h) R1909 (775h) R1910 (776h) R1911 (777h) R1912 (778h) R1913 (779h) R1914 (77Ah) R1915 (77Bh) R1916 (77Ch) R1917 (77Dh) R1918 (77Eh) R1919 (77Fh) R1920 (780h) R1921 (781h) R1922 (782h) R1923 (783h) R1924 (784h) R1925 (785h) 294 Name AIF2TX5MIX_Input_1_ Source AIF2TX5MIX_Input_1_ Volume AIF2TX5MIX_Input_2_ Source AIF2TX5MIX_Input_2_ Volume AIF2TX5MIX_Input_3_ Source AIF2TX5MIX_Input_3_ Volume AIF2TX5MIX_Input_4_ Source AIF2TX5MIX_Input_4_ Volume AIF2TX6MIX_Input_1_ Source AIF2TX6MIX_Input_1_ Volume AIF2TX6MIX_Input_2_ Source AIF2TX6MIX_Input_2_ Volume AIF2TX6MIX_Input_3_ Source AIF2TX6MIX_Input_3_ Volume AIF2TX6MIX_Input_4_ Source AIF2TX6MIX_Input_4_ Volume AIF2TX7MIX_Input_1_ Source AIF2TX7MIX_Input_1_ Volume AIF2TX7MIX_Input_2_ Source AIF2TX7MIX_Input_2_ Volume AIF2TX7MIX_Input_3_ Source AIF2TX7MIX_Input_3_ Volume AIF2TX7MIX_Input_4_ Source AIF2TX7MIX_Input_4_ Volume AIF2TX8MIX_Input_1_ Source AIF2TX8MIX_Input_1_ Volume AIF2TX8MIX_Input_2_ Source AIF2TX8MIX_Input_2_ Volume AIF2TX8MIX_Input_3_ Source AIF2TX8MIX_Input_3_ Volume AIF2TX8MIX_Input_4_ Source AIF2TX8MIX_Input_4_ Volume AIF3TX1MIX_Input_1_ Source AIF3TX1MIX_Input_1_ Volume AIF3TX1MIX_Input_2_ Source AIF3TX1MIX_Input_2_ Volume AIF3TX1MIX_Input_3_ Source AIF3TX1MIX_Input_3_ Volume 15 14 13 12 11 10 9 8 AIF2TX5MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX5MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX5MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX5MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX6MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX6MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX6MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX6MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX7MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX7MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX7MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX7MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX8MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX8MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX8MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2TX8MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX1MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX1MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX1MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Default 0000h 0 0080h AIF2TX5MIX_SRC1 [7:0] AIF2TX5MIX_VOL1 [6:0] 0000h AIF2TX5MIX_SRC2 [7:0] AIF2TX5MIX_VOL2 [6:0] 0 0000h AIF2TX5MIX_SRC3 [7:0] AIF2TX5MIX_VOL3 [6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0080h 0000h AIF3TX1MIX_SRC3 [7:0] AIF3TX1MIX_VOL3 [6:0] 0080h 0000h AIF3TX1MIX_SRC2 [7:0] AIF3TX1MIX_VOL2 [6:0] 0080h 0000h AIF3TX1MIX_SRC1 [7:0] AIF3TX1MIX_VOL1 [6:0] 0080h 0000h AIF2TX8MIX_SRC4 [7:0] AIF2TX8MIX_VOL4 [6:0] 0080h 0000h AIF2TX8MIX_SRC3 [7:0] AIF2TX8MIX_VOL3 [6:0] 0080h 0000h AIF2TX8MIX_SRC2 [7:0] AIF2TX8MIX_VOL2 [6:0] 0080h 0000h AIF2TX8MIX_SRC1 [7:0] AIF2TX8MIX_VOL1 [6:0] 0080h 0000h AIF2TX7MIX_SRC4 [7:0] AIF2TX7MIX_VOL4 [6:0] 0080h 0000h AIF2TX7MIX_SRC3 [7:0] AIF2TX7MIX_VOL3 [6:0] 0080h 0000h AIF2TX7MIX_SRC2 [7:0] AIF2TX7MIX_VOL2 [6:0] 0080h 0000h AIF2TX7MIX_SRC1 [7:0] AIF2TX7MIX_VOL1 [6:0] 0080h 0000h AIF2TX6MIX_SRC4 [7:0] AIF2TX6MIX_VOL4 [6:0] 0080h 0000h AIF2TX6MIX_SRC3 [7:0] AIF2TX6MIX_VOL3 [6:0] 0080h 0000h AIF2TX6MIX_SRC2 [7:0] AIF2TX6MIX_VOL2 [6:0] 0080h 0000h AIF2TX6MIX_SRC1 [7:0] AIF2TX6MIX_VOL1 [6:0] 0080h 0000h AIF2TX5MIX_SRC4 [7:0] AIF2TX5MIX_VOL4 [6:0] 0080h 0 0080h DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R1926 (786h) R1927 (787h) R1928 (788h) R1929 (789h) R1930 (78Ah) R1931 (78Bh) R1932 (78Ch) R1933 (78Dh) R1934 (78Eh) R1935 (78Fh) R1936 (790h) R1937 (791h) R1938 (792h) R1939 (793h) R1940 (794h) R1941 (795h) R1942 (796h) R1943 (797h) R1944 (798h) R1945 (799h) R1946 (79Ah) R1947 (79Bh) R1948 (79Ch) R1949 (79Dh) R1950 (79Eh) R1951 (79Fh) R1952 (7A0h) R1953 (7A1h) R1954 (7A2h) R1955 (7A3h) R1956 (7A4h) R1957 (7A5h) R1958 (7A6h) R1959 (7A7h) R1960 (7A8h) R1961 (7A9h) R1962 (7AAh) R1963 (7ABh) Name AIF3TX1MIX_Input_4_ Source AIF3TX1MIX_Input_4_ Volume AIF3TX2MIX_Input_1_ Source AIF3TX2MIX_Input_1_ Volume AIF3TX2MIX_Input_2_ Source AIF3TX2MIX_Input_2_ Volume AIF3TX2MIX_Input_3_ Source AIF3TX2MIX_Input_3_ Volume AIF3TX2MIX_Input_4_ Source AIF3TX2MIX_Input_4_ Volume AIF3TX3MIX_Input_1_ Source AIF3TX3MIX_Input_1_ Volume AIF3TX3MIX_Input_2_ Source AIF3TX3MIX_Input_2_ Volume AIF3TX3MIX_Input_3_ Source AIF3TX3MIX_Input_3_ Volume AIF3TX3MIX_Input_4_ Source AIF3TX3MIX_Input_4_ Volume AIF3TX4MIX_Input_1_ Source AIF3TX4MIX_Input_1_ Volume AIF3TX4MIX_Input_2_ Source AIF3TX4MIX_Input_2_ Volume AIF3TX4MIX_Input_3_ Source AIF3TX4MIX_Input_3_ Volume AIF3TX4MIX_Input_4_ Source AIF3TX4MIX_Input_4_ Volume AIF3TX5MIX_Input_1_ Source AIF3TX5MIX_Input_1_ Volume AIF3TX5MIX_Input_2_ Source AIF3TX5MIX_Input_2_ Volume AIF3TX5MIX_Input_3_ Source AIF3TX5MIX_Input_3_ Volume AIF3TX5MIX_Input_4_ Source AIF3TX5MIX_Input_4_ Volume AIF3TX6MIX_Input_1_ Source AIF3TX6MIX_Input_1_ Volume AIF3TX6MIX_Input_2_ Source AIF3TX6MIX_Input_2_ Volume DS1162F1 15 14 13 12 11 10 9 8 AIF3TX1MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX2MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX2MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX2MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX2MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX3MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX3MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX3MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX3MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX4MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX4MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX4MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX4MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX5MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX5MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX5MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX5MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX6MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX6MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Default 0000h 0 0080h AIF3TX1MIX_SRC4 [7:0] AIF3TX1MIX_VOL4 [6:0] 0000h AIF3TX2MIX_SRC1 [7:0] AIF3TX2MIX_VOL1 [6:0] 0 0000h AIF3TX2MIX_SRC2 [7:0] AIF3TX2MIX_VOL2 [6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0080h 0000h AIF3TX6MIX_SRC2 [7:0] AIF3TX6MIX_VOL2 [6:0] 0080h 0000h AIF3TX6MIX_SRC1 [7:0] AIF3TX6MIX_VOL1 [6:0] 0080h 0000h AIF3TX5MIX_SRC4 [7:0] AIF3TX5MIX_VOL4 [6:0] 0080h 0000h AIF3TX5MIX_SRC3 [7:0] AIF3TX5MIX_VOL3 [6:0] 0080h 0000h AIF3TX5MIX_SRC2 [7:0] AIF3TX5MIX_VOL2 [6:0] 0080h 0000h AIF3TX5MIX_SRC1 [7:0] AIF3TX5MIX_VOL1 [6:0] 0080h 0000h AIF3TX4MIX_SRC4 [7:0] AIF3TX4MIX_VOL4 [6:0] 0080h 0000h AIF3TX4MIX_SRC3 [7:0] AIF3TX4MIX_VOL3 [6:0] 0080h 0000h AIF3TX4MIX_SRC2 [7:0] AIF3TX4MIX_VOL2 [6:0] 0080h 0000h AIF3TX4MIX_SRC1 [7:0] AIF3TX4MIX_VOL1 [6:0] 0080h 0000h AIF3TX3MIX_SRC4 [7:0] AIF3TX3MIX_VOL4 [6:0] 0080h 0000h AIF3TX3MIX_SRC3 [7:0] AIF3TX3MIX_VOL3 [6:0] 0080h 0000h AIF3TX3MIX_SRC2 [7:0] AIF3TX3MIX_VOL2 [6:0] 0080h 0000h AIF3TX3MIX_SRC1 [7:0] AIF3TX3MIX_VOL1 [6:0] 0080h 0000h AIF3TX2MIX_SRC4 [7:0] AIF3TX2MIX_VOL4 [6:0] 0080h 0000h AIF3TX2MIX_SRC3 [7:0] AIF3TX2MIX_VOL3 [6:0] 0080h 0 0080h 295 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R1964 (7ACh) R1965 (7ADh) R1966 (7AEh) R1967 (7AFh) R1968 (7B0h) R1969 (7B1h) R1970 (7B2h) R1971 (7B3h) R1972 (7B4h) R1973 (7B5h) R1974 (7B6h) R1975 (7B7h) R1976 (7B8h) R1977 (7B9h) R1978 (7BAh) R1979 (7BBh) R1980 (7BCh) R1981 (7BDh) R1982 (7BEh) R1983 (7BFh) R1984 (7C0h) R1985 (7C1h) R1986 (7C2h) R1987 (7C3h) R1988 (7C4h) R1989 (7C5h) R1990 (7C6h) R1991 (7C7h) R1992 (7C8h) R1993 (7C9h) R1994 (7CAh) R1995 (7CBh) R1996 (7CCh) R1997 (7CDh) R1998 (7CEh) R1999 (7CFh) R2000 (7D0h) R2001 (7D1h) 296 Name AIF3TX6MIX_Input_3_ Source AIF3TX6MIX_Input_3_ Volume AIF3TX6MIX_Input_4_ Source AIF3TX6MIX_Input_4_ Volume AIF3TX7MIX_Input_1_ Source AIF3TX7MIX_Input_1_ Volume AIF3TX7MIX_Input_2_ Source AIF3TX7MIX_Input_2_ Volume AIF3TX7MIX_Input_3_ Source AIF3TX7MIX_Input_3_ Volume AIF3TX7MIX_Input_4_ Source AIF3TX7MIX_Input_4_ Volume AIF3TX8MIX_Input_1_ Source AIF3TX8MIX_Input_1_ Volume AIF3TX8MIX_Input_2_ Source AIF3TX8MIX_Input_2_ Volume AIF3TX8MIX_Input_3_ Source AIF3TX8MIX_Input_3_ Volume AIF3TX8MIX_Input_4_ Source AIF3TX8MIX_Input_4_ Volume SLIMTX1MIX_Input_1_ Source SLIMTX1MIX_Input_1_ Volume SLIMTX1MIX_Input_2_ Source SLIMTX1MIX_Input_2_ Volume SLIMTX1MIX_Input_3_ Source SLIMTX1MIX_Input_3_ Volume SLIMTX1MIX_Input_4_ Source SLIMTX1MIX_Input_4_ Volume SLIMTX2MIX_Input_1_ Source SLIMTX2MIX_Input_1_ Volume SLIMTX2MIX_Input_2_ Source SLIMTX2MIX_Input_2_ Volume SLIMTX2MIX_Input_3_ Source SLIMTX2MIX_Input_3_ Volume SLIMTX2MIX_Input_4_ Source SLIMTX2MIX_Input_4_ Volume SLIMTX3MIX_Input_1_ Source SLIMTX3MIX_Input_1_ Volume 15 14 13 12 11 10 9 8 AIF3TX6MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX6MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX7MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX7MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX7MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX7MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX8MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX8MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX8MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3TX8MI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX1M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX1M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX1M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX1M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX2M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX2M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX2M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX2M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX3M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Default 0000h 0 0080h AIF3TX6MIX_SRC3 [7:0] AIF3TX6MIX_VOL3 [6:0] 0000h AIF3TX6MIX_SRC4 [7:0] AIF3TX6MIX_VOL4 [6:0] 0 0000h AIF3TX7MIX_SRC1 [7:0] AIF3TX7MIX_VOL1 [6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0080h 0000h SLIMTX3MIX_SRC1 [7:0] SLIMTX3MIX_VOL1 [6:0] 0080h 0000h SLIMTX2MIX_SRC4 [7:0] SLIMTX2MIX_VOL4 [6:0] 0080h 0000h SLIMTX2MIX_SRC3 [7:0] SLIMTX2MIX_VOL3 [6:0] 0080h 0000h SLIMTX2MIX_SRC2 [7:0] SLIMTX2MIX_VOL2 [6:0] 0080h 0000h SLIMTX2MIX_SRC1 [7:0] SLIMTX2MIX_VOL1 [6:0] 0080h 0000h SLIMTX1MIX_SRC4 [7:0] SLIMTX1MIX_VOL4 [6:0] 0080h 0000h SLIMTX1MIX_SRC3 [7:0] SLIMTX1MIX_VOL3 [6:0] 0080h 0000h SLIMTX1MIX_SRC2 [7:0] SLIMTX1MIX_VOL2 [6:0] 0080h 0000h SLIMTX1MIX_SRC1 [7:0] SLIMTX1MIX_VOL1 [6:0] 0080h 0000h AIF3TX8MIX_SRC4 [7:0] AIF3TX8MIX_VOL4 [6:0] 0080h 0000h AIF3TX8MIX_SRC3 [7:0] AIF3TX8MIX_VOL3 [6:0] 0080h 0000h AIF3TX8MIX_SRC2 [7:0] AIF3TX8MIX_VOL2 [6:0] 0080h 0000h AIF3TX8MIX_SRC1 [7:0] AIF3TX8MIX_VOL1 [6:0] 0080h 0000h AIF3TX7MIX_SRC4 [7:0] AIF3TX7MIX_VOL4 [6:0] 0080h 0000h AIF3TX7MIX_SRC3 [7:0] AIF3TX7MIX_VOL3 [6:0] 0080h 0000h AIF3TX7MIX_SRC2 [7:0] AIF3TX7MIX_VOL2 [6:0] 0080h 0 0080h DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R2002 (7D2h) R2003 (7D3h) R2004 (7D4h) R2005 (7D5h) R2006 (7D6h) R2007 (7D7h) R2008 (7D8h) R2009 (7D9h) R2010 (7DAh) R2011 (7DBh) R2012 (7DCh) R2013 (7DDh) R2014 (7DEh) R2015 (7DFh) R2016 (7E0h) R2017 (7E1h) R2018 (7E2h) R2019 (7E3h) R2020 (7E4h) R2021 (7E5h) R2022 (7E6h) R2023 (7E7h) R2024 (7E8h) R2025 (7E9h) R2026 (7EAh) R2027 (7EBh) R2028 (7ECh) R2029 (7EDh) R2030 (7EEh) R2031 (7EFh) R2032 (7F0h) R2033 (7F1h) R2034 (7F2h) R2035 (7F3h) R2036 (7F4h) R2037 (7F5h) R2038 (7F6h) R2039 (7F7h) Name SLIMTX3MIX_Input_2_ Source SLIMTX3MIX_Input_2_ Volume SLIMTX3MIX_Input_3_ Source SLIMTX3MIX_Input_3_ Volume SLIMTX3MIX_Input_4_ Source SLIMTX3MIX_Input_4_ Volume SLIMTX4MIX_Input_1_ Source SLIMTX4MIX_Input_1_ Volume SLIMTX4MIX_Input_2_ Source SLIMTX4MIX_Input_2_ Volume SLIMTX4MIX_Input_3_ Source SLIMTX4MIX_Input_3_ Volume SLIMTX4MIX_Input_4_ Source SLIMTX4MIX_Input_4_ Volume SLIMTX5MIX_Input_1_ Source SLIMTX5MIX_Input_1_ Volume SLIMTX5MIX_Input_2_ Source SLIMTX5MIX_Input_2_ Volume SLIMTX5MIX_Input_3_ Source SLIMTX5MIX_Input_3_ Volume SLIMTX5MIX_Input_4_ Source SLIMTX5MIX_Input_4_ Volume SLIMTX6MIX_Input_1_ Source SLIMTX6MIX_Input_1_ Volume SLIMTX6MIX_Input_2_ Source SLIMTX6MIX_Input_2_ Volume SLIMTX6MIX_Input_3_ Source SLIMTX6MIX_Input_3_ Volume SLIMTX6MIX_Input_4_ Source SLIMTX6MIX_Input_4_ Volume SLIMTX7MIX_Input_1_ Source SLIMTX7MIX_Input_1_ Volume SLIMTX7MIX_Input_2_ Source SLIMTX7MIX_Input_2_ Volume SLIMTX7MIX_Input_3_ Source SLIMTX7MIX_Input_3_ Volume SLIMTX7MIX_Input_4_ Source SLIMTX7MIX_Input_4_ Volume DS1162F1 15 14 13 12 11 10 9 8 SLIMTX3M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX3M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX3M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX4M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX4M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX4M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX4M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX5M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX5M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX5M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX5M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX6M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX6M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX6M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX6M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX7M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX7M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX7M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX7M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Default 0000h 0 0080h SLIMTX3MIX_SRC2 [7:0] SLIMTX3MIX_VOL2 [6:0] 0000h SLIMTX3MIX_SRC3 [7:0] SLIMTX3MIX_VOL3 [6:0] 0 0000h SLIMTX3MIX_SRC4 [7:0] SLIMTX3MIX_VOL4 [6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0080h 0000h SLIMTX7MIX_SRC4 [7:0] SLIMTX7MIX_VOL4 [6:0] 0080h 0000h SLIMTX7MIX_SRC3 [7:0] SLIMTX7MIX_VOL3 [6:0] 0080h 0000h SLIMTX7MIX_SRC2 [7:0] SLIMTX7MIX_VOL2 [6:0] 0080h 0000h SLIMTX7MIX_SRC1 [7:0] SLIMTX7MIX_VOL1 [6:0] 0080h 0000h SLIMTX6MIX_SRC4 [7:0] SLIMTX6MIX_VOL4 [6:0] 0080h 0000h SLIMTX6MIX_SRC3 [7:0] SLIMTX6MIX_VOL3 [6:0] 0080h 0000h SLIMTX6MIX_SRC2 [7:0] SLIMTX6MIX_VOL2 [6:0] 0080h 0000h SLIMTX6MIX_SRC1 [7:0] SLIMTX6MIX_VOL1 [6:0] 0080h 0000h SLIMTX5MIX_SRC4 [7:0] SLIMTX5MIX_VOL4 [6:0] 0080h 0000h SLIMTX5MIX_SRC3 [7:0] SLIMTX5MIX_VOL3 [6:0] 0080h 0000h SLIMTX5MIX_SRC2 [7:0] SLIMTX5MIX_VOL2 [6:0] 0080h 0000h SLIMTX5MIX_SRC1 [7:0] SLIMTX5MIX_VOL1 [6:0] 0080h 0000h SLIMTX4MIX_SRC4 [7:0] SLIMTX4MIX_VOL4 [6:0] 0080h 0000h SLIMTX4MIX_SRC3 [7:0] SLIMTX4MIX_VOL3 [6:0] 0080h 0000h SLIMTX4MIX_SRC2 [7:0] SLIMTX4MIX_VOL2 [6:0] 0080h 0000h SLIMTX4MIX_SRC1 [7:0] SLIMTX4MIX_VOL1 [6:0] 0080h 0 0080h 297 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R2040 (7F8h) R2041 (7F9h) R2042 (7FAh) R2043 (7FBh) R2044 (7FCh) R2045 (7FDh) R2046 (7FEh) R2047 (7FFh) R2048 (800h) R2049 (801h) R2056 (808h) R2057 (809h) R2176 (880h) R2177 (881h) R2178 (882h) R2179 (883h) R2180 (884h) R2181 (885h) R2182 (886h) R2183 (887h) R2184 (888h) R2185 (889h) R2186 (88Ah) R2187 (88Bh) R2188 (88Ch) R2189 (88Dh) R2190 (88Eh) R2191 (88Fh) R2192 (890h) R2193 (891h) R2194 (892h) R2195 (893h) R2196 (894h) R2197 (895h) R2198 (896h) R2199 (897h) R2200 (898h) R2201 (899h) 298 Name SLIMTX8MIX_Input_1_ Source SLIMTX8MIX_Input_1_ Volume SLIMTX8MIX_Input_2_ Source SLIMTX8MIX_Input_2_ Volume SLIMTX8MIX_Input_3_ Source SLIMTX8MIX_Input_3_ Volume SLIMTX8MIX_Input_4_ Source SLIMTX8MIX_Input_4_ Volume SPDIF1TX1MIX_Input_ 1_Source SPDIF1TX1MIX_Input_ 1_Volume SPDIF1TX2MIX_Input_ 1_Source SPDIF1TX2MIX_Input_ 1_Volume EQ1MIX_Input_1_ Source EQ1MIX_Input_1_ Volume EQ1MIX_Input_2_ Source EQ1MIX_Input_2_ Volume EQ1MIX_Input_3_ Source EQ1MIX_Input_3_ Volume EQ1MIX_Input_4_ Source EQ1MIX_Input_4_ Volume EQ2MIX_Input_1_ Source EQ2MIX_Input_1_ Volume EQ2MIX_Input_2_ Source EQ2MIX_Input_2_ Volume EQ2MIX_Input_3_ Source EQ2MIX_Input_3_ Volume EQ2MIX_Input_4_ Source EQ2MIX_Input_4_ Volume EQ3MIX_Input_1_ Source EQ3MIX_Input_1_ Volume EQ3MIX_Input_2_ Source EQ3MIX_Input_2_ Volume EQ3MIX_Input_3_ Source EQ3MIX_Input_3_ Volume EQ3MIX_Input_4_ Source EQ3MIX_Input_4_ Volume EQ4MIX_Input_1_ Source EQ4MIX_Input_1_ Volume 15 14 13 12 11 10 9 8 SLIMTX8M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX8M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX8M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLIMTX8M IX_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPDIF1TX 1_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPDIF1TX 2_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ1MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ1MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ1MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ1MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ2MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ2MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ2MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ2MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ3MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ3MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ3MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ3MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ4MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Default 0000h 0 0080h SLIMTX8MIX_SRC1 [7:0] SLIMTX8MIX_VOL1 [6:0] 0000h SLIMTX8MIX_SRC2 [7:0] SLIMTX8MIX_VOL2 [6:0] 0 0000h SLIMTX8MIX_SRC3 [7:0] SLIMTX8MIX_VOL3 [6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0080h 0000h EQ4MIX_SRC1 [7:0] EQ4MIX_VOL1 [6:0] 0080h 0000h EQ3MIX_SRC4 [7:0] EQ3MIX_VOL4 [6:0] 0080h 0000h EQ3MIX_SRC3 [7:0] EQ3MIX_VOL3 [6:0] 0080h 0000h EQ3MIX_SRC2 [7:0] EQ3MIX_VOL2 [6:0] 0080h 0000h EQ3MIX_SRC1 [7:0] EQ3MIX_VOL1 [6:0] 0080h 0000h EQ2MIX_SRC4 [7:0] EQ2MIX_VOL4 [6:0] 0080h 0000h EQ2MIX_SRC3 [7:0] EQ2MIX_VOL3 [6:0] 0080h 0000h EQ2MIX_SRC2 [7:0] EQ2MIX_VOL2 [6:0] 0080h 0000h EQ2MIX_SRC1 [7:0] EQ2MIX_VOL1 [6:0] 0080h 0000h EQ1MIX_SRC4 [7:0] EQ1MIX_VOL4 [6:0] 0080h 0000h EQ1MIX_SRC3 [7:0] EQ1MIX_VOL3 [6:0] 0080h 0000h EQ1MIX_SRC2 [7:0] EQ1MIX_VOL2 [6:0] 0080h 0000h EQ1MIX_SRC1 [7:0] EQ1MIX_VOL1 [6:0] 0080h 0000h SPDIF1TX2_SRC [7:0] SPDIF1TX2_VOL [6:0] 0080h 0000h SPDIF1TX1_SRC [7:0] SPDIF1TX1_VOL [6:0] 0080h 0000h SLIMTX8MIX_SRC4 [7:0] SLIMTX8MIX_VOL4 [6:0] 0080h 0 0080h DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R2202 (89Ah) R2203 (89Bh) R2204 (89Ch) R2205 (89Dh) R2206 (89Eh) R2207 (89Fh) R2240 (8C0h) R2241 (8C1h) R2242 (8C2h) R2243 (8C3h) R2244 (8C4h) R2245 (8C5h) R2246 (8C6h) R2247 (8C7h) R2248 (8C8h) R2249 (8C9h) R2250 (8CAh) R2251 (8CBh) R2252 (8CCh) R2253 (8CDh) R2254 (8CEh) R2255 (8CFh) R2256 (8D0h) R2257 (8D1h) R2258 (8D2h) R2259 (8D3h) R2260 (8D4h) R2261 (8D5h) R2262 (8D6h) R2263 (8D7h) R2264 (8D8h) R2265 (8D9h) R2266 (8DAh) R2267 (8DBh) R2268 (8DCh) R2269 (8DDh) R2270 (8DEh) R2271 (8DFh) Name EQ4MIX_Input_2_ Source EQ4MIX_Input_2_ Volume EQ4MIX_Input_3_ Source EQ4MIX_Input_3_ Volume EQ4MIX_Input_4_ Source EQ4MIX_Input_4_ Volume DRC1LMIX_Input_1_ Source DRC1LMIX_Input_1_ Volume DRC1LMIX_Input_2_ Source DRC1LMIX_Input_2_ Volume DRC1LMIX_Input_3_ Source DRC1LMIX_Input_3_ Volume DRC1LMIX_Input_4_ Source DRC1LMIX_Input_4_ Volume DRC1RMIX_Input_1_ Source DRC1RMIX_Input_1_ Volume DRC1RMIX_Input_2_ Source DRC1RMIX_Input_2_ Volume DRC1RMIX_Input_3_ Source DRC1RMIX_Input_3_ Volume DRC1RMIX_Input_4_ Source DRC1RMIX_Input_4_ Volume DRC2LMIX_Input_1_ Source DRC2LMIX_Input_1_ Volume DRC2LMIX_Input_2_ Source DRC2LMIX_Input_2_ Volume DRC2LMIX_Input_3_ Source DRC2LMIX_Input_3_ Volume DRC2LMIX_Input_4_ Source DRC2LMIX_Input_4_ Volume DRC2RMIX_Input_1_ Source DRC2RMIX_Input_1_ Volume DRC2RMIX_Input_2_ Source DRC2RMIX_Input_2_ Volume DRC2RMIX_Input_3_ Source DRC2RMIX_Input_3_ Volume DRC2RMIX_Input_4_ Source DRC2RMIX_Input_4_ Volume DS1162F1 15 14 13 12 11 10 9 8 EQ4MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ4MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ4MIX_ STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC1LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC1LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC1LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC1LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC1RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC1RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC1RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC1RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC2LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC2LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC2LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC2LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC2RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC2RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC2RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRC2RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Default 0000h 0 0080h EQ4MIX_SRC2 [7:0] EQ4MIX_VOL2 [6:0] 0000h EQ4MIX_SRC3 [7:0] EQ4MIX_VOL3 [6:0] 0 0000h EQ4MIX_SRC4 [7:0] EQ4MIX_VOL4 [6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0080h 0000h DRC2RMIX_SRC4 [7:0] DRC2RMIX_VOL4 [6:0] 0080h 0000h DRC2RMIX_SRC3 [7:0] DRC2RMIX_VOL3 [6:0] 0080h 0000h DRC2RMIX_SRC2 [7:0] DRC2RMIX_VOL2 [6:0] 0080h 0000h DRC2RMIX_SRC1 [7:0] DRC2RMIX_VOL1 [6:0] 0080h 0000h DRC2LMIX_SRC4 [7:0] DRC2LMIX_VOL4 [6:0] 0080h 0000h DRC2LMIX_SRC3 [7:0] DRC2LMIX_VOL3 [6:0] 0080h 0000h DRC2LMIX_SRC2 [7:0] DRC2LMIX_VOL2 [6:0] 0080h 0000h DRC2LMIX_SRC1 [7:0] DRC2LMIX_VOL1 [6:0] 0080h 0000h DRC1RMIX_SRC4 [7:0] DRC1RMIX_VOL4 [6:0] 0080h 0000h DRC1RMIX_SRC3 [7:0] DRC1RMIX_VOL3 [6:0] 0080h 0000h DRC1RMIX_SRC2 [7:0] DRC1RMIX_VOL2 [6:0] 0080h 0000h DRC1RMIX_SRC1 [7:0] DRC1RMIX_VOL1 [6:0] 0080h 0000h DRC1LMIX_SRC4 [7:0] DRC1LMIX_VOL4 [6:0] 0080h 0000h DRC1LMIX_SRC3 [7:0] DRC1LMIX_VOL3 [6:0] 0080h 0000h DRC1LMIX_SRC2 [7:0] DRC1LMIX_VOL2 [6:0] 0080h 0000h DRC1LMIX_SRC1 [7:0] DRC1LMIX_VOL1 [6:0] 0080h 0 0080h 299 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R2304 (900h) R2305 (901h) R2306 (902h) R2307 (903h) R2308 (904h) R2309 (905h) R2310 (906h) R2311 (907h) R2312 (908h) R2313 (909h) R2314 (90Ah) R2315 (90Bh) R2316 (90Ch) R2317 (90Dh) R2318 (90Eh) R2319 (90Fh) R2320 (910h) R2321 (911h) R2322 (912h) R2323 (913h) R2324 (914h) R2325 (915h) R2326 (916h) R2327 (917h) R2328 (918h) R2329 (919h) R2330 (91Ah) R2331 (91Bh) R2332 (91Ch) R2333 (91Dh) R2334 (91Eh) R2335 (91Fh) R2368 (940h) R2369 (941h) R2370 (942h) R2371 (943h) R2372 (944h) R2373 (945h) 300 Name HPLP1MIX_Input_1_ Source HPLP1MIX_Input_1_ Volume HPLP1MIX_Input_2_ Source HPLP1MIX_Input_2_ Volume HPLP1MIX_Input_3_ Source HPLP1MIX_Input_3_ Volume HPLP1MIX_Input_4_ Source HPLP1MIX_Input_4_ Volume HPLP2MIX_Input_1_ Source HPLP2MIX_Input_1_ Volume HPLP2MIX_Input_2_ Source HPLP2MIX_Input_2_ Volume HPLP2MIX_Input_3_ Source HPLP2MIX_Input_3_ Volume HPLP2MIX_Input_4_ Source HPLP2MIX_Input_4_ Volume HPLP3MIX_Input_1_ Source HPLP3MIX_Input_1_ Volume HPLP3MIX_Input_2_ Source HPLP3MIX_Input_2_ Volume HPLP3MIX_Input_3_ Source HPLP3MIX_Input_3_ Volume HPLP3MIX_Input_4_ Source HPLP3MIX_Input_4_ Volume HPLP4MIX_Input_1_ Source HPLP4MIX_Input_1_ Volume HPLP4MIX_Input_2_ Source HPLP4MIX_Input_2_ Volume HPLP4MIX_Input_3_ Source HPLP4MIX_Input_3_ Volume HPLP4MIX_Input_4_ Source HPLP4MIX_Input_4_ Volume DSP1LMIX_Input_1_ Source DSP1LMIX_Input_1_ Volume DSP1LMIX_Input_2_ Source DSP1LMIX_Input_2_ Volume DSP1LMIX_Input_3_ Source DSP1LMIX_Input_3_ Volume 15 14 13 12 11 10 9 8 LHPF1MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF1MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF1MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF1MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF2MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF2MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF2MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF2MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF3MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF3MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF3MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF3MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF4MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF4MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF4MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF4MIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Default 0000h 0 0080h LHPF1MIX_SRC1 [7:0] LHPF1MIX_VOL1 [6:0] 0000h LHPF1MIX_SRC2 [7:0] LHPF1MIX_VOL2 [6:0] 0 0000h LHPF1MIX_SRC3 [7:0] LHPF1MIX_VOL3 [6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0080h 0000h DSP1LMIX_SRC3 [7:0] DSP1LMIX_VOL3 [6:0] 0080h 0000h DSP1LMIX_SRC2 [7:0] DSP1LMIX_VOL2 [6:0] 0080h 0000h DSP1LMIX_SRC1 [7:0] DSP1LMIX_VOL1 [6:0] 0080h 0000h LHPF4MIX_SRC4 [7:0] LHPF4MIX_VOL4 [6:0] 0080h 0000h LHPF4MIX_SRC3 [7:0] LHPF4MIX_VOL3 [6:0] 0080h 0000h LHPF4MIX_SRC2 [7:0] LHPF4MIX_VOL2 [6:0] 0080h 0000h LHPF4MIX_SRC1 [7:0] LHPF4MIX_VOL1 [6:0] 0080h 0000h LHPF3MIX_SRC4 [7:0] LHPF3MIX_VOL4 [6:0] 0080h 0000h LHPF3MIX_SRC3 [7:0] LHPF3MIX_VOL3 [6:0] 0080h 0000h LHPF3MIX_SRC2 [7:0] LHPF3MIX_VOL2 [6:0] 0080h 0000h LHPF3MIX_SRC1 [7:0] LHPF3MIX_VOL1 [6:0] 0080h 0000h LHPF2MIX_SRC4 [7:0] LHPF2MIX_VOL4 [6:0] 0080h 0000h LHPF2MIX_SRC3 [7:0] LHPF2MIX_VOL3 [6:0] 0080h 0000h LHPF2MIX_SRC2 [7:0] LHPF2MIX_VOL2 [6:0] 0080h 0000h LHPF2MIX_SRC1 [7:0] LHPF2MIX_VOL1 [6:0] 0080h 0000h LHPF1MIX_SRC4 [7:0] LHPF1MIX_VOL4 [6:0] 0080h 0 0080h DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R2374 (946h) R2375 (947h) R2376 (948h) R2377 (949h) R2378 (94Ah) R2379 (94Bh) R2380 (94Ch) R2381 (94Dh) R2382 (94Eh) R2383 (94Fh) R2384 (950h) R2392 (958h) R2400 (960h) R2408 (968h) R2416 (970h) R2424 (978h) R2688 (A80h) R2696 (A88h) R2704 (A90h) R2712 (A98h) R2816 (B00h) R2824 (B08h) R2848 (B20h) R2856 (B28h) R2880 (B40h) R2888 (B48h) R2912 (B60h) R2920 (B68h) R3520 (DC0h) R3528 (DC8h) R3536 (DD0h) R3544 (DD8h) R3552 (DE0h) R3560 (DE8h) R3568 (DF0h) R3576 (DF8h) R3584 (E00h) R3585 (E01h) Name DSP1LMIX_Input_4_ Source DSP1LMIX_Input_4_ Volume DSP1RMIX_Input_1_ Source DSP1RMIX_Input_1_ Volume DSP1RMIX_Input_2_ Source DSP1RMIX_Input_2_ Volume DSP1RMIX_Input_3_ Source DSP1RMIX_Input_3_ Volume DSP1RMIX_Input_4_ Source DSP1RMIX_Input_4_ Volume DSP1AUX1MIX_Input_ 1_Source DSP1AUX2MIX_Input_ 1_Source DSP1AUX3MIX_Input_ 1_Source DSP1AUX4MIX_Input_ 1_Source DSP1AUX5MIX_Input_ 1_Source DSP1AUX6MIX_Input_ 1_Source ASRC1_1LMIX_Input_ 1_Source ASRC1_1RMIX_Input_ 1_Source ASRC1_2LMIX_Input_ 1_Source ASRC1_2RMIX_Input_ 1_Source ISRC1DEC1MIX_Input_ 1_Source ISRC1DEC2MIX_Input_ 1_Source ISRC1INT1MIX_Input_ 1_Source ISRC1INT2MIX_Input_ 1_Source ISRC2DEC1MIX_Input_ 1_Source ISRC2DEC2MIX_Input_ 1_Source ISRC2INT1MIX_Input_ 1_Source ISRC2INT2MIX_Input_ 1_Source DFC1MIX_Input_1_ Source DFC2MIX_Input_1_ Source DFC3MIX_Input_1_ Source DFC4MIX_Input_1_ Source DFC5MIX_Input_1_ Source DFC6MIX_Input_1_ Source DFC7MIX_Input_1_ Source DFC8MIX_Input_1_ Source FX_Ctrl1 FX_Ctrl2 DS1162F1 15 14 13 12 11 10 9 8 DSP1LMIX _STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1RMI X_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1AUX 1_STS 0 0 0 0 0 0 0 DSP1AUX1_SRC [7:0] 0000h DSP1AUX 2_STS 0 0 0 0 0 0 0 DSP1AUX2_SRC [7:0] 0000h DSP1AUX 3_STS 0 0 0 0 0 0 0 DSP1AUX3_SRC [7:0] 0000h DSP1AUX 4_STS 0 0 0 0 0 0 0 DSP1AUX4_SRC [7:0] 0000h DSP1AUX 5_STS 0 0 0 0 0 0 0 DSP1AUX5_SRC [7:0] 0000h DSP1AUX 6_STS 0 0 0 0 0 0 0 DSP1AUX6_SRC [7:0] 0000h ASRC1_ IN1L_STS 0 0 0 0 0 0 0 ASRC1_IN1L_SRC [7:0] 0000h ASRC1_ IN1R_STS 0 0 0 0 0 0 0 ASRC1_IN1R_SRC [7:0] 0000h ASRC1_ IN2L_STS 0 0 0 0 0 0 0 ASRC1_IN2L_SRC [7:0] 0000h ASRC1_ IN2R_STS 0 0 0 0 0 0 0 ASRC1_IN2R_SRC [7:0] 0000h ISRC1DEC 1_STS 0 0 0 0 0 0 0 ISRC1DEC1_SRC [7:0] 0000h ISRC1DEC 2_STS 0 0 0 0 0 0 0 ISRC1DEC2_SRC [7:0] 0000h ISRC1INT 1_STS 0 0 0 0 0 0 0 ISRC1INT1_SRC [7:0] 0000h ISRC1INT 2_STS 0 0 0 0 0 0 0 ISRC1INT2_SRC [7:0] 0000h ISRC2DEC 1_STS 0 0 0 0 0 0 0 ISRC2DEC1_SRC [7:0] 0000h ISRC2DEC 2_STS 0 0 0 0 0 0 0 ISRC2DEC2_SRC [7:0] 0000h ISRC2INT 1_STS 0 0 0 0 0 0 0 ISRC2INT1_SRC [7:0] 0000h ISRC2INT 2_STS 0 0 0 0 0 0 0 ISRC2INT2_SRC [7:0] 0000h DFC1_ STS 0 0 0 0 0 0 0 DFC1_SRC [7:0] 0000h DFC2_ STS 0 0 0 0 0 0 0 DFC2_SRC [7:0] 0000h DFC3_ STS 0 0 0 0 0 0 0 DFC3_SRC [7:0] 0000h DFC4_ STS 0 0 0 0 0 0 0 DFC4_SRC [7:0] 0000h DFC5_ STS 0 0 0 0 0 0 0 DFC5_SRC [7:0] 0000h DFC6_ STS 0 0 0 0 0 0 0 DFC6_SRC [7:0] 0000h DFC7_ STS 0 0 0 0 0 0 0 DFC7_SRC [7:0] 0000h DFC8_ STS 0 0 0 0 0 0 0 DFC8_SRC [7:0] 0000h 0 0 0 FX_RATE [4:0] FX_STS [11:0] 7 6 5 4 3 2 1 0 Default 0000h 0 0080h DSP1LMIX_SRC4 [7:0] DSP1LMIX_VOL4 [6:0] 0000h DSP1RMIX_SRC1 [7:0] DSP1RMIX_VOL1 [6:0] 0 0000h DSP1RMIX_SRC2 [7:0] DSP1RMIX_VOL2 [6:0] 0 DSP1RMIX_VOL3 [6:0] 0 DSP1RMIX_VOL4 [6:0] 0 0 0080h 0000h DSP1RMIX_SRC4 [7:0] 0 0080h 0000h DSP1RMIX_SRC3 [7:0] 0 0080h 0 0080h 0 0 0 0 0000h 0 0 1 0 0002h 301 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R3600 (E10h) R3601 (E11h) R3602 (E12h) R3603 (E13h) R3604 (E14h) R3605 (E15h) R3606 (E16h) R3607 (E17h) R3608 (E18h) R3609 (E19h) R3610 (E1Ah) R3611 (E1Bh) R3612 (E1Ch) R3613 (E1Dh) R3614 (E1Eh) R3615 (E1Fh) R3616 (E20h) R3617 (E21h) R3618 (E22h) R3619 (E23h) R3620 (E24h) R3622 (E26h) R3623 (E27h) R3624 (E28h) R3625 (E29h) R3626 (E2Ah) R3627 (E2Bh) R3628 (E2Ch) R3629 (E2Dh) R3630 (E2Eh) R3631 (E2Fh) R3632 (E30h) R3633 (E31h) R3634 (E32h) R3635 (E33h) R3636 (E34h) R3637 (E35h) R3638 (E36h) 302 Name 15 14 13 12 11 10 9 8 EQ1_1 EQ1_B1_GAIN [4:0] EQ1_B2_GAIN [4:0] EQ1_2 EQ1_B4_GAIN [4:0] EQ1_B5_GAIN [4:0] 7 6 5 4 3 2 1 EQ1_B3_GAIN [4:0] 0 0 0 0 EQ1_ENA 0 0 EQ1_B1_ MODE Default 6318h 6300h EQ1_3 EQ1_B1_A [15:0] 0FC8h EQ1_4 EQ1_B1_B [15:0] 03FEh EQ1_5 EQ1_B1_PG [15:0] 00E0h EQ1_6 EQ1_B2_A [15:0] 1EC4h EQ1_7 EQ1_B2_B [15:0] F136h EQ1_8 EQ1_B2_C [15:0] 0409h EQ1_9 EQ1_B2_PG [15:0] 04CCh EQ1_10 EQ1_B3_A [15:0] 1C9Bh EQ1_11 EQ1_B3_B [15:0] F337h EQ1_12 EQ1_B3_C [15:0] 040Bh EQ1_13 EQ1_B3_PG [15:0] 0CBBh EQ1_14 EQ1_B4_A [15:0] 16F8h EQ1_15 EQ1_B4_B [15:0] F7D9h EQ1_16 EQ1_B4_C [15:0] 040Ah EQ1_17 EQ1_B4_PG [15:0] 1F14h EQ1_18 EQ1_B5_A [15:0] 058Ch EQ1_19 EQ1_B5_B [15:0] 0563h EQ1_20 EQ1_B5_PG [15:0] 4000h EQ1_21 EQ1_B1_C [15:0] 0B75h EQ2_1 EQ2_B1_GAIN [4:0] EQ2_B2_GAIN [4:0] EQ2_2 EQ2_B4_GAIN [4:0] EQ2_B5_GAIN [4:0] EQ2_B3_GAIN [4:0] 0 0 0 0 0 EQ2_ENA 6318h EQ2_B1_ MODE 6300h EQ2_3 EQ2_B1_A [15:0] 0FC8h EQ2_4 EQ2_B1_B [15:0] 03FEh EQ2_5 EQ2_B1_PG [15:0] 00E0h EQ2_6 EQ2_B2_A [15:0] 1EC4h EQ2_7 EQ2_B2_B [15:0] F136h EQ2_8 EQ2_B2_C [15:0] 0409h EQ2_9 EQ2_B2_PG [15:0] 04CCh EQ2_10 EQ2_B3_A [15:0] 1C9Bh EQ2_11 EQ2_B3_B [15:0] F337h EQ2_12 EQ2_B3_C [15:0] 040Bh EQ2_13 EQ2_B3_PG [15:0] 0CBBh EQ2_14 EQ2_B4_A [15:0] 16F8h EQ2_15 EQ2_B4_B [15:0] F7D9h EQ2_16 EQ2_B4_C [15:0] 040Ah EQ2_17 EQ2_B4_PG [15:0] 1F14h DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R3639 (E37h) R3640 (E38h) R3641 (E39h) R3642 (E3Ah) R3644 (E3Ch) R3645 (E3Dh) R3646 (E3Eh) R3647 (E3Fh) R3648 (E40h) R3649 (E41h) R3650 (E42h) R3651 (E43h) R3652 (E44h) R3653 (E45h) R3654 (E46h) R3655 (E47h) R3656 (E48h) R3657 (E49h) R3658 (E4Ah) R3659 (E4Bh) R3660 (E4Ch) R3661 (E4Dh) R3662 (E4Eh) R3663 (E4Fh) R3664 (E50h) R3666 (E52h) R3667 (E53h) R3668 (E54h) R3669 (E55h) R3670 (E56h) R3671 (E57h) R3672 (E58h) R3673 (E59h) R3674 (E5Ah) R3675 (E5Bh) R3676 (E5Ch) R3677 (E5Dh) R3678 (E5Eh) Name 15 14 EQ2_18 13 12 11 10 9 EQ2_B5_A [15:0] 8 Default 058Ch EQ2_19 EQ2_B5_B [15:0] 0563h EQ2_20 EQ2_B5_PG [15:0] 4000h EQ2_21 EQ2_B1_C [15:0] 0B75h EQ3_1 EQ3_B1_GAIN [4:0] EQ3_B2_GAIN [4:0] EQ3_2 EQ3_B4_GAIN [4:0] EQ3_B5_GAIN [4:0] 7 6 5 4 3 2 1 EQ3_B3_GAIN [4:0] 0 0 0 0 0 0 EQ3_ENA 6318h EQ3_B1_ MODE 6300h EQ3_3 EQ3_B1_A [15:0] 0FC8h EQ3_4 EQ3_B1_B [15:0] 03FEh EQ3_5 EQ3_B1_PG [15:0] 00E0h EQ3_6 EQ3_B2_A [15:0] 1EC4h EQ3_7 EQ3_B2_B [15:0] F136h EQ3_8 EQ3_B2_C [15:0] 0409h EQ3_9 EQ3_B2_PG [15:0] 04CCh EQ3_10 EQ3_B3_A [15:0] 1C9Bh EQ3_11 EQ3_B3_B [15:0] F337h EQ3_12 EQ3_B3_C [15:0] 040Bh EQ3_13 EQ3_B3_PG [15:0] 0CBBh EQ3_14 EQ3_B4_A [15:0] 16F8h EQ3_15 EQ3_B4_B [15:0] F7D9h EQ3_16 EQ3_B4_C [15:0] 040Ah EQ3_17 EQ3_B4_PG [15:0] 1F14h EQ3_18 EQ3_B5_A [15:0] 058Ch EQ3_19 EQ3_B5_B [15:0] 0563h EQ3_20 EQ3_B5_PG [15:0] 4000h EQ3_21 EQ3_B1_C [15:0] 0B75h EQ4_1 EQ4_B1_GAIN [4:0] EQ4_B2_GAIN [4:0] EQ4_2 EQ4_B4_GAIN [4:0] EQ4_B5_GAIN [4:0] EQ4_B3_GAIN [4:0] 0 0 0 0 0 EQ4_ENA 6318h EQ4_B1_ MODE 6300h EQ4_3 EQ4_B1_A [15:0] 0FC8h EQ4_4 EQ4_B1_B [15:0] 03FEh EQ4_5 EQ4_B1_PG [15:0] 00E0h EQ4_6 EQ4_B2_A [15:0] 1EC4h EQ4_7 EQ4_B2_B [15:0] F136h EQ4_8 EQ4_B2_C [15:0] 0409h EQ4_9 EQ4_B2_PG [15:0] 04CCh EQ4_10 EQ4_B3_A [15:0] 1C9Bh EQ4_11 EQ4_B3_B [15:0] F337h EQ4_12 EQ4_B3_C [15:0] 040Bh EQ4_13 EQ4_B3_PG [15:0] 0CBBh DS1162F1 303 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R3679 (E5Fh) R3680 (E60h) R3681 (E61h) R3682 (E62h) R3683 (E63h) R3684 (E64h) R3685 (E65h) R3686 (E66h) R3712 (E80h) Name 15 EQ4_14 EQ4_B4_A [15:0] Default 16F8h EQ4_15 EQ4_B4_B [15:0] F7D9h EQ4_16 EQ4_B4_C [15:0] 040Ah EQ4_17 EQ4_B4_PG [15:0] 1F14h EQ4_18 EQ4_B5_A [15:0] 058Ch EQ4_19 EQ4_B5_B [15:0] 0563h EQ4_20 EQ4_B5_PG [15:0] 4000h EQ4_21 EQ4_B1_C [15:0] 0B75h DRC1_ctrl1 14 13 DRC1_SIG_DET_RMS [4:0] R3713 (E81h) R3714 (E82h) R3715 (E83h) R3716 (E84h) R3720 (E88h) DRC1_ctrl2 R3721 (E89h) R3722 (E8Ah) R3723 (E8Bh) R3724 (E8Ch) R3776 (EC0h) R3777 (EC1h) R3780 (EC4h) R3781 (EC5h) R3784 (EC8h) R3785 (EC9h) R3788 (ECCh) R3789 (ECDh) R3808 (EE0h) R3809 (EE1h) DRC2_ctrl2 R3810 (EE2h) R3811 (EE3h) R3824 (EF0h) R3825 (EF1h) R3826 (EF2h) ASRC1_RATE1 R3827 (EF3h) R3828 (EF4h) R3829 (EF5h) ISRC2_CTRL_1 ISRC2_FSH [4:0] ISRC2_CTRL_2 ISRC2_FSL [4:0] 0 DRC1_ctrl3 0 0 DRC1_NG_MINGAIN [3:0] 11 0 0 0 0 DRC1_ctrl5 0 0 0 0 0 DRC2_SIG_DET_RMS [4:0] 0 DRC2_ctrl3 0 9 0 DRC2_NG_MINGAIN [3:0] 0 5 4 3 DRC1_HI_COMP [2:0] DRC1_KNEE2_IP [4:0] DRC2_NG_EXP [1:0] DRC2_QR_THR [1:0] DRC2_QR_DCY [1:0] 0 0 0 0 DRC2_ctrl5 0 0 0 0 0 0 HPLPF1_1 0 0 0 0 0 0 2 1 0 DRC1_LO_COMP [2:0] DRC2_KNEE2_IP [4:0] 0 0 0 0 0 0 0 0 0 0 0 0 HPLPF2_2 0 0 0 0 0 0 0 0 HPLPF3_2 0 0 0000h DRC2L_ DRC2R_ ENA ENA 0018h DRC2_MAXGAIN [1:0] 0933h DRC2_LO_COMP [2:0] 0 0 0 0 0 0 HPLPF4_2 0 0 0018h DRC2_KNEE_OP [4:0] 0000h DRC2_KNEE2_OP [4:0] 0000h 0 0 LHPF1_ MODE LHPF1_ ENA 0000h 0000h 0 0 0 0 0 LHPF2_ MODE LHPF2_ ENA 0000h 0000h 0 0 0 0 0 LHPF3_ MODE LHPF3_ ENA 0000h 0000h LHPF3_COEFF [15:0] 0 0018h DRC1_KNEE2_OP [4:0] LHPF2_COEFF [15:0] 0 0933h 0000h LHPF1_COEFF [15:0] 0 0018h DRC1_KNEE_OP [4:0] DRC2_HI_COMP [2:0] DRC2_KNEE_IP [5:0] HPLPF1_2 HPLPF4_1 6 DRC2_SIG_DET_PK DRC2_ DRC2_ DRC2_ DRC2_ DRC2_QR DRC2_ 0 [1:0] NG_ENA SIG_DET_ SIG_DET KNEE2_ ANTICLIP MODE OP_ENA DRC2_ATK [3:0] DRC2_DCY [3:0] DRC2_MINGAIN [2:0] 0 HPLPF3_1 7 DRC1_KNEE_IP [5:0] DRC2_ctrl4 HPLPF2_1 8 DRC1_NG_EXP [1:0] DRC1_QR_THR [1:0] DRC1_QR_DCY [1:0] 0 DRC2_ctrl1 10 DRC1_SIG_DET_PK DRC1_ DRC1_ DRC1_ DRC1_ DRC1_QR DRC1_ DRC1_ DRC1L_ DRC1R_ [1:0] NG_ENA SIG_DET_ SIG_DET KNEE2_ ANTICLIP WSEQ_ ENA ENA MODE OP_ENA SIG_DET_ ENA DRC1_ATK [3:0] DRC1_DCY [3:0] DRC1_MINGAIN [2:0] DRC1_MAXGAIN [1:0] DRC1_ctrl4 0 0 0 0 0 LHPF4_ MODE LHPF4_ ENA 0000h 0000h LHPF4_COEFF [15:0] ASRC1_ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 ASRC1_ ASRC1_ ASRC1_ ASRC1_ IN2L_ENA IN2R_ENA IN1L_ENA IN1R_ENA 0000h ASRC1_STATUS 0 0 0 0 0 0 0 0 0 0 0 0 0000h ASRC1_RATE1 [4:0] 0 0 0 0 0 0 0 ASRC1_ ASRC1_ ASRC1_ ASRC1_ IN2L_ IN2R_ IN1L_ IN1R_ ENA_STS ENA_STS ENA_STS ENA_STS 0 0 0 0 ASRC1_RATE2 ASRC1_RATE2 [4:0] 0 0 0 0 0 0 0 0 0 0 0 4000h ISRC1_CTRL_1 ISRC1_FSH [4:0] 0 0 0 0 0 0 0 0 0 0 0 0000h ISRC1_CTRL_2 ISRC1_FSL [4:0] 0 0 0 0 0 0 0 0 0 0 1 0001h 0 ISRC1_ DEC2_ ENA 0 0 0 0 0 0 0 0 0 0000h 0 ISRC1_ DEC1_ ENA 0 0 0 0 0 0 0 0 0 0000h 0 0 0 0 0 0 0 0 0 0 1 0001h ISRC2_ DEC2_ ENA 0 0 0 0 0 0 0 0 0000h 0 0 0 US1_ENA 2030h ISRC1_CTRL_3 ISRC2_CTRL_3 R4224 US1_Ctrl_0 (1080h) 304 12 ISRC1_ ISRC1_ INT1_ENA INT2_ENA ISRC2_ ISRC2_ INT1_ENA INT2_ENA 0 0 0 0 0 0 US1_GAIN [1:0] 0 0 0 ISRC2_ DEC1_ ENA US1_SRC [3:0] 0 US1_FREQ [2:0] 0000h DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R4225 (1081h) R4226 (1082h) R4227 (1083h) R4288 (10C0h) R4289 (10C1h) R5248 (1480h) R5250 (1482h) R5252 (1484h) R5254 (1486h) R5256 (1488h) R5258 (148Ah) R5260 (148Ch) R5262 (148Eh) R5264 (1490h) R5266 (1492h) R5268 (1494h) R5270 (1496h) R5272 (1498h) R5274 (149Ah) R5276 (149Ch) R5278 (149Eh) R5280 (14A0h) R5282 (14A2h) R5284 (14A4h) R5286 (14A6h) R5288 (14A8h) R5290 (14AAh) R5292 (14ACh) R5294 (14AEh) R5302 (14B6h) R5303 (14B7h) R5632 (1600h) R5633 (1601h) R5634 (1602h) R5635 (1603h) R5636 (1604h) R5637 (1605h) R5638 (1606h) Name US1_Ctrl_1 15 US2_Ctrl_0 0 14 0 US2_Ctrl_1 AUXPDM1_Ctrl_0 AUXPDM1_Ctrl_1 13 12 11 US1_RATE [4:0] US2_GAIN [1:0] 0 AUXPDM1_CLK_ FREQ[1:0] 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 Default 0000h 0 0 0 US2_ENA 2030h 0 0 0 0 0000h 0 AUXPDM1 _ENA 0008h 0 0 4000h US2_SRC [3:0] US2_RATE [4:0] 0 10 0 0 0 0 AUXPDM1_SRC[3:0] US2_FREQ [2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXPDM1 AUXPDM1 AUXPDM1 _TXEDGE _MSTR _MUTE 0 0 0 DFC1_CTRL_W0 0 0 0 DFC1_RX_W0 0 0 0 DFC1_RX_DATA_WIDTH [4:0] 0 0 0 0 DFC1_TX_W0 0 0 0 DFC1_TX_DATA_WIDTH [4:0] 0 0 0 0 DFC2_CTRL_W0 0 0 0 DFC2_RX_W0 0 0 0 DFC2_RX_DATA_WIDTH [4:0] 0 0 0 0 DFC2_TX_W0 0 0 0 DFC2_TX_DATA_WIDTH [4:0] 0 0 0 0 DFC3_CTRL_W0 0 0 0 DFC3_RX_W0 0 0 0 DFC3_RX_DATA_WIDTH [4:0] 0 0 0 0 DFC3_TX_W0 0 0 0 DFC3_TX_DATA_WIDTH [4:0] 0 0 0 0 DFC4_CTRL_W0 0 0 0 DFC4_RX_W0 0 0 0 DFC4_RX_DATA_WIDTH [4:0] 0 0 0 0 DFC4_TX_W0 0 0 0 DFC4_TX_DATA_WIDTH [4:0] 0 0 0 0 DFC5_CTRL_W0 0 0 0 DFC5_RX_W0 0 0 0 DFC5_RX_DATA_WIDTH [4:0] 0 0 0 0 DFC5_TX_W0 0 0 0 DFC5_TX_DATA_WIDTH [4:0] 0 0 0 0 DFC6_CTRL_W0 0 0 0 DFC6_RX_W0 0 0 0 DFC6_RX_DATA_WIDTH [4:0] 0 0 0 0 DFC6_TX_W0 0 0 0 DFC6_TX_DATA_WIDTH [4:0] 0 0 0 0 DFC7_CTRL_W0 0 0 0 DFC7_RX_W0 0 0 0 DFC7_RX_DATA_WIDTH [4:0] 0 0 0 0 DFC7_TX_W0 0 0 0 DFC7_TX_DATA_WIDTH [4:0] 0 0 0 0 DFC8_CTRL_W0 0 0 0 DFC8_RX_W0 0 0 0 DFC8_RX_DATA_WIDTH [4:0] 0 0 0 0 DFC8_TX_W0 0 0 0 DFC8_TX_DATA_WIDTH [4:0] 0 0 0 0 DFC_STATUS_W0 0 0 0 0 0 0 0 0 DFC_STATUS_W1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFC_DITH_TYPE [1:0] 0000h ADSP2_IRQ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_IRQ2DSP_IRQ1 0000h ADSP2_IRQ1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_IRQ4DSP_IRQ3 0000h ADSP2_IRQ2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_IRQ6DSP_IRQ5 0000h ADSP2_IRQ3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_IRQ8DSP_IRQ7 0000h ADSP2_IRQ4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_ DSP_IRQ9 IRQ10 0000h ADSP2_IRQ5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_ IRQ12 DSP_ IRQ11 0000h ADSP2_IRQ6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_ IRQ14 DSP_ IRQ13 0000h DS1162F1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFC1_ DFC1_ DITH_ENA ENA 0000h 0 DFC1_RX_DATA_TYPE [2:0] 1F00h 0 DFC1_TX_DATA_TYPE [2:0] 1F00h DFC2_ DFC2_ DITH_ENA ENA 0000h 0 DFC2_RX_DATA_TYPE [2:0] 1F00h 0 DFC2_TX_DATA_TYPE [2:0] 1F00h DFC3_ DFC3_ DITH_ENA ENA 0000h 0 DFC3_RX_DATA_TYPE [2:0] 1F00h 0 DFC3_TX_DATA_TYPE [2:0] 1F00h DFC4_ DFC4_ DITH_ENA ENA 0000h 0 DFC4_RX_DATA_TYPE [2:0] 1F00h 0 DFC4_TX_DATA_TYPE [2:0] 1F00h DFC5_ DFC5_ DITH_ENA ENA 0000h 0 DFC5_RX_DATA_TYPE [2:0] 1F00h 0 DFC5_TX_DATA_TYPE [2:0] 1F00h DFC6_ DFC6_ DITH_ENA ENA 0000h 0 DFC6_RX_DATA_TYPE [2:0] 1F00h 0 DFC6_TX_DATA_TYPE [2:0] 1F00h DFC7_ DFC7_ DITH_ENA ENA 0000h 0 DFC7_RX_DATA_TYPE [2:0] 1F00h 0 DFC7_TX_DATA_TYPE [2:0] 1F00h DFC8_ DFC8_ DITH_ENA ENA 0000h 0 DFC8_RX_DATA_TYPE [2:0] 1F00h 0 DFC8_TX_DATA_TYPE [2:0] 1F00h DFC1_RATE [4:0] 0 DFC2_RATE [4:0] 0 DFC3_RATE [4:0] 0 DFC4_RATE [4:0] 0 DFC5_RATE [4:0] 0 DFC6_RATE [4:0] 0 DFC7_RATE [4:0] 0 DFC8_RATE [4:0] 0000h DFC_ERR_CHAN [7:0] 305 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register R5639 (1607h) R5888 (1700h) R5889 (1701h) R5890 (1702h) R5891 (1703h) R5892 (1704h) R5893 (1705h) R5894 (1706h) R5895 (1707h) R5896 (1708h) R5897 (1709h) R5898 (170Ah) R5899 (170Bh) R5900 (170Ch) R5901 (170Dh) R5902 (170Eh) R5903 (170Fh) R5904 (1710h) R5905 (1711h) R5906 (1712h) R5907 (1713h) R5908 (1714h) R5909 (1715h) R5910 (1716h) R5911 (1717h) R5912 (1718h) R5913 (1719h) R5914 (171Ah) R5915 (171Bh) R5916 (171Ch) R5917 (171Dh) R5918 (171Eh) R5919 (171Fh) R6144 (1800h) Name ADSP2_IRQ7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_ IRQ16 DSP_ IRQ15 GPIO1_CTRL_1 GP1_LVL GP1_OP_ GP1_DB GP1_POL CFG 0 0 GPIO1_CTRL_2 GP1_DIR GP1_PU GP1_PD GP1_ DRV_STR 0 0 GPIO2_CTRL_1 GP2_LVL GP2_OP_ GP2_DB GP2_POL CFG 0 0 GPIO2_CTRL_2 GP2_DIR GP2_PU GP2_PD GP2_ DRV_STR 0 0 GPIO3_CTRL_1 GP3_LVL GP3_OP_ GP3_DB GP3_POL CFG 0 0 GPIO3_CTRL_2 GP3_DIR GP3_PU GP3_PD GP3_ DRV_STR 0 0 GPIO4_CTRL_1 GP4_LVL GP4_OP_ GP4_DB GP4_POL CFG 0 0 GPIO4_CTRL_2 GP4_DIR GP4_PU GP4_PD GP4_ DRV_STR 0 0 GPIO5_CTRL_1 GP5_LVL GP5_OP_ GP5_DB GP5_POL CFG 0 0 GPIO5_CTRL_2 GP5_DIR GP5_PU GP5_PD GP5_ DRV_STR 0 0 GPIO6_CTRL_1 GP6_LVL GP6_OP_ GP6_DB GP6_POL CFG 0 0 GPIO6_CTRL_2 GP6_DIR GP6_PU GP6_PD GP6_ DRV_STR 0 0 GPIO7_CTRL_1 GP7_LVL GP7_OP_ GP7_DB GP7_POL CFG 0 0 GPIO7_CTRL_2 GP7_DIR GP7_PU GP7_PD GP7_ DRV_STR 0 0 GPIO8_CTRL_1 GP8_LVL GP8_OP_ GP8_DB GP8_POL CFG 0 0 GPIO8_CTRL_2 GP8_DIR GP8_PU GP8_PD GP8_ DRV_STR 0 0 GPIO9_CTRL_1 GP9_LVL GP9_OP_ GP9_DB GP9_POL CFG 0 0 GPIO9_CTRL_2 GP9_DIR GP9_PU GP9_PD GP9_ DRV_STR 0 0 GPIO10_CTRL_1 GP10_LVL GP10_ GP10_DB OP_CFG GP10_ POL 0 0 GPIO10_CTRL_2 GP10_DIR GP10_PU GP10_PD GP10_ DRV_STR 0 0 GPIO11_CTRL_1 GP11_LVL GP11_OP_ GP11_DB GP11_POL CFG 0 0 GPIO11_CTRL_2 GP11_DIR GP11_PU GP11_PD GP11_ DRV_STR 0 0 GPIO12_CTRL_1 GP12_LVL GP12_ GP12_DB OP_CFG GP12_ POL 0 0 GPIO12_CTRL_2 GP12_DIR GP12_PU GP12_PD GP12_ DRV_STR 0 0 GPIO13_CTRL_1 GP13_LVL GP13_ GP13_DB OP_CFG GP13_ POL 0 0 GPIO13_CTRL_2 GP13_DIR GP13_PU GP13_PD GP13_ DRV_STR 0 0 GPIO14_CTRL_1 GP14_LVL GP14_ GP14_DB OP_CFG GP14_ POL 0 0 GPIO14_CTRL_2 GP14_DIR GP14_PU GP14_PD GP14_ DRV_STR 0 0 GPIO15_CTRL_1 GP15_LVL GP15_ GP15_DB OP_CFG GP15_ POL 0 0 GPIO15_CTRL_2 GP15_DIR GP15_PU GP15_PD GP15_ DRV_STR 0 0 GPIO16_CTRL_1 GP16_LVL GP16_ GP16_DB OP_CFG GP16_ POL 0 0 GPIO16_CTRL_2 GP16_DIR GP16_PU GP16_PD GP16_ DRV_STR 0 0 CTRLIF_ ERR_ EINT1 CLK_ CLK_SYS_ ASYNC_ ERR_ ERR_ EINT1 EINT1 0 0 0 0 0 0 0 0 IRQ1_Status_1 0 0 R6145 IRQ1_Status_2 (1801h) 0 0 R6149 IRQ1_Status_6 (1805h) R6150 IRQ1_Status_7 (1806h) 0 0 0 0 306 0 0 0 MICD_ MICD_ CLAMP2_ CLAMP2_ FALL_ RISE_ EINT1 EINT1 2001h GP1_FN [9:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F000h 2001h GP15_FN [9:0] 0 F000h 2001h GP14_FN [9:0] 0 F000h 2001h GP13_FN [9:0] 0 F000h 2001h GP12_FN [9:0] 0 F000h 2001h GP11_FN [9:0] 0 F000h 2001h GP10_FN [9:0] 0 F000h 2001h GP9_FN [9:0] 0 F000h 2001h GP8_FN [9:0] 0 F000h 2001h GP7_FN [9:0] 0 F000h 2001h GP6_FN [9:0] 0 F000h 2001h GP5_FN [9:0] 0 F000h 2001h GP4_FN [9:0] 0 F000h 2001h GP3_FN [9:0] 0 F000h 2001h GP2_FN [9:0] 0 Default 0000h 0 0 0 0 F000h 2001h GP16_FN [9:0] 0 0 0 0 0 0 0 0 F000h SYSCLK_ 0 FAIL_ EINT1 FLL2_ FLL1_ LOCK_ LOCK_ EINT1 EINT1 BOOT_ DONE_ EINT1 0 0 0 0 0 0 0 0 0000h 0 0 0 0 0000h 0 FLL1_ REF_ LOST_ EINT1 0 0 MICDET2_ MICDET1_ EINT1 EINT1 FLL2_ REF_ LOST_ EINT1 0 0 0 0 0 HPDET_ EINT1 0000h 0 0 JD2_ FALL_ EINT1 JD2_ RISE_ EINT1 JD1_ FALL_ EINT1 JD1_ RISE_ EINT1 0000h 0 JD3_ FALL_ EINT1 0 JD3_ RISE_ EINT1 MICD_ MICD_ CLAMP1_ CLAMP1_ FALL_ RISE_ EINT1 EINT1 DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register Name R6152 IRQ1_Status_9 (1808h) 15 14 13 12 11 10 0 0 0 0 0 0 9 8 R6154 IRQ1_Status_11 (180Ah) DSP_ IRQ16_ EINT1 0 DSP_ IRQ15_ EINT1 0 DSP_ IRQ14_ EINT1 0 DSP_ IRQ13_ EINT1 0 DSP_ IRQ12_ EINT1 0 0 0 0 0 0 0 0 0 R6157 IRQ1_Status_14 (180Dh) 0 0 0 0 0 0 0 R6158 IRQ1_Status_15 (180Eh) 0 0 0 0 0 R6160 IRQ1_Status_17 (1810h) R6164 IRQ1_Status_21 (1814h) R6165 IRQ1_Status_22 (1815h) GP16_ EINT1 GP15_ EINT1 GP12_ EINT1 0 0 0 0 0 0 0 R6166 IRQ1_Status_23 (1816h) 0 0 R6167 IRQ1_Status_24 (1817h) 0 R6168 IRQ1_Status_25 (1818h) 7 ASRC1_ ASRC1_ 0 IN2_ IN1_ LOCK_ LOCK_ EINT1 EINT1 DSP_ DSP_ DSP_ DSP_ IRQ11_ IRQ10_ IRQ9_ IRQ8_ EINT1 EINT1 EINT1 EINT1 0 HP4R_ HP4L_SC_ 0 SC_EINT1 EINT1 6 5 4 3 0 0 0 0 2 1 0 INPUTS_ DRC2_ DRC1_ SIG_DET_ SIG_DET_ SIG_DET_ EINT1 EINT1 EINT1 Default 0000h DSP_ IRQ7_ EINT1 0 DSP_ DSP_ DSP_ DSP_ DSP_ DSP_ IRQ6_ IRQ5_ IRQ4_ IRQ3_ IRQ2_ IRQ1_ EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 HP3R_ HP3L_SC_ HP2R_ HP2L_SC_ HP1R_ HP1L_SC_ SC_EINT1 EINT1 SC_EINT1 EINT1 SC_EINT1 EINT1 0000h 0 0 0000h 0 0 0 0 0 0 0 HP3R_ HP3L_ HP2R_ HP2L_ HP1R_ HP1L_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ DONE_ DONE_ DONE_ DONE_ DONE_ DONE_ EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 HP3R_ HP3L_ HP2R_ HP2L_ HP1R_ HP1L_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DONE_ DONE_ DONE_ DONE_ DONE_ DONE_ EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 0 0 0 0 0 0 GP11_ EINT1 GP10_ EINT1 GP9_ EINT1 GP8_ EINT1 GP7_ EINT1 GP6_ EINT1 GP5_ EINT1 GP4_ EINT1 GP3_ EINT1 GP2_ EINT1 GP1_ EINT1 0000h 0 0 0 0 0 0 0 0 0 0 0 TIMER1_ EINT1 0000h 0 0 0 0 0 0 0 0 0 0 0 0 0000h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6170 IRQ1_Status_27 (181Ah) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6171 IRQ1_Status_28 (181Bh) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6173 IRQ1_Status_30 (181Dh) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6176 IRQ1_Status_33 (1820h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6179 IRQ1_Status_36 (1823h) 0 0 0 0 0 0 0 0 0 0 0 0 R6183 IRQ1_Status_40 (1827h) 0 0 0 0 0 0 0 0 0 TIMER_ ALM1_ CH3_ EINT1 0 R6208 IRQ1_Mask_1 (1840h) 0 0 0 0 0 0 0 0 0 0 0 0 1200h R6209 IRQ1_Mask_2 (1841h) 0 1 0 0 FLL2_ SYNC_ ACTIVE_ EINT1 IM_ SYSCLK_ FAIL_ EINT1 IM_FLL2_ LOCK_ EINT1 TIMER_ ALM1_ CH4_ EINT1 0 EVENT1_ NOT_ EMPTY_ EINT1 0 EVENT1_ FULL_ EINT1 0 EVENT1_ WMARK_ EINT1 0 DSP1_ DMA_ EINT1 0 DSP1_ START1_ EINT1 0 DSP1_ START2_ EINT1 0 DSP1_ BUSY_ EINT1 0 DSP1_ BUS_ ERR_ EINT1 TIMER_ TIMER_ ALM1_ ALM1_ CH2_ CH1_ EINT1 EINT1 0 0 0 0 0 0 0 77E0h R6213 IRQ1_Mask_6 (1845h) 0 0 0 0 R6155 IRQ1_Status_12 (180Bh) R6156 IRQ1_Status_13 (180Ch) R6214 IRQ1_Mask_7 (1846h) R6216 IRQ1_Mask_9 (1848h) R6218 IRQ1_Mask_11 (184Ah) R6219 IRQ1_Mask_12 (184Bh) R6220 IRQ1_Mask_13 (184Ch) DFC_ SATURAT E_EINT1 GP14_ GP13_ EINT1 EINT1 IM_ CTRLIF_ ERR_ EINT1 IM_CLK_ IM_CLK_ ASYNC_ SYS_ ERR_ ERR_ EINT1 EINT1 0 0 FLL1_ 0 SYNC_ ACTIVE_ EINT1 0 IM_BOOT_ DONE_ EINT1 IM_FLL1_ LOCK_ EINT1 0 IM_FLL2_ IM_FLL1_ REF_ REF_ LOST_ LOST_ EINT1 EINT1 0 0 IM_ IM_ 0 0 0 0 0 IM_ MICDET2_ MICDET1_ HPDET_ EINT1 EINT1 EINT1 0 0 0 0 IM_MICD_ IM_MICD_ IM_JD3_ IM_JD3_ 0 0 IM_MICD_ IM_MICD_ IM_JD2_ IM_JD2_ IM_JD1_ IM_JD1_ CLAMP2_ CLAMP2_ FALL_ RISE_ CLAMP1_ CLAMP1_ FALL_ RISE_ FALL_ RISE_ FALL_ RISE_ EINT1 EINT1 FALL_ RISE_ EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 0 0 0 0 0 0 IM_ IM_ 0 0 0 1 1 IM_ IM_DRC2_ IM_DRC1_ ASRC1_ ASRC1_ INPUTS_ SIG_DET_ SIG_DET_ IN2_ IN1_ SIG_DET_ EINT1 EINT1 LOCK_ LOCK_ EINT1 EINT1 EINT1 IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IRQ16_ IRQ15_ IRQ14_ IRQ13_ IRQ12_ IRQ11_ IRQ10_ IRQ9_ IRQ8_ IRQ7_ IRQ6_ IRQ5_ IRQ4_ IRQ3_ IRQ2_ IRQ1_ EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 0 0 0 0 0 0 IM_HP4R_ IM_HP4L_ 0 0 IM_HP3R_ IM_HP3L_ IM_HP2R_ IM_HP2L_ IM_HP1R_ IM_HP1L_ SC_EINT1 SC_EINT1 SC_EINT1 SC_EINT1 SC_EINT1 SC_EINT1 SC_EINT1 SC_EINT1 0 0 0 0 0 0 0 0 0 0 R6221 IRQ1_Mask_14 (184Dh) 0 0 0 0 0 0 0 0 0 0 R6222 IRQ1_Mask_15 (184Eh) 0 0 0 IM_DFC_ SATURAT E_EINT1 0 0 0 0 0 0 DS1162F1 IM_HP3R_ IM_HP3L_ IM_HP2R_ IM_HP2L_ IM_HP1R_ IM_HP1L_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ DONE_ DONE_ DONE_ DONE_ DONE_ DONE_ EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 IM_HP3R_ IM_HP3L_ IM_HP2R_ IM_HP2L_ IM_HP1R_ IM_HP1L_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DONE_ DONE_ DONE_ DONE_ DONE_ DONE_ EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 0 0 0 0 0 0 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0301h 0F3Fh 031Fh FFFFh 033Fh 003Fh 003Fh 1000h 307 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register Name R6224 IRQ1_Mask_17 (1850h) R6228 IRQ1_Mask_21 (1854h) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IM_GP16_ IM_GP15_ IM_GP14_ IM_GP13_ IM_GP12_ IM_GP11_ IM_GP10_ IM_GP9_ IM_GP8_ IM_GP7_ IM_GP6_ IM_GP5_ IM_GP4_ IM_GP3_ IM_GP2_ IM_GP1_ EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 EINT1 0 0 0 0 0 0 0 0 0 0 0 0 0 R6229 IRQ1_Mask_22 (1855h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6230 IRQ1_Mask_23 (1856h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6231 IRQ1_Mask_24 (1857h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6232 IRQ1_Mask_25 (1858h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6234 IRQ1_Mask_27 (185Ah) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6235 IRQ1_Mask_28 (185Bh) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6237 IRQ1_Mask_30 (185Dh) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6240 IRQ1_Mask_33 (1860h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6243 IRQ1_Mask_36 (1863h) 0 0 0 0 0 0 0 0 0 0 0 0 R6247 IRQ1_Mask_40 (1867h) 0 0 0 0 0 0 0 0 0 IM_ TIMER_ ALM1_ CH4_ EINT1 0 IM_ TIMER_ ALM1_ CH3_ EINT1 0 R6272 IRQ1_Raw_Status_1 (1880h) 0 0 0 0 0 0 0 0 0 0 0 0 0000h R6273 IRQ1_Raw_Status_2 (1881h) 0 0 0 0 0 0 0 0 0 0000h R6278 IRQ1_Raw_Status_7 (1886h) 0 0 0 0 FLL1_ REF_ LOST_ STS1 0 0 JD2_STS1 0 JD1_STS1 0000h R6280 IRQ1_Raw_Status_9 (1888h) 0 0 0 0 0 0 0 MICD_ CLAMP_ STS1 0 0 INPUTS_ DRC2_ DRC1_ SIG_DET_ SIG_DET_ SIG_DET_ STS1 STS1 STS1 0000h R6283 IRQ1_Raw_Status_12 (188Bh) R6284 IRQ1_Raw_Status_13 (188Ch) 0 0 0 0 0 0 HP3R_ HP3L_SC_ HP2R_ HP2L_SC_ HP1R_ HP1L_SC_ SC_STS1 STS1 SC_STS1 STS1 SC_STS1 STS1 0000h 0 0 0 0 0 0 0000h R6285 IRQ1_Raw_Status_14 (188Dh) 0 0 0 0 0 0 R6288 IRQ1_Raw_Status_17 (1890h) R6292 IRQ1_Raw_Status_21 (1894h) R6293 IRQ1_Raw_Status_22 (1895h) GP16_ STS1 GP15_ STS1 GP14_ STS1 GP13_ STS1 GP12_ STS1 GP11_ STS1 HP3R_ HP3L_ HP2R_ HP2L_ HP1R_ HP1L_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ DONE_ DONE_ DONE_ DONE_ DONE_ DONE_ STS1 STS1 STS1 STS1 STS1 STS1 0 0 0 0 HP3R_ HP3L_ HP2R_ HP2L_ HP1R_ HP1L_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DONE_ DONE_ DONE_ DONE_ DONE_ DONE_ STS1 STS1 STS1 STS1 STS1 STS1 GP10_ GP9_STS1GP8_STS1GP7_STS1GP6_STS1GP5_STS1GP4_STS1GP3_STS1GP2_STS1GP1_STS1 STS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6294 IRQ1_Raw_Status_23 (1896h) 0 0 0 0 0 0 0 0 0 0 0 0 R6295 IRQ1_Raw_Status_24 (1897h) 0 0 0 0 0 0 0 0 0 0 0 0 R6296 IRQ1_Raw_Status_25 (1898h) 0 0 0 0 0 0 0 0 0 0 0 0 R6301 IRQ1_Raw_Status_30 (189Dh) 0 0 0 0 0 0 0 0 0 0 0 0 R6304 IRQ1_Raw_Status_33 (18A0h) 0 0 0 0 0 0 0 0 0 0 0 0 R6307 IRQ1_Raw_Status_36 (18A3h) 0 0 0 0 0 0 0 0 0 0 0 0 308 CTRLIF_ ERR_ STS1 CLK_ CLK_SYS_ ASYNC_ ERR_ ERR_ STS1 STS1 0 0 JD3_STS1 0 FLL2_ REF_ LOST_ STS1 0 ASRC1_ ASRC1_ IN2_ IN1_ LOCK_ LOCK_ STS1 STS1 HP4R_ HP4L_SC_ SC_STS1 STS1 0 0 0 0 0 0 0 0 0 IM_ TIMER1_ EINT1 0 IM_ EVENT1_ NOT_ EMPTY_ EINT1 0 IM_ EVENT1_ FULL_ EINT1 0 IM_ EVENT1_ WMARK_ EINT1 0 IM_DSP1_ DMA_ EINT1 0 IM_DSP1_ START1_ EINT1 0 IM_DSP1_ START2_ EINT1 0 IM_DSP1_ BUSY_ EINT1 0 IM_DSP1_ BUS_ ERR_ EINT1 IM_ IM_ TIMER_ TIMER_ ALM1_ ALM1_ CH2_ CH1_ EINT1 EINT1 0 0 0001h 0 IM_FLL2_ IM_FLL1_ 0 SYNC_ SYNC_ ACTIVE_ ACTIVE_ EINT1 EINT1 0 0 BOOT_ DONE_ STS1 FLL2_ FLL1_ 0 LOCK_ LOCK_ STS1 STS1 0 Default FFFFh TIMER1_ STS1 EVENT1_ NOT_ EMPTY_ STS1 0 0 0 EVENT1_ FULL_ STS1 0 0 0 EVENT1_ WMARK_ STS1 0 0 0 DSP1_ DMA_ STS1 0 0 0 DSP1_ BUSY_ STS1 0 0 0 DSP1_ BUS_ ERR_ STS1 TIMER_ TIMER_ TIMER_ TIMER_ ALM1_ ALM1_ ALM1_ ALM1_ CH4_STS1CH3_STS1CH2_STS1CH1_STS1 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 000Fh 0300h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register Name R6311 IRQ1_Raw_Status_40 (18A7h) 15 14 13 12 11 10 0 0 0 0 0 0 R6400 IRQ2_Status_1 (1900h) 0 0 0 0 0 R6401 IRQ2_Status_2 (1901h) 0 0 0 0 R6405 IRQ2_Status_6 (1905h) R6406 IRQ2_Status_7 (1906h) 0 0 0 0 0 0 0 0 0 0 R6408 IRQ2_Status_9 (1908h) 0 0 0 0 0 0 R6410 IRQ2_Status_11 (190Ah) DSP_ IRQ16_ EINT2 0 DSP_ IRQ15_ EINT2 0 DSP_ IRQ14_ EINT2 0 DSP_ IRQ13_ EINT2 0 DSP_ IRQ12_ EINT2 0 0 0 0 0 0 0 0 0 R6413 IRQ2_Status_14 (190Dh) 0 0 0 0 0 0 0 R6414 IRQ2_Status_15 (190Eh) 0 0 0 0 0 R6416 IRQ2_Status_17 (1910h) R6420 IRQ2_Status_21 (1914h) R6421 IRQ2_Status_22 (1915h) GP16_ EINT2 GP15_ EINT2 GP12_ EINT2 0 0 0 0 0 0 0 R6422 IRQ2_Status_23 (1916h) 0 0 R6423 IRQ2_Status_24 (1917h) 0 R6424 IRQ2_Status_25 (1918h) CTRLIF_ ERR_ EINT2 CLK_ CLK_SYS_ ASYNC_ ERR_ ERR_ EINT2 EINT2 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Default 0000h 0 0 0 0 0 0 0 0000h FLL1_ REF_ LOST_ EINT2 0 0 0 0 0 0 0000h 0 FLL2_ REF_ LOST_ EINT2 0 0 0 0 0 HPDET_ EINT2 0000h 0 0 JD2_ FALL_ EINT2 JD2_ RISE_ EINT2 JD1_ FALL_ EINT2 JD1_ RISE_ EINT2 0000h FLL2_ FLL1_ 0 SYNC_ SYNC_ ACTIVE_ ACTIVE_ STS1 STS1 SYSCLK_ 0 BOOT_ FAIL_ DONE_ EINT2 EINT2 FLL2_ FLL1_ 0 LOCK_ LOCK_ EINT2 EINT2 MICDET2_ MICDET1_ EINT2 EINT2 JD3_ FALL_ EINT2 JD3_ RISE_ EINT2 MICD_ MICD_ CLAMP_ CLAMP_ FALL_ RISE_ EINT2 EINT2 0 0 INPUTS_ DRC2_ DRC1_ SIG_DET_ SIG_DET_ SIG_DET_ EINT2 EINT2 EINT2 0000h DSP_ IRQ7_ EINT2 0 DSP_ DSP_ DSP_ DSP_ DSP_ DSP_ IRQ6_ IRQ5_ IRQ4_ IRQ3_ IRQ2_ IRQ1_ EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 HP3R_ HP3L_SC_ HP2R_ HP2L_SC_ HP1R_ HP1L_SC_ SC_EINT2 EINT2 SC_EINT2 EINT2 SC_EINT2 EINT2 0000h 0 0 0000h 0 0 0 0 0 0 0 HP3R_ HP3L_ HP2R_ HP2L_ HP1R_ HP1L_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ DONE_ DONE_ DONE_ DONE_ DONE_ DONE_ EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 HP3R_ HP3L_ HP2R_ HP2L_ HP1R_ HP1L_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DONE_ DONE_ DONE_ DONE_ DONE_ DONE_ EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 0 0 0 0 0 0 GP11_ EINT2 GP10_ EINT2 GP9_ EINT2 GP8_ EINT2 GP7_ EINT2 GP6_ EINT2 GP5_ EINT2 GP4_ EINT2 GP3_ EINT2 GP2_ EINT2 GP1_ EINT2 0000h 0 0 0 0 0 0 0 0 0 0 0 TIMER1_ EINT2 0000h 0 0 0 0 0 0 0 0 0 0 0 0 0000h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6426 IRQ2_Status_27 (191Ah) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6427 IRQ2_Status_28 (191Bh) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6429 IRQ2_Status_30 (191Dh) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6432 IRQ2_Status_33 (1920h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6435 IRQ2_Status_36 (1923h) 0 0 0 0 0 0 0 0 0 0 0 0 R6439 IRQ2_Status_40 (1927h) 0 0 0 0 0 0 0 0 0 TIMER_ ALM1_ CH3_ EINT2 0 R6464 IRQ2_Mask_1 (1940h) 0 0 0 0 0 0 0 0 0 0 0 0 1280h R6465 IRQ2_Mask_2 (1941h) 0 1 0 0 FLL2_ SYNC_ ACTIVE_ EINT2 IM_ SYSCLK_ FAIL_ EINT2 IM_FLL2_ LOCK_ EINT2 TIMER_ ALM1_ CH4_ EINT2 0 EVENT1_ NOT_ EMPTY_ EINT2 0 EVENT1_ FULL_ EINT2 0 EVENT1_ WMARK_ EINT2 0 DSP1_ DMA_ EINT2 0 DSP1_ START1_ EINT2 0 DSP1_ START2_ EINT2 0 DSP1_ BUSY_ EINT2 0 DSP1_ BUS_ ERR_ EINT2 TIMER_ TIMER_ ALM1_ ALM1_ CH2_ CH1_ EINT2 EINT2 0 0 0 0 0 0 0 77E0h R6469 IRQ2_Mask_6 (1945h) 0 0 0 0 0 0 0 0 R6470 IRQ2_Mask_7 (1946h) 0 0 0 0 R6411 IRQ2_Status_12 (190Bh) R6412 IRQ2_Status_13 (190Ch) DS1162F1 DFC_ SATURAT E_EINT2 GP14_ GP13_ EINT2 EINT2 IM_ CTRLIF_ ERR_ EINT2 IM_CLK_ IM_CLK_ ASYNC_ SYS_ ERR_ ERR_ EINT2 EINT2 0 0 0 0 ASRC1_ ASRC1_ 0 IN2_ IN1_ LOCK_ LOCK_ EINT2 EINT2 DSP_ DSP_ DSP_ DSP_ IRQ11_ IRQ10_ IRQ9_ IRQ8_ EINT2 EINT2 EINT2 EINT2 0 HP4R_ HP4L_SC_ 0 SC_EINT2 EINT2 FLL1_ 0 SYNC_ ACTIVE_ EINT2 0 IM_BOOT_ DONE_ EINT2 IM_FLL1_ LOCK_ EINT2 0 IM_ IM_ MICDET2_ MICDET1_ EINT2 EINT2 IM_JD3_ IM_JD3_ FALL_ RISE_ EINT2 EINT2 0 0 0 IM_FLL2_ IM_FLL1_ REF_ REF_ LOST_ LOST_ EINT2 EINT2 0 0 0 0 IM_ HPDET_ EINT2 IM_MICD_ IM_MICD_ IM_JD2_ IM_JD2_ IM_JD1_ IM_JD1_ CLAMP_ CLAMP_ FALL_ RISE_ FALL_ RISE_ FALL_ RISE_ EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0301h 033Fh 309 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register Name R6472 IRQ2_Mask_9 (1948h) R6474 IRQ2_Mask_11 (194Ah) R6475 IRQ2_Mask_12 (194Bh) R6476 IRQ2_Mask_13 (194Ch) 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 0 0 0 0 0 0 0 0 0 0 R6477 IRQ2_Mask_14 (194Dh) 0 0 0 0 0 0 0 0 0 0 R6478 IRQ2_Mask_15 (194Eh) 0 0 0 R6480 IRQ2_Mask_17 (1950h) R6484 IRQ2_Mask_21 (1954h) 5 4 3 2 1 0 IM_ IM_ 0 0 0 1 1 IM_ IM_DRC2_ IM_DRC1_ ASRC1_ ASRC1_ INPUTS_ SIG_DET_ SIG_DET_ IN2_ IN1_ SIG_DET_ EINT2 EINT2 LOCK_ LOCK_ EINT2 EINT2 EINT2 IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IRQ16_ IRQ15_ IRQ14_ IRQ13_ IRQ12_ IRQ11_ IRQ10_ IRQ9_ IRQ8_ IRQ7_ IRQ6_ IRQ5_ IRQ4_ IRQ3_ IRQ2_ IRQ1_ EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 0 0 0 0 0 0 IM_HP4R_ IM_HP4L_ 0 0 IM_HP3R_ IM_HP3L_ IM_HP2R_ IM_HP2L_ IM_HP1R_ IM_HP1L_ SC_EINT2 SC_EINT2 SC_EINT2 SC_EINT2 SC_EINT2 SC_EINT2 SC_EINT2 SC_EINT2 IM_HP3R_ IM_HP3L_ IM_HP2R_ IM_HP2L_ IM_HP1R_ IM_HP1L_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ DONE_ DONE_ DONE_ DONE_ DONE_ DONE_ EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 IM_HP3R_ IM_HP3L_ IM_HP2R_ IM_HP2L_ IM_HP1R_ IM_HP1L_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DONE_ DONE_ DONE_ DONE_ DONE_ DONE_ EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 0 0 0 0 0 0 IM_DFC_ 0 0 0 0 0 0 SATURAT E_EINT2 IM_GP16_ IM_GP15_ IM_GP14_ IM_GP13_ IM_GP12_ IM_GP11_ IM_GP10_ IM_GP9_ IM_GP8_ IM_GP7_ IM_GP6_ IM_GP5_ IM_GP4_ IM_GP3_ IM_GP2_ IM_GP1_ EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 EINT2 033Fh 003Fh 003Fh 1000h FFFFh 0001h 0 0 0 0 0 0 0 0 0 0 0 0 0 R6485 IRQ2_Mask_22 (1955h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6486 IRQ2_Mask_23 (1956h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6487 IRQ2_Mask_24 (1957h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6488 IRQ2_Mask_25 (1958h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6490 IRQ2_Mask_27 (195Ah) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6491 IRQ2_Mask_28 (195Bh) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6493 IRQ2_Mask_30 (195Dh) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6496 IRQ2_Mask_33 (1960h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6499 IRQ2_Mask_36 (1963h) 0 0 0 0 0 0 0 0 0 0 0 0 R6503 IRQ2_Mask_40 (1967h) 0 0 0 0 0 0 0 0 0 IM_ TIMER_ ALM1_ CH4_ EINT2 0 IM_ TIMER_ ALM1_ CH3_ EINT2 0 R6528 IRQ2_Raw_Status_1 (1980h) 0 0 0 0 0 0 0 0 0 0 0 0 0000h R6529 IRQ2_Raw_Status_2 (1981h) 0 0 0 0 0 0 0 0 0 0000h R6534 IRQ2_Raw_Status_7 (1986h) 0 0 0 0 FLL1_ REF_ LOST_ STS2 0 0 JD2_STS2 0 JD1_STS2 0000h R6536 IRQ2_Raw_Status_9 (1988h) 0 0 0 0 0 0 0 MICD_ CLAMP_ STS2 0 0 INPUTS_ DRC2_ DRC1_ SIG_DET_ SIG_DET_ SIG_DET_ STS2 STS2 STS2 0000h R6539 IRQ2_Raw_Status_12 (198Bh) R6540 IRQ2_Raw_Status_13 (198Ch) 0 0 0 0 0 0 HP3R_ HP3L_SC_ HP2R_ HP2L_SC_ HP1R_ HP1L_SC_ SC_STS2 STS2 SC_STS2 STS2 SC_STS2 STS2 0000h 0 0 0 0 0 0 0000h R6541 IRQ2_Raw_Status_14 (198Dh) 0 0 0 0 0 0 R6544 IRQ2_Raw_Status_17 (1990h) R6548 IRQ2_Raw_Status_21 (1994h) GP16_ STS2 GP15_ STS2 GP14_ STS2 GP13_ STS2 GP12_ STS2 GP11_ STS2 HP3R_ HP3L_ HP2R_ HP2L_ HP1R_ HP1L_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ ENABLE_ DONE_ DONE_ DONE_ DONE_ DONE_ DONE_ STS2 STS2 STS2 STS2 STS2 STS2 0 0 0 0 HP3R_ HP3L_ HP2R_ HP2L_ HP1R_ HP1L_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DISABLE_ DONE_ DONE_ DONE_ DONE_ DONE_ DONE_ STS2 STS2 STS2 STS2 STS2 STS2 GP10_ GP9_STS2GP8_STS2GP7_STS2GP6_STS2GP5_STS2GP4_STS2GP3_STS2GP2_STS2GP1_STS2 STS2 0 0 0 0 0 0 310 CTRLIF_ ERR_ STS2 CLK_ CLK_SYS_ ASYNC_ ERR_ ERR_ STS2 STS2 0 0 JD3_STS2 0 FLL2_ REF_ LOST_ STS2 0 ASRC1_ ASRC1_ IN2_ IN1_ LOCK_ LOCK_ STS2 STS2 HP4R_ HP4L_SC_ SC_STS2 STS2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM_ TIMER1_ EINT2 0 IM_ EVENT1_ NOT_ EMPTY_ EINT2 0 IM_ EVENT1_ FULL_ EINT2 0 IM_ EVENT1_ WMARK_ EINT2 0 IM_DSP1_ DMA_ EINT2 0 IM_DSP1_ START1_ EINT2 0 IM_DSP1_ START2_ EINT2 0 IM_DSP1_ BUSY_ EINT2 0 IM_DSP1_ BUS_ ERR_ EINT2 IM_ IM_ TIMER_ TIMER_ ALM1_ ALM1_ CH2_ CH1_ EINT2 EINT2 0 0 FFFFh 0 IM_FLL2_ IM_FLL1_ 0 SYNC_ SYNC_ ACTIVE_ ACTIVE_ EINT2 EINT2 0 0 BOOT_ DONE_ STS2 FLL2_ FLL1_ 0 LOCK_ LOCK_ STS2 STS2 0 Default 031Fh 0 TIMER1_ STS2 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 000Fh 0300h 0000h 0000h 0000h DS1162F1 CS42L92 6 Register Map Table 6-1. Register Map Definition—16-bit region (Cont.) Register Name R6549 IRQ2_Raw_Status_22 (1995h) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6550 IRQ2_Raw_Status_23 (1996h) 0 0 0 0 0 0 0 0 0 0 0 0 R6551 IRQ2_Raw_Status_24 (1997h) 0 0 0 0 0 0 0 0 0 0 0 0 R6552 IRQ2_Raw_Status_25 (1998h) 0 0 0 0 0 0 0 0 0 0 0 0 R6557 IRQ2_Raw_Status_30 (199Dh) 0 0 0 0 0 0 0 0 0 0 0 0 R6560 IRQ2_Raw_Status_33 (19A0h) 0 0 0 0 0 0 0 0 0 0 0 0 R6563 IRQ2_Raw_Status_36 (19A3h) 0 0 0 0 0 0 0 0 0 0 0 0 R6567 IRQ2_Raw_Status_40 (19A7h) 0 0 0 0 0 0 0 0 0 0 R6662 Interrupt_Debounce_7 (1A06h) 0 0 0 0 0 0 0 0 0 0 JD2_DB 0 JD1_DB 0000h R6784 (1A80h) R6786 (1A82h) R6816 (1AA0h) R6848 (1AC0h) R6864 (1AD0h) IRQ1_CTRL 0 1 0 0 IM_IRQ1 IRQ_POL IRQ_OP_ CFG 0 0 0 0 MICD_ CLAMP_ DB 0 0 0 0 0 4400h IRQ2_CTRL 0 0 0 0 IM_IRQ2 0 0 0 0 0 0 0 0 0 0 0 0000h Interrupt_Raw_Status_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_Debounce_Config 0 0 0 0 0 0 0 0 0 0 0 0 AOD_Pad_Ctrl 0 1 0 0 0 0 0 0 0 0 0 0 0 0 20 4 19 3 18 2 FLL2_ FLL1_ SYNC_ SYNC_ ACTIVE_ ACTIVE_ STS2 STS2 0 JD3_DB 0 EVENT1_ NOT_ EMPTY_ STS2 0 0 0 EVENT1_ FULL_ STS2 0 0 0 EVENT1_ WMARK_ STS2 0 0 0 DSP1_ DMA_ STS2 0 0 0 DSP1_ BUSY_ STS2 0 0 0 DSP1_ BUS_ ERR_ STS2 TIMER_ TIMER_ TIMER_ TIMER_ ALM1_ ALM1_ ALM1_ ALM1_ CH4_STS2CH3_STS2CH2_STS2CH1_STS2 0 0 0 0 IRQ2_STS IRQ1_STS Default 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h GP_DBTIME [3:0] RESET_ RESET_ PU PD 4002h The 32-bit register space is described in Table 6-2. Table 6-2. Register Map Definition—32-bit region Register Name R12288 WSEQ_Sequence_1 (3000h) R12290 WSEQ_Sequence_2 (3002h) R12292 WSEQ_Sequence_3 (3004h) R12294 WSEQ_Sequence_4 (3006h) R12296 WSEQ_Sequence_5 (3008h) R12298 WSEQ_Sequence_6 (300Ah) R12300 WSEQ_Sequence_7 (300Ch) R12302 WSEQ_Sequence_8 (300Eh) R12304 WSEQ_Sequence_9 (3010h) R12306 WSEQ_Sequence_10 (3012h) R12308 WSEQ_Sequence_11 (3014h) R12310 WSEQ_Sequence_12 (3016h) R12312 WSEQ_Sequence_13 (3018h) R12314 WSEQ_Sequence_14 (301Ah) R12316 WSEQ_Sequence_15 (301Ch) R12318 WSEQ_Sequence_16 (301Eh) DS1162F1 31 15 30 14 29 13 WSEQ_DATA_WIDTH0 [2:0] WSEQ_DELAY0 [3:0] WSEQ_DATA_WIDTH1 [2:0] WSEQ_DELAY1 [3:0] WSEQ_DATA_WIDTH2 [2:0] WSEQ_DELAY2 [3:0] WSEQ_DATA_WIDTH3 [2:0] WSEQ_DELAY3 [3:0] WSEQ_DATA_WIDTH4 [2:0] WSEQ_DELAY4 [3:0] WSEQ_DATA_WIDTH5 [2:0] WSEQ_DELAY5 [3:0] WSEQ_DATA_WIDTH6 [2:0] WSEQ_DELAY6 [3:0] WSEQ_DATA_WIDTH7 [2:0] WSEQ_DELAY7 [3:0] WSEQ_DATA_WIDTH8 [2:0] WSEQ_DELAY8 [3:0] WSEQ_DATA_WIDTH9 [2:0] WSEQ_DELAY9 [3:0] WSEQ_DATA_WIDTH10 [2:0] WSEQ_DELAY10 [3:0] WSEQ_DATA_WIDTH11 [2:0] WSEQ_DELAY11 [3:0] WSEQ_DATA_WIDTH12 [2:0] WSEQ_DELAY12 [3:0] WSEQ_DATA_WIDTH13 [2:0] WSEQ_DELAY13 [3:0] WSEQ_DATA_WIDTH14 [2:0] WSEQ_DELAY14 [3:0] WSEQ_DATA_WIDTH15 [2:0] WSEQ_DELAY15 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 Default WSEQ_DATA0 [7:0] 0000F000h WSEQ_ADDR1 [12:0] WSEQ_DATA_START1 [3:0] WSEQ_DATA1 [7:0] 0000F000h WSEQ_ADDR2 [12:0] WSEQ_DATA_START2 [3:0] WSEQ_DATA2 [7:0] 0000F000h WSEQ_ADDR3 [12:0] WSEQ_DATA_START3 [3:0] WSEQ_DATA3 [7:0] 82253719h WSEQ_ADDR4 [12:0] WSEQ_DATA_START4 [3:0] WSEQ_DATA4 [7:0] C2300001h WSEQ_ADDR5 [12:0] WSEQ_DATA_START5 [3:0] WSEQ_DATA5 [7:0] 02251301h WSEQ_ADDR6 [12:0] WSEQ_DATA_START6 [3:0] WSEQ_DATA6 [7:0] 8225191Fh WSEQ_ADDR7 [12:0] WSEQ_DATA_START7 [3:0] WSEQ_DATA7 [7:0] 82310B00h WSEQ_ADDR8 [12:0] WSEQ_DATA_START8 [3:0] WSEQ_DATA8 [7:0] E231023Bh WSEQ_ADDR9 [12:0] WSEQ_DATA_START9 [3:0] WSEQ_DATA9 [7:0] 02313B01h WSEQ_ADDR10 [12:0] WSEQ_DATA_START10 [3:0] WSEQ_DATA10 [7:0] 62300000h WSEQ_ADDR11 [12:0] WSEQ_DATA_START11 [3:0] WSEQ_DATA11 [7:0] E2314288h WSEQ_ADDR12 [12:0] WSEQ_DATA_START12 [3:0] WSEQ_DATA12 [7:0] 02310B00h WSEQ_ADDR13 [12:0] WSEQ_DATA_START13 [3:0] WSEQ_DATA13 [7:0] 02310B00h WSEQ_ADDR14 [12:0] WSEQ_DATA_START14 [3:0] WSEQ_DATA14 [7:0] 02250E01h WSEQ_ADDR15 [12:0] WSEQ_DATA_START15 [3:0] 16 0 0000F000h WSEQ_ADDR0 [12:0] WSEQ_DATA_START0 [3:0] 17 1 WSEQ_DATA15 [7:0] 311 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R12320 WSEQ_Sequence_17 (3020h) R12322 WSEQ_Sequence_18 (3022h) R12324 WSEQ_Sequence_19 (3024h) R12326 WSEQ_Sequence_20 (3026h) R12328 WSEQ_Sequence_21 (3028h) R12330 WSEQ_Sequence_22 (302Ah) R12332 WSEQ_Sequence_23 (302Ch) R12334 WSEQ_Sequence_24 (302Eh) R12336 WSEQ_Sequence_25 (3030h) R12338 WSEQ_Sequence_26 (3032h) R12340 WSEQ_Sequence_27 (3034h) R12342 WSEQ_Sequence_28 (3036h) R12344 WSEQ_Sequence_29 (3038h) R12346 WSEQ_Sequence_30 (303Ah) R12348 WSEQ_Sequence_31 (303Ch) R12350 WSEQ_Sequence_32 (303Eh) R12352 WSEQ_Sequence_33 (3040h) R12354 WSEQ_Sequence_34 (3042h) R12356 WSEQ_Sequence_35 (3044h) R12358 WSEQ_Sequence_36 (3046h) R12360 WSEQ_Sequence_37 (3048h) R12362 WSEQ_Sequence_38 (304Ah) R12364 WSEQ_Sequence_39 (304Ch) R12366 WSEQ_Sequence_40 (304Eh) R12368 WSEQ_Sequence_41 (3050h) R12370 WSEQ_Sequence_42 (3052h) R12372 WSEQ_Sequence_43 (3054h) R12374 WSEQ_Sequence_44 (3056h) R12376 WSEQ_Sequence_45 (3058h) R12378 WSEQ_Sequence_46 (305Ah) R12380 WSEQ_Sequence_47 (305Ch) R12382 WSEQ_Sequence_48 (305Eh) R12384 WSEQ_Sequence_49 (3060h) R12386 WSEQ_Sequence_50 (3062h) R12388 WSEQ_Sequence_51 (3064h) R12390 WSEQ_Sequence_52 (3066h) 312 31 15 30 14 29 13 WSEQ_DATA_WIDTH16 [2:0] WSEQ_DELAY16 [3:0] WSEQ_DATA_WIDTH17 [2:0] WSEQ_DELAY17 [3:0] WSEQ_DATA_WIDTH18 [2:0] WSEQ_DELAY18 [3:0] WSEQ_DATA_WIDTH19 [2:0] WSEQ_DELAY19 [3:0] WSEQ_DATA_WIDTH20 [2:0] WSEQ_DELAY20 [3:0] WSEQ_DATA_WIDTH21 [2:0] WSEQ_DELAY21 [3:0] WSEQ_DATA_WIDTH22 [2:0] WSEQ_DELAY22 [3:0] WSEQ_DATA_WIDTH23 [2:0] WSEQ_DELAY23 [3:0] WSEQ_DATA_WIDTH24 [2:0] WSEQ_DELAY24 [3:0] WSEQ_DATA_WIDTH25 [2:0] WSEQ_DELAY25 [3:0] WSEQ_DATA_WIDTH26 [2:0] WSEQ_DELAY26 [3:0] WSEQ_DATA_WIDTH27 [2:0] WSEQ_DELAY27 [3:0] WSEQ_DATA_WIDTH28 [2:0] WSEQ_DELAY28 [3:0] WSEQ_DATA_WIDTH29 [2:0] WSEQ_DELAY29 [3:0] WSEQ_DATA_WIDTH30 [2:0] WSEQ_DELAY30 [3:0] WSEQ_DATA_WIDTH31 [2:0] WSEQ_DELAY31 [3:0] WSEQ_DATA_WIDTH32 [2:0] WSEQ_DELAY32 [3:0] WSEQ_DATA_WIDTH33 [2:0] WSEQ_DELAY33 [3:0] WSEQ_DATA_WIDTH34 [2:0] WSEQ_DELAY34 [3:0] WSEQ_DATA_WIDTH35 [2:0] WSEQ_DELAY35 [3:0] WSEQ_DATA_WIDTH36 [2:0] WSEQ_DELAY36 [3:0] WSEQ_DATA_WIDTH37 [2:0] WSEQ_DELAY37 [3:0] WSEQ_DATA_WIDTH38 [2:0] WSEQ_DELAY38 [3:0] WSEQ_DATA_WIDTH39 [2:0] WSEQ_DELAY39 [3:0] WSEQ_DATA_WIDTH40 [2:0] WSEQ_DELAY40 [3:0] WSEQ_DATA_WIDTH41 [2:0] WSEQ_DELAY41 [3:0] WSEQ_DATA_WIDTH42 [2:0] WSEQ_DELAY42 [3:0] WSEQ_DATA_WIDTH43 [2:0] WSEQ_DELAY43 [3:0] WSEQ_DATA_WIDTH44 [2:0] WSEQ_DELAY44 [3:0] WSEQ_DATA_WIDTH45 [2:0] WSEQ_DELAY45 [3:0] WSEQ_DATA_WIDTH46 [2:0] WSEQ_DELAY46 [3:0] WSEQ_DATA_WIDTH47 [2:0] WSEQ_DELAY47 [3:0] WSEQ_DATA_WIDTH48 [2:0] WSEQ_DELAY48 [3:0] WSEQ_DATA_WIDTH49 [2:0] WSEQ_DELAY49 [3:0] WSEQ_DATA_WIDTH50 [2:0] WSEQ_DELAY50 [3:0] WSEQ_DATA_WIDTH51 [2:0] WSEQ_DELAY51 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA16 [7:0] E2310227h WSEQ_ADDR17 [12:0] WSEQ_DATA_START17 [3:0] WSEQ_DATA17 [7:0] 02313B01h WSEQ_ADDR18 [12:0] WSEQ_DATA_START18 [3:0] WSEQ_DATA18 [7:0] E2314266h WSEQ_ADDR19 [12:0] WSEQ_DATA_START19 [3:0] WSEQ_DATA19 [7:0] E2315294h WSEQ_ADDR20 [12:0] WSEQ_DATA_START20 [3:0] WSEQ_DATA20 [7:0] 02310B00h WSEQ_ADDR21 [12:0] WSEQ_DATA_START21 [3:0] WSEQ_DATA21 [7:0] 02310B00h WSEQ_ADDR22 [12:0] WSEQ_DATA_START22 [3:0] WSEQ_DATA22 [7:0] E2251734h WSEQ_ADDR23 [12:0] WSEQ_DATA_START23 [3:0] WSEQ_DATA23 [7:0] 0225F501h WSEQ_ADDR24 [12:0] WSEQ_DATA_START24 [3:0] WSEQ_DATA24 [7:0] 0000F000h WSEQ_ADDR25 [12:0] WSEQ_DATA_START25 [3:0] WSEQ_DATA25 [7:0] 0000F000h WSEQ_ADDR26 [12:0] WSEQ_DATA_START26 [3:0] WSEQ_DATA26 [7:0] 0000F000h WSEQ_ADDR27 [12:0] WSEQ_DATA_START27 [3:0] WSEQ_DATA27 [7:0] 0000F000h WSEQ_ADDR28 [12:0] WSEQ_DATA_START28 [3:0] WSEQ_DATA28 [7:0] 0000F000h WSEQ_ADDR29 [12:0] WSEQ_DATA_START29 [3:0] WSEQ_DATA29 [7:0] 0000F000h WSEQ_ADDR30 [12:0] WSEQ_DATA_START30 [3:0] WSEQ_DATA30 [7:0] 02253A01h WSEQ_ADDR31 [12:0] WSEQ_DATA_START31 [3:0] WSEQ_DATA31 [7:0] C2251300h WSEQ_ADDR32 [12:0] WSEQ_DATA_START32 [3:0] WSEQ_DATA32 [7:0] 02250B00h WSEQ_ADDR33 [12:0] WSEQ_DATA_START33 [3:0] WSEQ_DATA33 [7:0] 0225FF01h WSEQ_ADDR34 [12:0] WSEQ_DATA_START34 [3:0] WSEQ_DATA34 [7:0] 0000F000h WSEQ_ADDR35 [12:0] WSEQ_DATA_START35 [3:0] WSEQ_DATA35 [7:0] 0000F000h WSEQ_ADDR36 [12:0] WSEQ_DATA_START36 [3:0] WSEQ_DATA36 [7:0] 0000F000h WSEQ_ADDR37 [12:0] WSEQ_DATA_START37 [3:0] WSEQ_DATA37 [7:0] 0000F000h WSEQ_ADDR38 [12:0] WSEQ_DATA_START38 [3:0] WSEQ_DATA38 [7:0] 0000F000h WSEQ_ADDR39 [12:0] WSEQ_DATA_START39 [3:0] WSEQ_DATA39 [7:0] 0000F000h WSEQ_ADDR40 [12:0] WSEQ_DATA_START40 [3:0] WSEQ_DATA40 [7:0] 0000F000h WSEQ_ADDR41 [12:0] WSEQ_DATA_START41 [3:0] WSEQ_DATA41 [7:0] 0000F000h WSEQ_ADDR42 [12:0] WSEQ_DATA_START42 [3:0] WSEQ_DATA42 [7:0] 0000F000h WSEQ_ADDR43 [12:0] WSEQ_DATA_START43 [3:0] WSEQ_DATA43 [7:0] 82263719h WSEQ_ADDR44 [12:0] WSEQ_DATA_START44 [3:0] WSEQ_DATA44 [7:0] C2300001h WSEQ_ADDR45 [12:0] WSEQ_DATA_START45 [3:0] WSEQ_DATA45 [7:0] 02261301h WSEQ_ADDR46 [12:0] WSEQ_DATA_START46 [3:0] WSEQ_DATA46 [7:0] 8226191Fh WSEQ_ADDR47 [12:0] WSEQ_DATA_START47 [3:0] WSEQ_DATA47 [7:0] 82310B02h WSEQ_ADDR48 [12:0] WSEQ_DATA_START48 [3:0] WSEQ_DATA48 [7:0] E231023Bh WSEQ_ADDR49 [12:0] WSEQ_DATA_START49 [3:0] WSEQ_DATA49 [7:0] 02313B01h WSEQ_ADDR50 [12:0] WSEQ_DATA_START50 [3:0] WSEQ_DATA50 [7:0] 62300000h WSEQ_ADDR51 [12:0] WSEQ_DATA_START51 [3:0] 17 1 42310C02h WSEQ_ADDR16 [12:0] WSEQ_DATA_START16 [3:0] 18 2 WSEQ_DATA51 [7:0] DS1162F1 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R12392 WSEQ_Sequence_53 (3068h) R12394 WSEQ_Sequence_54 (306Ah) R12396 WSEQ_Sequence_55 (306Ch) R12398 WSEQ_Sequence_56 (306Eh) R12400 WSEQ_Sequence_57 (3070h) R12402 WSEQ_Sequence_58 (3072h) R12404 WSEQ_Sequence_59 (3074h) R12406 WSEQ_Sequence_60 (3076h) R12408 WSEQ_Sequence_61 (3078h) R12410 WSEQ_Sequence_62 (307Ah) R12412 WSEQ_Sequence_63 (307Ch) R12414 WSEQ_Sequence_64 (307Eh) R12416 WSEQ_Sequence_65 (3080h) R12418 WSEQ_Sequence_66 (3082h) R12420 WSEQ_Sequence_67 (3084h) R12422 WSEQ_Sequence_68 (3086h) R12424 WSEQ_Sequence_69 (3088h) R12426 WSEQ_Sequence_70 (308Ah) R12428 WSEQ_Sequence_71 (308Ch) R12430 WSEQ_Sequence_72 (308Eh) R12432 WSEQ_Sequence_73 (3090h) R12434 WSEQ_Sequence_74 (3092h) R12436 WSEQ_Sequence_75 (3094h) R12438 WSEQ_Sequence_76 (3096h) R12440 WSEQ_Sequence_77 (3098h) R12442 WSEQ_Sequence_78 (309Ah) R12444 WSEQ_Sequence_79 (309Ch) R12446 WSEQ_Sequence_80 (309Eh) R12448 WSEQ_Sequence_81 (30A0h) R12450 WSEQ_Sequence_82 (30A2h) R12452 WSEQ_Sequence_83 (30A4h) R12454 WSEQ_Sequence_84 (30A6h) R12456 WSEQ_Sequence_85 (30A8h) R12458 WSEQ_Sequence_86 (30AAh) R12460 WSEQ_Sequence_87 (30ACh) R12462 WSEQ_Sequence_88 (30AEh) DS1162F1 31 15 30 14 29 13 WSEQ_DATA_WIDTH52 [2:0] WSEQ_DELAY52 [3:0] WSEQ_DATA_WIDTH53 [2:0] WSEQ_DELAY53 [3:0] WSEQ_DATA_WIDTH54 [2:0] WSEQ_DELAY54 [3:0] WSEQ_DATA_WIDTH55 [2:0] WSEQ_DELAY55 [3:0] WSEQ_DATA_WIDTH56 [2:0] WSEQ_DELAY56 [3:0] WSEQ_DATA_WIDTH57 [2:0] WSEQ_DELAY57 [3:0] WSEQ_DATA_WIDTH58 [2:0] WSEQ_DELAY58 [3:0] WSEQ_DATA_WIDTH59 [2:0] WSEQ_DELAY59 [3:0] WSEQ_DATA_WIDTH60 [2:0] WSEQ_DELAY60 [3:0] WSEQ_DATA_WIDTH61 [2:0] WSEQ_DELAY61 [3:0] WSEQ_DATA_WIDTH62 [2:0] WSEQ_DELAY62 [3:0] WSEQ_DATA_WIDTH63 [2:0] WSEQ_DELAY63 [3:0] WSEQ_DATA_WIDTH64 [2:0] WSEQ_DELAY64 [3:0] WSEQ_DATA_WIDTH65 [2:0] WSEQ_DELAY65 [3:0] WSEQ_DATA_WIDTH66 [2:0] WSEQ_DELAY66 [3:0] WSEQ_DATA_WIDTH67 [2:0] WSEQ_DELAY67 [3:0] WSEQ_DATA_WIDTH68 [2:0] WSEQ_DELAY68 [3:0] WSEQ_DATA_WIDTH69 [2:0] WSEQ_DELAY69 [3:0] WSEQ_DATA_WIDTH70 [2:0] WSEQ_DELAY70 [3:0] WSEQ_DATA_WIDTH71 [2:0] WSEQ_DELAY71 [3:0] WSEQ_DATA_WIDTH72 [2:0] WSEQ_DELAY72 [3:0] WSEQ_DATA_WIDTH73 [2:0] WSEQ_DELAY73 [3:0] WSEQ_DATA_WIDTH74 [2:0] WSEQ_DELAY74 [3:0] WSEQ_DATA_WIDTH75 [2:0] WSEQ_DELAY75 [3:0] WSEQ_DATA_WIDTH76 [2:0] WSEQ_DELAY76 [3:0] WSEQ_DATA_WIDTH77 [2:0] WSEQ_DELAY77 [3:0] WSEQ_DATA_WIDTH78 [2:0] WSEQ_DELAY78 [3:0] WSEQ_DATA_WIDTH79 [2:0] WSEQ_DELAY79 [3:0] WSEQ_DATA_WIDTH80 [2:0] WSEQ_DELAY80 [3:0] WSEQ_DATA_WIDTH81 [2:0] WSEQ_DELAY81 [3:0] WSEQ_DATA_WIDTH82 [2:0] WSEQ_DELAY82 [3:0] WSEQ_DATA_WIDTH83 [2:0] WSEQ_DELAY83 [3:0] WSEQ_DATA_WIDTH84 [2:0] WSEQ_DELAY84 [3:0] WSEQ_DATA_WIDTH85 [2:0] WSEQ_DELAY85 [3:0] WSEQ_DATA_WIDTH86 [2:0] WSEQ_DELAY86 [3:0] WSEQ_DATA_WIDTH87 [2:0] WSEQ_DELAY87 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA52 [7:0] 02310B00h WSEQ_ADDR53 [12:0] WSEQ_DATA_START53 [3:0] WSEQ_DATA53 [7:0] 02310B00h WSEQ_ADDR54 [12:0] WSEQ_DATA_START54 [3:0] WSEQ_DATA54 [7:0] 02260E01h WSEQ_ADDR55 [12:0] WSEQ_DATA_START55 [3:0] WSEQ_DATA55 [7:0] 42310C03h WSEQ_ADDR56 [12:0] WSEQ_DATA_START56 [3:0] WSEQ_DATA56 [7:0] E2310227h WSEQ_ADDR57 [12:0] WSEQ_DATA_START57 [3:0] WSEQ_DATA57 [7:0] 02313B01h WSEQ_ADDR58 [12:0] WSEQ_DATA_START58 [3:0] WSEQ_DATA58 [7:0] E2314266h WSEQ_ADDR59 [12:0] WSEQ_DATA_START59 [3:0] WSEQ_DATA59 [7:0] E2315294h WSEQ_ADDR60 [12:0] WSEQ_DATA_START60 [3:0] WSEQ_DATA60 [7:0] 02310B00h WSEQ_ADDR61 [12:0] WSEQ_DATA_START61 [3:0] WSEQ_DATA61 [7:0] 02310B00h WSEQ_ADDR62 [12:0] WSEQ_DATA_START62 [3:0] WSEQ_DATA62 [7:0] E2261734h WSEQ_ADDR63 [12:0] WSEQ_DATA_START63 [3:0] WSEQ_DATA63 [7:0] 0226F501h WSEQ_ADDR64 [12:0] WSEQ_DATA_START64 [3:0] WSEQ_DATA64 [7:0] 0000F000h WSEQ_ADDR65 [12:0] WSEQ_DATA_START65 [3:0] WSEQ_DATA65 [7:0] 0000F000h WSEQ_ADDR66 [12:0] WSEQ_DATA_START66 [3:0] WSEQ_DATA66 [7:0] 0000F000h WSEQ_ADDR67 [12:0] WSEQ_DATA_START67 [3:0] WSEQ_DATA67 [7:0] 0000F000h WSEQ_ADDR68 [12:0] WSEQ_DATA_START68 [3:0] WSEQ_DATA68 [7:0] 0000F000h WSEQ_ADDR69 [12:0] WSEQ_DATA_START69 [3:0] WSEQ_DATA69 [7:0] 0000F000h WSEQ_ADDR70 [12:0] WSEQ_DATA_START70 [3:0] WSEQ_DATA70 [7:0] 02263A01h WSEQ_ADDR71 [12:0] WSEQ_DATA_START71 [3:0] WSEQ_DATA71 [7:0] C2261300h WSEQ_ADDR72 [12:0] WSEQ_DATA_START72 [3:0] WSEQ_DATA72 [7:0] 02260B00h WSEQ_ADDR73 [12:0] WSEQ_DATA_START73 [3:0] WSEQ_DATA73 [7:0] 0226FF01h WSEQ_ADDR74 [12:0] WSEQ_DATA_START74 [3:0] WSEQ_DATA74 [7:0] 0000F000h WSEQ_ADDR75 [12:0] WSEQ_DATA_START75 [3:0] WSEQ_DATA75 [7:0] 0000F000h WSEQ_ADDR76 [12:0] WSEQ_DATA_START76 [3:0] WSEQ_DATA76 [7:0] 0000F000h WSEQ_ADDR77 [12:0] WSEQ_DATA_START77 [3:0] WSEQ_DATA77 [7:0] 0000F000h WSEQ_ADDR78 [12:0] WSEQ_DATA_START78 [3:0] WSEQ_DATA78 [7:0] 0000F000h WSEQ_ADDR79 [12:0] WSEQ_DATA_START79 [3:0] WSEQ_DATA79 [7:0] 0000F000h WSEQ_ADDR80 [12:0] WSEQ_DATA_START80 [3:0] WSEQ_DATA80 [7:0] 0000F000h WSEQ_ADDR81 [12:0] WSEQ_DATA_START81 [3:0] WSEQ_DATA81 [7:0] 0000F000h WSEQ_ADDR82 [12:0] WSEQ_DATA_START82 [3:0] WSEQ_DATA82 [7:0] 0000F000h WSEQ_ADDR83 [12:0] WSEQ_DATA_START83 [3:0] WSEQ_DATA83 [7:0] 82273719h WSEQ_ADDR84 [12:0] WSEQ_DATA_START84 [3:0] WSEQ_DATA84 [7:0] C2400001h WSEQ_ADDR85 [12:0] WSEQ_DATA_START85 [3:0] WSEQ_DATA85 [7:0] 02271301h WSEQ_ADDR86 [12:0] WSEQ_DATA_START86 [3:0] WSEQ_DATA86 [7:0] 8227191Fh WSEQ_ADDR87 [12:0] WSEQ_DATA_START87 [3:0] 17 1 E2314288h WSEQ_ADDR52 [12:0] WSEQ_DATA_START52 [3:0] 18 2 WSEQ_DATA87 [7:0] 313 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R12464 WSEQ_Sequence_89 (30B0h) R12466 WSEQ_Sequence_90 (30B2h) R12468 WSEQ_Sequence_91 (30B4h) R12470 WSEQ_Sequence_92 (30B6h) R12472 WSEQ_Sequence_93 (30B8h) R12474 WSEQ_Sequence_94 (30BAh) R12476 WSEQ_Sequence_95 (30BCh) R12478 WSEQ_Sequence_96 (30BEh) R12480 WSEQ_Sequence_97 (30C0h) R12482 WSEQ_Sequence_98 (30C2h) R12484 WSEQ_Sequence_99 (30C4h) R12486 WSEQ_Sequence_100 (30C6h) R12488 WSEQ_Sequence_101 (30C8h) R12490 WSEQ_Sequence_102 (30CAh) R12492 WSEQ_Sequence_103 (30CCh) R12494 WSEQ_Sequence_104 (30CEh) R12496 WSEQ_Sequence_105 (30D0h) R12498 WSEQ_Sequence_106 (30D2h) R12500 WSEQ_Sequence_107 (30D4h) R12502 WSEQ_Sequence_108 (30D6h) R12504 WSEQ_Sequence_109 (30D8h) R12506 WSEQ_Sequence_110 (30DAh) R12508 WSEQ_Sequence_111 (30DCh) R12510 WSEQ_Sequence_112 (30DEh) R12512 WSEQ_Sequence_113 (30E0h) R12514 WSEQ_Sequence_114 (30E2h) R12516 WSEQ_Sequence_115 (30E4h) R12518 WSEQ_Sequence_116 (30E6h) R12520 WSEQ_Sequence_117 (30E8h) R12522 WSEQ_Sequence_118 (30EAh) R12524 WSEQ_Sequence_119 (30ECh) R12526 WSEQ_Sequence_120 (30EEh) R12528 WSEQ_Sequence_121 (30F0h) R12530 WSEQ_Sequence_122 (30F2h) R12532 WSEQ_Sequence_123 (30F4h) R12534 WSEQ_Sequence_124 (30F6h) 314 31 15 30 14 29 13 WSEQ_DATA_WIDTH88 [2:0] WSEQ_DELAY88 [3:0] WSEQ_DATA_WIDTH89 [2:0] WSEQ_DELAY89 [3:0] WSEQ_DATA_WIDTH90 [2:0] WSEQ_DELAY90 [3:0] WSEQ_DATA_WIDTH91 [2:0] WSEQ_DELAY91 [3:0] WSEQ_DATA_WIDTH92 [2:0] WSEQ_DELAY92 [3:0] WSEQ_DATA_WIDTH93 [2:0] WSEQ_DELAY93 [3:0] WSEQ_DATA_WIDTH94 [2:0] WSEQ_DELAY94 [3:0] WSEQ_DATA_WIDTH95 [2:0] WSEQ_DELAY95 [3:0] WSEQ_DATA_WIDTH96 [2:0] WSEQ_DELAY96 [3:0] WSEQ_DATA_WIDTH97 [2:0] WSEQ_DELAY97 [3:0] WSEQ_DATA_WIDTH98 [2:0] WSEQ_DELAY98 [3:0] WSEQ_DATA_WIDTH99 [2:0] WSEQ_DELAY99 [3:0] WSEQ_DATA_WIDTH100 [2:0] WSEQ_DELAY100 [3:0] WSEQ_DATA_WIDTH101 [2:0] WSEQ_DELAY101 [3:0] WSEQ_DATA_WIDTH102 [2:0] WSEQ_DELAY102 [3:0] WSEQ_DATA_WIDTH103 [2:0] WSEQ_DELAY103 [3:0] WSEQ_DATA_WIDTH104 [2:0] WSEQ_DELAY104 [3:0] WSEQ_DATA_WIDTH105 [2:0] WSEQ_DELAY105 [3:0] WSEQ_DATA_WIDTH106 [2:0] WSEQ_DELAY106 [3:0] WSEQ_DATA_WIDTH107 [2:0] WSEQ_DELAY107 [3:0] WSEQ_DATA_WIDTH108 [2:0] WSEQ_DELAY108 [3:0] WSEQ_DATA_WIDTH109 [2:0] WSEQ_DELAY109 [3:0] WSEQ_DATA_WIDTH110 [2:0] WSEQ_DELAY110 [3:0] WSEQ_DATA_WIDTH111 [2:0] WSEQ_DELAY111 [3:0] WSEQ_DATA_WIDTH112 [2:0] WSEQ_DELAY112 [3:0] WSEQ_DATA_WIDTH113 [2:0] WSEQ_DELAY113 [3:0] WSEQ_DATA_WIDTH114 [2:0] WSEQ_DELAY114 [3:0] WSEQ_DATA_WIDTH115 [2:0] WSEQ_DELAY115 [3:0] WSEQ_DATA_WIDTH116 [2:0] WSEQ_DELAY116 [3:0] WSEQ_DATA_WIDTH117 [2:0] WSEQ_DELAY117 [3:0] WSEQ_DATA_WIDTH118 [2:0] WSEQ_DELAY118 [3:0] WSEQ_DATA_WIDTH119 [2:0] WSEQ_DELAY119 [3:0] WSEQ_DATA_WIDTH120 [2:0] WSEQ_DELAY120 [3:0] WSEQ_DATA_WIDTH121 [2:0] WSEQ_DELAY121 [3:0] WSEQ_DATA_WIDTH122 [2:0] WSEQ_DELAY122 [3:0] WSEQ_DATA_WIDTH123 [2:0] WSEQ_DELAY123 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA88 [7:0] E241023Bh WSEQ_ADDR89 [12:0] WSEQ_DATA_START89 [3:0] WSEQ_DATA89 [7:0] 02413B01h WSEQ_ADDR90 [12:0] WSEQ_DATA_START90 [3:0] WSEQ_DATA90 [7:0] 62400000h WSEQ_ADDR91 [12:0] WSEQ_DATA_START91 [3:0] WSEQ_DATA91 [7:0] E2414288h WSEQ_ADDR92 [12:0] WSEQ_DATA_START92 [3:0] WSEQ_DATA92 [7:0] 02410B00h WSEQ_ADDR93 [12:0] WSEQ_DATA_START93 [3:0] WSEQ_DATA93 [7:0] 02410B00h WSEQ_ADDR94 [12:0] WSEQ_DATA_START94 [3:0] WSEQ_DATA94 [7:0] 02270E01h WSEQ_ADDR95 [12:0] WSEQ_DATA_START95 [3:0] WSEQ_DATA95 [7:0] 42410C02h WSEQ_ADDR96 [12:0] WSEQ_DATA_START96 [3:0] WSEQ_DATA96 [7:0] E2410227h WSEQ_ADDR97 [12:0] WSEQ_DATA_START97 [3:0] WSEQ_DATA97 [7:0] 02413B01h WSEQ_ADDR98 [12:0] WSEQ_DATA_START98 [3:0] WSEQ_DATA98 [7:0] E2414266h WSEQ_ADDR99 [12:0] WSEQ_DATA_START99 [3:0] WSEQ_DATA99 [7:0] E2415294h WSEQ_ADDR100 [12:0] WSEQ_DATA_START100 [3:0] WSEQ_DATA100 [7:0] 02410B00h WSEQ_ADDR101 [12:0] WSEQ_DATA_START101 [3:0] WSEQ_DATA101 [7:0] 02410B00h WSEQ_ADDR102 [12:0] WSEQ_DATA_START102 [3:0] WSEQ_DATA102 [7:0] E2271734h WSEQ_ADDR103 [12:0] WSEQ_DATA_START103 [3:0] WSEQ_DATA103 [7:0] 0227F501h WSEQ_ADDR104 [12:0] WSEQ_DATA_START104 [3:0] WSEQ_DATA104 [7:0] 0000F000h WSEQ_ADDR105 [12:0] WSEQ_DATA_START105 [3:0] WSEQ_DATA105 [7:0] 0000F000h WSEQ_ADDR106 [12:0] WSEQ_DATA_START106 [3:0] WSEQ_DATA106 [7:0] 0000F000h WSEQ_ADDR107 [12:0] WSEQ_DATA_START107 [3:0] WSEQ_DATA107 [7:0] 0000F000h WSEQ_ADDR108 [12:0] WSEQ_DATA_START108 [3:0] WSEQ_DATA108 [7:0] 0000F000h WSEQ_ADDR109 [12:0] WSEQ_DATA_START109 [3:0] WSEQ_DATA109 [7:0] 0000F000h WSEQ_ADDR110 [12:0] WSEQ_DATA_START110 [3:0] WSEQ_DATA110 [7:0] 02273A01h WSEQ_ADDR111 [12:0] WSEQ_DATA_START111 [3:0] WSEQ_DATA111 [7:0] C2271300h WSEQ_ADDR112 [12:0] WSEQ_DATA_START112 [3:0] WSEQ_DATA112 [7:0] 02270B00h WSEQ_ADDR113 [12:0] WSEQ_DATA_START113 [3:0] WSEQ_DATA113 [7:0] 0227FF01h WSEQ_ADDR114 [12:0] WSEQ_DATA_START114 [3:0] WSEQ_DATA114 [7:0] 0000F000h WSEQ_ADDR115 [12:0] WSEQ_DATA_START115 [3:0] WSEQ_DATA115 [7:0] 0000F000h WSEQ_ADDR116 [12:0] WSEQ_DATA_START116 [3:0] WSEQ_DATA116 [7:0] 0000F000h WSEQ_ADDR117 [12:0] WSEQ_DATA_START117 [3:0] WSEQ_DATA117 [7:0] 0000F000h WSEQ_ADDR118 [12:0] WSEQ_DATA_START118 [3:0] WSEQ_DATA118 [7:0] 0000F000h WSEQ_ADDR119 [12:0] WSEQ_DATA_START119 [3:0] WSEQ_DATA119 [7:0] 0000F000h WSEQ_ADDR120 [12:0] WSEQ_DATA_START120 [3:0] WSEQ_DATA120 [7:0] 0000F000h WSEQ_ADDR121 [12:0] WSEQ_DATA_START121 [3:0] WSEQ_DATA121 [7:0] 0000F000h WSEQ_ADDR122 [12:0] WSEQ_DATA_START122 [3:0] WSEQ_DATA122 [7:0] 0000F000h WSEQ_ADDR123 [12:0] WSEQ_DATA_START123 [3:0] 17 1 82410B00h WSEQ_ADDR88 [12:0] WSEQ_DATA_START88 [3:0] 18 2 WSEQ_DATA123 [7:0] DS1162F1 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R12536 WSEQ_Sequence_125 (30F8h) R12538 WSEQ_Sequence_126 (30FAh) R12540 WSEQ_Sequence_127 (30FCh) R12542 WSEQ_Sequence_128 (30FEh) R12544 WSEQ_Sequence_129 (3100h) R12546 WSEQ_Sequence_130 (3102h) R12548 WSEQ_Sequence_131 (3104h) R12550 WSEQ_Sequence_132 (3106h) R12552 WSEQ_Sequence_133 (3108h) R12554 WSEQ_Sequence_134 (310Ah) R12556 WSEQ_Sequence_135 (310Ch) R12558 WSEQ_Sequence_136 (310Eh) R12560 WSEQ_Sequence_137 (3110h) R12562 WSEQ_Sequence_138 (3112h) R12564 WSEQ_Sequence_139 (3114h) R12566 WSEQ_Sequence_140 (3116h) R12568 WSEQ_Sequence_141 (3118h) R12570 WSEQ_Sequence_142 (311Ah) R12572 WSEQ_Sequence_143 (311Ch) R12574 WSEQ_Sequence_144 (311Eh) R12576 WSEQ_Sequence_145 (3120h) R12578 WSEQ_Sequence_146 (3122h) R12580 WSEQ_Sequence_147 (3124h) R12582 WSEQ_Sequence_148 (3126h) R12584 WSEQ_Sequence_149 (3128h) R12586 WSEQ_Sequence_150 (312Ah) R12588 WSEQ_Sequence_151 (312Ch) R12590 WSEQ_Sequence_152 (312Eh) R12592 WSEQ_Sequence_153 (3130h) R12594 WSEQ_Sequence_154 (3132h) R12596 WSEQ_Sequence_155 (3134h) R12598 WSEQ_Sequence_156 (3136h) R12600 WSEQ_Sequence_157 (3138h) R12602 WSEQ_Sequence_158 (313Ah) R12604 WSEQ_Sequence_159 (313Ch) R12606 WSEQ_Sequence_160 (313Eh) DS1162F1 31 15 30 14 29 13 WSEQ_DATA_WIDTH124 [2:0] WSEQ_DELAY124 [3:0] WSEQ_DATA_WIDTH125 [2:0] WSEQ_DELAY125 [3:0] WSEQ_DATA_WIDTH126 [2:0] WSEQ_DELAY126 [3:0] WSEQ_DATA_WIDTH127 [2:0] WSEQ_DELAY127 [3:0] WSEQ_DATA_WIDTH128 [2:0] WSEQ_DELAY128 [3:0] WSEQ_DATA_WIDTH129 [2:0] WSEQ_DELAY129 [3:0] WSEQ_DATA_WIDTH130 [2:0] WSEQ_DELAY130 [3:0] WSEQ_DATA_WIDTH131 [2:0] WSEQ_DELAY131 [3:0] WSEQ_DATA_WIDTH132 [2:0] WSEQ_DELAY132 [3:0] WSEQ_DATA_WIDTH133 [2:0] WSEQ_DELAY133 [3:0] WSEQ_DATA_WIDTH134 [2:0] WSEQ_DELAY134 [3:0] WSEQ_DATA_WIDTH135 [2:0] WSEQ_DELAY135 [3:0] WSEQ_DATA_WIDTH136 [2:0] WSEQ_DELAY136 [3:0] WSEQ_DATA_WIDTH137 [2:0] WSEQ_DELAY137 [3:0] WSEQ_DATA_WIDTH138 [2:0] WSEQ_DELAY138 [3:0] WSEQ_DATA_WIDTH139 [2:0] WSEQ_DELAY139 [3:0] WSEQ_DATA_WIDTH140 [2:0] WSEQ_DELAY140 [3:0] WSEQ_DATA_WIDTH141 [2:0] WSEQ_DELAY141 [3:0] WSEQ_DATA_WIDTH142 [2:0] WSEQ_DELAY142 [3:0] WSEQ_DATA_WIDTH143 [2:0] WSEQ_DELAY143 [3:0] WSEQ_DATA_WIDTH144 [2:0] WSEQ_DELAY144 [3:0] WSEQ_DATA_WIDTH145 [2:0] WSEQ_DELAY145 [3:0] WSEQ_DATA_WIDTH146 [2:0] WSEQ_DELAY146 [3:0] WSEQ_DATA_WIDTH147 [2:0] WSEQ_DELAY147 [3:0] WSEQ_DATA_WIDTH148 [2:0] WSEQ_DELAY148 [3:0] WSEQ_DATA_WIDTH149 [2:0] WSEQ_DELAY149 [3:0] WSEQ_DATA_WIDTH150 [2:0] WSEQ_DELAY150 [3:0] WSEQ_DATA_WIDTH151 [2:0] WSEQ_DELAY151 [3:0] WSEQ_DATA_WIDTH152 [2:0] WSEQ_DELAY152 [3:0] WSEQ_DATA_WIDTH153 [2:0] WSEQ_DELAY153 [3:0] WSEQ_DATA_WIDTH154 [2:0] WSEQ_DELAY154 [3:0] WSEQ_DATA_WIDTH155 [2:0] WSEQ_DELAY155 [3:0] WSEQ_DATA_WIDTH156 [2:0] WSEQ_DELAY156 [3:0] WSEQ_DATA_WIDTH157 [2:0] WSEQ_DELAY157 [3:0] WSEQ_DATA_WIDTH158 [2:0] WSEQ_DELAY158 [3:0] WSEQ_DATA_WIDTH159 [2:0] WSEQ_DELAY159 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA124 [7:0] C2400001h WSEQ_ADDR125 [12:0] WSEQ_DATA_START125 [3:0] WSEQ_DATA125 [7:0] 02281301h WSEQ_ADDR126 [12:0] WSEQ_DATA_START126 [3:0] WSEQ_DATA126 [7:0] 8228191Fh WSEQ_ADDR127 [12:0] WSEQ_DATA_START127 [3:0] WSEQ_DATA127 [7:0] 82410B02h WSEQ_ADDR128 [12:0] WSEQ_DATA_START128 [3:0] WSEQ_DATA128 [7:0] E241023Bh WSEQ_ADDR129 [12:0] WSEQ_DATA_START129 [3:0] WSEQ_DATA129 [7:0] 02413B01h WSEQ_ADDR130 [12:0] WSEQ_DATA_START130 [3:0] WSEQ_DATA130 [7:0] 62400000h WSEQ_ADDR131 [12:0] WSEQ_DATA_START131 [3:0] WSEQ_DATA131 [7:0] E2414288h WSEQ_ADDR132 [12:0] WSEQ_DATA_START132 [3:0] WSEQ_DATA132 [7:0] 02410B00h WSEQ_ADDR133 [12:0] WSEQ_DATA_START133 [3:0] WSEQ_DATA133 [7:0] 02410B00h WSEQ_ADDR134 [12:0] WSEQ_DATA_START134 [3:0] WSEQ_DATA134 [7:0] 02280E01h WSEQ_ADDR135 [12:0] WSEQ_DATA_START135 [3:0] WSEQ_DATA135 [7:0] 42410C03h WSEQ_ADDR136 [12:0] WSEQ_DATA_START136 [3:0] WSEQ_DATA136 [7:0] E2410227h WSEQ_ADDR137 [12:0] WSEQ_DATA_START137 [3:0] WSEQ_DATA137 [7:0] 02413B01h WSEQ_ADDR138 [12:0] WSEQ_DATA_START138 [3:0] WSEQ_DATA138 [7:0] E2414266h WSEQ_ADDR139 [12:0] WSEQ_DATA_START139 [3:0] WSEQ_DATA139 [7:0] E2415294h WSEQ_ADDR140 [12:0] WSEQ_DATA_START140 [3:0] WSEQ_DATA140 [7:0] 02410B00h WSEQ_ADDR141 [12:0] WSEQ_DATA_START141 [3:0] WSEQ_DATA141 [7:0] 02410B00h WSEQ_ADDR142 [12:0] WSEQ_DATA_START142 [3:0] WSEQ_DATA142 [7:0] E2281734h WSEQ_ADDR143 [12:0] WSEQ_DATA_START143 [3:0] WSEQ_DATA143 [7:0] 0228F501h WSEQ_ADDR144 [12:0] WSEQ_DATA_START144 [3:0] WSEQ_DATA144 [7:0] 0000F000h WSEQ_ADDR145 [12:0] WSEQ_DATA_START145 [3:0] WSEQ_DATA145 [7:0] 0000F000h WSEQ_ADDR146 [12:0] WSEQ_DATA_START146 [3:0] WSEQ_DATA146 [7:0] 0000F000h WSEQ_ADDR147 [12:0] WSEQ_DATA_START147 [3:0] WSEQ_DATA147 [7:0] 0000F000h WSEQ_ADDR148 [12:0] WSEQ_DATA_START148 [3:0] WSEQ_DATA148 [7:0] 0000F000h WSEQ_ADDR149 [12:0] WSEQ_DATA_START149 [3:0] WSEQ_DATA149 [7:0] 0000F000h WSEQ_ADDR150 [12:0] WSEQ_DATA_START150 [3:0] WSEQ_DATA150 [7:0] 02283A01h WSEQ_ADDR151 [12:0] WSEQ_DATA_START151 [3:0] WSEQ_DATA151 [7:0] C2281300h WSEQ_ADDR152 [12:0] WSEQ_DATA_START152 [3:0] WSEQ_DATA152 [7:0] 02280B00h WSEQ_ADDR153 [12:0] WSEQ_DATA_START153 [3:0] WSEQ_DATA153 [7:0] 0228FF01h WSEQ_ADDR154 [12:0] WSEQ_DATA_START154 [3:0] WSEQ_DATA154 [7:0] 0000F000h WSEQ_ADDR155 [12:0] WSEQ_DATA_START155 [3:0] WSEQ_DATA155 [7:0] 0000F000h WSEQ_ADDR156 [12:0] WSEQ_DATA_START156 [3:0] WSEQ_DATA156 [7:0] 0000F000h WSEQ_ADDR157 [12:0] WSEQ_DATA_START157 [3:0] WSEQ_DATA157 [7:0] 0000F000h WSEQ_ADDR158 [12:0] WSEQ_DATA_START158 [3:0] WSEQ_DATA158 [7:0] 0000F000h WSEQ_ADDR159 [12:0] WSEQ_DATA_START159 [3:0] 17 1 82283719h WSEQ_ADDR124 [12:0] WSEQ_DATA_START124 [3:0] 18 2 WSEQ_DATA159 [7:0] 315 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R12608 WSEQ_Sequence_161 (3140h) R12610 WSEQ_Sequence_162 (3142h) R12612 WSEQ_Sequence_163 (3144h) R12614 WSEQ_Sequence_164 (3146h) R12616 WSEQ_Sequence_165 (3148h) R12618 WSEQ_Sequence_166 (314Ah) R12620 WSEQ_Sequence_167 (314Ch) R12622 WSEQ_Sequence_168 (314Eh) R12624 WSEQ_Sequence_169 (3150h) R12626 WSEQ_Sequence_170 (3152h) R12628 WSEQ_Sequence_171 (3154h) R12630 WSEQ_Sequence_172 (3156h) R12632 WSEQ_Sequence_173 (3158h) R12634 WSEQ_Sequence_174 (315Ah) R12636 WSEQ_Sequence_175 (315Ch) R12638 WSEQ_Sequence_176 (315Eh) R12640 WSEQ_Sequence_177 (3160h) R12642 WSEQ_Sequence_178 (3162h) R12644 WSEQ_Sequence_179 (3164h) R12646 WSEQ_Sequence_180 (3166h) R12648 WSEQ_Sequence_181 (3168h) R12650 WSEQ_Sequence_182 (316Ah) R12652 WSEQ_Sequence_183 (316Ch) R12654 WSEQ_Sequence_184 (316Eh) R12656 WSEQ_Sequence_185 (3170h) R12658 WSEQ_Sequence_186 (3172h) R12660 WSEQ_Sequence_187 (3174h) R12662 WSEQ_Sequence_188 (3176h) R12664 WSEQ_Sequence_189 (3178h) R12666 WSEQ_Sequence_190 (317Ah) R12668 WSEQ_Sequence_191 (317Ch) R12670 WSEQ_Sequence_192 (317Eh) R12672 WSEQ_Sequence_193 (3180h) R12674 WSEQ_Sequence_194 (3182h) R12676 WSEQ_Sequence_195 (3184h) R12678 WSEQ_Sequence_196 (3186h) 316 31 15 30 14 29 13 WSEQ_DATA_WIDTH160 [2:0] WSEQ_DELAY160 [3:0] WSEQ_DATA_WIDTH161 [2:0] WSEQ_DELAY161 [3:0] WSEQ_DATA_WIDTH162 [2:0] WSEQ_DELAY162 [3:0] WSEQ_DATA_WIDTH163 [2:0] WSEQ_DELAY163 [3:0] WSEQ_DATA_WIDTH164 [2:0] WSEQ_DELAY164 [3:0] WSEQ_DATA_WIDTH165 [2:0] WSEQ_DELAY165 [3:0] WSEQ_DATA_WIDTH166 [2:0] WSEQ_DELAY166 [3:0] WSEQ_DATA_WIDTH167 [2:0] WSEQ_DELAY167 [3:0] WSEQ_DATA_WIDTH168 [2:0] WSEQ_DELAY168 [3:0] WSEQ_DATA_WIDTH169 [2:0] WSEQ_DELAY169 [3:0] WSEQ_DATA_WIDTH170 [2:0] WSEQ_DELAY170 [3:0] WSEQ_DATA_WIDTH171 [2:0] WSEQ_DELAY171 [3:0] WSEQ_DATA_WIDTH172 [2:0] WSEQ_DELAY172 [3:0] WSEQ_DATA_WIDTH173 [2:0] WSEQ_DELAY173 [3:0] WSEQ_DATA_WIDTH174 [2:0] WSEQ_DELAY174 [3:0] WSEQ_DATA_WIDTH175 [2:0] WSEQ_DELAY175 [3:0] WSEQ_DATA_WIDTH176 [2:0] WSEQ_DELAY176 [3:0] WSEQ_DATA_WIDTH177 [2:0] WSEQ_DELAY177 [3:0] WSEQ_DATA_WIDTH178 [2:0] WSEQ_DELAY178 [3:0] WSEQ_DATA_WIDTH179 [2:0] WSEQ_DELAY179 [3:0] WSEQ_DATA_WIDTH180 [2:0] WSEQ_DELAY180 [3:0] WSEQ_DATA_WIDTH181 [2:0] WSEQ_DELAY181 [3:0] WSEQ_DATA_WIDTH182 [2:0] WSEQ_DELAY182 [3:0] WSEQ_DATA_WIDTH183 [2:0] WSEQ_DELAY183 [3:0] WSEQ_DATA_WIDTH184 [2:0] WSEQ_DELAY184 [3:0] WSEQ_DATA_WIDTH185 [2:0] WSEQ_DELAY185 [3:0] WSEQ_DATA_WIDTH186 [2:0] WSEQ_DELAY186 [3:0] WSEQ_DATA_WIDTH187 [2:0] WSEQ_DELAY187 [3:0] WSEQ_DATA_WIDTH188 [2:0] WSEQ_DELAY188 [3:0] WSEQ_DATA_WIDTH189 [2:0] WSEQ_DELAY189 [3:0] WSEQ_DATA_WIDTH190 [2:0] WSEQ_DELAY190 [3:0] WSEQ_DATA_WIDTH191 [2:0] WSEQ_DELAY191 [3:0] WSEQ_DATA_WIDTH192 [2:0] WSEQ_DELAY192 [3:0] WSEQ_DATA_WIDTH193 [2:0] WSEQ_DELAY193 [3:0] WSEQ_DATA_WIDTH194 [2:0] WSEQ_DELAY194 [3:0] WSEQ_DATA_WIDTH195 [2:0] WSEQ_DELAY195 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA160 [7:0] 0000F000h WSEQ_ADDR161 [12:0] WSEQ_DATA_START161 [3:0] WSEQ_DATA161 [7:0] 0000F000h WSEQ_ADDR162 [12:0] WSEQ_DATA_START162 [3:0] WSEQ_DATA162 [7:0] 0000F000h WSEQ_ADDR163 [12:0] WSEQ_DATA_START163 [3:0] WSEQ_DATA163 [7:0] 82293719h WSEQ_ADDR164 [12:0] WSEQ_DATA_START164 [3:0] WSEQ_DATA164 [7:0] C2500001h WSEQ_ADDR165 [12:0] WSEQ_DATA_START165 [3:0] WSEQ_DATA165 [7:0] 02291301h WSEQ_ADDR166 [12:0] WSEQ_DATA_START166 [3:0] WSEQ_DATA166 [7:0] 8229191Fh WSEQ_ADDR167 [12:0] WSEQ_DATA_START167 [3:0] WSEQ_DATA167 [7:0] 82510B00h WSEQ_ADDR168 [12:0] WSEQ_DATA_START168 [3:0] WSEQ_DATA168 [7:0] E251023Bh WSEQ_ADDR169 [12:0] WSEQ_DATA_START169 [3:0] WSEQ_DATA169 [7:0] 02513B01h WSEQ_ADDR170 [12:0] WSEQ_DATA_START170 [3:0] WSEQ_DATA170 [7:0] 62500000h WSEQ_ADDR171 [12:0] WSEQ_DATA_START171 [3:0] WSEQ_DATA171 [7:0] E2514288h WSEQ_ADDR172 [12:0] WSEQ_DATA_START172 [3:0] WSEQ_DATA172 [7:0] 02510B00h WSEQ_ADDR173 [12:0] WSEQ_DATA_START173 [3:0] WSEQ_DATA173 [7:0] 02510B00h WSEQ_ADDR174 [12:0] WSEQ_DATA_START174 [3:0] WSEQ_DATA174 [7:0] 02290E01h WSEQ_ADDR175 [12:0] WSEQ_DATA_START175 [3:0] WSEQ_DATA175 [7:0] 42510C02h WSEQ_ADDR176 [12:0] WSEQ_DATA_START176 [3:0] WSEQ_DATA176 [7:0] E2510227h WSEQ_ADDR177 [12:0] WSEQ_DATA_START177 [3:0] WSEQ_DATA177 [7:0] 02513B01h WSEQ_ADDR178 [12:0] WSEQ_DATA_START178 [3:0] WSEQ_DATA178 [7:0] E2514266h WSEQ_ADDR179 [12:0] WSEQ_DATA_START179 [3:0] WSEQ_DATA179 [7:0] E2515294h WSEQ_ADDR180 [12:0] WSEQ_DATA_START180 [3:0] WSEQ_DATA180 [7:0] 02510B00h WSEQ_ADDR181 [12:0] WSEQ_DATA_START181 [3:0] WSEQ_DATA181 [7:0] 02510B00h WSEQ_ADDR182 [12:0] WSEQ_DATA_START182 [3:0] WSEQ_DATA182 [7:0] E2291734h WSEQ_ADDR183 [12:0] WSEQ_DATA_START183 [3:0] WSEQ_DATA183 [7:0] 0229F501h WSEQ_ADDR184 [12:0] WSEQ_DATA_START184 [3:0] WSEQ_DATA184 [7:0] 0000F000h WSEQ_ADDR185 [12:0] WSEQ_DATA_START185 [3:0] WSEQ_DATA185 [7:0] 0000F000h WSEQ_ADDR186 [12:0] WSEQ_DATA_START186 [3:0] WSEQ_DATA186 [7:0] 0000F000h WSEQ_ADDR187 [12:0] WSEQ_DATA_START187 [3:0] WSEQ_DATA187 [7:0] 0000F000h WSEQ_ADDR188 [12:0] WSEQ_DATA_START188 [3:0] WSEQ_DATA188 [7:0] 0000F000h WSEQ_ADDR189 [12:0] WSEQ_DATA_START189 [3:0] WSEQ_DATA189 [7:0] 0000F000h WSEQ_ADDR190 [12:0] WSEQ_DATA_START190 [3:0] WSEQ_DATA190 [7:0] 02293A01h WSEQ_ADDR191 [12:0] WSEQ_DATA_START191 [3:0] WSEQ_DATA191 [7:0] C2291300h WSEQ_ADDR192 [12:0] WSEQ_DATA_START192 [3:0] WSEQ_DATA192 [7:0] 02290B00h WSEQ_ADDR193 [12:0] WSEQ_DATA_START193 [3:0] WSEQ_DATA193 [7:0] 0229FF01h WSEQ_ADDR194 [12:0] WSEQ_DATA_START194 [3:0] WSEQ_DATA194 [7:0] 0000F000h WSEQ_ADDR195 [12:0] WSEQ_DATA_START195 [3:0] 17 1 0000F000h WSEQ_ADDR160 [12:0] WSEQ_DATA_START160 [3:0] 18 2 WSEQ_DATA195 [7:0] DS1162F1 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R12680 WSEQ_Sequence_197 (3188h) R12682 WSEQ_Sequence_198 (318Ah) R12684 WSEQ_Sequence_199 (318Ch) R12686 WSEQ_Sequence_200 (318Eh) R12688 WSEQ_Sequence_201 (3190h) R12690 WSEQ_Sequence_202 (3192h) R12692 WSEQ_Sequence_203 (3194h) R12694 WSEQ_Sequence_204 (3196h) R12696 WSEQ_Sequence_205 (3198h) R12698 WSEQ_Sequence_206 (319Ah) R12700 WSEQ_Sequence_207 (319Ch) R12702 WSEQ_Sequence_208 (319Eh) R12704 WSEQ_Sequence_209 (31A0h) R12706 WSEQ_Sequence_210 (31A2h) R12708 WSEQ_Sequence_211 (31A4h) R12710 WSEQ_Sequence_212 (31A6h) R12712 WSEQ_Sequence_213 (31A8h) R12714 WSEQ_Sequence_214 (31AAh) R12716 WSEQ_Sequence_215 (31ACh) R12718 WSEQ_Sequence_216 (31AEh) R12720 WSEQ_Sequence_217 (31B0h) R12722 WSEQ_Sequence_218 (31B2h) R12724 WSEQ_Sequence_219 (31B4h) R12726 WSEQ_Sequence_220 (31B6h) R12728 WSEQ_Sequence_221 (31B8h) R12730 WSEQ_Sequence_222 (31BAh) R12732 WSEQ_Sequence_223 (31BCh) R12734 WSEQ_Sequence_224 (31BEh) R12736 WSEQ_Sequence_225 (31C0h) R12738 WSEQ_Sequence_226 (31C2h) R12740 WSEQ_Sequence_227 (31C4h) R12742 WSEQ_Sequence_228 (31C6h) R12744 WSEQ_Sequence_229 (31C8h) R12746 WSEQ_Sequence_230 (31CAh) R12748 WSEQ_Sequence_231 (31CCh) R12750 WSEQ_Sequence_232 (31CEh) DS1162F1 31 15 30 14 29 13 WSEQ_DATA_WIDTH196 [2:0] WSEQ_DELAY196 [3:0] WSEQ_DATA_WIDTH197 [2:0] WSEQ_DELAY197 [3:0] WSEQ_DATA_WIDTH198 [2:0] WSEQ_DELAY198 [3:0] WSEQ_DATA_WIDTH199 [2:0] WSEQ_DELAY199 [3:0] WSEQ_DATA_WIDTH200 [2:0] WSEQ_DELAY200 [3:0] WSEQ_DATA_WIDTH201 [2:0] WSEQ_DELAY201 [3:0] WSEQ_DATA_WIDTH202 [2:0] WSEQ_DELAY202 [3:0] WSEQ_DATA_WIDTH203 [2:0] WSEQ_DELAY203 [3:0] WSEQ_DATA_WIDTH204 [2:0] WSEQ_DELAY204 [3:0] WSEQ_DATA_WIDTH205 [2:0] WSEQ_DELAY205 [3:0] WSEQ_DATA_WIDTH206 [2:0] WSEQ_DELAY206 [3:0] WSEQ_DATA_WIDTH207 [2:0] WSEQ_DELAY207 [3:0] WSEQ_DATA_WIDTH208 [2:0] WSEQ_DELAY208 [3:0] WSEQ_DATA_WIDTH209 [2:0] WSEQ_DELAY209 [3:0] WSEQ_DATA_WIDTH210 [2:0] WSEQ_DELAY210 [3:0] WSEQ_DATA_WIDTH211 [2:0] WSEQ_DELAY211 [3:0] WSEQ_DATA_WIDTH212 [2:0] WSEQ_DELAY212 [3:0] WSEQ_DATA_WIDTH213 [2:0] WSEQ_DELAY213 [3:0] WSEQ_DATA_WIDTH214 [2:0] WSEQ_DELAY214 [3:0] WSEQ_DATA_WIDTH215 [2:0] WSEQ_DELAY215 [3:0] WSEQ_DATA_WIDTH216 [2:0] WSEQ_DELAY216 [3:0] WSEQ_DATA_WIDTH217 [2:0] WSEQ_DELAY217 [3:0] WSEQ_DATA_WIDTH218 [2:0] WSEQ_DELAY218 [3:0] WSEQ_DATA_WIDTH219 [2:0] WSEQ_DELAY219 [3:0] WSEQ_DATA_WIDTH220 [2:0] WSEQ_DELAY220 [3:0] WSEQ_DATA_WIDTH221 [2:0] WSEQ_DELAY221 [3:0] WSEQ_DATA_WIDTH222 [2:0] WSEQ_DELAY222 [3:0] WSEQ_DATA_WIDTH223 [2:0] WSEQ_DELAY223 [3:0] WSEQ_DATA_WIDTH224 [2:0] WSEQ_DELAY224 [3:0] WSEQ_DATA_WIDTH225 [2:0] WSEQ_DELAY225 [3:0] WSEQ_DATA_WIDTH226 [2:0] WSEQ_DELAY226 [3:0] WSEQ_DATA_WIDTH227 [2:0] WSEQ_DELAY227 [3:0] WSEQ_DATA_WIDTH228 [2:0] WSEQ_DELAY228 [3:0] WSEQ_DATA_WIDTH229 [2:0] WSEQ_DELAY229 [3:0] WSEQ_DATA_WIDTH230 [2:0] WSEQ_DELAY230 [3:0] WSEQ_DATA_WIDTH231 [2:0] WSEQ_DELAY231 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA196 [7:0] 0000F000h WSEQ_ADDR197 [12:0] WSEQ_DATA_START197 [3:0] WSEQ_DATA197 [7:0] 0000F000h WSEQ_ADDR198 [12:0] WSEQ_DATA_START198 [3:0] WSEQ_DATA198 [7:0] 0000F000h WSEQ_ADDR199 [12:0] WSEQ_DATA_START199 [3:0] WSEQ_DATA199 [7:0] 0000F000h WSEQ_ADDR200 [12:0] WSEQ_DATA_START200 [3:0] WSEQ_DATA200 [7:0] 0000F000h WSEQ_ADDR201 [12:0] WSEQ_DATA_START201 [3:0] WSEQ_DATA201 [7:0] 0000F000h WSEQ_ADDR202 [12:0] WSEQ_DATA_START202 [3:0] WSEQ_DATA202 [7:0] 0000F000h WSEQ_ADDR203 [12:0] WSEQ_DATA_START203 [3:0] WSEQ_DATA203 [7:0] 822A3719h WSEQ_ADDR204 [12:0] WSEQ_DATA_START204 [3:0] WSEQ_DATA204 [7:0] C2500001h WSEQ_ADDR205 [12:0] WSEQ_DATA_START205 [3:0] WSEQ_DATA205 [7:0] 022A1301h WSEQ_ADDR206 [12:0] WSEQ_DATA_START206 [3:0] WSEQ_DATA206 [7:0] 822A191Fh WSEQ_ADDR207 [12:0] WSEQ_DATA_START207 [3:0] WSEQ_DATA207 [7:0] 82510B02h WSEQ_ADDR208 [12:0] WSEQ_DATA_START208 [3:0] WSEQ_DATA208 [7:0] E251023Bh WSEQ_ADDR209 [12:0] WSEQ_DATA_START209 [3:0] WSEQ_DATA209 [7:0] 02513B01h WSEQ_ADDR210 [12:0] WSEQ_DATA_START210 [3:0] WSEQ_DATA210 [7:0] 62500000h WSEQ_ADDR211 [12:0] WSEQ_DATA_START211 [3:0] WSEQ_DATA211 [7:0] E2514288h WSEQ_ADDR212 [12:0] WSEQ_DATA_START212 [3:0] WSEQ_DATA212 [7:0] 02510B00h WSEQ_ADDR213 [12:0] WSEQ_DATA_START213 [3:0] WSEQ_DATA213 [7:0] 02510B00h WSEQ_ADDR214 [12:0] WSEQ_DATA_START214 [3:0] WSEQ_DATA214 [7:0] 022A0E01h WSEQ_ADDR215 [12:0] WSEQ_DATA_START215 [3:0] WSEQ_DATA215 [7:0] 42510C03h WSEQ_ADDR216 [12:0] WSEQ_DATA_START216 [3:0] WSEQ_DATA216 [7:0] E2510227h WSEQ_ADDR217 [12:0] WSEQ_DATA_START217 [3:0] WSEQ_DATA217 [7:0] 02513B01h WSEQ_ADDR218 [12:0] WSEQ_DATA_START218 [3:0] WSEQ_DATA218 [7:0] E2514266h WSEQ_ADDR219 [12:0] WSEQ_DATA_START219 [3:0] WSEQ_DATA219 [7:0] E2515294h WSEQ_ADDR220 [12:0] WSEQ_DATA_START220 [3:0] WSEQ_DATA220 [7:0] 02510B00h WSEQ_ADDR221 [12:0] WSEQ_DATA_START221 [3:0] WSEQ_DATA221 [7:0] 02510B00h WSEQ_ADDR222 [12:0] WSEQ_DATA_START222 [3:0] WSEQ_DATA222 [7:0] E22A1734h WSEQ_ADDR223 [12:0] WSEQ_DATA_START223 [3:0] WSEQ_DATA223 [7:0] 022AF501h WSEQ_ADDR224 [12:0] WSEQ_DATA_START224 [3:0] WSEQ_DATA224 [7:0] 0000F000h WSEQ_ADDR225 [12:0] WSEQ_DATA_START225 [3:0] WSEQ_DATA225 [7:0] 0000F000h WSEQ_ADDR226 [12:0] WSEQ_DATA_START226 [3:0] WSEQ_DATA226 [7:0] 0000F000h WSEQ_ADDR227 [12:0] WSEQ_DATA_START227 [3:0] WSEQ_DATA227 [7:0] 0000F000h WSEQ_ADDR228 [12:0] WSEQ_DATA_START228 [3:0] WSEQ_DATA228 [7:0] 0000F000h WSEQ_ADDR229 [12:0] WSEQ_DATA_START229 [3:0] WSEQ_DATA229 [7:0] 0000F000h WSEQ_ADDR230 [12:0] WSEQ_DATA_START230 [3:0] WSEQ_DATA230 [7:0] 022A3A01h WSEQ_ADDR231 [12:0] WSEQ_DATA_START231 [3:0] 17 1 0000F000h WSEQ_ADDR196 [12:0] WSEQ_DATA_START196 [3:0] 18 2 WSEQ_DATA231 [7:0] 317 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R12752 WSEQ_Sequence_233 (31D0h) R12754 WSEQ_Sequence_234 (31D2h) R12756 WSEQ_Sequence_235 (31D4h) R12758 WSEQ_Sequence_236 (31D6h) R12760 WSEQ_Sequence_237 (31D8h) R12762 WSEQ_Sequence_238 (31DAh) R12764 WSEQ_Sequence_239 (31DCh) R12766 WSEQ_Sequence_240 (31DEh) R12768 WSEQ_Sequence_241 (31E0h) R12770 WSEQ_Sequence_242 (31E2h) R12772 WSEQ_Sequence_243 (31E4h) R12774 WSEQ_Sequence_244 (31E6h) R12776 WSEQ_Sequence_245 (31E8h) R12778 WSEQ_Sequence_246 (31EAh) R12780 WSEQ_Sequence_247 (31ECh) R12782 WSEQ_Sequence_248 (31EEh) R12784 WSEQ_Sequence_249 (31F0h) R12786 WSEQ_Sequence_250 (31F2h) R12788 WSEQ_Sequence_251 (31F4h) R12790 WSEQ_Sequence_252 (31F6h) R12792 WSEQ_Sequence_253 (31F8h) R12794 WSEQ_Sequence_254 (31FAh) R12796 WSEQ_Sequence_255 (31FCh) R12798 WSEQ_Sequence_256 (31FEh) R12800 WSEQ_Sequence_257 (3200h) R12802 WSEQ_Sequence_258 (3202h) R12804 WSEQ_Sequence_259 (3204h) R12806 WSEQ_Sequence_260 (3206h) R12808 WSEQ_Sequence_261 (3208h) R12810 WSEQ_Sequence_262 (320Ah) R12812 WSEQ_Sequence_263 (320Ch) R12814 WSEQ_Sequence_264 (320Eh) R12816 WSEQ_Sequence_265 (3210h) R12818 WSEQ_Sequence_266 (3212h) R12820 WSEQ_Sequence_267 (3214h) R12822 WSEQ_Sequence_268 (3216h) 318 31 15 30 14 29 13 WSEQ_DATA_WIDTH232 [2:0] WSEQ_DELAY232 [3:0] WSEQ_DATA_WIDTH233 [2:0] WSEQ_DELAY233 [3:0] WSEQ_DATA_WIDTH234 [2:0] WSEQ_DELAY234 [3:0] WSEQ_DATA_WIDTH235 [2:0] WSEQ_DELAY235 [3:0] WSEQ_DATA_WIDTH236 [2:0] WSEQ_DELAY236 [3:0] WSEQ_DATA_WIDTH237 [2:0] WSEQ_DELAY237 [3:0] WSEQ_DATA_WIDTH238 [2:0] WSEQ_DELAY238 [3:0] WSEQ_DATA_WIDTH239 [2:0] WSEQ_DELAY239 [3:0] WSEQ_DATA_WIDTH240 [2:0] WSEQ_DELAY240 [3:0] WSEQ_DATA_WIDTH241 [2:0] WSEQ_DELAY241 [3:0] WSEQ_DATA_WIDTH242 [2:0] WSEQ_DELAY242 [3:0] WSEQ_DATA_WIDTH243 [2:0] WSEQ_DELAY243 [3:0] WSEQ_DATA_WIDTH244 [2:0] WSEQ_DELAY244 [3:0] WSEQ_DATA_WIDTH245 [2:0] WSEQ_DELAY245 [3:0] WSEQ_DATA_WIDTH246 [2:0] WSEQ_DELAY246 [3:0] WSEQ_DATA_WIDTH247 [2:0] WSEQ_DELAY247 [3:0] WSEQ_DATA_WIDTH248 [2:0] WSEQ_DELAY248 [3:0] WSEQ_DATA_WIDTH249 [2:0] WSEQ_DELAY249 [3:0] WSEQ_DATA_WIDTH250 [2:0] WSEQ_DELAY250 [3:0] WSEQ_DATA_WIDTH251 [2:0] WSEQ_DELAY251 [3:0] WSEQ_DATA_WIDTH252 [2:0] WSEQ_DELAY252 [3:0] WSEQ_DATA_WIDTH253 [2:0] WSEQ_DELAY253 [3:0] WSEQ_DATA_WIDTH254 [2:0] WSEQ_DELAY254 [3:0] WSEQ_DATA_WIDTH255 [2:0] WSEQ_DELAY255 [3:0] WSEQ_DATA_WIDTH256 [2:0] WSEQ_DELAY256 [3:0] WSEQ_DATA_WIDTH257 [2:0] WSEQ_DELAY257 [3:0] WSEQ_DATA_WIDTH258 [2:0] WSEQ_DELAY258 [3:0] WSEQ_DATA_WIDTH259 [2:0] WSEQ_DELAY259 [3:0] WSEQ_DATA_WIDTH260 [2:0] WSEQ_DELAY260 [3:0] WSEQ_DATA_WIDTH261 [2:0] WSEQ_DELAY261 [3:0] WSEQ_DATA_WIDTH262 [2:0] WSEQ_DELAY262 [3:0] WSEQ_DATA_WIDTH263 [2:0] WSEQ_DELAY263 [3:0] WSEQ_DATA_WIDTH264 [2:0] WSEQ_DELAY264 [3:0] WSEQ_DATA_WIDTH265 [2:0] WSEQ_DELAY265 [3:0] WSEQ_DATA_WIDTH266 [2:0] WSEQ_DELAY266 [3:0] WSEQ_DATA_WIDTH267 [2:0] WSEQ_DELAY267 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA232 [7:0] 022A0B00h WSEQ_ADDR233 [12:0] WSEQ_DATA_START233 [3:0] WSEQ_DATA233 [7:0] 022AFF01h WSEQ_ADDR234 [12:0] WSEQ_DATA_START234 [3:0] WSEQ_DATA234 [7:0] 0000F000h WSEQ_ADDR235 [12:0] WSEQ_DATA_START235 [3:0] WSEQ_DATA235 [7:0] 0000F000h WSEQ_ADDR236 [12:0] WSEQ_DATA_START236 [3:0] WSEQ_DATA236 [7:0] 0000F000h WSEQ_ADDR237 [12:0] WSEQ_DATA_START237 [3:0] WSEQ_DATA237 [7:0] 0000F000h WSEQ_ADDR238 [12:0] WSEQ_DATA_START238 [3:0] WSEQ_DATA238 [7:0] 0000F000h WSEQ_ADDR239 [12:0] WSEQ_DATA_START239 [3:0] WSEQ_DATA239 [7:0] 0000F000h WSEQ_ADDR240 [12:0] WSEQ_DATA_START240 [3:0] WSEQ_DATA240 [7:0] 0000F000h WSEQ_ADDR241 [12:0] WSEQ_DATA_START241 [3:0] WSEQ_DATA241 [7:0] 0000F000h WSEQ_ADDR242 [12:0] WSEQ_DATA_START242 [3:0] WSEQ_DATA242 [7:0] 0000F000h WSEQ_ADDR243 [12:0] WSEQ_DATA_START243 [3:0] WSEQ_DATA243 [7:0] 0000F000h WSEQ_ADDR244 [12:0] WSEQ_DATA_START244 [3:0] WSEQ_DATA244 [7:0] 0000F000h WSEQ_ADDR245 [12:0] WSEQ_DATA_START245 [3:0] WSEQ_DATA245 [7:0] 0000F000h WSEQ_ADDR246 [12:0] WSEQ_DATA_START246 [3:0] WSEQ_DATA246 [7:0] 0000F000h WSEQ_ADDR247 [12:0] WSEQ_DATA_START247 [3:0] WSEQ_DATA247 [7:0] 0000F000h WSEQ_ADDR248 [12:0] WSEQ_DATA_START248 [3:0] WSEQ_DATA248 [7:0] 0000F000h WSEQ_ADDR249 [12:0] WSEQ_DATA_START249 [3:0] WSEQ_DATA249 [7:0] 0000F000h WSEQ_ADDR250 [12:0] WSEQ_DATA_START250 [3:0] WSEQ_DATA250 [7:0] 0000F000h WSEQ_ADDR251 [12:0] WSEQ_DATA_START251 [3:0] WSEQ_DATA251 [7:0] 0000F000h WSEQ_ADDR252 [12:0] WSEQ_DATA_START252 [3:0] WSEQ_DATA252 [7:0] 0000F000h WSEQ_ADDR253 [12:0] WSEQ_DATA_START253 [3:0] WSEQ_DATA253 [7:0] 0000F000h WSEQ_ADDR254 [12:0] WSEQ_DATA_START254 [3:0] WSEQ_DATA254 [7:0] 0000F000h WSEQ_ADDR255 [12:0] WSEQ_DATA_START255 [3:0] WSEQ_DATA255 [7:0] 0000F000h WSEQ_ADDR256 [12:0] WSEQ_DATA_START256 [3:0] WSEQ_DATA256 [7:0] 0000F000h WSEQ_ADDR257 [12:0] WSEQ_DATA_START257 [3:0] WSEQ_DATA257 [7:0] 0000F000h WSEQ_ADDR258 [12:0] WSEQ_DATA_START258 [3:0] WSEQ_DATA258 [7:0] 0000F000h WSEQ_ADDR259 [12:0] WSEQ_DATA_START259 [3:0] WSEQ_DATA259 [7:0] 0000F000h WSEQ_ADDR260 [12:0] WSEQ_DATA_START260 [3:0] WSEQ_DATA260 [7:0] 0000F000h WSEQ_ADDR261 [12:0] WSEQ_DATA_START261 [3:0] WSEQ_DATA261 [7:0] 0000F000h WSEQ_ADDR262 [12:0] WSEQ_DATA_START262 [3:0] WSEQ_DATA262 [7:0] 0000F000h WSEQ_ADDR263 [12:0] WSEQ_DATA_START263 [3:0] WSEQ_DATA263 [7:0] 0000F000h WSEQ_ADDR264 [12:0] WSEQ_DATA_START264 [3:0] WSEQ_DATA264 [7:0] 0000F000h WSEQ_ADDR265 [12:0] WSEQ_DATA_START265 [3:0] WSEQ_DATA265 [7:0] 0000F000h WSEQ_ADDR266 [12:0] WSEQ_DATA_START266 [3:0] WSEQ_DATA266 [7:0] 0000F000h WSEQ_ADDR267 [12:0] WSEQ_DATA_START267 [3:0] 17 1 C22A1300h WSEQ_ADDR232 [12:0] WSEQ_DATA_START232 [3:0] 18 2 WSEQ_DATA267 [7:0] DS1162F1 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R12824 WSEQ_Sequence_269 (3218h) R12826 WSEQ_Sequence_270 (321Ah) R12828 WSEQ_Sequence_271 (321Ch) R12830 WSEQ_Sequence_272 (321Eh) R12832 WSEQ_Sequence_273 (3220h) R12834 WSEQ_Sequence_274 (3222h) R12836 WSEQ_Sequence_275 (3224h) R12838 WSEQ_Sequence_276 (3226h) R12840 WSEQ_Sequence_277 (3228h) R12842 WSEQ_Sequence_278 (322Ah) R12844 WSEQ_Sequence_279 (322Ch) R12846 WSEQ_Sequence_280 (322Eh) R12848 WSEQ_Sequence_281 (3230h) R12850 WSEQ_Sequence_282 (3232h) R12852 WSEQ_Sequence_283 (3234h) R12854 WSEQ_Sequence_284 (3236h) R12856 WSEQ_Sequence_285 (3238h) R12858 WSEQ_Sequence_286 (323Ah) R12860 WSEQ_Sequence_287 (323Ch) R12862 WSEQ_Sequence_288 (323Eh) R12864 WSEQ_Sequence_289 (3240h) R12866 WSEQ_Sequence_290 (3242h) R12868 WSEQ_Sequence_291 (3244h) R12870 WSEQ_Sequence_292 (3246h) R12872 WSEQ_Sequence_293 (3248h) R12874 WSEQ_Sequence_294 (324Ah) R12876 WSEQ_Sequence_295 (324Ch) R12878 WSEQ_Sequence_296 (324Eh) R12880 WSEQ_Sequence_297 (3250h) R12882 WSEQ_Sequence_298 (3252h) R12884 WSEQ_Sequence_299 (3254h) R12886 WSEQ_Sequence_300 (3256h) R12888 WSEQ_Sequence_301 (3258h) R12890 WSEQ_Sequence_302 (325Ah) R12892 WSEQ_Sequence_303 (325Ch) R12894 WSEQ_Sequence_304 (325Eh) DS1162F1 31 15 30 14 29 13 WSEQ_DATA_WIDTH268 [2:0] WSEQ_DELAY268 [3:0] WSEQ_DATA_WIDTH269 [2:0] WSEQ_DELAY269 [3:0] WSEQ_DATA_WIDTH270 [2:0] WSEQ_DELAY270 [3:0] WSEQ_DATA_WIDTH271 [2:0] WSEQ_DELAY271 [3:0] WSEQ_DATA_WIDTH272 [2:0] WSEQ_DELAY272 [3:0] WSEQ_DATA_WIDTH273 [2:0] WSEQ_DELAY273 [3:0] WSEQ_DATA_WIDTH274 [2:0] WSEQ_DELAY274 [3:0] WSEQ_DATA_WIDTH275 [2:0] WSEQ_DELAY275 [3:0] WSEQ_DATA_WIDTH276 [2:0] WSEQ_DELAY276 [3:0] WSEQ_DATA_WIDTH277 [2:0] WSEQ_DELAY277 [3:0] WSEQ_DATA_WIDTH278 [2:0] WSEQ_DELAY278 [3:0] WSEQ_DATA_WIDTH279 [2:0] WSEQ_DELAY279 [3:0] WSEQ_DATA_WIDTH280 [2:0] WSEQ_DELAY280 [3:0] WSEQ_DATA_WIDTH281 [2:0] WSEQ_DELAY281 [3:0] WSEQ_DATA_WIDTH282 [2:0] WSEQ_DELAY282 [3:0] WSEQ_DATA_WIDTH283 [2:0] WSEQ_DELAY283 [3:0] WSEQ_DATA_WIDTH284 [2:0] WSEQ_DELAY284 [3:0] WSEQ_DATA_WIDTH285 [2:0] WSEQ_DELAY285 [3:0] WSEQ_DATA_WIDTH286 [2:0] WSEQ_DELAY286 [3:0] WSEQ_DATA_WIDTH287 [2:0] WSEQ_DELAY287 [3:0] WSEQ_DATA_WIDTH288 [2:0] WSEQ_DELAY288 [3:0] WSEQ_DATA_WIDTH289 [2:0] WSEQ_DELAY289 [3:0] WSEQ_DATA_WIDTH290 [2:0] WSEQ_DELAY290 [3:0] WSEQ_DATA_WIDTH291 [2:0] WSEQ_DELAY291 [3:0] WSEQ_DATA_WIDTH292 [2:0] WSEQ_DELAY292 [3:0] WSEQ_DATA_WIDTH293 [2:0] WSEQ_DELAY293 [3:0] WSEQ_DATA_WIDTH294 [2:0] WSEQ_DELAY294 [3:0] WSEQ_DATA_WIDTH295 [2:0] WSEQ_DELAY295 [3:0] WSEQ_DATA_WIDTH296 [2:0] WSEQ_DELAY296 [3:0] WSEQ_DATA_WIDTH297 [2:0] WSEQ_DELAY297 [3:0] WSEQ_DATA_WIDTH298 [2:0] WSEQ_DELAY298 [3:0] WSEQ_DATA_WIDTH299 [2:0] WSEQ_DELAY299 [3:0] WSEQ_DATA_WIDTH300 [2:0] WSEQ_DELAY300 [3:0] WSEQ_DATA_WIDTH301 [2:0] WSEQ_DELAY301 [3:0] WSEQ_DATA_WIDTH302 [2:0] WSEQ_DELAY302 [3:0] WSEQ_DATA_WIDTH303 [2:0] WSEQ_DELAY303 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA268 [7:0] 0000F000h WSEQ_ADDR269 [12:0] WSEQ_DATA_START269 [3:0] WSEQ_DATA269 [7:0] 0000F000h WSEQ_ADDR270 [12:0] WSEQ_DATA_START270 [3:0] WSEQ_DATA270 [7:0] 0000F000h WSEQ_ADDR271 [12:0] WSEQ_DATA_START271 [3:0] WSEQ_DATA271 [7:0] 0000F000h WSEQ_ADDR272 [12:0] WSEQ_DATA_START272 [3:0] WSEQ_DATA272 [7:0] 0000F000h WSEQ_ADDR273 [12:0] WSEQ_DATA_START273 [3:0] WSEQ_DATA273 [7:0] 0000F000h WSEQ_ADDR274 [12:0] WSEQ_DATA_START274 [3:0] WSEQ_DATA274 [7:0] 0000F000h WSEQ_ADDR275 [12:0] WSEQ_DATA_START275 [3:0] WSEQ_DATA275 [7:0] 0000F000h WSEQ_ADDR276 [12:0] WSEQ_DATA_START276 [3:0] WSEQ_DATA276 [7:0] 0000F000h WSEQ_ADDR277 [12:0] WSEQ_DATA_START277 [3:0] WSEQ_DATA277 [7:0] 0000F000h WSEQ_ADDR278 [12:0] WSEQ_DATA_START278 [3:0] WSEQ_DATA278 [7:0] 0000F000h WSEQ_ADDR279 [12:0] WSEQ_DATA_START279 [3:0] WSEQ_DATA279 [7:0] 0000F000h WSEQ_ADDR280 [12:0] WSEQ_DATA_START280 [3:0] WSEQ_DATA280 [7:0] 0000F000h WSEQ_ADDR281 [12:0] WSEQ_DATA_START281 [3:0] WSEQ_DATA281 [7:0] 0000F000h WSEQ_ADDR282 [12:0] WSEQ_DATA_START282 [3:0] WSEQ_DATA282 [7:0] 0000F000h WSEQ_ADDR283 [12:0] WSEQ_DATA_START283 [3:0] WSEQ_DATA283 [7:0] 0000F000h WSEQ_ADDR284 [12:0] WSEQ_DATA_START284 [3:0] WSEQ_DATA284 [7:0] 0000F000h WSEQ_ADDR285 [12:0] WSEQ_DATA_START285 [3:0] WSEQ_DATA285 [7:0] 0000F000h WSEQ_ADDR286 [12:0] WSEQ_DATA_START286 [3:0] WSEQ_DATA286 [7:0] 0000F000h WSEQ_ADDR287 [12:0] WSEQ_DATA_START287 [3:0] WSEQ_DATA287 [7:0] 0000F000h WSEQ_ADDR288 [12:0] WSEQ_DATA_START288 [3:0] WSEQ_DATA288 [7:0] 0000F000h WSEQ_ADDR289 [12:0] WSEQ_DATA_START289 [3:0] WSEQ_DATA289 [7:0] 0000F000h WSEQ_ADDR290 [12:0] WSEQ_DATA_START290 [3:0] WSEQ_DATA290 [7:0] 0000F000h WSEQ_ADDR291 [12:0] WSEQ_DATA_START291 [3:0] WSEQ_DATA291 [7:0] 0000F000h WSEQ_ADDR292 [12:0] WSEQ_DATA_START292 [3:0] WSEQ_DATA292 [7:0] 0000F000h WSEQ_ADDR293 [12:0] WSEQ_DATA_START293 [3:0] WSEQ_DATA293 [7:0] 0000F000h WSEQ_ADDR294 [12:0] WSEQ_DATA_START294 [3:0] WSEQ_DATA294 [7:0] 0000F000h WSEQ_ADDR295 [12:0] WSEQ_DATA_START295 [3:0] WSEQ_DATA295 [7:0] 0000F000h WSEQ_ADDR296 [12:0] WSEQ_DATA_START296 [3:0] WSEQ_DATA296 [7:0] 0000F000h WSEQ_ADDR297 [12:0] WSEQ_DATA_START297 [3:0] WSEQ_DATA297 [7:0] 0000F000h WSEQ_ADDR298 [12:0] WSEQ_DATA_START298 [3:0] WSEQ_DATA298 [7:0] 0000F000h WSEQ_ADDR299 [12:0] WSEQ_DATA_START299 [3:0] WSEQ_DATA299 [7:0] 0000F000h WSEQ_ADDR300 [12:0] WSEQ_DATA_START300 [3:0] WSEQ_DATA300 [7:0] 0000F000h WSEQ_ADDR301 [12:0] WSEQ_DATA_START301 [3:0] WSEQ_DATA301 [7:0] 0000F000h WSEQ_ADDR302 [12:0] WSEQ_DATA_START302 [3:0] WSEQ_DATA302 [7:0] 0000F000h WSEQ_ADDR303 [12:0] WSEQ_DATA_START303 [3:0] 17 1 0000F000h WSEQ_ADDR268 [12:0] WSEQ_DATA_START268 [3:0] 18 2 WSEQ_DATA303 [7:0] 319 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R12896 WSEQ_Sequence_305 (3260h) R12898 WSEQ_Sequence_306 (3262h) R12900 WSEQ_Sequence_307 (3264h) R12902 WSEQ_Sequence_308 (3266h) R12904 WSEQ_Sequence_309 (3268h) R12906 WSEQ_Sequence_310 (326Ah) R12908 WSEQ_Sequence_311 (326Ch) R12910 WSEQ_Sequence_312 (326Eh) R12912 WSEQ_Sequence_313 (3270h) R12914 WSEQ_Sequence_314 (3272h) R12916 WSEQ_Sequence_315 (3274h) R12918 WSEQ_Sequence_316 (3276h) R12920 WSEQ_Sequence_317 (3278h) R12922 WSEQ_Sequence_318 (327Ah) R12924 WSEQ_Sequence_319 (327Ch) R12926 WSEQ_Sequence_320 (327Eh) R12928 WSEQ_Sequence_321 (3280h) R12930 WSEQ_Sequence_322 (3282h) R12932 WSEQ_Sequence_323 (3284h) R12934 WSEQ_Sequence_324 (3286h) R12936 WSEQ_Sequence_325 (3288h) R12938 WSEQ_Sequence_326 (328Ah) R12940 WSEQ_Sequence_327 (328Ch) R12942 WSEQ_Sequence_328 (328Eh) R12944 WSEQ_Sequence_329 (3290h) R12946 WSEQ_Sequence_330 (3292h) R12948 WSEQ_Sequence_331 (3294h) R12950 WSEQ_Sequence_332 (3296h) R12952 WSEQ_Sequence_333 (3298h) R12954 WSEQ_Sequence_334 (329Ah) R12956 WSEQ_Sequence_335 (329Ch) R12958 WSEQ_Sequence_336 (329Eh) R12960 WSEQ_Sequence_337 (32A0h) R12962 WSEQ_Sequence_338 (32A2h) R12964 WSEQ_Sequence_339 (32A4h) R12966 WSEQ_Sequence_340 (32A6h) 320 31 15 30 14 29 13 WSEQ_DATA_WIDTH304 [2:0] WSEQ_DELAY304 [3:0] WSEQ_DATA_WIDTH305 [2:0] WSEQ_DELAY305 [3:0] WSEQ_DATA_WIDTH306 [2:0] WSEQ_DELAY306 [3:0] WSEQ_DATA_WIDTH307 [2:0] WSEQ_DELAY307 [3:0] WSEQ_DATA_WIDTH308 [2:0] WSEQ_DELAY308 [3:0] WSEQ_DATA_WIDTH309 [2:0] WSEQ_DELAY309 [3:0] WSEQ_DATA_WIDTH310 [2:0] WSEQ_DELAY310 [3:0] WSEQ_DATA_WIDTH311 [2:0] WSEQ_DELAY311 [3:0] WSEQ_DATA_WIDTH312 [2:0] WSEQ_DELAY312 [3:0] WSEQ_DATA_WIDTH313 [2:0] WSEQ_DELAY313 [3:0] WSEQ_DATA_WIDTH314 [2:0] WSEQ_DELAY314 [3:0] WSEQ_DATA_WIDTH315 [2:0] WSEQ_DELAY315 [3:0] WSEQ_DATA_WIDTH316 [2:0] WSEQ_DELAY316 [3:0] WSEQ_DATA_WIDTH317 [2:0] WSEQ_DELAY317 [3:0] WSEQ_DATA_WIDTH318 [2:0] WSEQ_DELAY318 [3:0] WSEQ_DATA_WIDTH319 [2:0] WSEQ_DELAY319 [3:0] WSEQ_DATA_WIDTH320 [2:0] WSEQ_DELAY320 [3:0] WSEQ_DATA_WIDTH321 [2:0] WSEQ_DELAY321 [3:0] WSEQ_DATA_WIDTH322 [2:0] WSEQ_DELAY322 [3:0] WSEQ_DATA_WIDTH323 [2:0] WSEQ_DELAY323 [3:0] WSEQ_DATA_WIDTH324 [2:0] WSEQ_DELAY324 [3:0] WSEQ_DATA_WIDTH325 [2:0] WSEQ_DELAY325 [3:0] WSEQ_DATA_WIDTH326 [2:0] WSEQ_DELAY326 [3:0] WSEQ_DATA_WIDTH327 [2:0] WSEQ_DELAY327 [3:0] WSEQ_DATA_WIDTH328 [2:0] WSEQ_DELAY328 [3:0] WSEQ_DATA_WIDTH329 [2:0] WSEQ_DELAY329 [3:0] WSEQ_DATA_WIDTH330 [2:0] WSEQ_DELAY330 [3:0] WSEQ_DATA_WIDTH331 [2:0] WSEQ_DELAY331 [3:0] WSEQ_DATA_WIDTH332 [2:0] WSEQ_DELAY332 [3:0] WSEQ_DATA_WIDTH333 [2:0] WSEQ_DELAY333 [3:0] WSEQ_DATA_WIDTH334 [2:0] WSEQ_DELAY334 [3:0] WSEQ_DATA_WIDTH335 [2:0] WSEQ_DELAY335 [3:0] WSEQ_DATA_WIDTH336 [2:0] WSEQ_DELAY336 [3:0] WSEQ_DATA_WIDTH337 [2:0] WSEQ_DELAY337 [3:0] WSEQ_DATA_WIDTH338 [2:0] WSEQ_DELAY338 [3:0] WSEQ_DATA_WIDTH339 [2:0] WSEQ_DELAY339 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA304 [7:0] 0000F000h WSEQ_ADDR305 [12:0] WSEQ_DATA_START305 [3:0] WSEQ_DATA305 [7:0] 0000F000h WSEQ_ADDR306 [12:0] WSEQ_DATA_START306 [3:0] WSEQ_DATA306 [7:0] 0000F000h WSEQ_ADDR307 [12:0] WSEQ_DATA_START307 [3:0] WSEQ_DATA307 [7:0] 0000F000h WSEQ_ADDR308 [12:0] WSEQ_DATA_START308 [3:0] WSEQ_DATA308 [7:0] 0000F000h WSEQ_ADDR309 [12:0] WSEQ_DATA_START309 [3:0] WSEQ_DATA309 [7:0] 0000F000h WSEQ_ADDR310 [12:0] WSEQ_DATA_START310 [3:0] WSEQ_DATA310 [7:0] 0000F000h WSEQ_ADDR311 [12:0] WSEQ_DATA_START311 [3:0] WSEQ_DATA311 [7:0] 0000F000h WSEQ_ADDR312 [12:0] WSEQ_DATA_START312 [3:0] WSEQ_DATA312 [7:0] 0000F000h WSEQ_ADDR313 [12:0] WSEQ_DATA_START313 [3:0] WSEQ_DATA313 [7:0] 0000F000h WSEQ_ADDR314 [12:0] WSEQ_DATA_START314 [3:0] WSEQ_DATA314 [7:0] 0000F000h WSEQ_ADDR315 [12:0] WSEQ_DATA_START315 [3:0] WSEQ_DATA315 [7:0] 0000F000h WSEQ_ADDR316 [12:0] WSEQ_DATA_START316 [3:0] WSEQ_DATA316 [7:0] 0000F000h WSEQ_ADDR317 [12:0] WSEQ_DATA_START317 [3:0] WSEQ_DATA317 [7:0] 0000F000h WSEQ_ADDR318 [12:0] WSEQ_DATA_START318 [3:0] WSEQ_DATA318 [7:0] 0000F000h WSEQ_ADDR319 [12:0] WSEQ_DATA_START319 [3:0] WSEQ_DATA319 [7:0] 0000F000h WSEQ_ADDR320 [12:0] WSEQ_DATA_START320 [3:0] WSEQ_DATA320 [7:0] 0000F000h WSEQ_ADDR321 [12:0] WSEQ_DATA_START321 [3:0] WSEQ_DATA321 [7:0] 0000F000h WSEQ_ADDR322 [12:0] WSEQ_DATA_START322 [3:0] WSEQ_DATA322 [7:0] 0000F000h WSEQ_ADDR323 [12:0] WSEQ_DATA_START323 [3:0] WSEQ_DATA323 [7:0] 0000F000h WSEQ_ADDR324 [12:0] WSEQ_DATA_START324 [3:0] WSEQ_DATA324 [7:0] 0000F000h WSEQ_ADDR325 [12:0] WSEQ_DATA_START325 [3:0] WSEQ_DATA325 [7:0] 0000F000h WSEQ_ADDR326 [12:0] WSEQ_DATA_START326 [3:0] WSEQ_DATA326 [7:0] 0000F000h WSEQ_ADDR327 [12:0] WSEQ_DATA_START327 [3:0] WSEQ_DATA327 [7:0] 0000F000h WSEQ_ADDR328 [12:0] WSEQ_DATA_START328 [3:0] WSEQ_DATA328 [7:0] 0000F000h WSEQ_ADDR329 [12:0] WSEQ_DATA_START329 [3:0] WSEQ_DATA329 [7:0] 0000F000h WSEQ_ADDR330 [12:0] WSEQ_DATA_START330 [3:0] WSEQ_DATA330 [7:0] 0000F000h WSEQ_ADDR331 [12:0] WSEQ_DATA_START331 [3:0] WSEQ_DATA331 [7:0] 0000F000h WSEQ_ADDR332 [12:0] WSEQ_DATA_START332 [3:0] WSEQ_DATA332 [7:0] 0000F000h WSEQ_ADDR333 [12:0] WSEQ_DATA_START333 [3:0] WSEQ_DATA333 [7:0] 0000F000h WSEQ_ADDR334 [12:0] WSEQ_DATA_START334 [3:0] WSEQ_DATA334 [7:0] 0000F000h WSEQ_ADDR335 [12:0] WSEQ_DATA_START335 [3:0] WSEQ_DATA335 [7:0] 0000F000h WSEQ_ADDR336 [12:0] WSEQ_DATA_START336 [3:0] WSEQ_DATA336 [7:0] 0000F000h WSEQ_ADDR337 [12:0] WSEQ_DATA_START337 [3:0] WSEQ_DATA337 [7:0] 0000F000h WSEQ_ADDR338 [12:0] WSEQ_DATA_START338 [3:0] WSEQ_DATA338 [7:0] 0000F000h WSEQ_ADDR339 [12:0] WSEQ_DATA_START339 [3:0] 17 1 0000F000h WSEQ_ADDR304 [12:0] WSEQ_DATA_START304 [3:0] 18 2 WSEQ_DATA339 [7:0] DS1162F1 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R12968 WSEQ_Sequence_341 (32A8h) R12970 WSEQ_Sequence_342 (32AAh) R12972 WSEQ_Sequence_343 (32ACh) R12974 WSEQ_Sequence_344 (32AEh) R12976 WSEQ_Sequence_345 (32B0h) R12978 WSEQ_Sequence_346 (32B2h) R12980 WSEQ_Sequence_347 (32B4h) R12982 WSEQ_Sequence_348 (32B6h) R12984 WSEQ_Sequence_349 (32B8h) R12986 WSEQ_Sequence_350 (32BAh) R12988 WSEQ_Sequence_351 (32BCh) R12990 WSEQ_Sequence_352 (32BEh) R12992 WSEQ_Sequence_353 (32C0h) R12994 WSEQ_Sequence_354 (32C2h) R12996 WSEQ_Sequence_355 (32C4h) R12998 WSEQ_Sequence_356 (32C6h) R13000 WSEQ_Sequence_357 (32C8h) R13002 WSEQ_Sequence_358 (32CAh) R13004 WSEQ_Sequence_359 (32CCh) R13006 WSEQ_Sequence_360 (32CEh) R13008 WSEQ_Sequence_361 (32D0h) R13010 WSEQ_Sequence_362 (32D2h) R13012 WSEQ_Sequence_363 (32D4h) R13014 WSEQ_Sequence_364 (32D6h) R13016 WSEQ_Sequence_365 (32D8h) R13018 WSEQ_Sequence_366 (32DAh) R13020 WSEQ_Sequence_367 (32DCh) R13022 WSEQ_Sequence_368 (32DEh) R13024 WSEQ_Sequence_369 (32E0h) R13026 WSEQ_Sequence_370 (32E2h) R13028 WSEQ_Sequence_371 (32E4h) R13030 WSEQ_Sequence_372 (32E6h) R13032 WSEQ_Sequence_373 (32E8h) R13034 WSEQ_Sequence_374 (32EAh) R13036 WSEQ_Sequence_375 (32ECh) R13038 WSEQ_Sequence_376 (32EEh) DS1162F1 31 15 30 14 29 13 WSEQ_DATA_WIDTH340 [2:0] WSEQ_DELAY340 [3:0] WSEQ_DATA_WIDTH341 [2:0] WSEQ_DELAY341 [3:0] WSEQ_DATA_WIDTH342 [2:0] WSEQ_DELAY342 [3:0] WSEQ_DATA_WIDTH343 [2:0] WSEQ_DELAY343 [3:0] WSEQ_DATA_WIDTH344 [2:0] WSEQ_DELAY344 [3:0] WSEQ_DATA_WIDTH345 [2:0] WSEQ_DELAY345 [3:0] WSEQ_DATA_WIDTH346 [2:0] WSEQ_DELAY346 [3:0] WSEQ_DATA_WIDTH347 [2:0] WSEQ_DELAY347 [3:0] WSEQ_DATA_WIDTH348 [2:0] WSEQ_DELAY348 [3:0] WSEQ_DATA_WIDTH349 [2:0] WSEQ_DELAY349 [3:0] WSEQ_DATA_WIDTH350 [2:0] WSEQ_DELAY350 [3:0] WSEQ_DATA_WIDTH351 [2:0] WSEQ_DELAY351 [3:0] WSEQ_DATA_WIDTH352 [2:0] WSEQ_DELAY352 [3:0] WSEQ_DATA_WIDTH353 [2:0] WSEQ_DELAY353 [3:0] WSEQ_DATA_WIDTH354 [2:0] WSEQ_DELAY354 [3:0] WSEQ_DATA_WIDTH355 [2:0] WSEQ_DELAY355 [3:0] WSEQ_DATA_WIDTH356 [2:0] WSEQ_DELAY356 [3:0] WSEQ_DATA_WIDTH357 [2:0] WSEQ_DELAY357 [3:0] WSEQ_DATA_WIDTH358 [2:0] WSEQ_DELAY358 [3:0] WSEQ_DATA_WIDTH359 [2:0] WSEQ_DELAY359 [3:0] WSEQ_DATA_WIDTH360 [2:0] WSEQ_DELAY360 [3:0] WSEQ_DATA_WIDTH361 [2:0] WSEQ_DELAY361 [3:0] WSEQ_DATA_WIDTH362 [2:0] WSEQ_DELAY362 [3:0] WSEQ_DATA_WIDTH363 [2:0] WSEQ_DELAY363 [3:0] WSEQ_DATA_WIDTH364 [2:0] WSEQ_DELAY364 [3:0] WSEQ_DATA_WIDTH365 [2:0] WSEQ_DELAY365 [3:0] WSEQ_DATA_WIDTH366 [2:0] WSEQ_DELAY366 [3:0] WSEQ_DATA_WIDTH367 [2:0] WSEQ_DELAY367 [3:0] WSEQ_DATA_WIDTH368 [2:0] WSEQ_DELAY368 [3:0] WSEQ_DATA_WIDTH369 [2:0] WSEQ_DELAY369 [3:0] WSEQ_DATA_WIDTH370 [2:0] WSEQ_DELAY370 [3:0] WSEQ_DATA_WIDTH371 [2:0] WSEQ_DELAY371 [3:0] WSEQ_DATA_WIDTH372 [2:0] WSEQ_DELAY372 [3:0] WSEQ_DATA_WIDTH373 [2:0] WSEQ_DELAY373 [3:0] WSEQ_DATA_WIDTH374 [2:0] WSEQ_DELAY374 [3:0] WSEQ_DATA_WIDTH375 [2:0] WSEQ_DELAY375 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA340 [7:0] 0000F000h WSEQ_ADDR341 [12:0] WSEQ_DATA_START341 [3:0] WSEQ_DATA341 [7:0] 0000F000h WSEQ_ADDR342 [12:0] WSEQ_DATA_START342 [3:0] WSEQ_DATA342 [7:0] 0000F000h WSEQ_ADDR343 [12:0] WSEQ_DATA_START343 [3:0] WSEQ_DATA343 [7:0] 0000F000h WSEQ_ADDR344 [12:0] WSEQ_DATA_START344 [3:0] WSEQ_DATA344 [7:0] 0000F000h WSEQ_ADDR345 [12:0] WSEQ_DATA_START345 [3:0] WSEQ_DATA345 [7:0] 0000F000h WSEQ_ADDR346 [12:0] WSEQ_DATA_START346 [3:0] WSEQ_DATA346 [7:0] 0000F000h WSEQ_ADDR347 [12:0] WSEQ_DATA_START347 [3:0] WSEQ_DATA347 [7:0] 0000F000h WSEQ_ADDR348 [12:0] WSEQ_DATA_START348 [3:0] WSEQ_DATA348 [7:0] 0000F000h WSEQ_ADDR349 [12:0] WSEQ_DATA_START349 [3:0] WSEQ_DATA349 [7:0] 0000F000h WSEQ_ADDR350 [12:0] WSEQ_DATA_START350 [3:0] WSEQ_DATA350 [7:0] 0000F000h WSEQ_ADDR351 [12:0] WSEQ_DATA_START351 [3:0] WSEQ_DATA351 [7:0] 0000F000h WSEQ_ADDR352 [12:0] WSEQ_DATA_START352 [3:0] WSEQ_DATA352 [7:0] 0000F000h WSEQ_ADDR353 [12:0] WSEQ_DATA_START353 [3:0] WSEQ_DATA353 [7:0] 0000F000h WSEQ_ADDR354 [12:0] WSEQ_DATA_START354 [3:0] WSEQ_DATA354 [7:0] 0000F000h WSEQ_ADDR355 [12:0] WSEQ_DATA_START355 [3:0] WSEQ_DATA355 [7:0] 0000F000h WSEQ_ADDR356 [12:0] WSEQ_DATA_START356 [3:0] WSEQ_DATA356 [7:0] 0000F000h WSEQ_ADDR357 [12:0] WSEQ_DATA_START357 [3:0] WSEQ_DATA357 [7:0] 0000F000h WSEQ_ADDR358 [12:0] WSEQ_DATA_START358 [3:0] WSEQ_DATA358 [7:0] 0000F000h WSEQ_ADDR359 [12:0] WSEQ_DATA_START359 [3:0] WSEQ_DATA359 [7:0] 0000F000h WSEQ_ADDR360 [12:0] WSEQ_DATA_START360 [3:0] WSEQ_DATA360 [7:0] 0000F000h WSEQ_ADDR361 [12:0] WSEQ_DATA_START361 [3:0] WSEQ_DATA361 [7:0] 0000F000h WSEQ_ADDR362 [12:0] WSEQ_DATA_START362 [3:0] WSEQ_DATA362 [7:0] 0000F000h WSEQ_ADDR363 [12:0] WSEQ_DATA_START363 [3:0] WSEQ_DATA363 [7:0] 0000F000h WSEQ_ADDR364 [12:0] WSEQ_DATA_START364 [3:0] WSEQ_DATA364 [7:0] 0000F000h WSEQ_ADDR365 [12:0] WSEQ_DATA_START365 [3:0] WSEQ_DATA365 [7:0] 0000F000h WSEQ_ADDR366 [12:0] WSEQ_DATA_START366 [3:0] WSEQ_DATA366 [7:0] 0000F000h WSEQ_ADDR367 [12:0] WSEQ_DATA_START367 [3:0] WSEQ_DATA367 [7:0] 0000F000h WSEQ_ADDR368 [12:0] WSEQ_DATA_START368 [3:0] WSEQ_DATA368 [7:0] 0000F000h WSEQ_ADDR369 [12:0] WSEQ_DATA_START369 [3:0] WSEQ_DATA369 [7:0] 0000F000h WSEQ_ADDR370 [12:0] WSEQ_DATA_START370 [3:0] WSEQ_DATA370 [7:0] 0000F000h WSEQ_ADDR371 [12:0] WSEQ_DATA_START371 [3:0] WSEQ_DATA371 [7:0] 0000F000h WSEQ_ADDR372 [12:0] WSEQ_DATA_START372 [3:0] WSEQ_DATA372 [7:0] 0000F000h WSEQ_ADDR373 [12:0] WSEQ_DATA_START373 [3:0] WSEQ_DATA373 [7:0] 0000F000h WSEQ_ADDR374 [12:0] WSEQ_DATA_START374 [3:0] WSEQ_DATA374 [7:0] 0000F000h WSEQ_ADDR375 [12:0] WSEQ_DATA_START375 [3:0] 17 1 0000F000h WSEQ_ADDR340 [12:0] WSEQ_DATA_START340 [3:0] 18 2 WSEQ_DATA375 [7:0] 321 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R13040 WSEQ_Sequence_377 (32F0h) R13042 WSEQ_Sequence_378 (32F2h) R13044 WSEQ_Sequence_379 (32F4h) R13046 WSEQ_Sequence_380 (32F6h) R13048 WSEQ_Sequence_381 (32F8h) R13050 WSEQ_Sequence_382 (32FAh) R13052 WSEQ_Sequence_383 (32FCh) R13054 WSEQ_Sequence_384 (32FEh) R13056 WSEQ_Sequence_385 (3300h) R13058 WSEQ_Sequence_386 (3302h) R13060 WSEQ_Sequence_387 (3304h) R13062 WSEQ_Sequence_388 (3306h) R13064 WSEQ_Sequence_389 (3308h) R13066 WSEQ_Sequence_390 (330Ah) R13068 WSEQ_Sequence_391 (330Ch) R13070 WSEQ_Sequence_392 (330Eh) R13072 WSEQ_Sequence_393 (3310h) R13074 WSEQ_Sequence_394 (3312h) R13076 WSEQ_Sequence_395 (3314h) R13078 WSEQ_Sequence_396 (3316h) R13080 WSEQ_Sequence_397 (3318h) R13082 WSEQ_Sequence_398 (331Ah) R13084 WSEQ_Sequence_399 (331Ch) R13086 WSEQ_Sequence_400 (331Eh) R13088 WSEQ_Sequence_401 (3320h) R13090 WSEQ_Sequence_402 (3322h) R13092 WSEQ_Sequence_403 (3324h) R13094 WSEQ_Sequence_404 (3326h) R13096 WSEQ_Sequence_405 (3328h) R13098 WSEQ_Sequence_406 (332Ah) R13100 WSEQ_Sequence_407 (332Ch) R13102 WSEQ_Sequence_408 (332Eh) R13104 WSEQ_Sequence_409 (3330h) R13106 WSEQ_Sequence_410 (3332h) R13108 WSEQ_Sequence_411 (3334h) R13110 WSEQ_Sequence_412 (3336h) 322 31 15 30 14 29 13 WSEQ_DATA_WIDTH376 [2:0] WSEQ_DELAY376 [3:0] WSEQ_DATA_WIDTH377 [2:0] WSEQ_DELAY377 [3:0] WSEQ_DATA_WIDTH378 [2:0] WSEQ_DELAY378 [3:0] WSEQ_DATA_WIDTH379 [2:0] WSEQ_DELAY379 [3:0] WSEQ_DATA_WIDTH380 [2:0] WSEQ_DELAY380 [3:0] WSEQ_DATA_WIDTH381 [2:0] WSEQ_DELAY381 [3:0] WSEQ_DATA_WIDTH382 [2:0] WSEQ_DELAY382 [3:0] WSEQ_DATA_WIDTH383 [2:0] WSEQ_DELAY383 [3:0] WSEQ_DATA_WIDTH384 [2:0] WSEQ_DELAY384 [3:0] WSEQ_DATA_WIDTH385 [2:0] WSEQ_DELAY385 [3:0] WSEQ_DATA_WIDTH386 [2:0] WSEQ_DELAY386 [3:0] WSEQ_DATA_WIDTH387 [2:0] WSEQ_DELAY387 [3:0] WSEQ_DATA_WIDTH388 [2:0] WSEQ_DELAY388 [3:0] WSEQ_DATA_WIDTH389 [2:0] WSEQ_DELAY389 [3:0] WSEQ_DATA_WIDTH390 [2:0] WSEQ_DELAY390 [3:0] WSEQ_DATA_WIDTH391 [2:0] WSEQ_DELAY391 [3:0] WSEQ_DATA_WIDTH392 [2:0] WSEQ_DELAY392 [3:0] WSEQ_DATA_WIDTH393 [2:0] WSEQ_DELAY393 [3:0] WSEQ_DATA_WIDTH394 [2:0] WSEQ_DELAY394 [3:0] WSEQ_DATA_WIDTH395 [2:0] WSEQ_DELAY395 [3:0] WSEQ_DATA_WIDTH396 [2:0] WSEQ_DELAY396 [3:0] WSEQ_DATA_WIDTH397 [2:0] WSEQ_DELAY397 [3:0] WSEQ_DATA_WIDTH398 [2:0] WSEQ_DELAY398 [3:0] WSEQ_DATA_WIDTH399 [2:0] WSEQ_DELAY399 [3:0] WSEQ_DATA_WIDTH400 [2:0] WSEQ_DELAY400 [3:0] WSEQ_DATA_WIDTH401 [2:0] WSEQ_DELAY401 [3:0] WSEQ_DATA_WIDTH402 [2:0] WSEQ_DELAY402 [3:0] WSEQ_DATA_WIDTH403 [2:0] WSEQ_DELAY403 [3:0] WSEQ_DATA_WIDTH404 [2:0] WSEQ_DELAY404 [3:0] WSEQ_DATA_WIDTH405 [2:0] WSEQ_DELAY405 [3:0] WSEQ_DATA_WIDTH406 [2:0] WSEQ_DELAY406 [3:0] WSEQ_DATA_WIDTH407 [2:0] WSEQ_DELAY407 [3:0] WSEQ_DATA_WIDTH408 [2:0] WSEQ_DELAY408 [3:0] WSEQ_DATA_WIDTH409 [2:0] WSEQ_DELAY409 [3:0] WSEQ_DATA_WIDTH410 [2:0] WSEQ_DELAY410 [3:0] WSEQ_DATA_WIDTH411 [2:0] WSEQ_DELAY411 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA376 [7:0] 0000F000h WSEQ_ADDR377 [12:0] WSEQ_DATA_START377 [3:0] WSEQ_DATA377 [7:0] 0000F000h WSEQ_ADDR378 [12:0] WSEQ_DATA_START378 [3:0] WSEQ_DATA378 [7:0] 0000F000h WSEQ_ADDR379 [12:0] WSEQ_DATA_START379 [3:0] WSEQ_DATA379 [7:0] 0000F000h WSEQ_ADDR380 [12:0] WSEQ_DATA_START380 [3:0] WSEQ_DATA380 [7:0] 0000F000h WSEQ_ADDR381 [12:0] WSEQ_DATA_START381 [3:0] WSEQ_DATA381 [7:0] 0000F000h WSEQ_ADDR382 [12:0] WSEQ_DATA_START382 [3:0] WSEQ_DATA382 [7:0] 0000F000h WSEQ_ADDR383 [12:0] WSEQ_DATA_START383 [3:0] WSEQ_DATA383 [7:0] FFFFFFFFh WSEQ_ADDR384 [12:0] WSEQ_DATA_START384 [3:0] WSEQ_DATA384 [7:0] FFFFFFFFh WSEQ_ADDR385 [12:0] WSEQ_DATA_START385 [3:0] WSEQ_DATA385 [7:0] FFFFFFFFh WSEQ_ADDR386 [12:0] WSEQ_DATA_START386 [3:0] WSEQ_DATA386 [7:0] FFFFFFFFh WSEQ_ADDR387 [12:0] WSEQ_DATA_START387 [3:0] WSEQ_DATA387 [7:0] FFFFFFFFh WSEQ_ADDR388 [12:0] WSEQ_DATA_START388 [3:0] WSEQ_DATA388 [7:0] FFFFFFFFh WSEQ_ADDR389 [12:0] WSEQ_DATA_START389 [3:0] WSEQ_DATA389 [7:0] FFFFFFFFh WSEQ_ADDR390 [12:0] WSEQ_DATA_START390 [3:0] WSEQ_DATA390 [7:0] FFFFFFFFh WSEQ_ADDR391 [12:0] WSEQ_DATA_START391 [3:0] WSEQ_DATA391 [7:0] FFFFFFFFh WSEQ_ADDR392 [12:0] WSEQ_DATA_START392 [3:0] WSEQ_DATA392 [7:0] FFFFFFFFh WSEQ_ADDR393 [12:0] WSEQ_DATA_START393 [3:0] WSEQ_DATA393 [7:0] FFFFFFFFh WSEQ_ADDR394 [12:0] WSEQ_DATA_START394 [3:0] WSEQ_DATA394 [7:0] FFFFFFFFh WSEQ_ADDR395 [12:0] WSEQ_DATA_START395 [3:0] WSEQ_DATA395 [7:0] FFFFFFFFh WSEQ_ADDR396 [12:0] WSEQ_DATA_START396 [3:0] WSEQ_DATA396 [7:0] FFFFFFFFh WSEQ_ADDR397 [12:0] WSEQ_DATA_START397 [3:0] WSEQ_DATA397 [7:0] FFFFFFFFh WSEQ_ADDR398 [12:0] WSEQ_DATA_START398 [3:0] WSEQ_DATA398 [7:0] FFFFFFFFh WSEQ_ADDR399 [12:0] WSEQ_DATA_START399 [3:0] WSEQ_DATA399 [7:0] FFFFFFFFh WSEQ_ADDR400 [12:0] WSEQ_DATA_START400 [3:0] WSEQ_DATA400 [7:0] FFFFFFFFh WSEQ_ADDR401 [12:0] WSEQ_DATA_START401 [3:0] WSEQ_DATA401 [7:0] FFFFFFFFh WSEQ_ADDR402 [12:0] WSEQ_DATA_START402 [3:0] WSEQ_DATA402 [7:0] FFFFFFFFh WSEQ_ADDR403 [12:0] WSEQ_DATA_START403 [3:0] WSEQ_DATA403 [7:0] FFFFFFFFh WSEQ_ADDR404 [12:0] WSEQ_DATA_START404 [3:0] WSEQ_DATA404 [7:0] FFFFFFFFh WSEQ_ADDR405 [12:0] WSEQ_DATA_START405 [3:0] WSEQ_DATA405 [7:0] FFFFFFFFh WSEQ_ADDR406 [12:0] WSEQ_DATA_START406 [3:0] WSEQ_DATA406 [7:0] FFFFFFFFh WSEQ_ADDR407 [12:0] WSEQ_DATA_START407 [3:0] WSEQ_DATA407 [7:0] FFFFFFFFh WSEQ_ADDR408 [12:0] WSEQ_DATA_START408 [3:0] WSEQ_DATA408 [7:0] FFFFFFFFh WSEQ_ADDR409 [12:0] WSEQ_DATA_START409 [3:0] WSEQ_DATA409 [7:0] FFFFFFFFh WSEQ_ADDR410 [12:0] WSEQ_DATA_START410 [3:0] WSEQ_DATA410 [7:0] FFFFFFFFh WSEQ_ADDR411 [12:0] WSEQ_DATA_START411 [3:0] 17 1 0000F000h WSEQ_ADDR376 [12:0] WSEQ_DATA_START376 [3:0] 18 2 WSEQ_DATA411 [7:0] DS1162F1 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R13112 WSEQ_Sequence_413 (3338h) R13114 WSEQ_Sequence_414 (333Ah) R13116 WSEQ_Sequence_415 (333Ch) R13118 WSEQ_Sequence_416 (333Eh) R13120 WSEQ_Sequence_417 (3340h) R13122 WSEQ_Sequence_418 (3342h) R13124 WSEQ_Sequence_419 (3344h) R13126 WSEQ_Sequence_420 (3346h) R13128 WSEQ_Sequence_421 (3348h) R13130 WSEQ_Sequence_422 (334Ah) R13132 WSEQ_Sequence_423 (334Ch) R13134 WSEQ_Sequence_424 (334Eh) R13136 WSEQ_Sequence_425 (3350h) R13138 WSEQ_Sequence_426 (3352h) R13140 WSEQ_Sequence_427 (3354h) R13142 WSEQ_Sequence_428 (3356h) R13144 WSEQ_Sequence_429 (3358h) R13146 WSEQ_Sequence_430 (335Ah) R13148 WSEQ_Sequence_431 (335Ch) R13150 WSEQ_Sequence_432 (335Eh) R13152 WSEQ_Sequence_433 (3360h) R13154 WSEQ_Sequence_434 (3362h) R13156 WSEQ_Sequence_435 (3364h) R13158 WSEQ_Sequence_436 (3366h) R13160 WSEQ_Sequence_437 (3368h) R13162 WSEQ_Sequence_438 (336Ah) R13164 WSEQ_Sequence_439 (336Ch) R13166 WSEQ_Sequence_440 (336Eh) R13168 WSEQ_Sequence_441 (3370h) R13170 WSEQ_Sequence_442 (3372h) R13172 WSEQ_Sequence_443 (3374h) R13174 WSEQ_Sequence_444 (3376h) R13176 WSEQ_Sequence_445 (3378h) R13178 WSEQ_Sequence_446 (337Ah) R13180 WSEQ_Sequence_447 (337Ch) R13182 WSEQ_Sequence_448 (337Eh) DS1162F1 31 15 30 14 29 13 WSEQ_DATA_WIDTH412 [2:0] WSEQ_DELAY412 [3:0] WSEQ_DATA_WIDTH413 [2:0] WSEQ_DELAY413 [3:0] WSEQ_DATA_WIDTH414 [2:0] WSEQ_DELAY414 [3:0] WSEQ_DATA_WIDTH415 [2:0] WSEQ_DELAY415 [3:0] WSEQ_DATA_WIDTH416 [2:0] WSEQ_DELAY416 [3:0] WSEQ_DATA_WIDTH417 [2:0] WSEQ_DELAY417 [3:0] WSEQ_DATA_WIDTH418 [2:0] WSEQ_DELAY418 [3:0] WSEQ_DATA_WIDTH419 [2:0] WSEQ_DELAY419 [3:0] WSEQ_DATA_WIDTH420 [2:0] WSEQ_DELAY420 [3:0] WSEQ_DATA_WIDTH421 [2:0] WSEQ_DELAY421 [3:0] WSEQ_DATA_WIDTH422 [2:0] WSEQ_DELAY422 [3:0] WSEQ_DATA_WIDTH423 [2:0] WSEQ_DELAY423 [3:0] WSEQ_DATA_WIDTH424 [2:0] WSEQ_DELAY424 [3:0] WSEQ_DATA_WIDTH425 [2:0] WSEQ_DELAY425 [3:0] WSEQ_DATA_WIDTH426 [2:0] WSEQ_DELAY426 [3:0] WSEQ_DATA_WIDTH427 [2:0] WSEQ_DELAY427 [3:0] WSEQ_DATA_WIDTH428 [2:0] WSEQ_DELAY428 [3:0] WSEQ_DATA_WIDTH429 [2:0] WSEQ_DELAY429 [3:0] WSEQ_DATA_WIDTH430 [2:0] WSEQ_DELAY430 [3:0] WSEQ_DATA_WIDTH431 [2:0] WSEQ_DELAY431 [3:0] WSEQ_DATA_WIDTH432 [2:0] WSEQ_DELAY432 [3:0] WSEQ_DATA_WIDTH433 [2:0] WSEQ_DELAY433 [3:0] WSEQ_DATA_WIDTH434 [2:0] WSEQ_DELAY434 [3:0] WSEQ_DATA_WIDTH435 [2:0] WSEQ_DELAY435 [3:0] WSEQ_DATA_WIDTH436 [2:0] WSEQ_DELAY436 [3:0] WSEQ_DATA_WIDTH437 [2:0] WSEQ_DELAY437 [3:0] WSEQ_DATA_WIDTH438 [2:0] WSEQ_DELAY438 [3:0] WSEQ_DATA_WIDTH439 [2:0] WSEQ_DELAY439 [3:0] WSEQ_DATA_WIDTH440 [2:0] WSEQ_DELAY440 [3:0] WSEQ_DATA_WIDTH441 [2:0] WSEQ_DELAY441 [3:0] WSEQ_DATA_WIDTH442 [2:0] WSEQ_DELAY442 [3:0] WSEQ_DATA_WIDTH443 [2:0] WSEQ_DELAY443 [3:0] WSEQ_DATA_WIDTH444 [2:0] WSEQ_DELAY444 [3:0] WSEQ_DATA_WIDTH445 [2:0] WSEQ_DELAY445 [3:0] WSEQ_DATA_WIDTH446 [2:0] WSEQ_DELAY446 [3:0] WSEQ_DATA_WIDTH447 [2:0] WSEQ_DELAY447 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA412 [7:0] FFFFFFFFh WSEQ_ADDR413 [12:0] WSEQ_DATA_START413 [3:0] WSEQ_DATA413 [7:0] FFFFFFFFh WSEQ_ADDR414 [12:0] WSEQ_DATA_START414 [3:0] WSEQ_DATA414 [7:0] FFFFFFFFh WSEQ_ADDR415 [12:0] WSEQ_DATA_START415 [3:0] WSEQ_DATA415 [7:0] FFFFFFFFh WSEQ_ADDR416 [12:0] WSEQ_DATA_START416 [3:0] WSEQ_DATA416 [7:0] FFFFFFFFh WSEQ_ADDR417 [12:0] WSEQ_DATA_START417 [3:0] WSEQ_DATA417 [7:0] FFFFFFFFh WSEQ_ADDR418 [12:0] WSEQ_DATA_START418 [3:0] WSEQ_DATA418 [7:0] FFFFFFFFh WSEQ_ADDR419 [12:0] WSEQ_DATA_START419 [3:0] WSEQ_DATA419 [7:0] FFFFFFFFh WSEQ_ADDR420 [12:0] WSEQ_DATA_START420 [3:0] WSEQ_DATA420 [7:0] FFFFFFFFh WSEQ_ADDR421 [12:0] WSEQ_DATA_START421 [3:0] WSEQ_DATA421 [7:0] FFFFFFFFh WSEQ_ADDR422 [12:0] WSEQ_DATA_START422 [3:0] WSEQ_DATA422 [7:0] FFFFFFFFh WSEQ_ADDR423 [12:0] WSEQ_DATA_START423 [3:0] WSEQ_DATA423 [7:0] FFFFFFFFh WSEQ_ADDR424 [12:0] WSEQ_DATA_START424 [3:0] WSEQ_DATA424 [7:0] FFFFFFFFh WSEQ_ADDR425 [12:0] WSEQ_DATA_START425 [3:0] WSEQ_DATA425 [7:0] FFFFFFFFh WSEQ_ADDR426 [12:0] WSEQ_DATA_START426 [3:0] WSEQ_DATA426 [7:0] FFFFFFFFh WSEQ_ADDR427 [12:0] WSEQ_DATA_START427 [3:0] WSEQ_DATA427 [7:0] FFFFFFFFh WSEQ_ADDR428 [12:0] WSEQ_DATA_START428 [3:0] WSEQ_DATA428 [7:0] FFFFFFFFh WSEQ_ADDR429 [12:0] WSEQ_DATA_START429 [3:0] WSEQ_DATA429 [7:0] FFFFFFFFh WSEQ_ADDR430 [12:0] WSEQ_DATA_START430 [3:0] WSEQ_DATA430 [7:0] FFFFFFFFh WSEQ_ADDR431 [12:0] WSEQ_DATA_START431 [3:0] WSEQ_DATA431 [7:0] FFFFFFFFh WSEQ_ADDR432 [12:0] WSEQ_DATA_START432 [3:0] WSEQ_DATA432 [7:0] FFFFFFFFh WSEQ_ADDR433 [12:0] WSEQ_DATA_START433 [3:0] WSEQ_DATA433 [7:0] FFFFFFFFh WSEQ_ADDR434 [12:0] WSEQ_DATA_START434 [3:0] WSEQ_DATA434 [7:0] FFFFFFFFh WSEQ_ADDR435 [12:0] WSEQ_DATA_START435 [3:0] WSEQ_DATA435 [7:0] FFFFFFFFh WSEQ_ADDR436 [12:0] WSEQ_DATA_START436 [3:0] WSEQ_DATA436 [7:0] FFFFFFFFh WSEQ_ADDR437 [12:0] WSEQ_DATA_START437 [3:0] WSEQ_DATA437 [7:0] FFFFFFFFh WSEQ_ADDR438 [12:0] WSEQ_DATA_START438 [3:0] WSEQ_DATA438 [7:0] FFFFFFFFh WSEQ_ADDR439 [12:0] WSEQ_DATA_START439 [3:0] WSEQ_DATA439 [7:0] FFFFFFFFh WSEQ_ADDR440 [12:0] WSEQ_DATA_START440 [3:0] WSEQ_DATA440 [7:0] FFFFFFFFh WSEQ_ADDR441 [12:0] WSEQ_DATA_START441 [3:0] WSEQ_DATA441 [7:0] FFFFFFFFh WSEQ_ADDR442 [12:0] WSEQ_DATA_START442 [3:0] WSEQ_DATA442 [7:0] FFFFFFFFh WSEQ_ADDR443 [12:0] WSEQ_DATA_START443 [3:0] WSEQ_DATA443 [7:0] FFFFFFFFh WSEQ_ADDR444 [12:0] WSEQ_DATA_START444 [3:0] WSEQ_DATA444 [7:0] FFFFFFFFh WSEQ_ADDR445 [12:0] WSEQ_DATA_START445 [3:0] WSEQ_DATA445 [7:0] FFFFFFFFh WSEQ_ADDR446 [12:0] WSEQ_DATA_START446 [3:0] WSEQ_DATA446 [7:0] FFFFFFFFh WSEQ_ADDR447 [12:0] WSEQ_DATA_START447 [3:0] 17 1 FFFFFFFFh WSEQ_ADDR412 [12:0] WSEQ_DATA_START412 [3:0] 18 2 WSEQ_DATA447 [7:0] 323 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R13184 WSEQ_Sequence_449 (3380h) R13186 WSEQ_Sequence_450 (3382h) R13188 WSEQ_Sequence_451 (3384h) R13190 WSEQ_Sequence_452 (3386h) R13192 WSEQ_Sequence_453 (3388h) R13194 WSEQ_Sequence_454 (338Ah) R13196 WSEQ_Sequence_455 (338Ch) R13198 WSEQ_Sequence_456 (338Eh) R13200 WSEQ_Sequence_457 (3390h) R13202 WSEQ_Sequence_458 (3392h) R13204 WSEQ_Sequence_459 (3394h) R13206 WSEQ_Sequence_460 (3396h) R13208 WSEQ_Sequence_461 (3398h) R13210 WSEQ_Sequence_462 (339Ah) R13212 WSEQ_Sequence_463 (339Ch) R13214 WSEQ_Sequence_464 (339Eh) R13216 WSEQ_Sequence_465 (33A0h) R13218 WSEQ_Sequence_466 (33A2h) R13220 WSEQ_Sequence_467 (33A4h) R13222 WSEQ_Sequence_468 (33A6h) R13224 WSEQ_Sequence_469 (33A8h) R13226 WSEQ_Sequence_470 (33AAh) R13228 WSEQ_Sequence_471 (33ACh) R13230 WSEQ_Sequence_472 (33AEh) R13232 WSEQ_Sequence_473 (33B0h) R13234 WSEQ_Sequence_474 (33B2h) R13236 WSEQ_Sequence_475 (33B4h) R13238 WSEQ_Sequence_476 (33B6h) R13240 WSEQ_Sequence_477 (33B8h) R13242 WSEQ_Sequence_478 (33BAh) R13244 WSEQ_Sequence_479 (33BCh) R13246 WSEQ_Sequence_480 (33BEh) R13248 WSEQ_Sequence_481 (33C0h) R13250 WSEQ_Sequence_482 (33C2h) R13252 WSEQ_Sequence_483 (33C4h) R13254 WSEQ_Sequence_484 (33C6h) 324 31 15 30 14 29 13 WSEQ_DATA_WIDTH448 [2:0] WSEQ_DELAY448 [3:0] WSEQ_DATA_WIDTH449 [2:0] WSEQ_DELAY449 [3:0] WSEQ_DATA_WIDTH450 [2:0] WSEQ_DELAY450 [3:0] WSEQ_DATA_WIDTH451 [2:0] WSEQ_DELAY451 [3:0] WSEQ_DATA_WIDTH452 [2:0] WSEQ_DELAY452 [3:0] WSEQ_DATA_WIDTH453 [2:0] WSEQ_DELAY453 [3:0] WSEQ_DATA_WIDTH454 [2:0] WSEQ_DELAY454 [3:0] WSEQ_DATA_WIDTH455 [2:0] WSEQ_DELAY455 [3:0] WSEQ_DATA_WIDTH456 [2:0] WSEQ_DELAY456 [3:0] WSEQ_DATA_WIDTH457 [2:0] WSEQ_DELAY457 [3:0] WSEQ_DATA_WIDTH458 [2:0] WSEQ_DELAY458 [3:0] WSEQ_DATA_WIDTH459 [2:0] WSEQ_DELAY459 [3:0] WSEQ_DATA_WIDTH460 [2:0] WSEQ_DELAY460 [3:0] WSEQ_DATA_WIDTH461 [2:0] WSEQ_DELAY461 [3:0] WSEQ_DATA_WIDTH462 [2:0] WSEQ_DELAY462 [3:0] WSEQ_DATA_WIDTH463 [2:0] WSEQ_DELAY463 [3:0] WSEQ_DATA_WIDTH464 [2:0] WSEQ_DELAY464 [3:0] WSEQ_DATA_WIDTH465 [2:0] WSEQ_DELAY465 [3:0] WSEQ_DATA_WIDTH466 [2:0] WSEQ_DELAY466 [3:0] WSEQ_DATA_WIDTH467 [2:0] WSEQ_DELAY467 [3:0] WSEQ_DATA_WIDTH468 [2:0] WSEQ_DELAY468 [3:0] WSEQ_DATA_WIDTH469 [2:0] WSEQ_DELAY469 [3:0] WSEQ_DATA_WIDTH470 [2:0] WSEQ_DELAY470 [3:0] WSEQ_DATA_WIDTH471 [2:0] WSEQ_DELAY471 [3:0] WSEQ_DATA_WIDTH472 [2:0] WSEQ_DELAY472 [3:0] WSEQ_DATA_WIDTH473 [2:0] WSEQ_DELAY473 [3:0] WSEQ_DATA_WIDTH474 [2:0] WSEQ_DELAY474 [3:0] WSEQ_DATA_WIDTH475 [2:0] WSEQ_DELAY475 [3:0] WSEQ_DATA_WIDTH476 [2:0] WSEQ_DELAY476 [3:0] WSEQ_DATA_WIDTH477 [2:0] WSEQ_DELAY477 [3:0] WSEQ_DATA_WIDTH478 [2:0] WSEQ_DELAY478 [3:0] WSEQ_DATA_WIDTH479 [2:0] WSEQ_DELAY479 [3:0] WSEQ_DATA_WIDTH480 [2:0] WSEQ_DELAY480 [3:0] WSEQ_DATA_WIDTH481 [2:0] WSEQ_DELAY481 [3:0] WSEQ_DATA_WIDTH482 [2:0] WSEQ_DELAY482 [3:0] WSEQ_DATA_WIDTH483 [2:0] WSEQ_DELAY483 [3:0] 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 16 0 Default WSEQ_DATA448 [7:0] FFFFFFFFh WSEQ_ADDR449 [12:0] WSEQ_DATA_START449 [3:0] WSEQ_DATA449 [7:0] FFFFFFFFh WSEQ_ADDR450 [12:0] WSEQ_DATA_START450 [3:0] WSEQ_DATA450 [7:0] FFFFFFFFh WSEQ_ADDR451 [12:0] WSEQ_DATA_START451 [3:0] WSEQ_DATA451 [7:0] FFFFFFFFh WSEQ_ADDR452 [12:0] WSEQ_DATA_START452 [3:0] WSEQ_DATA452 [7:0] FFFFFFFFh WSEQ_ADDR453 [12:0] WSEQ_DATA_START453 [3:0] WSEQ_DATA453 [7:0] FFFFFFFFh WSEQ_ADDR454 [12:0] WSEQ_DATA_START454 [3:0] WSEQ_DATA454 [7:0] FFFFFFFFh WSEQ_ADDR455 [12:0] WSEQ_DATA_START455 [3:0] WSEQ_DATA455 [7:0] FFFFFFFFh WSEQ_ADDR456 [12:0] WSEQ_DATA_START456 [3:0] WSEQ_DATA456 [7:0] FFFFFFFFh WSEQ_ADDR457 [12:0] WSEQ_DATA_START457 [3:0] WSEQ_DATA457 [7:0] FFFFFFFFh WSEQ_ADDR458 [12:0] WSEQ_DATA_START458 [3:0] WSEQ_DATA458 [7:0] FFFFFFFFh WSEQ_ADDR459 [12:0] WSEQ_DATA_START459 [3:0] WSEQ_DATA459 [7:0] FFFFFFFFh WSEQ_ADDR460 [12:0] WSEQ_DATA_START460 [3:0] WSEQ_DATA460 [7:0] FFFFFFFFh WSEQ_ADDR461 [12:0] WSEQ_DATA_START461 [3:0] WSEQ_DATA461 [7:0] FFFFFFFFh WSEQ_ADDR462 [12:0] WSEQ_DATA_START462 [3:0] WSEQ_DATA462 [7:0] FFFFFFFFh WSEQ_ADDR463 [12:0] WSEQ_DATA_START463 [3:0] WSEQ_DATA463 [7:0] FFFFFFFFh WSEQ_ADDR464 [12:0] WSEQ_DATA_START464 [3:0] WSEQ_DATA464 [7:0] FFFFFFFFh WSEQ_ADDR465 [12:0] WSEQ_DATA_START465 [3:0] WSEQ_DATA465 [7:0] FFFFFFFFh WSEQ_ADDR466 [12:0] WSEQ_DATA_START466 [3:0] WSEQ_DATA466 [7:0] FFFFFFFFh WSEQ_ADDR467 [12:0] WSEQ_DATA_START467 [3:0] WSEQ_DATA467 [7:0] FFFFFFFFh WSEQ_ADDR468 [12:0] WSEQ_DATA_START468 [3:0] WSEQ_DATA468 [7:0] FFFFFFFFh WSEQ_ADDR469 [12:0] WSEQ_DATA_START469 [3:0] WSEQ_DATA469 [7:0] FFFFFFFFh WSEQ_ADDR470 [12:0] WSEQ_DATA_START470 [3:0] WSEQ_DATA470 [7:0] FFFFFFFFh WSEQ_ADDR471 [12:0] WSEQ_DATA_START471 [3:0] WSEQ_DATA471 [7:0] FFFFFFFFh WSEQ_ADDR472 [12:0] WSEQ_DATA_START472 [3:0] WSEQ_DATA472 [7:0] FFFFFFFFh WSEQ_ADDR473 [12:0] WSEQ_DATA_START473 [3:0] WSEQ_DATA473 [7:0] FFFFFFFFh WSEQ_ADDR474 [12:0] WSEQ_DATA_START474 [3:0] WSEQ_DATA474 [7:0] FFFFFFFFh WSEQ_ADDR475 [12:0] WSEQ_DATA_START475 [3:0] WSEQ_DATA475 [7:0] FFFFFFFFh WSEQ_ADDR476 [12:0] WSEQ_DATA_START476 [3:0] WSEQ_DATA476 [7:0] FFFFFFFFh WSEQ_ADDR477 [12:0] WSEQ_DATA_START477 [3:0] WSEQ_DATA477 [7:0] FFFFFFFFh WSEQ_ADDR478 [12:0] WSEQ_DATA_START478 [3:0] WSEQ_DATA478 [7:0] FFFFFFFFh WSEQ_ADDR479 [12:0] WSEQ_DATA_START479 [3:0] WSEQ_DATA479 [7:0] FFFFFFFFh WSEQ_ADDR480 [12:0] WSEQ_DATA_START480 [3:0] WSEQ_DATA480 [7:0] FFFFFFFFh WSEQ_ADDR481 [12:0] WSEQ_DATA_START481 [3:0] WSEQ_DATA481 [7:0] FFFFFFFFh WSEQ_ADDR482 [12:0] WSEQ_DATA_START482 [3:0] WSEQ_DATA482 [7:0] FFFFFFFFh WSEQ_ADDR483 [12:0] WSEQ_DATA_START483 [3:0] 17 1 FFFFFFFFh WSEQ_ADDR448 [12:0] WSEQ_DATA_START448 [3:0] 18 2 WSEQ_DATA483 [7:0] DS1162F1 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R13256 WSEQ_Sequence_485 (33C8h) R13258 WSEQ_Sequence_486 (33CAh) R13260 WSEQ_Sequence_487 (33CCh) R13262 WSEQ_Sequence_488 (33CEh) R13264 WSEQ_Sequence_489 (33D0h) R13266 WSEQ_Sequence_490 (33D2h) R13268 WSEQ_Sequence_491 (33D4h) R13270 WSEQ_Sequence_492 (33D6h) R13272 WSEQ_Sequence_493 (33D8h) R13274 WSEQ_Sequence_494 (33DAh) R13276 WSEQ_Sequence_495 (33DCh) R13278 WSEQ_Sequence_496 (33DEh) R13280 WSEQ_Sequence_497 (33E0h) R13282 WSEQ_Sequence_498 (33E2h) R13284 WSEQ_Sequence_499 (33E4h) R13286 WSEQ_Sequence_500 (33E6h) R13288 WSEQ_Sequence_501 (33E8h) R13290 WSEQ_Sequence_502 (33EAh) R13292 WSEQ_Sequence_503 (33ECh) R13294 WSEQ_Sequence_504 (33EEh) R13296 WSEQ_Sequence_505 (33F0h) R13298 WSEQ_Sequence_506 (33F2h) R13300 WSEQ_Sequence_507 (33F4h) R13302 WSEQ_Sequence_508 (33F6h) R131076 OTP_HPDET_Cal_1 (20004h) R131078 OTP_HPDET_Cal_2 (20006h) R294912 EVENTLOG1_ (48000h) CONTROL 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 WSEQ_DATA_WIDTH484 [2:0] WSEQ_DELAY484 [3:0] WSEQ_DATA_START484 [3:0] WSEQ_DATA_WIDTH485 [2:0] WSEQ_DELAY485 [3:0] WSEQ_DATA_START485 [3:0] WSEQ_DATA_WIDTH486 [2:0] WSEQ_DELAY486 [3:0] WSEQ_DATA_START486 [3:0] WSEQ_DATA_WIDTH487 [2:0] WSEQ_DELAY487 [3:0] WSEQ_DATA_START487 [3:0] WSEQ_DATA_WIDTH488 [2:0] WSEQ_DELAY488 [3:0] WSEQ_DATA_START488 [3:0] WSEQ_DATA_WIDTH489 [2:0] WSEQ_DELAY489 [3:0] WSEQ_DATA_START489 [3:0] WSEQ_DATA_WIDTH490 [2:0] WSEQ_DELAY490 [3:0] WSEQ_DATA_START490 [3:0] WSEQ_DATA_WIDTH491 [2:0] WSEQ_DELAY491 [3:0] WSEQ_DATA_START491 [3:0] WSEQ_DATA_WIDTH492 [2:0] WSEQ_DELAY492 [3:0] WSEQ_DATA_START492 [3:0] WSEQ_DATA_WIDTH493 [2:0] WSEQ_DELAY493 [3:0] WSEQ_DATA_START493 [3:0] WSEQ_DATA_WIDTH494 [2:0] WSEQ_DELAY494 [3:0] WSEQ_DATA_START494 [3:0] WSEQ_DATA_WIDTH495 [2:0] WSEQ_DELAY495 [3:0] WSEQ_DATA_START495 [3:0] WSEQ_DATA_WIDTH496 [2:0] WSEQ_DELAY496 [3:0] WSEQ_DATA_START496 [3:0] WSEQ_DATA_WIDTH497 [2:0] WSEQ_DELAY497 [3:0] WSEQ_DATA_START497 [3:0] WSEQ_DATA_WIDTH498 [2:0] WSEQ_DELAY498 [3:0] WSEQ_DATA_START498 [3:0] WSEQ_DATA_WIDTH499 [2:0] WSEQ_DELAY499 [3:0] WSEQ_DATA_START499 [3:0] WSEQ_DATA_WIDTH500 [2:0] WSEQ_DELAY500 [3:0] WSEQ_DATA_START500 [3:0] WSEQ_DATA_WIDTH501 [2:0] WSEQ_DELAY501 [3:0] WSEQ_DATA_START501 [3:0] WSEQ_DATA_WIDTH502 [2:0] WSEQ_DELAY502 [3:0] WSEQ_DATA_START502 [3:0] WSEQ_DATA_WIDTH503 [2:0] WSEQ_DELAY503 [3:0] WSEQ_DATA_START503 [3:0] WSEQ_DATA_WIDTH504 [2:0] WSEQ_DELAY504 [3:0] WSEQ_DATA_START504 [3:0] WSEQ_DATA_WIDTH505 [2:0] WSEQ_DELAY505 [3:0] WSEQ_DATA_START505 [3:0] WSEQ_DATA_WIDTH506 [2:0] WSEQ_DELAY506 [3:0] WSEQ_DATA_START506 [3:0] WSEQ_DATA_WIDTH507 [2:0] WSEQ_DELAY507 [3:0] WSEQ_DATA_START507 [3:0] HP_OFFSET_11 [7:0] HP_OFFSET_01 [7:0] SPARE2 [7:0] HP_GRADIENT_1X [7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 7 22 6 21 5 20 4 Default FFFFFFFFh WSEQ_ADDR485 [12:0] WSEQ_DATA485 [7:0] FFFFFFFFh WSEQ_ADDR486 [12:0] WSEQ_DATA486 [7:0] FFFFFFFFh WSEQ_ADDR487 [12:0] WSEQ_DATA487 [7:0] FFFFFFFFh WSEQ_ADDR488 [12:0] WSEQ_DATA488 [7:0] FFFFFFFFh WSEQ_ADDR489 [12:0] WSEQ_DATA489 [7:0] FFFFFFFFh WSEQ_ADDR490 [12:0] WSEQ_DATA490 [7:0] FFFFFFFFh WSEQ_ADDR491 [12:0] WSEQ_DATA491 [7:0] FFFFFFFFh WSEQ_ADDR492 [12:0] WSEQ_DATA492 [7:0] FFFFFFFFh WSEQ_ADDR493 [12:0] WSEQ_DATA493 [7:0] FFFFFFFFh WSEQ_ADDR494 [12:0] WSEQ_DATA494 [7:0] FFFFFFFFh WSEQ_ADDR495 [12:0] WSEQ_DATA495 [7:0] FFFFFFFFh WSEQ_ADDR496 [12:0] WSEQ_DATA496 [7:0] FFFFFFFFh WSEQ_ADDR497 [12:0] WSEQ_DATA497 [7:0] FFFFFFFFh WSEQ_ADDR498 [12:0] WSEQ_DATA498 [7:0] FFFFFFFFh WSEQ_ADDR499 [12:0] WSEQ_DATA499 [7:0] FFFFFFFFh WSEQ_ADDR500 [12:0] WSEQ_DATA500 [7:0] FFFFFFFFh WSEQ_ADDR501 [12:0] WSEQ_DATA501 [7:0] FFFFFFFFh WSEQ_ADDR502 [12:0] WSEQ_DATA502 [7:0] FFFFFFFFh WSEQ_ADDR503 [12:0] WSEQ_DATA503 [7:0] FFFFFFFFh WSEQ_ADDR504 [12:0] WSEQ_DATA504 [7:0] FFFFFFFFh WSEQ_ADDR505 [12:0] WSEQ_DATA505 [7:0] FFFFFFFFh WSEQ_ADDR506 [12:0] WSEQ_DATA506 [7:0] FFFFFFFFh WSEQ_ADDR507 [12:0] 0 0 0 0 0 0 WSEQ_DATA507 [7:0] HP_OFFSET_10 [7:0] HP_OFFSET_00 [7:0] SPARE1 [7:0] HP_GRADIENT_0X [7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R294924 EVENTLOG1_FIFO_ (4800Ch) CONTROL1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTLO G1_CH8_ ENA 0 EVENTLO G1_CH8_ STS 0 0 EVENTLO G1_CH7_ ENA 0 EVENTLO G1_CH7_ STS 0 0 EVENTLO G1_CH6_ ENA 0 EVENTLO G1_CH6_ STS 0 0 EVENTLO G1_CH5_ ENA 0 EVENTLO G1_CH5_ STS DS1162F1 16 0 FFFFFFFFh 0 0 0 0 0 0 EVENTLOG1_FIFO_WPTR [3:0] 0 0 0 0 0 0 0 0 EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO G1_CH16_ G1_CH15_ G1_CH14_ G1_CH13_ G1_CH12_ G1_CH11_ G1_CH10_ G1_CH9_ ENA ENA ENA ENA ENA ENA ENA ENA 0 0 0 0 0 0 0 0 R294948 EVENTLOG1_EVENT_ (48024h) STATUS EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO G1_CH16_ G1_CH15_ G1_CH14_ G1_CH13_ G1_CH12_ G1_CH11_ G1_CH10_ G1_CH9_ STS STS STS STS STS STS STS STS 17 1 WSEQ_DATA484 [7:0] 0 0 R294944 EVENTLOG1_CH_ (48020h) ENABLE1 18 2 WSEQ_ADDR484 [12:0] R294916 EVENTLOG1_TIMER_ (48004h) SEL R294926 EVENTLOG1_FIFO_ (4800Eh) POINTER1 19 3 00000000h 00000000h 0 0 0 0 EVENTLO EVENTLO G1_RST G1_ENA 0 0 0 0 0 0 EVENTLOG1_ TIMER_SEL [1:0] 0 0 0 0 EVENTLOG1_FIFO_WMARK [3:0] 0 EVENTLO EVENTLO EVENTLO G1_FULL G1_ G1_NOT_ WMARK_ EMPTY STS EVENTLOG1_FIFO_RPTR [3:0] 0 0 0 0 EVENTLO EVENTLO EVENTLO EVENTLO G1_CH4_ G1_CH3_ G1_CH2_ G1_CH1_ ENA ENA ENA ENA 0 0 0 0 EVENTLO EVENTLO EVENTLO EVENTLO G1_CH4_ G1_CH3_ G1_CH2_ G1_CH1_ STS STS STS STS 00000000h 00000000h 00000001h 00000000h 00000000h 00000000h 325 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R294976 EVENTLOG1_CH1_ (48040h) DEFINE R294978 EVENTLOG1_CH2_ (48042h) DEFINE R294980 EVENTLOG1_CH3_ (48044h) DEFINE R294982 EVENTLOG1_CH4_ (48046h) DEFINE R294984 EVENTLOG1_CH5_ (48048h) DEFINE R294986 EVENTLOG1_CH6_ (4804Ah) DEFINE R294988 EVENTLOG1_CH7_ (4804Ch) DEFINE R294990 EVENTLOG1_CH8_ (4804Eh) DEFINE R294992 EVENTLOG1_CH9_ (48050h) DEFINE R294994 EVENTLOG1_CH10_ (48052h) DEFINE R294996 EVENTLOG1_CH11_ (48054h) DEFINE R294998 EVENTLOG1_CH12_ (48056h) DEFINE R295000 EVENTLOG1_CH13_ (48058h) DEFINE R295002 EVENTLOG1_CH14_ (4805Ah) DEFINE R295004 EVENTLOG1_CH15_ (4805Ch) DEFINE R295006 EVENTLOG1_CH16_ (4805Eh) DEFINE R295040 EVENTLOG1_FIFO0_ (48080h) READ 31 15 30 14 29 13 28 12 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH1_ G1_CH1_ G1_CH1_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH2_ G1_CH2_ G1_CH2_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH3_ G1_CH3_ G1_CH3_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH4_ G1_CH4_ G1_CH4_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH5_ G1_CH5_ G1_CH5_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH6_ G1_CH6_ G1_CH6_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH7_ G1_CH7_ G1_CH7_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH8_ G1_CH8_ G1_CH8_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH9_ G1_CH9_ G1_CH9_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH10_ G1_CH10_ G1_CH10_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH11_ G1_CH11_ G1_CH11_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH12_ G1_CH12_ G1_CH12_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH13_ G1_CH13_ G1_CH13_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH14_ G1_CH14_ G1_CH14_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH15_ G1_CH15_ G1_CH15_ DB POL FILT 0 0 0 0 EVENTLO EVENTLO EVENTLO 0 G1_CH16_ G1_CH16_ G1_CH16_ DB POL FILT 0 0 0 0 0 0 0 EVENTLO G1_ FIFO0_ POL 27 11 26 10 25 9 24 8 23 7 22 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 2 17 1 16 0 Default 0 0 0 EVENTLOG1_CH1_SEL [9:0] 0 0 0 00000000h 0 0 0 0 EVENTLOG1_CH2_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 EVENTLOG1_CH3_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 EVENTLOG1_CH4_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 EVENTLOG1_CH5_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 0 0 EVENTLOG1_CH6_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 0 0 0 0 EVENTLOG1_CH7_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 0 0 0 0 EVENTLOG1_CH8_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 0 0 0 0 EVENTLOG1_CH9_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 0 0 0 0 EVENTLOG1_CH10_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 0 0 0 0 EVENTLOG1_CH11_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 0 0 0 0 EVENTLOG1_CH12_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 0 0 0 0 EVENTLOG1_CH13_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 0 0 0 0 EVENTLOG1_CH14_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 0 0 0 0 EVENTLOG1_CH15_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 0 0 0 0 EVENTLOG1_CH16_SEL [9:0] 0 0 0 00000000h 0 0 0 0 0 0 0 0 0 0 0 EVENTLOG1_FIFO0_ID [9:0] 0 0 0 00000000h R295042 EVENTLOG1_FIFO0_ (48082h) TIME R295044 EVENTLOG1_FIFO1_ (48084h) READ 0 0 0 0 0 0 0 EVENTLO G1_ FIFO1_ POL 0 0 0 0 R295046 EVENTLOG1_FIFO1_ (48086h) TIME R295048 EVENTLOG1_FIFO2_ (48088h) READ R295050 EVENTLOG1_FIFO2_ (4808Ah) TIME 326 0 0 0 0 0 0 0 EVENTLO G1_ FIFO2_ POL 0 0 0 0 EVENTLOG1_FIFO0_TIME [31:16] EVENTLOG1_FIFO0_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO1_TIME [31:16] EVENTLOG1_FIFO1_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO2_TIME [31:16] EVENTLOG1_FIFO2_TIME [15:0] 21 5 20 4 19 3 00000000h 0 0 0 EVENTLOG1_FIFO1_ID [9:0] 0 0 0 00000000h 00000000h 0 0 0 EVENTLOG1_FIFO2_ID [9:0] 0 0 0 00000000h 00000000h DS1162F1 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R295052 EVENTLOG1_FIFO3_ (4808Ch) READ 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 0 0 0 0 0 0 0 EVENTLO G1_ FIFO3_ POL 0 0 0 0 0 0 0 0 R295054 EVENTLOG1_FIFO3_ (4808Eh) TIME R295056 EVENTLOG1_FIFO4_ (48090h) READ 0 0 0 0 0 0 0 EVENTLO G1_ FIFO4_ POL 0 0 0 0 R295058 EVENTLOG1_FIFO4_ (48092h) TIME R295060 EVENTLOG1_FIFO5_ (48094h) READ 0 0 0 0 0 0 0 EVENTLO G1_ FIFO5_ POL 0 0 0 0 R295062 EVENTLOG1_FIFO5_ (48096h) TIME R295064 EVENTLOG1_FIFO6_ (48098h) READ 0 0 0 0 0 0 0 EVENTLO G1_ FIFO6_ POL 0 0 0 0 R295066 EVENTLOG1_FIFO6_ (4809Ah) TIME R295068 EVENTLOG1_FIFO7_ (4809Ch) READ 0 0 0 0 0 0 0 EVENTLO G1_ FIFO7_ POL 0 0 0 0 R295070 EVENTLOG1_FIFO7_ (4809Eh) TIME R295072 EVENTLOG1_FIFO8_ (480A0h) READ 0 0 0 0 0 0 0 EVENTLO G1_ FIFO8_ POL 0 0 0 0 R295074 EVENTLOG1_FIFO8_ (480A2h) TIME R295076 EVENTLOG1_FIFO9_ (480A4h) READ 0 0 0 0 0 0 0 EVENTLO G1_ FIFO9_ POL 0 0 0 0 R295078 EVENTLOG1_FIFO9_ (480A6h) TIME R295080 EVENTLOG1_FIFO10_ (480A8h) READ 0 0 0 0 0 0 0 EVENTLO G1_ FIFO10_ POL 0 0 0 0 R295082 EVENTLOG1_FIFO10_ (480AAh) TIME R295084 EVENTLOG1_FIFO11_ (480ACh) READ 0 0 0 0 0 0 0 EVENTLO G1_ FIFO11_ POL 0 0 0 0 R295086 EVENTLOG1_FIFO11_ (480AEh) TIME R295088 EVENTLOG1_FIFO12_ (480B0h) READ 0 0 0 0 0 0 0 EVENTLO G1_ FIFO12_ POL 0 0 0 0 R295090 EVENTLOG1_FIFO12_ (480B2h) TIME R295092 EVENTLOG1_FIFO13_ (480B4h) READ 0 0 0 0 0 0 0 EVENTLO G1_ FIFO13_ POL 0 0 0 0 R295094 EVENTLOG1_FIFO13_ (480B6h) TIME R295096 EVENTLOG1_FIFO14_ (480B8h) READ R295098 EVENTLOG1_FIFO14_ (480BAh) TIME DS1162F1 0 0 0 0 0 0 0 EVENTLO G1_ FIFO14_ POL 0 0 0 0 EVENTLOG1_FIFO3_TIME [31:16] EVENTLOG1_FIFO3_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO4_TIME [31:16] EVENTLOG1_FIFO4_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO5_TIME [31:16] EVENTLOG1_FIFO5_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO6_TIME [31:16] EVENTLOG1_FIFO6_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO7_TIME [31:16] EVENTLOG1_FIFO7_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO8_TIME [31:16] EVENTLOG1_FIFO8_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO9_TIME [31:16] EVENTLOG1_FIFO9_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO10_TIME [31:16] EVENTLOG1_FIFO10_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO11_TIME [31:16] EVENTLOG1_FIFO11_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO12_TIME [31:16] EVENTLOG1_FIFO12_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO13_TIME [31:16] EVENTLOG1_FIFO13_TIME [15:0] 0 0 0 0 EVENTLOG1_FIFO14_TIME [31:16] EVENTLOG1_FIFO14_TIME [15:0] 21 5 20 4 19 3 0 0 0 EVENTLOG1_FIFO3_ID [9:0] 18 2 17 1 16 0 Default 0 0 0 00000000h 00000000h 0 0 0 EVENTLOG1_FIFO4_ID [9:0] 0 0 0 00000000h 00000000h 0 0 0 EVENTLOG1_FIFO5_ID [9:0] 0 0 0 00000000h 00000000h 0 0 0 EVENTLOG1_FIFO6_ID [9:0] 0 0 0 00000000h 00000000h 0 0 0 EVENTLOG1_FIFO7_ID [9:0] 0 0 0 00000000h 00000000h 0 0 0 EVENTLOG1_FIFO8_ID [9:0] 0 0 0 00000000h 00000000h 0 0 0 EVENTLOG1_FIFO9_ID [9:0] 0 0 0 00000000h 00000000h 0 0 0 EVENTLOG1_FIFO10_ID [9:0] 0 0 0 00000000h 00000000h 0 0 0 EVENTLOG1_FIFO11_ID [9:0] 0 0 0 00000000h 00000000h 0 0 0 EVENTLOG1_FIFO12_ID [9:0] 0 0 0 00000000h 00000000h 0 0 0 EVENTLOG1_FIFO13_ID [9:0] 0 0 0 00000000h 00000000h 0 0 0 EVENTLOG1_FIFO14_ID [9:0] 0 0 0 00000000h 00000000h 327 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R295100 EVENTLOG1_FIFO15_ (480BCh) READ 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 0 0 0 0 0 0 0 EVENTLO G1_ FIFO15_ POL 0 0 0 0 0 0 0 0 R295102 EVENTLOG1_FIFO15_ (480BEh) TIME 21 5 20 4 19 3 0 0 0 EVENTLOG1_FIFO15_ID [9:0] 18 2 17 1 16 0 Default 0 0 0 00000000h 00000000h R303104 ALM1_CFG (4A000h) 0 0 0 0 0 0 0 0 0 0 0 0 EVENTLOG1_FIFO15_TIME [31:16] EVENTLOG1_FIFO15_TIME [15:0] 0 0 0 0 0 0 0 0 R303120 ALM1_CONFIG1 (4A010h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM1_ CH1_UPD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM1_ CH2_ CONT 0 ALM1_ CH2_ STOP 0 0 0 0 0 0 0 0 R303122 ALM1_CTRL1 (4A012h) R303124 ALM1_TRIG_VAL1 (4A0124h) 0 0 0 0 0 0 0 0 0 ALM1_ CH1_ CONT 0 ALM1_ CH1_ STOP 0 0 0 0 0 0 0 0 R303128 ALM1_STATUS1 (4A018h) 0 0 0 0 0 0 0 0 0 0 0 0 R303136 ALM1_CONFIG2 (4A020h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM1_ CH2_UPD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM1_ CH3_ CONT 0 ALM1_ CH3_ STOP 0 0 0 0 0 0 0 0 R303138 ALM1_CTRL2 (4A022h) R303140 ALM1_TRIG_VAL2 (4A024h) 0 0 0 0 0 0 0 0 0 0 0 0 R303152 ALM1_CONFIG3 (4A030h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM1_ CH3_UPD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM1_ CH4_ CONT 0 ALM1_ CH4_ STOP 0 0 0 0 0 0 0 0 R303156 ALM1_TRIG_VAL3 (4A034h) 0 0 0 0 0 0 0 0 0 0 0 0 R303168 ALM1_CONFIG4 (4A040h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM1_ CH4_UPD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R303172 ALM1_TRIG_VAL4 (4A044h) R303176 ALM1_STATUS4 (4A048h) 0 0 0 0 0 0 0 0 0 0 0 0 ALM1_CH4_TRIG_VAL[31:16] ALM1_CH4_TRIG_VAL[15:0] ALM1_CH4_PULSE_DUR[31:16] ALM1_CH4_PULSE_DUR[15:0] 0 0 0 0 0 0 0 0 R311296 Timer1_Control (4C000h) 0 0 0 0 0 0 0 R303174 ALM1_PULSE_DUR4 (4A046h) 0 TIMER1_REFCLK_DIV [2:0] 0 R311298 Timer1_Count_Preset (4C002h) R311302 Timer1_Start_and_Stop (4C006h) 328 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_REFCLK_FREQ_SEL 0 0 [2:0] TIMER1_MAX_COUNT [31:16] TIMER1_MAX_COUNT [15:0] 0 0 0 0 0 0 0 0 0 0 0 00000000h ALM1_ CH1_STS 0 0 00000000h ALM1_CH2_TRIG_ MODE[1:0] 0 0 0 0 0 ALM1_ CH2_ START 00000000h 0 00000000h ALM1_ CH2_STS 0 0 00000000h ALM1_CH3_TRIG_ MODE[1:0] 0 0 0 0 0 ALM1_ CH3_ START 00000000h 00000000h R303160 ALM1_STATUS3 (4A038h) R303170 ALM1_CTRL4 (4A042h) 00000000h 00000000h ALM1_CH3_TRIG_VAL[31:16] ALM1_CH3_TRIG_VAL[15:0] ALM1_CH3_PULSE_DUR[31:16] ALM1_CH3_PULSE_DUR[15:0] 0 0 0 0 0 0 0 0 R303158 ALM1_PULSE_DUR3 (4A036h) 0 ALM1_ CH1_ START 00000000h 00000000h R303144 ALM1_STATUS2 (4A028h) R303154 ALM1_CTRL3 (4A032h) 0 0 00000000h 00000000h ALM1_CH2_TRIG_VAL[31:16] ALM1_CH2_TRIG_VAL[15:0] ALM1_CH2_PULSE_DUR[31:16] ALM1_CH2_PULSE_DUR[15:0] 0 0 0 0 0 0 0 0 R303142 ALM1_PULSE_DUR2 (4A026h) 0 ALM1_ TIMER_ SEL 0 0 ALM1_CH1_TRIG_ MODE[1:0] 00000000h ALM1_CH1_TRIG_VAL[31:16] ALM1_CH1_TRIG_VAL[15:0] ALM1_CH1_PULSE_DUR[31:16] ALM1_CH1_PULSE_DUR[15:0] 0 0 0 0 0 0 0 0 R303126 ALM1_PULSE_DUR1 (4A016h) 0 0 00000000h 0 00000000h ALM1_ CH3_STS 0 0 00000000h ALM1_CH4_TRIG_ MODE[1:0] 0 0 0 0 0 ALM1_ CH4_ START 00000000h 00000000h 00000000h 0 0 0 0 TIMER1_ TIMER1_ CONTINU DIR OUS 0 0 0 0 0 0 00000000h ALM1_ CH4_STS TIMER1_PRESCALE [2:0] 00000000h 0 0 0 0 TIMER1_REFCLK_SRC [3:0] 00000000h 0 0 0 TIMER1_ STOP 0 0 0 0 0 0 0 00000000h TIMER1_ START DS1162F1 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name R311304 Timer1_Status (4C008h) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R311306 Timer1_Count_ (4C00Ah) Readback R311308 Timer1_DSP_Clock_ (4C00Ch) Config 0 0 0 0 0 0 R311310 Timer1_DSP_Clock_ (4C00Eh) Status 0 0 0 0 0 0 0 DSPGP16 _STS 0 DSPGP16 _SET1_ MASK 0 DSPGP16 _SET1_ DIR 0 DSPGP16 _SET1_ LVL 0 DSPGP16 _SET2_ MASK 0 DSPGP16 _SET2_ DIR 0 DSPGP16 _SET2_ LVL 0 DSPGP16 _SET3_ MASK 0 DSPGP16 _SET3_ DIR 0 DSPGP16 _SET3_ LVL 0 DSPGP16 _SET4_ MASK 0 DSPGP16 _SET4_ DIR 0 DSPGP16 _SET4_ LVL 0 DSPGP16 _SET5_ MASK 0 DSPGP16 _SET5_ DIR 0 DSPGP16 _SET5_ LVL 0 DSPGP16 _SET6_ MASK 0 DSPGP16 _SET6_ DIR 0 DSPGP16 _SET6_ LVL 0 DSPGP15 _STS 0 DSPGP15 _SET1_ MASK 0 DSPGP15 _SET1_ DIR 0 DSPGP15 _SET1_ LVL 0 DSPGP15 _SET2_ MASK 0 DSPGP15 _SET2_ DIR 0 DSPGP15 _SET2_ LVL 0 DSPGP15 _SET3_ MASK 0 DSPGP15 _SET3_ DIR 0 DSPGP15 _SET3_ LVL 0 DSPGP15 _SET4_ MASK 0 DSPGP15 _SET4_ DIR 0 DSPGP15 _SET4_ LVL 0 DSPGP15 _SET5_ MASK 0 DSPGP15 _SET5_ DIR 0 DSPGP15 _SET5_ LVL 0 DSPGP15 _SET6_ MASK 0 DSPGP15 _SET6_ DIR 0 DSPGP15 _SET6_ LVL 0 DSPGP14 _STS 0 DSPGP14 _SET1_ MASK 0 DSPGP14 _SET1_ DIR 0 DSPGP14 _SET1_ LVL 0 DSPGP14 _SET2_ MASK 0 DSPGP14 _SET2_ DIR 0 DSPGP14 _SET2_ LVL 0 DSPGP14 _SET3_ MASK 0 DSPGP14 _SET3_ DIR 0 DSPGP14 _SET3_ LVL 0 DSPGP14 _SET4_ MASK 0 DSPGP14 _SET4_ DIR 0 DSPGP14 _SET4_ LVL 0 DSPGP14 _SET5_ MASK 0 DSPGP14 _SET5_ DIR 0 DSPGP14 _SET5_ LVL 0 DSPGP14 _SET6_ MASK 0 DSPGP14 _SET6_ DIR 0 DSPGP14 _SET6_ LVL 0 DSPGP13 _STS 0 DSPGP13 _SET1_ MASK 0 DSPGP13 _SET1_ DIR 0 DSPGP13 _SET1_ LVL 0 DSPGP13 _SET2_ MASK 0 DSPGP13 _SET2_ DIR 0 DSPGP13 _SET2_ LVL 0 DSPGP13 _SET3_ MASK 0 DSPGP13 _SET3_ DIR 0 DSPGP13 _SET3_ LVL 0 DSPGP13 _SET4_ MASK 0 DSPGP13 _SET4_ DIR 0 DSPGP13 _SET4_ LVL 0 DSPGP13 _SET5_ MASK 0 DSPGP13 _SET5_ DIR 0 DSPGP13 _SET5_ LVL 0 DSPGP13 _SET6_ MASK 0 DSPGP13 _SET6_ DIR 0 DSPGP13 _SET6_ LVL 0 DSPGP12 _STS 0 DSPGP12 _SET1_ MASK 0 DSPGP12 _SET1_ DIR 0 DSPGP12 _SET1_ LVL 0 DSPGP12 _SET2_ MASK 0 DSPGP12 _SET2_ DIR 0 DSPGP12 _SET2_ LVL 0 DSPGP12 _SET3_ MASK 0 DSPGP12 _SET3_ DIR 0 DSPGP12 _SET3_ LVL 0 DSPGP12 _SET4_ MASK 0 DSPGP12 _SET4_ DIR 0 DSPGP12 _SET4_ LVL 0 DSPGP12 _SET5_ MASK 0 DSPGP12 _SET5_ DIR 0 DSPGP12 _SET5_ LVL 0 DSPGP12 _SET6_ MASK 0 DSPGP12 _SET6_ DIR 0 DSPGP12 _SET6_ LVL 0 DSPGP11 _STS 0 DSPGP11 _SET1_ MASK 0 DSPGP11 _SET1_ DIR 0 DSPGP11 _SET1_ LVL 0 DSPGP11 _SET2_ MASK 0 DSPGP11 _SET2_ DIR 0 DSPGP11 _SET2_ LVL 0 DSPGP11 _SET3_ MASK 0 DSPGP11 _SET3_ DIR 0 DSPGP11 _SET3_ LVL 0 DSPGP11 _SET4_ MASK 0 DSPGP11 _SET4_ DIR 0 DSPGP11 _SET4_ LVL 0 DSPGP11 _SET5_ MASK 0 DSPGP11 _SET5_ DIR 0 DSPGP11 _SET5_ LVL 0 DSPGP11 _SET6_ MASK 0 DSPGP11 _SET6_ DIR 0 DSPGP11 _SET6_ LVL R315392 DSPGP_Status_1 (4D000h) R315424 DSPGP_SET1_Mask_1 (4D020h) R315432 DSPGP_SET1_ (4D028h) Direction_1 R315440 DSPGP_SET1_Level_1 (4D030h) R315456 DSPGP_SET2_Mask_1 (4D040h) R315464 DSPGP_SET2_ (4D048h) Direction_1 R315472 DSPGP_SET2_Level_1 (4D050h) R315488 DSPGP_SET3_Mask_1 (4D060h) R315496 DSPGP_SET3_ (4D068h) Direction_1 R315504 DSPGP_SET3_Level_1 (4D070h) R315520 DSPGP_SET4_Mask_1 (4D080h) R315528 DSPGP_SET4_ (4D088h) Direction_1 R315536 DSPGP_SET4_Level_1 (4D090h) R315552 DSPGP_SET5_Mask_1 (4D0A0h) R315560 DSPGP_SET5_ (4D0A8h) Direction_1 R315568 DSPGP_SET5_Level_1 (4D0B0h) R315584 DSPGP_SET6_Mask_1 (4D0C0h) R315592 DSPGP_SET6_ (4D0C8h) Direction_1 R315600 DSPGP_SET6_Level_1 (4D0D0h) DS1162F1 16 0 Default 0 00000000h TIMER1_ RUNNING _STS TIMER1_CUR_COUNT [31:16] TIMER1_CUR_COUNT [15:0] 0 0 0 0 0 0 0 0 0 0 TIMER1_DSPCLK_FREQ_SEL [15:0] 0 0 0 0 0 0 0 0 0 0 TIMER1_DSPCLK_FREQ_STS [15:0] 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _STS STS STS STS STS STS STS STS STS STS 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET1_ SET1_ SET1_ SET1_ SET1_ SET1_ SET1_ SET1_ SET1_ SET1_ MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET1_ SET1_DIR SET1_DIR SET1_DIR SET1_DIR SET1_DIR SET1_DIR SET1_DIR SET1_DIR SET1_DIR DIR 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET1_ SET1_LVL SET1_LVL SET1_LVL SET1_LVL SET1_LVL SET1_LVL SET1_LVL SET1_LVL SET1_LVL LVL 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET2_ SET2_ SET2_ SET2_ SET2_ SET2_ SET2_ SET2_ SET2_ SET2_ MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET2_ SET2_DIR SET2_DIR SET2_DIR SET2_DIR SET2_DIR SET2_DIR SET2_DIR SET2_DIR SET2_DIR DIR 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET2_ SET2_LVL SET2_LVL SET2_LVL SET2_LVL SET2_LVL SET2_LVL SET2_LVL SET2_LVL SET2_LVL LVL 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET3_ SET3_ SET3_ SET3_ SET3_ SET3_ SET3_ SET3_ SET3_ SET3_ MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET3_ SET3_DIR SET3_DIR SET3_DIR SET3_DIR SET3_DIR SET3_DIR SET3_DIR SET3_DIR SET3_DIR DIR 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET3_ SET3_LVL SET3_LVL SET3_LVL SET3_LVL SET3_LVL SET3_LVL SET3_LVL SET3_LVL SET3_LVL LVL 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET4_ SET4_ SET4_ SET4_ SET4_ SET4_ SET4_ SET4_ SET4_ SET4_ MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET4_ SET4_DIR SET4_DIR SET4_DIR SET4_DIR SET4_DIR SET4_DIR SET4_DIR SET4_DIR SET4_DIR DIR 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET4_ SET4_LVL SET4_LVL SET4_LVL SET4_LVL SET4_LVL SET4_LVL SET4_LVL SET4_LVL SET4_LVL LVL 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET5_ SET5_ SET5_ SET5_ SET5_ SET5_ SET5_ SET5_ SET5_ SET5_ MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET5_ SET5_DIR SET5_DIR SET5_DIR SET5_DIR SET5_DIR SET5_DIR SET5_DIR SET5_DIR SET5_DIR DIR 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET5_ SET5_LVL SET5_LVL SET5_LVL SET5_LVL SET5_LVL SET5_LVL SET5_LVL SET5_LVL SET5_LVL LVL 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET6_ SET6_ SET6_ SET6_ SET6_ SET6_ SET6_ SET6_ SET6_ SET6_ MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET6_ SET6_DIR SET6_DIR SET6_DIR SET6_DIR SET6_DIR SET6_DIR SET6_DIR SET6_DIR SET6_DIR DIR 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET6_ SET6_LVL SET6_LVL SET6_LVL SET6_LVL SET6_LVL SET6_LVL SET6_LVL SET6_LVL SET6_LVL LVL 00000000h 00000000h 00000000h 00000000h 0000FFFFh 0000FFFFh 00000000h 0000FFFFh 0000FFFFh 00000000h 0000FFFFh 0000FFFFh 00000000h 0000FFFFh 0000FFFFh 00000000h 0000FFFFh 0000FFFFh 00000000h 0000FFFFh 0000FFFFh 00000000h 329 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R315616 DSPGP_SET7_Mask_1 0000FFFFh (4D0E0h) DSPGP16 DSPGP15 DSPGP14 DSPGP13 DSPGP12 DSPGP11 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET7_ MASK 0 R315624 DSPGP_SET7_ (4D0E8h) Direction_1 DSPGP16 _SET7_ DIR 0 R315632 DSPGP_SET7_Level_1 (4D0F0h) DSPGP16 _SET7_ LVL 0 R315648 DSPGP_SET8_Mask_1 (4D100h) DSPGP16 _SET8_ MASK 0 R315656 DSPGP_SET8_ (4D108h) Direction_1 DSPGP16 _SET8_ DIR 0 R315664 DSPGP_SET8_Level_1 (4D110h) DSPGP16 _SET8_ LVL 0 R524288 DSP1_PMEM_0 _SET7_ MASK 0 DSPGP15 _SET7_ DIR 0 DSPGP15 _SET7_ LVL 0 DSPGP15 _SET8_ MASK 0 DSPGP15 _SET8_ DIR 0 DSPGP15 _SET8_ LVL 0 _SET7_ MASK 0 DSPGP14 _SET7_ DIR 0 DSPGP14 _SET7_ LVL 0 DSPGP14 _SET8_ MASK 0 DSPGP14 _SET8_ DIR 0 DSPGP14 _SET8_ LVL 0 _SET7_ MASK 0 DSPGP13 _SET7_ DIR 0 DSPGP13 _SET7_ LVL 0 DSPGP13 _SET8_ MASK 0 DSPGP13 _SET8_ DIR 0 DSPGP13 _SET8_ LVL 0 _SET7_ MASK 0 DSPGP12 _SET7_ DIR 0 DSPGP12 _SET7_ LVL 0 DSPGP12 _SET8_ MASK 0 DSPGP12 _SET8_ DIR 0 DSPGP12 _SET8_ LVL 0 _SET7_ MASK 0 DSPGP11 _SET7_ DIR 0 DSPGP11 _SET7_ LVL 0 DSPGP11 _SET8_ MASK 0 DSPGP11 _SET8_ DIR 0 DSPGP11 _SET8_ LVL 0 0 0 0 0 0 (80000h) R524290 DSP1_PMEM_1 (80002h) 0 R524292 DSP1_PMEM_2 (80004h) R561146 DSP1_PMEM_18429 (88FFAh) R561148 DSP1_PMEM_18430 (88FFCh) 0 0 0 0 0 0 0 0 0 0 0 0 R561150 DSP1_PMEM_18431 (88FFEh) R655360 DSP1_XMEM_0 (A0000h) 0 0 0 0 0 0 R655362 DSP1_XMEM_1 (A0002h) 0 0 0 0 0 0 R696316 DSP1_XMEM_20478 (A9FFCh) 0 0 0 0 0 0 R696318 DSP1_XMEM_20479 (A9FFEh) 0 0 0 0 0 0 R786432 DSP1_YMEM_0 (C0000h) 0 0 0 0 0 0 R786434 DSP1_YMEM_1 (C0002h) 0 0 0 0 0 0 R802812 DSP1_YMEM_8190 (C3FFCh) 0 0 0 0 0 0 R802814 DSP1_YMEM_8191 (C3FFEh) 0 0 0 0 0 0 R917504 DSP1_ZMEM_0 (E0000h) 0 0 0 0 0 0 R917506 DSP1_ZMEM_1 (E0002h) 0 0 0 0 0 0 R925692 DSP1_ZMEM_4094 (E1FFCh) 0 0 0 0 0 0 R925694 DSP1_ZMEM_4095 (E1FFEh) 0 0 0 0 0 0 R1048064 DSP1_Config_1 (FFE00h) 0 0 0 0 0 0 R1048066 DSP1_Config_2 (FFE02h) 0 0 0 0 0 0 R1048068 DSP1_Status_1 (FFE04h) DSP1_ PING_ FULL 0 DSP1_ PONG_ FULL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R1048072 DSP1_Status_3 (FFE08h) 0 0 0 0 0 0 R1048074 DSP1_Watchdog_1 (FFE0Ah) 0 0 0 0 0 0 0 0 0 0 0 0 R1048070 DSP1_Status_2 (FFE06h) 330 0 0 DSP1_RATE [3:0] _SET7_ SET7_ SET7_ SET7_ SET7_ SET7_ SET7_ SET7_ SET7_ SET7_ MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET7_ SET7_DIR SET7_DIR SET7_DIR SET7_DIR SET7_DIR SET7_DIR SET7_DIR SET7_DIR SET7_DIR DIR 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET7_ SET7_LVL SET7_LVL SET7_LVL SET7_LVL SET7_LVL SET7_LVL SET7_LVL SET7_LVL SET7_LVL LVL 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET8_ SET8_ SET8_ SET8_ SET8_ SET8_ SET8_ SET8_ SET8_ SET8_ MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET8_ SET8_DIR SET8_DIR SET8_DIR SET8_DIR SET8_DIR SET8_DIR SET8_DIR SET8_DIR SET8_DIR DIR 0 0 0 0 0 0 0 0 0 0 DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_ _SET8_ SET8_LVL SET8_LVL SET8_LVL SET8_LVL SET8_LVL SET8_LVL SET8_LVL SET8_LVL SET8_LVL LVL 0 0 DSP1_PM_START [39:32] DSP1_PM_START [31:16] DSP1_PM_START [15:0] 0 0 DSP1_PM_1 [39:32] DSP1_PM_1 [31:16] DSP1_PM_1 [15:0] 0 0 DSP1_PM_12286 [39:32] DSP1_PM_12286 [31:16] DSP1_PM_12286 [15:0] 0 0 DSP1_PM_END [39:32] DSP1_PM_END [31:16] DSP1_PM_END [15:0] 0 0 DSP1_XM_START [23:16] DSP1_XM_START [15:0] 0 0 DSP1_XM_1 [23:16] DSP1_XM_1 [15:0] 0 0 DSP1_XM_20478 [23:16] DSP1_XM_20478 [15:0] 0 0 DSP1_XM_END [23:16] DSP1_XM_END [15:0] 0 0 DSP1_YM_START [23:16] DSP1_YM_START [15:0] 0 0 DSP1_YM_1 [23:16] DSP1_YM_1 [15:0] 0 0 DSP1_YM_8190 [23:16] DSP1_YM_8190 [15:0] 0 0 DSP1_YM_END [23:16] DSP1_YM_END [15:0] 0 0 DSP1_ZM_START [23:16] DSP1_ZM_START [15:0] 0 0 DSP1_ZM_1 [23:16] DSP1_ZM_1 [15:0] 0 0 DSP1_ZM_4094 [23:16] DSP1_ZM_4094 [15:0] 0 0 DSP1_ZM_END [23:16] DSP1_ZM_END [15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_ DSP1_ 0 DSP1_ DSP1_ MEM_ENA DBG_ CORE_ START CLK_ENA ENA 0 0 0 0 0 0 0 0 0 0 DSP1_CLK_FREQ_SEL [15:0] 0 0 DSP1_WDMA_ACTIVE_CHANNELS [7:0] 0 0 0 0 DSP1_DUALMEM_COLLISION_ADDR [15:0] 0 0 0 0 0 0 0 0 DSP1_CLK_FREQ_STS [15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_ CLK_ AVAIL 0 0 0 0 0000FFFFh 00000000h 0000FFFFh 0000FFFFh 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 0 0 0 DSP1_WDT_MAX_COUNT [3:0] 00000000h 0 00000000h DSP1_ WDT_ENA DS1162F1 CS42L92 6 Register Map Table 6-2. Register Map Definition—32-bit region (Cont.) Register Name 31 15 30 14 29 13 28 12 27 11 26 10 R1048080 DSP1_WDMA_Buffer_1 (FFE10h) R1048082 DSP1_WDMA_Buffer_2 (FFE12h) R1048084 DSP1_WDMA_Buffer_3 (FFE14h) R1048086 DSP1_WDMA_Buffer_4 (FFE16h) R1048096 DSP1_RDMA_Buffer_1 (FFE20h) R1048098 DSP1_RDMA_Buffer_2 (FFE22h) R1048100 DSP1_RDMA_Buffer_3 (FFE24h) R1048112 DSP1_DMA_Config_1 (FFE30h) 0 0 0 0 0 0 0 0 0 0 0 0 R1048118 DSP1_DMA_Config_4 (FFE36h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R1048120 DSP1_External_Start (FFE38h) 0 0 0 0 0 0 0 0 0 0 0 0 R1048114 DSP1_DMA_Config_2 (FFE32h) R1048116 DSP1_DMA_Config_3 (FFE34h) 25 9 24 8 23 7 22 6 0 0 0 0 0 0 R1048148 DSP1_Ext_window_A (FFE54h) DSP1_ EXT_A_ PSIZE16 0 0 0 0 0 R1048150 DSP1_Ext_window_B (FFE56h) DSP1_ EXT_B_ PSIZE16 0 0 0 0 0 0 R1048152 DSP1_Ext_window_C (FFE58h) DSP1_ EXT_C_ PSIZE16 0 0 0 0 0 R1048154 DSP1_Ext_window_D (FFE5Ah) DSP1_ EXT_D_ PSIZE16 0 0 0 0 0 R1048158 DSP1_Watchdog_2 (FFE5Eh) 0 0 0 0 0 0 R1048160 DSP1_Identity (FFE60h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R1048130 DSP1_Scratch_2 (FFE42h) R1048146 DSP1_Bus_Error_Addr (FFE52h) R1048164 DSP1_Region_lock_sts_ (FFE64h) 0 R1048166 DSP1_Region_lock_1__ (FFE66h) _DSP1_Region_lock_0 R1048168 DSP1_Region_lock_3__ (FFE68h) _DSP1_Region_lock_2 R1048170 DSP1_Region_lock_5__ (FFE6Ah) _DSP1_Region_lock_4 R1048172 DSP1_Region_lock_7__ (FFE6Ch) _DSP1_Region_lock_6 R1048174 DSP1_Region_lock_9__ (FFE6Eh) _DSP1_Region_lock_8 0 R1048186 DSP1_Region_lock_ctrl_ (FFE7Ah) 0 DSP1_ R1048188 DSP1_PMEM_Err_ (FFE7Ch) Addr___XMEM_Err_ Addr DS1162F1 0 0 DSP1_ DSP1_ LOCK_ ADDR_ WDT_ ERR_STS ERR_STS TIMEOUT_ STS 0 0 0 0 0 0 0 20 4 19 3 18 2 17 1 DSP1_START_ADDRESS_WDMA_BUFFER_1 [15:0] DSP1_START_ADDRESS_WDMA_BUFFER_0 [15:0] DSP1_START_ADDRESS_WDMA_BUFFER_3 [15:0] DSP1_START_ADDRESS_WDMA_BUFFER_2 [15:0] DSP1_START_ADDRESS_WDMA_BUFFER_5 [15:0] DSP1_START_ADDRESS_WDMA_BUFFER_4 [15:0] DSP1_START_ADDRESS_WDMA_BUFFER_7 [15:0] DSP1_START_ADDRESS_WDMA_BUFFER_6 [15:0] DSP1_START_ADDRESS_RDMA_BUFFER_1 [15:0] DSP1_START_ADDRESS_RDMA_BUFFER_0 [15:0] DSP1_START_ADDRESS_RDMA_BUFFER_3 [15:0] DSP1_START_ADDRESS_RDMA_BUFFER_2 [15:0] DSP1_START_ADDRESS_RDMA_BUFFER_5 [15:0] DSP1_START_ADDRESS_RDMA_BUFFER_4 [15:0] 0 0 DSP1_WDMA_CHANNEL_ENABLE [7:0] DSP1_DMA_BUFFER_LENGTH [13:0] 0 0 0 0 0 0 0 0 0 0 0 DSP1_WDMA_CHANNEL_OFFSET [7:0] 0 0 0 0 DSP1_RDMA_CHANNEL_OFFSET [5:0] 0 0 0 0 DSP1_RDMA_CHANNEL_ENABLE [5:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_SCRATCH_1 [15:0] DSP1_SCRATCH_0 [15:0] DSP1_SCRATCH_3 [15:0] DSP1_SCRATCH_2 [15:0] 0 0 DSP1_BUS_ERR_ADDR [15:0] 0 0 0 0 R1048128 DSP1_Scratch_1 (FFE40h) 21 5 0 0 0 0 0 0 0 0 DSP1_START_IN_SEL [4:0] 16 0 Default 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 0 00000000h 00000000h 0 DSP1_ DMA_ WORD_ SEL 0 00000000h 00000000h 00000000h 00000000h 00000000h DSP1_BUS_ERR_ADDR [23:16] 0 0 0 0 0 0 00000000h DSP1_EXT_A_PAGE [15:0] 0 0 0 0 0 0 0 0 0 00000000h 0 DSP1_EXT_B_PAGE [15:0] 0 0 0 0 0 0 0 0 0 00000000h 0 DSP1_EXT_C_PAGE [15:0] 0 0 0 0 0 0 0 0 0 00000000h DSP1_EXT_D_PAGE [15:0] 0 0 0 0 0 0 0 0 0 DSP1_WDT_RESET [15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_CORE_NUMBER [4:0] 0 0 0 0 0 0 0 0 0 0 DSP1_ DSP1_ DSP1_ DSP1_ DSP1_ DSP1_ DSP1_ DSP1_ DSP1_ DSP1_ CTRL_ CTRL_ CTRL_ CTRL_ CTRL_ CTRL_ CTRL_ CTRL_ CTRL_ CTRL_ REGION9_REGION8_REGION7_REGION6_REGION5_REGION4_REGION3_REGION2_REGION1_REGION0_ LOCK_ LOCK_ LOCK_ LOCK_ LOCK_ LOCK_ LOCK_ LOCK_ LOCK_ LOCK_ STS STS STS STS STS STS STS STS STS STS DSP1_CTRL_REGION1_LOCK [15:0] DSP1_CTRL_REGION0_LOCK [15:0] DSP1_CTRL_REGION3_LOCK [15:0] DSP1_CTRL_REGION2_LOCK [15:0] DSP1_CTRL_REGION5_LOCK [15:0] DSP1_CTRL_REGION4_LOCK [15:0] DSP1_CTRL_REGION7_LOCK [15:0] DSP1_CTRL_REGION6_LOCK [15:0] DSP1_CTRL_REGION9_LOCK [15:0] DSP1_CTRL_REGION8_LOCK [15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_ DSP1_ ERR_ ERR_ PAUSE CLEAR 0 DSP1_PMEM_ERR_ADDR [14:0] DSP1_XMEM_ERR_ADDR [15:0] 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 331 CS42L92 7 Thermal Characteristics 7 Thermal Characteristics Table 7-1. Typical JEDEC Four-Layer, 2s2p Board Thermal Characteristics Symbol WLCSP Units Junction-to-ambient thermal resistance Parameter JA 38.5 °C/W Junction-to-board thermal resistance JB 9.3 °C/W Junction-to-case thermal resistance JC 2.11 °C/W Junction-to-board thermal-characterization parameter JB 9.3 °C/W Junction-to-package-top thermal-characterization parameter JT 0.10 °C/W Notes: • Natural convection at the maximum recommended operating temperature TA (see Table 3-3) • Four-layer, 2s2p PCB as specified by JESD51-9 and JESD51-11; dimensions: 101.5 x 114.5 x 1.6 mm • Thermal parameters as defined by JESD51-12 332 DS1162F1 CS42L92 8 Package Dimensions 8 Package Dimensions Ball A1 Location Indicator (seen through package) A2 g X X A Ball A1 Location Indicator c2 A1 d2 Z Z Y Seating plane e d1 Y WAFER BACK SIDE b c1 104 x Øb Øddd Z X Y Øccc Z SIDE VIEW e e f BUMP SIDE Notes: • Dimensioning and tolerances per ASME Y 14.5M–2009. • The Ball A1 position indicator is for illustration purposes only and may not be to scale. • Dimension “b” applies to the solder sphere diameter and is measured at the midpoint between the package body and the seating plane Datum Z. Table 8-1. WLCSP Package Dimensions Dimension Millimeters Nominal 0.494 0.19 0.304 0.27 0.3579 0.2362 0.2607 0.236 0.4 0.3464 0.3464 4.7754 3.4722 Minimum 0.464 0.161 0.289 0.24 0.3279 0.2062 0.2307 0.206 BSC BSC REF 4.7504 3.4472 A A1 A2 b c1 d1 c2 d2 e f g X Y ccc = 0.05 ddd = 0.15 Note: Controlling dimension is millimeters. Maximum 0.524 0.219 0.319 0.3 0.3879 0.2662 0.2907 0.266 BSC BSC BSC 4.8004 3.4972 9 Ordering Information Table 9-1. Ordering Information Product CS42L92 Description 32-Bit 384-kHz Hi-Fi Audio Codec Package 104-ball WLCSP Halogen Free Pb Free Grade Temperature Range Yes Yes Commercial –40 to +85°C Container Order # Tape and Reel 1 CS42L92-CWZR 1.Reel quantity = 6000 units. DS1162F1 333 CS42L92 10 References 10 References • MIPI Alliance, MIPI Alliance Specification for Serial Low-Power Inter-Chip Media Bus (SLIMbus). http:// www.mipi.org/ • Google Inc, Android Wired Headset Specification, Version 1.1. http://source.android.com/accessories/ headset-spec.html • International Electrotechnical Commission, IEC60958-3 Digital Audio Interface—Consumer. http://www.ansi.org/ 11 Revision History Table 11-1. Revision History Revision F1 NOV ‘17 Changes • AVDD maximum rating amended (Table 3-2). • DSP memory sizes amended (Table 4-29). • Package dimension tolerances added (Section 8). Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products. Use of Cirrus Logic products may entail a choice between many different modes of operation, some or all of which may require action by the user, and some or all of which may be optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one mode over another. Likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they would not be suitable for operation. Features and operations described herein are for illustrative purposes only. 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