Confidential Draft 6/18/07
CS4352
192 kHz Stereo DAC with 2 Vrms Line Out
Features
Multi-bit Delta-Sigma Modulator 24-Bit Resolution Supports Sample Rates up to 192 kHz 106 dB A-wt Dynamic Range -93 dB THD+N Integrated Line Driver 2 Vrms Output into 5 kΩ AC Load Analog Low-Pass Filter Stereo Mutes with Auto-Mute Function Low Clock-Jitter Sensitivity Low-Latency Digital Filtering Popguard® Technology for Control of Clicks and Pops Single-Ended Outputs +3.3 V Core, +9 to 12 V Analog, and +1.5 to 3.3 V Interface Power Supplies Low Power Consumption 20-pin TSSOP, Lead-Free Assembly
Description
The CS4352 is a complete stereo digital-to-analog system including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-emphasis, analog filtering, and on-chip 2 Vrms line-level driver. The advantages of this architecture include ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components. The CS4352 is available in a 20-pin TSSOP package in both Commercial grade (-40°C to +85°C) and Automotive grade (-40°C to +105°C). The CDB4352 Customer Demonstration Board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 20 for complete details. These features are ideal for cost-sensitive, 2-channel audio systems including video game consoles, DVD players, A/V receivers, set-top boxes, digital TVs and DVD Recorders, mini-component systems, and mixing consoles.
1.5 V to 3.3 V
3.3 V
9 V to 12 V
Hardware Control Hardware Configuration Reset Level Translator Interpolation Filter Multibit ∆Σ Modulator
DAC
Amp + Filter
2 Vrms Line Level Left Channel Output
Serial Audio Input
PCM Serial Interface Interpolation Filter Multibit ∆Σ Modulator
DAC
Amp + Filter
2 Vrms Line Level Right Channel Output
Auto Speed Mode Detect Internal Voltage Reference
External Mute Control
Left and Right Mute Controls
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved)
JUN '07 DS684F2
CS4352
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................................. 3 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4 RECOMMENDED OPERATING CONDITIONS .................................................................................... 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4 DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ) ............................................................. 5 DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DZZ) .............................................................. 6 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................................ 7 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ................................................... 8 DIGITAL CHARACTERISTICS .............................................................................................................. 9 POWER AND THERMAL CHARACTERISTICS ................................................................................... 9 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 10 4. APPLICATIONS ................................................................................................................................... 11 4.6.1 Capacitor Placement ............................................................................................................. 13 4.7.1 Power-Up .............................................................................................................................. 14 4.7.2 Power-Down .......................................................................................................................... 14 4.7.3 Discharge Time ..................................................................................................................... 14 5. DIGITAL FILTER RESPONSE PLOTS ......................................................................................... 16 6. PARAMETER DEFINITIONS ................................................................................................................ 18 7. PACKAGE DIMENSIONS ................................................................................................................... 19 8. ORDERING INFORMATION ............................................................................................................... 20 9. REVISION HISTORY ............................................................................................................................ 20
LIST OF FIGURES
Figure 1.Serial Input Timing ........................................................................................................................ 8 Figure 2.Typical Connection Diagram ....................................................................................................... 10 Figure 3.I²S, up to 24-Bit Data .................................................................................................................. 12 Figure 4.Right-Justified Data ..................................................................................................................... 12 Figure 5.Left-Justified up to 24-Bit Data .................................................................................................... 12 Figure 6.De-Emphasis Curve .................................................................................................................... 13 Figure 7.Single-Speed Stopband Rejection .............................................................................................. 16 Figure 8.Single-Speed Transition Band .................................................................................................... 16 Figure 9.Single-Speed Transition Band (detail) ........................................................................................ 16 Figure 10.Single-Speed Passband Ripple ................................................................................................ 16 Figure 11.Double-Speed Stopband Rejection ........................................................................................... 16 Figure 12.Double-Speed Transition Band ................................................................................................. 16 Figure 13.Double-Speed Transition Band (detail) ..................................................................................... 17 Figure 14.Double-Speed Passband Ripple ............................................................................................... 17 Figure 15.Quad-Speed Stopband Rejection ............................................................................................. 17 Figure 16.Quad-Speed Transition Band ................................................................................................... 17 Figure 17.Quad-Speed Transition Band (detail) ....................................................................................... 17 Figure 18.Quad-Speed Passband Ripple ................................................................................................. 17
LIST OF TABLES
Table 1. CS4352 Auto-Detect ................................................................................................................... 11 Table 2. Single-Speed Mode Standard Frequencies ................................................................................ 11 Table 3. Double-Speed Mode Standard Frequencies ............................................................................... 11 Table 4. Quad-Speed Mode Standard Frequencies ................................................................................. 11 Table 5. Digital Interface Format ............................................................................................................... 12
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DS684F2
CS4352 1. PIN DESCRIPTIONS
SDIN SCLK LRCK MCLK VD GND DIF1 DIF0 DEM RST
Pin Name Pin #
SDIN SCLK LRCK MCLK VD GND DIF0 DIF1 DEM RST VA VBIAS VQ VA_H VL BMUTEC AMUTEC AOUTB AOUTA 1 2 3 4 5 6 16 8 7 9 10 11 12 13 17 20 14 19 15 18
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
VL AMUTEC AOUTA VA_H GND AOUTB BMUTEC VQ VBIAS VA
Pin Description
Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Serial Clock (Input) - Serial clock for the serial audio interface. Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Digital Power (Input) - Positive power supply for the digital section. Ground (Input) - Ground reference. Digital Interface Format (Input) - Defines the required relationship between the Left/Right Clock, Serial Clock, and Serial Audio Data. De-emphasis (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response for 44.1 kHz sample rates Reset (Input) - Powers down the device and resets all internal registers to their default settings when enabled. Low Voltage Analog Power (Input) - Positive power supply for the analog section. Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. High Voltage Analog Power (Input) - Positive power supply for the analog section. Serial Audio Interface Power (Input) - Positive power for the serial audio interface Mute Control (Output) - Control signal for optional mute circuit. Analog Outputs (Output) - The full-scale analog line output level is specified in the Analog Characteristics table.
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CS4352 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.) Parameters
DC Power Supply High Voltage Analog power Low Voltage Analog power Digital power Interface power Ambient Operating Temperature (power applied) -CZZ -DZZ
Symbol
VA_H VA VD VL TA
Min
8.40 3.13 3.13 1.43 -40 -40
Typ
9 3.3 3.3 1.5 -
Max
12.6 3.47 3.47 3.47 +85 +105
Units
V V V V °C °C
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.) Parameters
DC Power Supply High Voltage Analog power Low Voltage Analog power Digital power Interface power Digital Interface
Symbol
VA_H VA VD VL Iin VIN-L TA Tstg
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -55 -65
Max
14.0 3.63 3.63 3.63 ±10 VL+ 0.4 +125 +150
Units
V V V V mA V °C °C
Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature
Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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CS4352 DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ)
Test conditions (unless otherwise specified): TA = 25 °C, VA_H = 9 V, VA = 3.3 V, VD = 3.3 V GND = 0 V; VBIAS+ and VQ capacitors as shown in Figure 2 on page 10; input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz. Parameter All Speed Modes
Dynamic Range (Note 1) 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted (Note 1) 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB (A-wt) (1 kHz)
Symbol Fs = 48, 96, and 192 kHz
Min
100 97 1.84
Typ
106 103 98 95 -93 -83 -43 -93 -75 -35 106 99 2.00 4 575 1 0.1 100 50 -
Max
-89 -77 -37 2.11 100
Unit
dB dB dB dB dB dB dB dB dB dB dB dB Vrms Vdc µA µA dB ppm/°C Ω kΩ pF
Total Harmonic Distortion + Noise 24-bit
16-bit
Idle Channel Noise / Signal-to-noise ratio Interchannel Isolation
Analog Output - All Modes
Full Scale Output Voltage Common Mode Voltage Max Current draw from an AOUT pin Max Current draw from VQ Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance Load Capacitance ZOUT RL CL VQ IOUTmax IQmax 5 -
Notes: 1. One-half LSB of triangular PDF dither is added to data.
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CS4352 DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DZZ)
Test conditions (unless otherwise specified): TA = -40°C to 85°C, VA_H = 9 V, VA = 3.3 V, VD = 3.3 V GND = 0 V; VBIAS+ and VQ capacitors as shown in Figure 2 on page 10; input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz. Parameter All Speed Modes
Dynamic Range (Note 2) 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted (Note 2) 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB (A-wt) (1 kHz)
Symbol Fs = 48, 96, and 192 kHz
Min
96 93 1.81
Typ
106 103 98 95 -93 -83 -43 -93 -75 -35 106 99 2.00 4 575 1 0.1 100 50 -
Max
-89 -73 -33 2.17 100
Unit
dB dB dB dB dB dB dB dB dB dB dB dB Vrms Vdc µA µA dB ppm/°C Ω kΩ pF
Total Harmonic Distortion + Noise 24-bit
16-bit
Idle Channel Noise / Signal-to-noise ratio Interchannel Isolation
Analog Output - All Modes
Full Scale Output Voltage Common Mode Voltage Max Current draw from an AOUT pin Max Current draw from VQ Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance Load Capacitance ZOUT RL CL VQ IOUTmax IQmax 5 -
Notes: 2. One-half LSB of triangular PDF dither is added to data.
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DS684F2
CS4352 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Amplitude vs. frequency plots of the data in the table below are available in “Digital Filter Response Plots” on page 16.) Parameter Min Typ Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 3) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Total Group Delay (Fs = Output Sample Rate) Intra-channel Phase Deviation Inter-channel Phase Deviation De-emphasis Error (Note 5)(Relative to 1 kHz) Passband (Note 3) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Total Group Delay (Fs = Output Sample Rate) Intra-channel Phase Deviation Inter-channel Phase Deviation Passband (Note 3) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Total Group Delay (Fs = Output Sample Rate) Intra-channel Phase Deviation Inter-channel Phase Deviation to -0.01 dB corner to -3 dB corner 0 0 -0.01 0.547 102 0 0 -0.01 .583 80 0 0 -0.01 .635 90 9.4/Fs 4.6/Fs 4.7/Fs -
Max
.454 .499 +0.01 ±0.56/Fs 0 ±0.14 .430 .499 0.01 ±0.03/Fs 0 .105 .490 0.01 ±0.01/Fs 0
Unit
Fs Fs dB Fs dB s s s dB Fs Fs dB Fs dB s s s Fs Fs dB Fs dB s s s
(Note 4)
Fs = 44.1 kHz to -0.01 dB corner to -3 dB corner
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz
(Note 4)
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz
to -0.01 dB corner to -3 dB corner
(Note 4)
Notes: 3. Response is clock-dependent and will scale with Fs. 4. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 5. De-emphasis is available only in Single-Speed Mode.
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7
CS4352 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters
MCLK Frequency MCLK Duty Cycle Input Sample Rate (Auto selection) Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs
Symbol
Min
1.024 45 4 84 170 40
Max
48.0 55 54 108 216 60 -
Units
MHz % kHz kHz kHz % ns ns ns ns ns ns
LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Period Single-Speed Mode Double-Speed Mode Quad-Speed Mode SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time tsclkl tsclkh tsclkw tsclkw tsclkw tslrd tslrs tsdlrs tsdh
20 20 1 --------------------( 128 ) Fs 1 -----------------( 64 ) Fs 2 ---------------MCLK 20 20 20 20
LR C K t slrd t slrs t sclkl t sclkh
S C LK t sd lrs S D ATA t sd h
Figure 1. Serial Input Timing
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DS684F2
CS4352 DIGITAL CHARACTERISTICS
Parameters
High-Level Input Voltage VL = 3.3 V VL = 2.5 V VL = 1.5 V VL = 3.3 V VL = 2.5 V VL = 1.5 V
Symbol
VIH VIH VIH VIL VIL VIL Iin
Min
2.0 1.7 1.05 -
Typ
8 2 VA_H 0
Max
0.8 0.7 0.38 ±10 -
Units
V V V V V V µA pF mA V V
Low-Level Input Voltage
Input Leakage Current Input Capacitance Maximum MUTEC Drive Current MUTEC High-Level Output Voltage MUTEC Low-Level Output Voltage
VOH VOL
POWER AND THERMAL CHARACTERISTICS
Parameters Power Supplies
Power Supply Current (Note 6) normal operation, VA_H = 12 V VA_H = 9 V VA= 3.3 V VD= 3.3 V Interface current VL= 3.3 V power-down state, all supplies (Note 7) Power Dissipation (all supplies) (Note 6) VA_H = 12 V normal operation power-down (Note 7) VA_H = 9 V normal operation power-down (Note 7) Power Supply Rejection Ratio (Note 8) (1 kHz) (60 Hz) IA_H IA_H IA ID IL Ipd 12 10 3 12 0.02 380 21 16 4 16 0.09 mA mA mA mA mA µA
Symbol
Min
Typ
Max
Units
PSRR
-
121 1 91 1 60 60
158 122 -
mW mW mW mW dB dB
Notes: 6. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are based on highest FS and highest MCLK. Variance between speed modes is small. 7. Power down mode is defined as RST pin = Low with all clock and data lines held static low. All digital inputs have a weak pull-down which is only present during reset. Opposing this pull-down will slightly increase the power-down current (pull-down is equivalent to a 50 kΩ resistor per pin). 8. Valid with the recommended capacitor values on VQ and VBIAS as shown in the typical connection diagram in Section 3.
DS684F2
9
CS4352 3. TYPICAL CONNECTION DIAGRAM
5.1 Ω∗ +3.3 V * *Remove this supply if 10 µF optional resistor is present. The decoupling caps should remain. +3.3 V 0.1 µF 5
VD
*Optional 11
VA
0.1 µF
10 µF 3.3 µF
4 Digital Audio Source 3 2 1
MCLK LRCK
VBIAS+ 12
VA_H SCLK SDIN
17 0.1 µF 10 µF
+9 V to +12 V
AMUTEC 19 +1.5 V to VD 0.1 µF 20 VL 560 Ω
CS4352 AOUTA
18 3.3 µF 10 k Ω 2.2 nF*
Optional Mute Circuit Left Out
BMUTEC 14 10 Mode Configuration 7 8 9 RST DIF1 DIF0 DEM VQ 13
N D N D
560 Ω AOUTB 15 3.3 µF 10 k Ω 2.2 nF*
Optional Mute Circuit
Right Out
*Shown value is for Fc=130 kHz 3.3 µF
G G
6
15
Figure 2. Typical Connection Diagram
10
DS684F2
CS4352 4. APPLICATIONS
4.1 Sample Rate Range/Operational Mode Detect
The device operates in one of three operational modes. The allowed sample rate range in each mode is auto-detected. The CS4352 will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 1. Sample rates outside the specified range for each mode are not supported. Input Sample Rate (FS)
4 kHz - 54 kHz 84 kHz - 108 kHz 170 kHz - 216 kHz Table 1. CS4352 Auto-Detect
Mode
Single-Speed Mode Double-Speed Mode Quad-Speed Mode
4.2
System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 2-4. Refer to Section 4.3 for the required SCLK timing associated with the selected Digital Interface Format and to “Switching Specifications - Serial Audio Interface” on page 8 for the maximum allowed clock frequencies.
Sample Rate (kHz)
32 44.1 48
256x
8.1920 11.2896 12.2880
384x
12.2880 16.9344 18.4320
MCLK (MHz) 512x
16.3840 22.5792 24.5760
768x
24.5760 33.8688 36.8640
1024x
32.7680 45.1584 49.1520
Table 2. Single-Speed Mode Standard Frequencies
Sample Rate (kHz)
88.2 96
128x
11.2896 12.2880
192x
16.9344 18.4320
MCLK (MHz) 256x
22.5792 24.5760
384x
33.8688 36.8640
512x
45.1584 49.1520
Table 3. Double-Speed Mode Standard Frequencies
Sample Rate (kHz)
176.4 192
128x
22.5792 24.5760
MCLK (MHz) 192x
33.8688 36.8640
256x
45.1584 49.1520
Table 4. Quad-Speed Mode Standard Frequencies
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11
CS4352
4.3 Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats, as illustrated in Table 5. The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between the LRCK, SCLK and SDIN, see Figures 3-5. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2 and 48 cycles per LRCK period in format 3. For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Channel Serial Audio Interface: A Tutorial, available at www.cirrus.com.
DIF1
0 0 1 1
DIF0
0 1 0 1
DESCRIPTION I²S, up to 24-bit Data Right-Justified, 24-bit Data Left-Justified, up to 24-bit Data Right-Justified, 16-bit Data
FORMAT
0 1 2 3
FIGURE
3 4 5 4
Table 5. Digital Interface Format
LR CK
L e ft C h a n n e l
R ig h t C h a n n e l
SCLK
S D IN
M SB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
M SB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 3. I²S, up to 24-Bit Data
LR C K
L e ft C h a n ne l
R ig h t C h a n n e l
SC LK
SD IN
M SB
MSB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
LS B
MSB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
LS B
Figure 4. Right-Justified Data
LR C K
L e ft C h a n n e l
R ig h t C h a n n e l
SCLK
S D IN
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
M SB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LS B
Figure 5. Left-Justified up to 24-Bit Data
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CS4352
4.4 De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 6 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve scales with changes in sample rate, Fs. The De-emphasis error will increase for sample rates other than 44.1 kHz When pulled to VL, the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND, the DEM pin turns off the de-emphasis filter.
Gain dB T1=50 µs 0dB
T2 = 15 µs
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 6. De-Emphasis Curve
Note:
De-emphasis is only available in Single-Speed Mode.
4.5
Recommended Power-Up Sequence
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in Section 4.2. In this state, VQ will remain low and VBIAS will be connected to VA. 2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in DoubleSpeed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.6
Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4352 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 2 shows the recommended power arrangements, with VA_H, VA, VD, and VL connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS4352 should be connected to the analog ground plane. All signals, especially clocks, should be kept away from the VBIAS and VQ pins in order to avoid unwanted coupling into the DAC.
4.6.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low-value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin. Note: All decoupling capacitors should be referenced to analog ground.
The CDB4352 evaluation board demonstrates the optimum layout and power supply arrangements. DS684F2 13
CS4352
4.7 Popguard Transient Control
The CS4352 uses a novel technique to minimize the effects of output transients during power-up and powerdown. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended, single-supply converters. It is activated inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors.
4.7.1
Power-Up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing audible power-up transients.
4.7.2
Power-Down
To prevent audible transients at power-down, the device must first enter its power-down state. When this occurs, audio output ceases, and the internal output buffers are disconnected from AOUTA and AOUTB. In their place, a soft-start current sink is substituted that allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on.
4.7.3
Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning on the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to GND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.
4.8
Mute Control
The Mute Control pins go active during power-up initialization, reset, muting, or if the MCLK to LRCK ratio is incorrect. These pins are intended to be used as control for external mute circuits to prevent the clicks and pops that can occur in any single-ended, single-supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. Please see the CDB4352 data sheet for a suggested mute circuit for dual-supply systems. Alternately, the FET muting circuit from the CS4351 data sheet may be used as well. This FET circuit must be placed in series after the RC filter; otherwise noise may occur during muting conditions. Further ESD protection will need to be taken into consideration for the FET used.
14
DS684F2
CS4352
4.9 Initialization and Power-Down Sequence Diagram
USER: Apply Power
Power-Down State
VQ and outputs low
VQ and outputs ramp down
USER: Apply MCLK, SCLK, LRCK, and release RST USER: Apply RST
VQ and outputs ramp up
Wait State
USER: Remove LRCK or MCLK
USER: Apply MCLK, SCLK, and LRCK
MCLK/LRCK Ratio Detection
USER: change MCLK/LRCK ratio
Analog Output is Generated
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CS4352 5. DIGITAL FILTER RESPONSE PLOTS
0 0
−20
−20
Amplitude (dB)
Amplitude (dB)
−40
−40
−60
−60
−80
−80
−100
−100
−120 0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
−120 0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 7. Single-Speed Stopband Rejection
0 0.02
Figure 8. Single-Speed Transition Band
−1
0.015
−2 0.01 −3 0.005
Amplitude (dB)
Amplitude (dB)
−4
−5
0
−6
−0.005
−7 −0.01 −8 −0.015
−9
−10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
−0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 9. Single-Speed Transition Band (detail)
Figure 10. Single-Speed Passband Ripple
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 11. Double-Speed Stopband Rejection
Figure 12. Double-Speed Transition Band
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CS4352
0
0.02
1
0.015
2
0.01
3
Amplitude (dB)
5
Amplitude (dB)
4
0.005
0
6
0.005
7
0.01
8
9
0.015
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 13. Double-Speed Transition Band (detail)
Figure 14. Double-Speed Passband Ripple
0
0
20
20
40 Amplitude (dB)
Amplitude (dB)
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 15. Quad-Speed Stopband Rejection
0
0.2
Figure 16. Quad-Speed Transition Band
1
0.15
2
0.1
3
0.05
Amplitude (dB)
Amplitude (dB) 0.05 0.1 0.15 0.2
4
5
0
6
7
8
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0
0.05
0.1 0.15 Frequency(normalized to Fs)
0.2
0.25
Figure 17. Quad-Speed Transition Band (detail)
Figure 18. Quad-Speed Passband Ripple
DS684F2
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CS4352 6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Intra-channel Phase Deviation The deviation from linear phase within a given channel. Inter-channel Phase Deviation The difference in phase between channels.
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DS684F2
CS4352 7. PACKAGE DIMENSIONS 20L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
∝
e b2 SIDE VIEW
123
END VIEW
SEATING PLANE
TOP VIEW
DIM A A1 A2 b D E E1 e L µ
MIN -0.002 0.03346 0.00748 0.252 0.248 0.169 -0.020 0°
INCHES NOM -0.004 0.0354 0.0096 0.256 0.2519 0.1732 -0.024 4°
MAX 0.043 0.006 0.037 0.012 0.259 0.256 0.177 0.026 0.028 8°
MIN -0.05 0.85 0.19 6.40 6.30 4.30 -0.50 0°
MILLIMETERS NOM --0.90 0.245 6.50 6.40 4.40 -0.60 4°
NOTE MAX 1.10 0.15 0.95 0.30 6.60 6.50 4.50 0.65 0.70 8°
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters. 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
Parameters
Package Thermal Resistance 20L TSSOP
Symbol
θJA
Min
-
Typ
72
Max
-
Units
°C/Watt
DS684F2
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CS4352 8. ORDERING INFORMATION
Product CS4352 CDB4352 Description 20-pin, 192 kHz Stereo DAC with 2 Vrms Line Out Package 20-pin TSSOP Pb-Free YES Container Rail Commercial -40° to +85° C Tape & Reel Rail Automotive -40° to +105° C Tape & Reel Grade Temp Range Order # CS4352-CZZ CS4352-CZZR CS4352-DZZ CS4352-DZZR CDB4352
CS4352 Evaluation Board
9. REVISION HISTORY
Release
PP1 F1
Changes
Lowered VA_H minimum specification. Updated Idle channel noise specification to A-wt. Updated AOUT current draw specification. Updated VIL for VL=1.5V. Updated performance specifications and limits based on statistical data. Added Automotive grade specifications and ordering information. Updated Commercial grade idle channel noise specification. Lowered VIL maximum specifcation. Updated power supply current specification. Updated MCLK maximum specification.
F2
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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DS684F2
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