CS4384-CQZ

CS4384 103 dB, 192 kHz 8-Channel D/A Converter Features Advanced Multi-bit Delta Sigma Architecture 24-bit Conversion Automatic Detection of Sample Rates up to 192 kHz 103 dB Dynamic Range -88 dB THD+N Single-Ended Output Architecture Direct Stream Digital® (DSD™) Mode – Non-Decimating Volume Control – On-Chip 50 kHz Filter – Matched PCM and DSD Analog Output Levels Compatible with Industry-Standard Time Division Multiplexed (TDM) Serial Interface Selectable Digital Filters Volume Control with 1/2-dB Step Size and Soft Ramp Low Clock-Jitter Sensitivity +5 V Analog Supply, +2.5 V Digital Supply Separate 1.8 to 5 V Logic Supplies for the Control and Serial Ports C ontrol Port Supply = 1.8 V to 5 V Description The CS4384 is a complete 8-channel digital-to-analog system. This D/A system includes digital de-emphasis, half-dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpolation filters followed by an oversampled, multi-bit delta sigma modulator which includes mismatch shaping technology that eliminates distortion due to capacitor mismatch. Following this stage is a multi-element switched capacitor stage and low-pass filter with single-ended analog outputs. The CS4384 also has a proprietary DSD processor which allows for volume control and 50 kHz on-chip filtering without an intermediate decimation stage. It also offers an optional path for direct DSD conversion by directly using the multi-element switched capacitor array. The CS4384 accepts PCM data at sample rates from 4 kHz to 216 kHz, DSD audio data, and delivers excellent sound quality. These features are ideal for multichannel audio systems including SACD players, A/V receivers, digital TV’s, mixing consoles, effects processors, and sound cards. This product is available in 48-pin LQFP package in Commercial (-40°C to +85°C) temperature grade. See “Ordering Information” on page 51 for complete details. A nalog Supply = 5 V Digital Supply = 2.5 V Le ve l T ra nsla tor Hardware Mode or I2C /SPI Software Mode C ontrol Data Register/Hardware C onfiguration Internal Voltage Reference Reset Serial A udio Port Supply = 1.8 V to 5 V PC M Serial A udio Input TDM Serial A udio Input DSD A udio Input 8 Volume C ontrols Digital F ilters Multi-bit ∆Σ Modulators Le ve l T ra nsla tor S e ria l Inte rfa ce Switch-C ap DAC and Analog F ilters 8 E ight C hannels of Single-E nded O utputs DSD Processor -Volume control -50 kHz filter E xternal Mute C ontrol 2 Mute Signals http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) MAY '08 DS620F1 CS4384 TABLE OF CONTENTS 1. PIN DESCRIPTION................................................................................................................................. 6 2. CHARACTERISTICS AND SPECIFICATIONS...................................................................................... 8 RECOMMENDED OPERATING CONDITIONS .......................................................................................... 8 ABSOLUTE MAXIMUM RATINGS............................................................................................................... 8 DAC ANALOG CHARACTERISTICS........................................................................................................... 9 POWER AND THERMAL CHARACTERISTICS........................................................................................ 10 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE............................................ 11 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE............................................ 12 DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE .................................................. 12 DIGITAL CHARACTERISTICS .................................................................................................................. 13 SWITCHING CHARACTERISTICS - PCM ................................................................................................ 14 SWITCHING CHARACTERISTICS - DSD................................................................................................. 15 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT.................................................... 16 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT................................................... 17 3. TYPICAL CONNECTION DIAGRAM ................................................................................................ 18 4. APPLICATIONS ................................................................................................................................... 20 4.1 Master Clock.................................................................................................................................. 20 4.2 Mode Select.................................................................................................................................. 21 4.3 Digital Interface Formats ............................................................................................................... 22 4.3.1 OLM #1 ................................................................................................................................ 23 4.3.2 OLM #2 ................................................................................................................................ 23 4.3.3 OLM #3 ................................................................................................................................ 24 4.3.4 OLM #4 ................................................................................................................................ 24 4.3.5 TDM ..................................................................................................................................... 24 4.4 Oversampling Modes..................................................................................................................... 25 4.5 Interpolation Filter .......................................................................................................................... 25 4.6 De-Emphasis ................................................................................................................................. 25 4.7 ATAPI Specification ....................................................................................................................... 26 4.8 Direct Stream Digital (DSD) Mode................................................................................................. 26 4.9 Grounding and Power Supply Arrangements ................................................................................ 27 4.9.1 Capacitor Placement............................................................................................................ 27 4.10 Analog Output and Filtering ......................................................................................................... 27 4.11 The MUTEC Outputs ................................................................................................................... 28 4.12 Recommended Power-Up Sequence .......................................................................................... 29 4.12.1 Hardware Mode.................................................................................................................. 29 4.12.2 Software Mode ................................................................................................................... 29 4.13 Recommended Procedure for Switching Operational Modes...................................................... 30 4.14 Control Port Interface .................................................................................................................. 30 4.14.1 MAP Auto Increment .......................................................................................................... 30 4.14.2 I²C Mode ............................................................................................................................ 30 4.14.3 SPI Mode ........................................................................................................................... 31 4.15 Memory Address Pointer (MAP) ................................................................................................. 32 4.15.1 INCR (Auto Map Increment Enable) .................................................................................. 32 4.15.2 MAP4-0 (Memory Address Pointer) ................................................................................... 32 5. REGISTER QUICK REFERENCE ....................................................................................................... 33 6. REGISTER DESCRIPTION .................................................................................................................. 35 6.1 Chip Revision (Address 01h) ......................................................................................................... 35 6.1.1 Part Number ID (PART) [Read Only] ................................................................................... 35 6.1.2 Revision ID (REV) [Read Only] ............................................................................................ 35 6.2 Mode Control 1 (Address 02h) ...................................................................................................... 35 6.2.1 Control Port Enable (CPEN) ................................................................................................ 35 6.2.2 Freeze Controls (FREEZE) .................................................................................................. 35 2 DS620F1 CS4384 6.2.3 PCM/DSD Selection (DSD/PCM)......................................................................................... 36 6.2.4 DAC Pair Disable (DACx_DIS) ............................................................................................ 36 6.2.5 Power Down (PDN).............................................................................................................. 36 6.3 PCM Control (Address 03h) .......................................................................................................... 36 6.3.1 Digital Interface Format (DIF)............................................................................................... 36 6.3.2 Functional Mode (FM) .......................................................................................................... 37 6.4 DSD Control (Address 04h) ........................................................................................................... 37 6.4.1 DSD Mode Digital Interface Format (DSD_DIF) .................................................................. 37 6.4.2 Direct DSD Conversion (DIR_DSD)..................................................................................... 38 6.4.3 Static DSD Detect (STATIC_DSD) ...................................................................................... 38 6.4.4 Invalid DSD Detect (INVALID_DSD).................................................................................... 38 6.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE).................................................... 38 6.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN) ........................................................ 38 6.5 Filter Control (Address 05h) .......................................................................................................... 39 6.5.1 Interpolation Filter Select (FILT_SEL).................................................................................. 39 6.6 Invert Control (Address 06h) ......................................................................................................... 39 6.6.1 Invert Signal Polarity (INV_xx) ............................................................................................. 39 6.7 Group Control (Address 07h) ........................................................................................................ 39 6.7.1 Mutec Pin Control (MUTEC) ................................................................................................ 39 6.7.2 Channel A Volume = Channel B Volume (Px_A=B)............................................................. 39 6.7.3 Single Volume Control (SNGLVOL) ..................................................................................... 40 6.8 Ramp and Mute (Address 08h) ..................................................................................................... 40 6.8.1 Soft Ramp and Zero Cross Control (SZC) ........................................................................... 40 6.8.2 Soft Volume Ramp-Up After Error (RMP_UP) ..................................................................... 41 6.8.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) ................................................... 41 6.8.4 PCM Auto-Mute (PAMUTE) ................................................................................................. 41 6.8.5 DSD Auto-Mute (DAMUTE) ................................................................................................. 41 6.8.6 MUTE Polarity and DETECT (MUTEP1:0)........................................................................... 41 6.9 Mute Control (Address 09h) .......................................................................................................... 42 6.9.1 Mute (MUTE_xx) .................................................................................................................. 42 6.10 Mixing Control (Address 0Ah, 0Dh, 10h, 13h) ............................................................................. 42 6.10.1 De-Emphasis Control (PX_DEM1:0).................................................................................. 42 6.10.2 ATAPI Channel Mixing and Muting (ATAPI) ...................................................................... 43 6.11 Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h)........................................... 44 6.11.1 Digital Volume Control (xx_VOL7:0) .................................................................................. 44 6.12 PCM Clock Mode (Address 16h) ................................................................................................. 44 6.12.1 Master Clock Divide by 2 Enable (MCLKDIV).................................................................... 44 7. FILTER RESPONSE PLOTS ............................................................................................................... 45 8. REFERENCES...................................................................................................................................... 49 9. PARAMETER DEFINITIONS................................................................................................................ 49 10. PACKAGE DIMENSIONS .................................................................................................................. 50 11. ORDERING INFORMATION .............................................................................................................. 51 12. REVISION HISTORY ......................................................................................................................... 51 DS620F1 3 CS4384 LIST OF FIGURES Figure 1. Serial Audio Interface Timing...................................................................................................... 14 Figure 2. TDM Serial Audio Interface Timing ............................................................................................. 14 Figure 3. Direct Stream Digital - Serial Audio Input Timing........................................................................ 15 Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode........................... 15 Figure 5. Control Port Timing - I²C Format................................................................................................. 16 Figure 6. Control Port Timing - SPI Format................................................................................................ 17 Figure 7. Typical Connection Diagram, Software Mode............................................................................. 18 Figure 8. Typical Connection Diagram, Hardware Mode ........................................................................... 19 Figure 9. Format 0 - Left-Justified up to 24-bit Data .................................................................................. 22 Figure 10. Format 1 - I²S up to 24-bit Data ................................................................................................ 22 Figure 11. Format 2 - Right-Justified 16-bit Data ....................................................................................... 22 Figure 12. Format 3 - Right-Justified 24-bit Data ....................................................................................... 22 Figure 13. Format 4 - Right-Justified 20-bit Data ....................................................................................... 22 Figure 14. Format 5 - Right-Justified 18-bit Data ....................................................................................... 23 Figure 15. Format 8 - One Line Mode 1..................................................................................................... 23 Figure 16. Format 9 - One Line Mode 2..................................................................................................... 23 Figure 17. Format 10 - One Line Mode 3................................................................................................... 24 Figure 18. Format 11 - One Line Mode 4................................................................................................... 24 Figure 19. Format 12 - TDM Mode............................................................................................................. 24 Figure 20. De-Emphasis Curve.................................................................................................................. 25 Figure 21. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4) ............................................................... 26 Figure 22. DSD Phase Modulation Mode Diagram .................................................................................... 27 Figure 23. Full-Scale Output ...................................................................................................................... 28 Figure 24. Recommended Output Filter..................................................................................................... 28 Figure 25. Recommended Mute Circuitry .................................................................................................. 29 Figure 26. Control Port Timing, I²C Mode .................................................................................................. 31 Figure 27. Control Port Timing, SPI Mode ................................................................................................. 32 Figure 28. Single-Speed (fast) Stopband Rejection................................................................................... 45 Figure 29. Single-Speed (fast) Transition Band ......................................................................................... 45 Figure 30. Single-Speed (fast) Transition Band (detail) ............................................................................. 45 Figure 31. Single-Speed (fast) Passband Ripple ....................................................................................... 45 Figure 32. Single-Speed (slow) Stopband Rejection ................................................................................. 45 Figure 33. Single-Speed (slow) Transition Band........................................................................................ 45 Figure 34. Single-Speed (slow) Transition Band (detail)............................................................................ 46 Figure 35. Single-Speed (slow) Passband Ripple...................................................................................... 46 Figure 36. Double-Speed (fast) Stopband Rejection ................................................................................. 46 Figure 37. Double-Speed (fast) Transition Band........................................................................................ 46 Figure 38. Double-Speed (fast) Transition Band (detail)............................................................................ 46 Figure 39. Double-Speed (fast) Passband Ripple...................................................................................... 46 Figure 40. Double-Speed (slow) Stopband Rejection ................................................................................ 47 Figure 41. Double-Speed (slow) Transition Band ...................................................................................... 47 Figure 42. Double-Speed (slow) Transition Band (detail) .......................................................................... 47 Figure 43. Double-Speed (slow) Passband Ripple .................................................................................... 47 Figure 44. Quad-Speed (fast) Stopband Rejection .................................................................................... 47 Figure 45. Quad-Speed (fast) Transition Band .......................................................................................... 47 Figure 46. Quad-Speed (fast) Transition Band (detail) .............................................................................. 48 Figure 47. Quad-Speed (fast) Passband Ripple ........................................................................................ 48 Figure 48. Quad-Speed (slow) Stopband Rejection................................................................................... 48 Figure 49. Quad-Speed (slow) Transition Band......................................................................................... 48 Figure 50. Quad-Speed (slow) Transition Band (detail)............................................................................. 48 Figure 51. Quad-Speed (slow) Passband Ripple....................................................................................... 48 4 DS620F1 CS4384 LIST OF TABLES Table 1. Single-Speed Mode Standard Frequencies ................................................................................ Table 2. Double-Speed Mode Standard Frequencies............................................................................... Table 3. Quad-Speed Mode Standard Frequencies ................................................................................. Table 4. PCM Digital Interface Format, Hardware Mode Options............................................................. Table 5. Mode Selection, Hardware Mode Options .................................................................................. Table 6. Direct Stream Digital (DSD), Hardware Mode Options ............................................................... Table 7. Digital Interface Formats - PCM Mode........................................................................................ Table 8. Digital Interface Formats - DSD Mode ........................................................................................ Table 9. ATAPI Decode ............................................................................................................................ Table 10. Example Digital Volume Settings .............................................................................................. 20 20 20 21 21 21 37 37 43 44 DS620F1 5 CS4384 1. PIN DESCRIPTION DSD_SCLK MUTEC1 TST_OUT DSD5 DSD6 DSD7 DSD4 DSD8 VLS AOUT1 TST_OUT AOUT2 48 47 46 45 44 43 42 41 40 39 38 37 DSD3 DSD2 DSD1 VD GND MCLK LRCK SDIN1 SCLK M4(TST) SDIN2 M3(TST) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 TST_OUT AOUT3 AOUT4 TST_OUT VA GND TST_OUT AOUT5 AOUT6 TST_OUT TST_OUT AOUT7 CS4384 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 M1(SDA/CDIN) M2(SCL/CCLK) M0(AD0/CS) MUTEC2 TST_OUT AOUT8 SDIN3 RST SDIN4 FILT+ VLC VQ Pin Name VD GND MCLK LRCK SDIN1 SDIN2 SDIN3 SDIN4 SCLK VLC # 4 5 31 6 7 8 11 13 14 9 18 Pin Description Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operating Conditions for appropriate voltages. Ground (Input) - Ground reference. Should be connected to analog ground. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 1 illustrates several standard audio sample rates and the required master clock frequencies. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs. Serial Data Input (Input) - Input for two’s complement serial audio data. Serial Clock (Input) - Serial clocks for the serial audio interface. Control Port Power (Input) - Determines the required signal level for the control port and hardware mode configuration pins. Refer to the Recommended Operating Conditions for appropriate voltages. Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Requires the capacitive decoupling to analog ground as shown in the Typical Connection Diagram. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Mute Control (Output) - These pins are intended to be used as a control for external mute circuits on the line outputs to prevent the clicks and pops that can occur in any single supply system. RST 19 FILT+ VQ MUTEC1 MUTEC234 20 21 41 22 6 DS620F1 CS4384 Pin Name AOUT1 AOUT2 AOUT3 AOUT4 AOUT5 AOUT6 AOUT7 AOUT8 VA VLS # 39 38 35 34 29 28 25 24 32 43 Pin Description Analog Output (Output) - The full scale analog output level is specified in the Analog Characteristics specification table. Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Operating Conditions for appropriate voltages. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages. TST_OUT 23, 26 27, 30 Test Output - These pins need to be floating and not connected to any trace or plane. 33, 36 37, 40 Hardware Mode Definitions M0 M1 M2 M3 M4 17 16 15 12 10 Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables 4 and 5. Software Mode Definitions SCL/CCLK 15 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up resistor to the logic interface voltage in I²C® mode as shown in the Typical Connection Diagram. Serial Control Port Data (Input/Output) - SDA is a data I/O line in I²C mode and is open drain, requiring an external pull-up resistor to the logic interface voltage, as shown in the Typical Connection Diagram; CDIN is the input data line for the control port interface in SPI™ mode. Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS is the chip select signal for SPI mode. Test - These pins need to be tied to analog ground. SDA/CDIN 16 AD0/CS TST 17 10 12 DSD Definitions DSD1, DSD2 DSD3, DSD4 DSD5, DSD6 DSD7, DSD8 DSD_SCLK 3, 2 1, 48 Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data. 47,46 45, 44 42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface. DS620F1 7 CS4384 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Analog power Digital internal power Serial data port interface power Control port interface power Ambient Operating Temperature (Power Applied) -CQZ Symbol VA VD VLS VLC TA Min 4.75 2.37 1.71 1.71 -40 Typ 5.0 2.5 5.0 5.0 - Max 5.25 2.63 5.25 5.25 +85 Units V V V V °C ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.) Parameters Analog power Digital internal power Serial data port interface power Control port interface power Input Current Any Pin Except Supplies Digital Input Voltage Serial data port interface Control port interface Ambient Operating Temperature (power applied) Storage Temperature DC Power Supply Symbol VA VD VLS VLC Iin VIND-S VIND-C Top Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 -65 Max 6.0 3.2 6.0 6.0 ±10 VLS+ 0.4 VLC+ 0.4 125 150 Units V V V V mA V V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 8 DS620F1 CS4384 DAC ANALOG CHARACTERISTICS Test Conditions (unless otherwise indicated): VA = VLS = VLC = 5 V; VD = 2.5 V; TA = 25 °C; Full-Scale 997 Hz input sine wave (Note 1); Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as shown in “Typical Connection Diagram” on page 18; Measurement Bandwidth 10 Hz to 20 kHz. Parameters FS = 48 kHz, 96 kHz, 192 kHz and DSD Dynamic Range A-weighted unweighted 16-bit A-weighted (Note 2) unweighted 24-bit -0 dB THD+N -20 dB -60 dB 0 dB -20 dB -60 dB (1 kHz) 24-bit 97 94 103 100 97 94 -88 -80 -40 -88 -74 -34 100 110 0.1 100 -82 -74 -34 dB dB dB dB dB dB dB dB dB dB dB dB dB ppm/° C Vpp Vpp Ω mA kΩ pF VDC µA Symbol Min Typ Max Unit Total Harmonic Distortion + Noise (Note 2) 16-bit Idle Channel Noise / Signal-to-noise ratio Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Full Scale DifferentialOutput Voltage (Note 3) Output Impedance Max DC Current draw from an AOUT pin Min AC-Load Resistance Max Load Capacitance Quiescent Voltage Max Current draw from VQ PCM, DSD processor Direct DSD Mode VFS ZOUT IOUTmax RL CL VQ IQMAX 64%•VA 47%•VA 66%•VA 48%•VA 130 1.0 3 100 50% VA 10 68%•VA 49%•VA - Notes: 1. One-half LSB of triangular PDF dither is added to data. 2. Performance limited by 16-bit quantization noise. 3. VFS is tested under load RL and includes attenuation due to ZOUT DS620F1 9 CS4384 POWER AND THERMAL CHARACTERISTICS Parameters Power Supplies Power Supply Current (Note 4) normal operation, VA= 5 V VD= 2.5 V (Note 5) Interface current, VLC=5 V VLS=5 V (Note 6) power-down state (all supplies) Power Dissipation (Note 4) VA = 5 V, VD = 2.5 V normal operation (Note 6) power-down Package Thermal Resistance multi-layer dual-layer Power Supply Rejection Ratio (Note 7) (1 kHz) (60 Hz) IA ID ILC ILS Ipd 83 20 2 84 200 465 1 48 65 15 60 40 92 25 520 mA mA µA µA µA mW mW °C/Watt °C/Watt °C/Watt dB dB Symbol Min Typ Max Units θJA θJA θJC PSRR Notes: 4. Current consumption increases with increasing FS within a given speed mode and is signal dependant. Max values are based on highest FS and highest MCLK. 5. ILC measured with no external loading on the SDA pin. 6. Power Down Mode is defined as RST pin = Low with all clock and data lines held static. 7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 7 and 8. 10 DS620F1 CS4384 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. (See (Note 12)) Fast Roll-Off Parameter Min Typ Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 11) (Relative to 1 kHz) to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz (Note 10) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz (Note 10) 0 0 -0.01 0.547 102 0 0 -0.01 .583 80 0 0 -0.01 .635 90 10.4/Fs 6.15/Fs 7.1/Fs Max .454 .499 +0.01 ±0.36 ±0.21 ±0.14 .430 .499 +0.01 .105 .490 +0.01 - Unit Fs Fs dB Fs dB s dB dB dB Fs Fs dB Fs dB s Fs Fs dB Fs dB s Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz (Note 10) Notes: 8. Slow Roll-off interpolation filter is only available in Software Mode. 9. Response is clock dependent and will scale with Fs. 10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 11. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in Hardware Mode. 12. Amplitude vs. Frequency plots of this data are available in the “Filter Response Plots” on page 45. DS620F1 11 CS4384 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (CONTINED) Parameter Single-Speed Mode - 48 kHz Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 11) (Relative to 1 kHz) to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz (Note 10) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz (Note 10) Slow Roll-Off (Note 8) Min Typ Max 0 0 -0.01 .583 64 0 0 -0.01 .792 70 0 0 -0.01 .868 75 7.8/Fs 5.4/Fs 6.6/Fs 0.417 0.499 +0.01 ±0.36 ±0.21 ±0.14 .296 .499 +0.01 .104 .481 +0.01 - Unit Fs Fs dB Fs dB s dB dB dB Fs Fs dB Fs dB s Fs Fs dB Fs dB s Double-Speed Mode - 96 kHz Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay Quad-Speed Mode - 192 kHz Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz (Note 10) DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE Parameter DSD Processor Mode Passband (Note 9) Frequency Response Roll-off to -3 dB corner 10 Hz to 20 kHz 0 -0.05 27 0 0 -0.1 50 +0.05 26.9 176.4 0 kHz dB dB/Oct kHz kHz dB Min Typ Max Unit Direct DSD Mode Passband (Note 9) Frequency Response 10 Hz to 20 kHz to -0.1 dB corner to -3 dB corner 12 DS620F1 CS4384 DIGITAL CHARACTERISTICS Parameters Input Leakage Current Input Capacitance High-Level Input Voltage (Note 13) Symbol Iin VIH VIH VIL VIL VOL VOL VIH VIL Imax VOH VOL Min 70% 70% 70% - Typ 8 3 VA 0 Max ±10 30% 30% 20% 25% 30% - Units µA pF VLS VLC VLS VLC VLC VLC VA VA mA V V Serial I/O Control I/O Low-Level Input Voltage Serial I/O Control I/O Low-Level Output Voltage (IOL = -1.2 mA) Control I/O = 3.3 V, 5 V Control I/O = 1.8 V, 2.5 V MUTEC auto detect input high voltage MUTEC auto detect input low voltage Maximum MUTEC Drive Current MUTEC High-Level Output Voltage MUTEC Low-Level Output Voltage 13. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-up DS620F1 13 CS4384 SWITCHING CHARACTERISTICS - PCM (Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF) Parameters RST pin Low Pulse Width MCLK Frequency MCLK Duty Cycle Input Sample Rate - LRCK (Manual selection) (Note 15) Single-Speed Mode Double-Speed Mode Quad-Speed Mode Single-Speed Mode Double-Speed Mode Quad-Speed Mode (Note 16) tsckh tsckl tlcks tlckd tds tdh Fs Fs Fs Fs Fs Fs (Note 14) Symbol Min 1 1.024 45 4 50 100 4 84 170 45 45 8 8 5 5 3 5 Max 55.2 55 54 108 216 54 108 216 55 55 - Units ms MHz % kHz kHz kHz kHz kHz kHz % % ns ns ns ns ns ns Input Sample Rate - LRCK (Auto detect) LRCK Duty Cycle SCLK Duty Cycle SCLK High Time SCLK Low Time LRCK Edge to SCLK Rising Edge SCLK Rising Edge to LRCK Falling Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge Notes: 14. After powering up, RST should be held low until after the power supplies and clocks are settled. 15. See Tables 1 - 3 for suggested MCLK frequencies. 16. Not required for TDM Mode. LRCK LRCK tlcks tsckh tsckl t lcks t lckd t lcks t sckh t sckl SCLK SCLK tds SDINx tdh MSB MSB-1 SDIN1 t ds t dh MSB M SB-1 Figure 1. Serial Audio Interface Timing Figure 2. TDM Serial Audio Interface Timing 14 DS620F1 CS4384 SWITCHING CHARACTERISTICS - DSD (Logic 0 = AGND = DGND; Logic 1 = VLS; CL = 30 pF) Parameter MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency Symbol tsclkl tsclkh Min 40 160 160 1.024 2.048 20 20 -20 Typ - Max 60 3.2 6.4 20 Unit % ns ns MHz MHz ns ns ns (64x Oversampled) (128x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_A or DSD_B hold time DSD clock to data transition (Phase Modulation Mode) tsdlrs tsdh tdpm t sclkh t sclkl DSD_SCLK t sdlrs DSDxx t sdh Figure 3. Direct Stream Digital - Serial Audio Input Timing t dpm DSD_SCLK (128Fs) DSD_SCLK (64Fs) t dpm DSDxx Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode DS620F1 15 CS4384 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 17) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trc tfc, tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 1000 Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns Notes: 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. RST t irs Stop SDA t buf SCL R e p e a te d S ta rt S ta rt Stop t hdst t high t hdst tf t susp t lo w t hdd t sud t sust tr Figure 5. Control Port Timing - I²C Format 16 DS620F1 CS4384 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 19) (Note 20) (Note 20) (Note 18) Symbol fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2 Min 500 500 1.0 20 66 66 40 15 - Max 6 100 100 Unit MHz ns ns µs ns ns ns ns ns ns ns Notes: 18. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 19. Data must be held for sufficient time to bridge the transition time of CCLK. 20. For FSCK < 1 MHz. RST t srs CS t spi t css CCLK t r2 C D IN t scl t sch t csh t f2 t dsu t dh Figure 6. Control Port Timing - SPI Format DS620F1 17 CS4384 3. TYPICAL CONNECTION DIAGRAM +2.5 V 1 µF + 0.1 µF 4 VD 32 VA AOUT1 39 Analog Conditioning and Muting 0.1 µF + 1 µF +5 V 220 Ω 6 7 AOUT2 MCLK LRCK SCLK SDIN1 SDIN2 SDIN3 SDIN4 AOUT5 V LS AOUT4 AOUT3 38 Analog Conditioning and Muting PCM Digital Audio Source 9 8 11 13 14 470 Ω 35 Analog Conditioning and Muting 34 Analog Conditioning and Muting +1.8 V to +5 V 43 0.1 µF 29 Analog Conditioning and Muting CS4384 AOUT6 28 Analog Conditioning and Muting 470 Ω 3 2 1 DSD1 DSD2 DSD3 DSD4 AOUT8 DSD5 DSD6 DSD7 DSD8 DSD_SCLK MUTEC1 MUTEC234 AOUT7 25 Analog Conditioning and Muting DSD Audio Source 48 47 46 45 44 42 24 Analog Conditioning and Muting 41 22 Mute Drive 19 MicroController 15 16 17 RST SCL/CCLK SDA/CDIN ADO/CS FILT+ VQ 20 21 0.1 µ F + 1 µF 0.1 µ F + 47 µF 2 KΩ Note* 18 0.1 µF +1.8 V to +5 V 2 KΩ VLC TST_OUT Pins: 23, 26, 27, 30, 33, 36, 37, 40 Note: Necessary for I 2C control port operation GND 5 GND TST* 31 *Pins: 10, 12 Figure 7. Typical Connection Diagram, Software Mode 18 DS620F1 CS4384 +2.5 V 1 µF + 0.1 µF 4 VD 32 VA 0.1 µF + 1 µF +5 V AOUT1 220 Ω 39 Analog Conditioning and Muting 6 7 MCLK LRCK SCLK SDIN1 SDIN2 SDIN3 SDIN4 VLS AOUT2 38 Analog Conditioning and Muting PCM Digital Audio Source 9 8 11 13 14 470 Ω 43 0.1 µF 470 Ω AOUT3 35 Analog Conditioning and Muting AOUT4 34 Analog Conditioning and Muting +1.8 V to +5 V CS4384 3 2 1 DSDA1 DSDB1 DSDA2 DSDB2 DSDA3 DSDB3 DSDA4 DSDB4 DSD_SCLK AOUT5 29 Analog Conditioning and Muting AOUT6 28 Analog Conditioning and Muting DSD Audio Source 48 47 46 45 44 42 Optional 47 K Ω AOUT7 25 Analog Conditioning and Muting AOUT8 24 Analog Conditioning and Muting MUTEC1 MUTEC234 41 22 Mute Drive 10 12 15 16 17 19 M4 M3 M2 M1 M0 RST VQ FILT+ 20 21 0.1 µF + 1 µF 0.1 µF + 47 µF Stand-Alone Mode Configuration +1.8 V to +5 V 18 0.1 µF VLC TST_OUT GND 5 GND 31 Pins: 23, 26, 27, 30, 33, 36, 37, 40 Figure 8. Typical Connection Diagram, Hardware Mode DS620F1 19 CS4384 4. APPLICATIONS The CS4384 serially accepts twos complement formatted PCM data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. For more information on serial audio interfaces see AN282 “The 2-Channel Serial Audio Interface: A Tutorial”. The CS4384 can be configured in Hardware Mode by the M0, M1, M2, M3 and M4 pins and in Software Mode through I²C or SPI. 4.1 Master Clock MCLK/LRCK must be an integer ratio as shown in Tables 1 - 3. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and speed mode is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are then set to generate the proper internal clocks. Tables 1 - 3 illustrate several standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK and SCLK must be synchronous. Sample Rate (kHz) 32 44.1 48 MCLK (MHz) 256x 8.1920 11.2896 12.2880 384x 12.2880 16.9344 18.4320 512x 16.3840 22.5792 24.5760 768x 24.5760 33.8688 36.8640 1024x 32.7680 45.1584 49.1520 1152x 36.8640 Table 1. Single-Speed Mode Standard Frequencies Sample Rate (kHz) 64 88.2 96 MCLK (MHz) 128x 8.1920 11.2896 12.2880 192x 12.2880 16.9344 18.4320 256x 16.3840 22.5792 24.5760 384x 24.5760 33.8688 36.8640 512x 32.7680 45.1584 49.1520 Table 2. Double-Speed Mode Standard Frequencies Sample Rate (kHz) 176.4 192 MCLK (MHz) 64x 11.2896 12.2880 96x 16.9344 18.4320 128x 22.5792 24.5760 192x 33.8688 36.8640 256x 45.1584 49.1520 Table 3. Quad-Speed Mode Standard Frequencies = Denotes clock ratio and sample rate combinations which are NOT supported under auto speed-mode detection. Please see “Switching Characteristics - PCM” on page 14. 20 DS620F1 CS4384 4.2 Mode Select In Hardware Mode, operation is determined by the Mode Select pins. The states of these pins are continually scanned for any changes; however, the mode should only be changed while the device is in reset (RST pin low) to ensure proper switching from one mode to another. These pins require connection to supply or ground as outlined in Figure 8. For M0, M1, and M2, supply is VLC. For M3 and M4, supply is VLS. Tables 4 - 6 show the decode of these pins. In Software Mode, the operational mode and data format are set in the FM and DIF registers. See “PCM Control (Address 03h)” on page 36. M1 (DIF1) 0 0 1 1 M0 (DIF0) 0 1 0 1 I2S, DESCRIPTION Left Justified, up to 24-bit data up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data FORMAT 0 1 2 3 FIGURE 9 10 11 12 Table 4. PCM Digital Interface Format, Hardware Mode Options M4 0 0 0 0 1 1 1 M3 0 0 1 1 0 0 1 M2 (DEM) 0 1 0 1 0 1 M1 M0 DESCRIPTION Single-Speed without De-Emphasis (4 kHz to 50 kHz sample rates) Single-Speed with 44.1 kHz De-Emphasis; see Figure 20 Double-Speed (50 kHz to 100 kHz sample rates) Quad-Speed (100 kHz to 200 kHz sample rates) Auto Speed-Mode Detect (32 kHz to 200 kHz sample rates) Auto Speed-Mode Detect with 44.1 kHz De-Emphasis; see Figure 20 DSD Processor Mode Table 4 Table 6 Table 5. Mode Selection, Hardware Mode Options M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 DESCRIPTION 64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 6. Direct Stream Digital (DSD), Hardware Mode Options DS620F1 21 CS4384 4.3 Digital Interface Formats The serial port operates as a slave and supports the I²S, Left-Justified, Right-Justified, One-Line Mode (OLM) and TDM digital interface formats with varying bit depths from 16 to 32 as shown in Figures 9-19. Data is clocked into the DAC on the rising edge. OLM and TDM configurations are only supported in Software Mode. LRCK SCLK Left Channel Right Channel SDINx MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 9. Format 0 - Left-Justified up to 24-bit Data LRCK SCLK Left Channel Right Channel SDINx MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 10. Format 1 - I²S up to 24-bit Data LRCK Left Channel Right Channel SCLK SDINx 15 14 13 12 11 10 9 8 7 6 5 4 3 21 0 15 14 13 12 11 10 9 8 7 6 5 4 3 21 0 32 clocks Figure 11. Format 2 - Right-Justified 16-bit Data LRCK Left Channel Right Channel SCLK SDINx 0 23 22 21 20 19 18 7 6 5 4 3 21 0 23 22 21 20 19 18 7 6 5 4 3 21 0 32 clocks Figure 12. Format 3 - Right-Justified 24-bit Data LRCK Left Channel Right Channel SCLK SDINx 10 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 43 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 32 clocks 13. Format 4 - Right-Justified 20-bit Data 22 DS620F1 CS4384 LRCK Left Channel Right Channel SCLK SDINx 10 17 16 15 14 13 12 11 10 9 8 76 5 43 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 43 2 1 0 32 clocks Figure 14. Format 5 - Right-Justified 18-bit Data 4.3.1 OLM #1 OLM #1 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 128 Fs. Six channels of MSB first 20-bit PCM data are input on SDIN1. The last two channels are input on SDIN4. 64 clks 64 clks LRCK SCLK SDIN1 MSB Left Channel Right Channel LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB DAC_A1 20 clks SDIN4 DAC_A4 20 clks DAC_A2 20 clks DAC_A3 20 clks DAC_B1 20 clks DAC_B4 20 clks DAC_B2 20 clks DAC_B3 20 clks Figure 15. Format 8 - One Line Mode 1 4.3.2 OLM #2 OLM #2 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 256 Fs. Six channels of MSB first 24-bit PCM data are input on SDIN1. The last two channels are input on SDIN4. 128 clks 128 clks LRCK SCLK SDIN1 MSB Left Channel Right Channel LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB DAC_A1 24 clks SDIN4 DAC_A4 24 clks DAC_A2 24 clks DAC_A3 24 clks DAC_B1 24 clks DAC_B4 24 clks DAC_B2 24 clks DAC_B3 24 clks Figure 16. Format 9 - One Line Mode 2 DS620F1 23 CS4384 4.3.3 OLM #3 OLM #3 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 256 Fs. Eight channels of MSB first 20-bit PCM data are input on SDIN1. 128 clks LRCK SCLK SDIN1 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB DAC_A1 20 clks DAC_A2 20 clks DAC_A3 20 clks DAC_A4 20 clks DAC_B1 20 clks DAC_B2 20 clks DAC_B3 20 clks DAC_B4 20 clks 128 clks Left Channel Right Channel Figure 17. Format 10 - One Line Mode 3 4.3.4 OLM #4 OLM #4 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 256 Fs. Eight channels of MSB first 24-bit PCM data are input on SDIN1. 128 clks 128 clks LRCK SCLK SDIN1 MSB LSB MSB Left Channel Right Channel LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB DAC_A1 24 clks DAC_A2 24 clks DAC_A3 24 clks DAC_A4 24 clks DAC_B1 24 clks DAC_B2 24 clks DAC_B3 24 clks DAC_B4 24 clks Figure 18. Format 11 - One Line Mode 4 4.3.5 TDM The TDM serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 256 Fs. Data is received most significant bit first on the first SCLK after an LRCK transition and is valid on the rising edge of SCLK. LRCK identifies the start of a new frame and is equal to the sample rate, Fs. LRCK is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data sample and must be held valid for one SCLK period. Each time slot is 32 bits wide, with the valid data sample left justified within the time slot with the remaining bits being zero padded. 256 clks LRCK SCLK SDIN1 LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB DAC_A1 32 clks DAC_B1 32 clks DAC_A2 32 clks DAC_B2 32 clks DAC_A3 32 clks DAC_B3 32 clks DAC_A4 32 clks DAC_B4 32 clks Data MSB LSB zero Figure 19. Format 12 - TDM Mode 24 DS620F1 CS4384 4.4 Oversampling Modes The CS4384 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the M4, M3 and M2 pins in Hardware Mode or the FM bits in Software Mode. Single-Speed Mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x. The auto speed-mode detect feature allows for the automatic selection of speed mode based off of the incoming sample rate. This allows the CS4384 to accept a wide range of sample rates with no external intervention necessary. The auto speed-mode detect feature is available in both Hardware and Software Mode. 4.5 Interpolation Filter To accommodate the increasingly complex requirements of digital audio systems, the CS4384 incorporates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available in each of Single-, Double-, or Quad-Speed Modes. These filters have been designed to accommodate a variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the “Parameter Definitions” on page 49 for more details). When in Hardware Mode, only the “fast” roll-off filter is available. Filter specifications can be found in Section 2, and filter response plots can be found in Figures 28 to 51. 4.6 De-Emphasis The CS4384 includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. Figure 20 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs if the input sample rate does not match the coefficient which has been selected. In Software Mode the required de-emphasis filter coefficients for 32 kHz, 44.1 kHz, or 48 kHz are selected via the de-emphasis control bits. In Hardware Mode only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the input sample rate is not 44.1 kHz and de-emphasis has been selected then the corner frequencies of the de-emphasis filter will be scaled by a factor of the actual Fs over 44,100. Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 3.183 kHz F2 Frequency 10.61 kHz Figure 20. De-Emphasis Curve DS620F1 25 CS4384 4.7 ATAPI Specification The CS4384 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 9 on page 43 and Figure 21 for additional information. Left Channel Audio Data A Channel Volume Control MUTE Aout Ax SDINx Σ Σ Right Channel Audio Data B Channel Volume Control MUTE AoutBx Figure 21. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4) 4.8 Direct Stream Digital (DSD) Mode In Software Mode the DSD/PCM bits (Reg. 02h) are used to configure the device for DSD mode. The DSD_DIF bits (Reg 04h) then control the expected DSD rate and MCLK ratio. The DIR_DSD bit (Reg 04h) selects between two proprietary methods for DSD to analog conversion. The first method uses a decimation free DSD processing technique which allows for features such as matched PCM level output, DSD volume control, and 50kHz on chip filter. The second method sends the DSD data directly to the on-chip switched-capacitor filter for conversion (without the above mentioned features). The DSD_PM_EN bit (Reg. 04h) selects Phase Modulation (data plus data inverted) as the style of data input. In this mode the DSD_PM_Mode bit selects whether a 128Fs or 64x clock is used for phase modulated 64x data (see Figure 22). Use of Phase Modulation Mode may not directly effect the performance of the CS4384, but may lower the sensitivity to board level routing of the DSD data signals. The CS4384 can detect errors in the DSD data which does not comply with the SACD specification. The STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4384 to alter the incoming invalid DSD data. Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the MUTEC pins would be set according to the DAMUTE bit (Reg. 08h)). More information for any of these register bits can be found in the “Parameter Definitions” on page 49. The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation index) at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time however, performance at these levels is not guaranteed. If sustained +3 dB-SACD levels are required, the digital volume control should be set to -3.0 dB. This same volume control register affects PCM output levels. There is no need to change the volume control setting between PCM and DSD in order to have the 0 dB output levels match (both 0 dBFS and 0 dB-SACD will output at -3 dB in this case). 26 DS620F1 CS4384 DSD Normal Mode Not Used DSD Phase Modulation Mode DSD_SCLK BCKA (128Fs) BCKA (64Fs) DSD_SCLK DSD_SCLK BCKD (64Fs) Not Used D0 D1 D1 D2 DSDAx, DSDBx DSDAx, DSDBx D0 D1 D2 Not Used Figure 22. DSD Phase Modulation Mode Diagram 4.9 Grounding and Power Supply Arrangements As with any high resolution converter, the CS4384 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the recommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS4384 should be connected to the analog ground plane. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the DAC. 4.9.1 Capacitor Placement Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin. Note: All decoupling capacitors should be referenced to analog ground. The CDB4384 evaluation board demonstrates the optimum layout and power supply arrangements. 4.10 Analog Output and Filtering The CS4384 does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry. Figure 23 shows how the full-scale analog output level specification is derived. Figure 24 shows how the recommended output filtering with location for optional mute circuit. DS620F1 27 CS4384 4.175 V AOUT 2.5 V 0.825 V Full-Scale Output Level= AOUT= 3.35 Vpp Figure 23. Full-Scale Output Figure 24. Recommended Output Filter 4.11 The MUTEC Outputs The MUTEC1 and MUTEC234 pins have an auto-polarity detect feature. The MUTEC output pins are high impedance at the time of reset. The external mute circuitry needs to be self biased into an active state in order to be muted during reset. Upon release of reset, the CS4384 will detect the status of the MUTEC pins (high or low) and will then select that state as the polarity to drive when the mutes become active. The external-bias voltage level that the MUTEC pins see at the time of release of reset must meet the “MUTEC auto detect input high/low voltage” specs as outlined in the Digital Characteristics section. Figure 25 shows a single example of both an active high and an active low mute drive circuit. In these designs, the pull-up and pull-down resistors have been especially chosen to meet the input high/low threshold when used with the MMUN2111 and MMUN2211 internal bias resistances of 10 kΩ. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. 28 DS620F1 CS4384 Figure 25. Recommended Mute Circuitry 4.12 Recommended Power-Up Sequence 4.12.1 Hardware Mode 1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2. If RST can not be held low long enough the SDINx pins should remain static low until all other clocks are stable, and if possible the RST should be toggled low again once the system is stable. 2. Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). 4.12.2 Software Mode 1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2. 2. Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in QuadSpeed Mode). 3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in DoubleSpeed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1, then set the format and mode control bits to the desired settings. If more than the stated number of LRCK cycles passes before CPEN bit is written then the chip will enter Hardware Mode and begin to operate with the M0-M4 as the mode settings. CPEN bit may be written at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit can not be set in time then the SDINx pins should remain static low (this way no audio data can be DS620F1 29 CS4384 converted incorrectly by the Hardware Mode settings). 4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs. 4.13 Recommended Procedure for Switching Operational Modes For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources). The mute bits may then be released after clocks have settled and the proper modes have been set. It is required to have the device held in reset if the minimum high/low time specs of MCLK can not be met during clock source changes. 4.14 Control Port Interface The control port is used to load all the internal register settings in order to operate in Software Mode (see the “Parameter Definitions” on page 49). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in one of two modes: I²C or SPI. 4.14.1 MAP Auto Increment The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. 4.14.2 I²C Mode In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL (see Figure 26 for the clock to data relationship). There is no CS pin. Pin AD0 enables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND as required, before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up, SPI Mode will be selected. 4.14.2.1 I²C Write To write to the device, follow the procedure below while adhering to the control port Switching Specifications in Section 2. 1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be 001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus. DS620F1 2. 3. 4. 5. 30 CS4384 4.14.2.2 I²C Read To read from the device, follow the procedure below while adhering to the control port Switching Specifications. 1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be 001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP, or the default address (see Section 4.14.1) if an I²C read is the first operation performed on the device. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock and issue an ACK after each byte until all the desired registers are read, then initiate a STOP condition to the bus. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I²C Write instructions followed by step 1 of the I²C Read section. If no further reads from other registers are desired, initiate a STOP condition to the bus. N o te 1 SDA 0 01 1 00 ADDR AD 0 R /W ACK D AT A 1-8 ACK D A TA 1-8 ACK 2. 3. 4. 5. SCL S ta rt S top N o te : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P . Figure 26. Control Port Timing, I²C Mode 4.14.3 SPI Mode In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 27 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and is used to control SPI writes to the control port. When the device detects a high to low transition on the AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK. 4.14.3.1 SPI Write To write to the device, follow the procedure below while adhering to the control port Switching Specifications in Section 2. 1. 2. 3. 4. 5. Bring CS low. The address byte on the CDIN pin must then be 00110000. Write to the memory address pointer, MAP. This byte points to the register to be written. Write the desired data to the register pointed to by the MAP. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high. DS620F1 31 CS4384 6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high. CS C C LK C H IP ADDRESS C DIN 0011000 R /W MAP MSB D A TA LSB b yte 1 M A P = M e m ory A d dress P oin te r byte n Figure 27. Control Port Timing, SPI Mode 4.15 Memory Address Pointer (MAP) 6 Reserved 0 5 Reserved 0 4 MAP4 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0 7 INCR 0 4.15.1 INCR (Auto Map Increment Enable) Default = ‘0’ 0 - Disabled 1 - Enabled 4.15.2 MAP4-0 (Memory Address Pointer) Default = ‘00000’ 32 DS620F1 CS4384 5. REGISTER QUICK REFERENCE Addr 01h 02h 03h 04h Function Chip Revision default Mode Control default PCM Control default DSD Control default 7 PART4 0 CPEN 0 DIF3 0 6 PART3 0 FREEZE 0 DIF2 0 5 PART2 0 0 DIF1 0 4 PART1 0 0 DIF0 0 3 PART0 0 0 Reserved 0 2 REV2 x 0 Reserved 0 1 REV1 x 0 FM1 1 0 REV0 x PDN 1 FM0 1 DSD/PCM DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS DSD_DIF2 DSD_DIF1 DSD_DIF0 DIR_DSD 0 Reserved 0 INV_B4 0 Reserved 0 SZC1 1 0 Reserved 0 A1_VOL7 0 B1_VOL7 0 Reserved 0 A2_VOL7 0 B2_VOL7 0 Reserved 0 A3_VOL7 0 B3_VOL7 0 Reserved 0 0 Reserved 0 INV_A4 0 MUTEC 0 SZC0 0 0 P1_DEM1 0 A1_VOL6 0 B1_VOL6 0 P2_DEM1 0 A2_VOL6 0 B2_VOL6 0 P3_DEM1 0 A3_VOL6 0 B3_VOL6 0 P4_DEM1 0 0 Reserved 0 INV_B3 0 Reserved 0 RMP_UP 1 0 P1_DEM0 0 A1_VOL5 0 B1_VOL5 0 P2_DEM0 0 A2_VOL5 0 B2_VOL5 0 P3_DEM0 0 A3_VOL5 0 B3_VOL5 0 P4_DEM0 0 0 Reserved 0 INV_A3 0 P1_A=B 0 RMP_DN 1 0 P1ATAPI4 0 A1_VOL4 0 B1_VOL4 0 P2ATAPI4 0 A2_VOL4 0 B2_VOL4 0 P3ATAPI4 0 A3_VOL4 0 B3_VOL4 0 P4ATAPI4 0 STATIC_D INVALID_D DSD_PM_ DSD_PM_ SD SD MD EN 1 Reserved 0 INV_B2 0 P2_A=B 0 PAMUTE 1 0 P1ATAPI3 1 A1_VOL3 0 B1_VOL3 0 P2ATAPI3 1 A2_VOL3 0 B2_VOL3 0 P3ATAPI3 1 A3_VOL3 0 B3_VOL3 0 P4ATAPI3 1 0 Reserved 0 INV_A2 0 P3_A=B 0 DAMUTE 1 MUTE_A2 0 P1ATAPI2 0 A1_VOL2 0 B1_VOL2 0 P2ATAPI2 0 A2_VOL2 0 B2_VOL2 0 P3ATAPI2 0 A3_VOL2 0 B3_VOL2 0 P4ATAPI2 0 0 Reserved 0 INV_B1 0 P4_A=B 0 MUTE_P1 0 MUTE_B1 0 P1ATAPI1 0 A1_VOL1 0 B1_VOL1 0 P2ATAPI1 0 A2_VOL1 0 B2_VOL1 0 P3ATAPI1 0 A3_VOL1 0 B3_VOL1 0 P4ATAPI1 0 0 FILT_SEL 0 INV_A1 0 SNGLVOL 0 MUTE_P0 0 MUTE_A1 0 P1ATAPI0 1 A1_VOL0 0 B1_VOL0 0 P2ATAPI0 1 A2_VOL0 0 B2_VOL0 0 P3ATAPI0 1 A3_VOL0 0 B3_VOL0 0 P4ATAPI0 1 05h 06h 07h 08h 09h Filter Control default Invert Control default Group Control default Ramp and Mute default Mute Control default MUTE_B4 MUTE_A4 MUTE_B3 MUTE_A3 MUTE_B2 0Ah Mixing Control Pair 1 (AOUTx1) default 0Bh Vol. Control A1 default 0Ch Vol. Control B1 default 0Dh Mixing Control Pair 2 (AOUTx1) default 0Eh Vol. Control A2 default 0Fh 10h Vol. Control B2 default Mixing Control Pair 3 (AOUTx1) default 11h 12h 13h Vol. Control A3 default Vol. Control B3 default Mixing Control Pair 4 (AOUTx1) default DS620F1 33 CS4384 Addr 14h 15h 16h Function Vol. Control A4 default Vol. Control B4 default default 7 A4_VOL7 0 B4_VOL7 0 0 6 A4_VOL6 0 B4_VOL6 0 Reserved 0 5 A4_VOL5 0 B4_VOL5 0 MCLKDIV 0 4 A4_VOL4 0 B4_VOL4 0 Reserved 0 3 A4_VOL3 0 B4_VOL3 0 Reserved 0 2 A4_VOL2 0 B4_VOL2 0 Reserved 0 1 A4_VOL1 0 B4_VOL1 0 Reserved 0 0 A4_VOL0 0 B4_VOL0 0 Reserved 0 PCM clock mode Reserved 34 DS620F1 CS4384 6. REGISTER DESCRIPTION Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted. 6.1 Chip Revision (Address 01h) 7 PART4 0 6 PART3 0 5 PART2 0 4 PART1 0 3 PART0 0 2 REV2 1 REV1 0 REV0 - 6.1.1 Part Number ID (PART) [Read Only] 00000- CS4384 6.1.2 Revision ID (REV) [Read Only] 000 - Revision A0 001 - Revision B0 Function: This read-only register can be used to identify the model and revision number of the device. 6.2 7 Mode Control 1 (Address 02h) 6 FREEZE 0 5 DSD/PCM 0 4 DAC4_DIS 0 3 DAC3_DIS 0 2 DAC2_DIS 0 1 DAC1_DIS 0 0 PDN 1 CPEN 0 6.2.1 Control Port Enable (CPEN) Default = 0 0 - Disabled 1 - Enabled Function: This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user should write this bit within 10 ms following the release of Reset. 6.2.2 Freeze Controls (FREEZE) Default = 0 0 - Disabled 1 - Enabled Function: This function allows modifications to be made to the registers without the changes taking effect until the FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit. DS620F1 35 CS4384 6.2.3 PCM/DSD Selection (DSD/PCM) Default = 0 0 - PCM 1 - DSD Function: This function selects DSD or PCM Mode. The appropriate data and clocks should be present before changing modes, or else MUTE should be selected. 6.2.4 DAC Pair Disable (DACx_DIS) Default = 0 0 - DAC Pair x Enabled 1 - DAC Pair x Disabled Function: When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state. It is advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate the possibility of audible artifacts. Note: When the device is configured in TDM Mode by setting DIF[3:0] to 1100 (see Digital Interface Format (DIF)), this function is not available and these bits must be set to 0 for proper operation. 6.2.5 Power Down (PDN) Default = 1 0 - Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation in Control Port Mode can occur. 6.3 PCM Control (Address 03h) 7 DIF3 0 6 DIF2 0 5 DIF1 0 4 DIF0 0 3 Reserved 0 2 Reserved 0 1 FM1 1 0 FM0 1 6.3.1 Digital Interface Format (DIF) Default = 0000 - Format 0 (Left Justified, up to 24-bit data) Function: These bits select the interface format for the serial audio input. The DSD/PCM bit determines whether PCM or DSD Mode is selected. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 9-19. Note: While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set to ensure proper switching from one mode to another. 36 DS620F1 CS4384 DIF3 0 0 0 0 0 0 1 1 1 1 1 X DIF2 0 0 0 0 1 1 0 0 0 0 1 X DIF1 0 0 1 1 0 0 0 0 1 1 0 X DIF0 0 1 0 1 0 1 0 1 0 1 0 X DESCRIPTION Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit data Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 18-bit data One-line Mode 1, 24-bit Data +SDIN4 One-line Mode 2, 20-bit Data +SDIN4 One-line Mode 3, 24-bit 6-channel One-line Mode 4, 20-bit 6-channel TDM All other combinations are Reserved Format 0 1 2 3 4 5 8 9 10 11 12 FIGURE 9 10 11 12 13 14 15 16 17 18 19 Table 7. Digital Interface Formats - PCM Mode 6.3.2 Functional Mode (FM) Default = 11 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Auto Speed Mode detect (32 kHz to 200 kHz sample rates) Function: Selects the required range of input sample rates or Auto Speed Mode. 6.4 DSD Control (Address 04h) 6 DSD_DIF1 0 5 DSD_DIF0 0 4 DIR_DSD 0 3 STATIC_DSD 1 2 INVALID_DSD 1 1 DSD_PM_MD 0 0 DSD_PM_EN 0 7 DSD_DIF2 0 6.4.1 DSD Mode Digital Interface Format (DSD_DIF) Default = 000 - Format 0 (64x oversampled DSD data with a 4x MCLK to DSD data rate) Function: The relationship between the oversampling ratio of the DSD audio data and the required Master clock to DSD data rate is defined by the Digital Interface Format pins. The DSD/PCM bit determines whether PCM or DSD Mode is selected. DIF2 DIF1 DIFO DESCRIPTION 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate. 128x oversampled DSD data with a 3x MCLK to DSD data rate. 128x oversampled DSD data with a 4x MCLK to DSD data rate. 128x oversampled DSD data with a 6x MCLK to DSD data rate. Table 8. Digital Interface Formats - DSD Mode DS620F1 37 CS4384 6.4.2 Direct DSD Conversion (DIR_DSD) Function: When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control functions. When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion. In this mode, the full-scale DSD and PCM levels will not be matched (see Section 2), the dynamic range performance may be reduced, the volume control is inactive, and the 50 kHz low-pass filter is not available (see Section 2 for filter specifications). 6.4.3 Static DSD Detect (STATIC_DSD) Function: When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected, sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE register. When set to 0, this function is disabled. 6.4.4 Invalid DSD Detect (INVALID_DSD) Function: When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if detected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE register. When set to 0 (default), this function is disabled. 6.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE) Function: When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for Phase Modulation Mode. (See Figure 20 on page 25.) When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for Phase Modulation Mode. 6.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN) Function: When set to 1, DSD Phase Modulation Input Mode is enabled and the DSD_PM_MODE bit should be set accordingly. When set to 0 (default), this function is disabled (DSD normal mode). 38 DS620F1 CS4384 6.5 Filter Control (Address 05h) 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 FILT_SEL 0 7 Reserved 0 6.5.1 Interpolation Filter Select (FILT_SEL) Function: When set to 0 (default), the Interpolation Filter has a fast roll off. When set to 1, the Interpolation Filter has a slow roll off. The specifications for each filter can be found in the Analog characteristics table, and response plots can be found in Figures 26 to 49. 6.6 Invert Control (Address 06h) 6 INV_A4 0 5 INV_B3 0 4 INV_A3 0 3 INV_B2 0 2 INV_A2 0 1 INV_B1 0 0 INV_A1 0 7 INV_B4 0 6.6.1 Invert Signal Polarity (INV_xx) Function: When set to 1, this bit inverts the signal polarity of channel xx. When set to 0 (default), this function is disabled. 6.7 Group Control (Address 07h) 6 MUTEC 0 5 Reserved 0 4 P1_A=B 0 3 P2_A=B 0 2 P3_A=B 0 1 P4_A=B 0 0 SNGLVOL 0 7 Reserved 0 6.7.1 Mutec Pin Control (MUTEC) Default = 0 0 - Two Mute control signals 1 - Single mute control signal on MUTEC1 Function: Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to ‘0’, a logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the mute control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND of all DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more information on the use of the mute control function see the MUTEC1 and MUTEC234 pins in Section 4.11. 6.7.2 Channel A Volume = Channel B Volume (Px_A=B) Default = 0 0 - Disabled 1 - Enabled Function: DS620F1 39 CS4384 The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are determined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled. 6.7.3 Single Volume Control (SNGLVOL) Default = 0 0 - Disabled 1 - Enabled Function: The individual channel volume levels are independently controlled by their respective Volume Control Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled. 6.8 Ramp and Mute (Address 08h) 7 SZC1 1 6 SZC0 0 5 RMP_UP 1 4 RMP_DN 1 3 PAMUTE 1 2 DAMUTE 1 1 MUTE_P1 0 0 MUTE_P0 0 6.8.1 Soft Ramp and Zero Cross Control (SZC) Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. 40 DS620F1 CS4384 6.8.2 Soft Volume Ramp-Up After Error (RMP_UP) Function: An un-mute will be performed after executing an LRCK/MCLK ratio change or error, and after changing the Functional Mode. When set to 1 (default), this un-mute is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate un-mute is performed in these instances. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit. 6.8.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) Function: If either the FILT_SEL or DEM bits are changed the DAC will stop conversion for a period of time to change its filter values. This bit selects how the data is effected prior to and after the change of the filter values. When set to 1 (default), a mute will be performed prior to executing a filter mode change and an un-mute will be performed after executing the filter mode change. This mute and un-mute are effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate mute is performed prior to executing a filter mode change. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit. 6.8.4 PCM Auto-Mute (PAMUTE) Function: When set to 1 (default) the Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. When set to 0 this function is disabled. 6.8.5 DSD Auto-Mute (DAMUTE) Function: When set to 1 (default) the Digital-to-Analog converter output will mute following the reception of 256 repeated 8-bit DSD mute patterns (as defined in the SACD specification). A single bit not fitting the repeated mute pattern (mentioned above) will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. 6.8.6 MUTE Polarity and DETECT (MUTEP1:0) Default = 00 00 - Auto polarity detect, selected from MUTEC1 pin 01 - Reserved 10 - Active low mute polarity 11 - Active high mute polarity DS620F1 41 CS4384 Function: Auto mute polarity detect (00) See Section 4.11 on page 28 for the description. Active low mute polarity (10) When RST is low the outputs are high impedance and will need to be biased active. Once reset has been released and after this bit is set, the MUTEC output pins will be active low polarity. Active high mute polarity (11) At reset time the outputs are high impedance and will need to be biased active. Once reset has been released and after this bit is set, the MUTEC output pins will be active high polarity. 6.9 Mute Control (Address 09h) 6 MUTE_A4 0 5 MUTE_B3 0 4 MUTE_A3 0 3 MUTE_B2 0 2 MUTE_A2 0 1 MUTE_B1 0 0 MUTE_A1 0 7 MUTE_B4 0 6.9.1 Mute (MUTE_xx) Default = 0 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be retained. The muting function is affected, similarly to attenuation changes, by the Soft and Zero Cross bits. The MUTE pins will go active during the mute period according to the MUTEC bit. 6.10 Mixing Control (Address 0Ah, 0Dh, 10h, 13h) 6 Px_DEM1 0 5 Px_DEM0 0 4 PxATAPI4 0 3 PxATAPI3 1 2 PxATAPI2 0 1 PxATAPI1 0 0 PxATAPI0 1 7 Reserved 0 6.10.1 De-Emphasis Control (PX_DEM1:0) Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (Figure 20 on page 25) De-emphasis is only available in Single-Speed Mode. 42 DS620F1 CS4384 6.10.2 ATAPI Channel Mixing and Muting (ATAPI) Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4384 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 9 and Figure 21 for additional information. ATAPI4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AOUTAx MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL [(aL+bR)/2] [(aL+bR)/2] [(bL+aR)/2] [(aL+bR)/2] AOUTBx MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL [(bL+aR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2] Table 9. ATAPI Decode DS620F1 43 CS4384 6.11 Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h) 6 xx_VOL6 0 5 xx_VOL5 0 4 xx_VOL4 0 3 xx_VOL3 0 2 xx_VOL2 0 1 xx_VOL1 0 0 xx_VOL0 0 7 xx_VOL7 0 These eight registers provide individual volume and mute control for each of the eight channels. The values for “xx” in the bit fields above are as follows: Register address 0Bh - xx = A1 Register address 0Ch - xx = B1 Register address 0Eh - xx = A2 Register address 0Fh - xx = B2 Register address 11h - xx = A3 Register address 12h - xx = B3 Register address 14h - xx = A4 Register address 15h - xx = B4 6.11.1 Digital Volume Control (xx_VOL7:0) Default = 00h (0 dB) Function: The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments from 0 to -127.5 dB. Volume settings are decoded as shown in Table 10. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. Note that the values in the volume setting column in Table 10 are approximate. The actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12. Binary Code 00000000 00000001 00000110 11111111 Decimal Value 0 1 6 255 Volume Setting 0 dB -0.5 dB -3.0 dB -127.5 dB Table 10. Example Digital Volume Settings 6.12 PCM Clock Mode (Address 16h) 6 Reserved 0 5 MCLKDIV 0 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 0 7 Reserved 0 6.12.1 Master Clock Divide by 2 Enable (MCLKDIV) Function: When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry. When set to 0 (default), MCLK is unchanged. 44 DS620F1 CS4384 7. FILTER RESPONSE PLOTS 0 0 −20 −20 Amplitude (dB) Amplitude (dB) −40 −40 −60 −60 −80 −80 −100 −100 −120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1 −120 0.4 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 28. Single-Speed (fast) Stopband Rejection 0 Figure 29. Single-Speed (fast) Transition Band 0.02 −1 0.015 −2 0.01 −3 0.005 Amplitude (dB) Amplitude (dB) −4 −5 0 −6 −0.005 −7 −0.01 −8 −0.015 −9 −10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 −0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 Figure 30. Single-Speed (fast) Transition Band (detail) Figure 31. Single-Speed (fast) Passband Ripple 0 0 −20 −20 Amplitude (dB) −60 Amplitude (dB) −40 −40 −60 −80 −80 −100 −100 −120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1 −120 0.4 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 32. Single-Speed (slow) Stopband Rejection Figure 33. Single-Speed (slow) Transition Band DS620F1 45 CS4384 0 0.02 −1 0.015 −2 0.01 −3 0.005 Amplitude (dB) Amplitude (dB) −4 −5 0 −6 −0.005 −7 −0.01 −8 −0.015 −9 −10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 −0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 Figure 34. Single-Speed (slow) Transition Band (detail) Figure 35. Single-Speed (slow) Passband Ripple 0 0 20 20 Amplitude (dB) Amplitude (dB) 40 40 60 60 80 80 100 100 120 120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1 0.4 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 36. Double-Speed (fast) Stopband Rejection 0 Figure 37. Double-Speed (fast) Transition Band 0.02 1 0.015 2 0.01 3 Amplitude (dB) 5 Amplitude (dB) 4 0.005 0 6 0.005 7 0.01 8 9 0.015 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 Figure 38. Double-Speed (fast) Transition Band (detail) Figure 39. Double-Speed (fast) Passband Ripple 46 DS620F1 CS4384 0 0 20 20 Amplitude (dB) Amplitude (dB) 40 40 60 60 80 80 100 100 120 120 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 40. Double-Speed (slow) Stopband Rejection 0 Figure 41. Double-Speed (slow) Transition Band 0.02 1 0.015 2 0.01 3 0.005 Amplitude (dB) 5 Amplitude (dB) 4 0 6 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0.02 0 0.05 0.1 0.15 0.2 Frequency(normalized to Fs) 0.25 0.3 0.35 Figure 42. Double-Speed (slow) Transition Band (detail) Figure 43. Double-Speed (slow) Passband Ripple 0 0 20 20 40 Amplitude (dB) Amplitude (dB) 40 60 60 80 80 100 100 120 120 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 44. Quad-Speed (fast) Stopband Rejection Figure 45. Quad-Speed (fast) Transition Band DS620F1 47 CS4384 0.2 0 1 0.15 2 0.1 3 0.05 Amplitude (dB) Amplitude (dB) 0.05 0.1 0.15 0.2 4 5 0 6 7 8 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0 0.05 0.1 0.15 Frequency(normalized to Fs) 0.2 0.25 Figure 46. Quad-Speed (fast) Transition Band (detail) Figure 47. Quad-Speed (fast) Passband Ripple 0 0 20 20 Amplitude (dB) Amplitude (dB) 40 40 60 60 80 80 100 100 120 120 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 0.1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 0.9 Figure 48. Quad-Speed (slow) Stopband Rejection 0 Figure 49. Quad-Speed (slow) Transition Band 0.02 1 0.015 2 0.01 3 0.005 Amplitude (dB) Amplitude (dB) 4 5 0 6 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0.02 0 0.02 0.04 0.06 0.08 Frequency(normalized to Fs) 0.1 0.12 Figure 50. Quad-Speed (slow) Transition Band (detail) Figure 51. Quad-Speed (slow) Passband Ripple 48 DS620F1 CS4384 8. REFERENCES 1. How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters, by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB4364 data sheet, available at http://www.cirrus.com. 3. Design Notes for a 2-Pole Filter with Differential Input, by Steven Green. Cirrus Logic Application Note AN48 4. The I²C-Bus Specification: Version 2.0, Philips Semiconductors, December 1998. http://www.semiconductors.philips.com 5. AN282 “The 2-Channel Serial Audio Interface: A Tutorial” 9. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. DS620F1 49 CS4384 10.PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING E E1 D D1 1 e ∝ B A A1 L INCHES NOM 0.055 0.004 0.009 0.354 0.28 0.354 0.28 0.020 0.24 4° MILLIMETERS NOM 1.40 0.10 0.22 9.0 BSC 7.0 BSC 9.0 BSC 7.0 BSC 0.50 BSC 0.60 4° DIM A A1 B D D1 E E1 e* L MIN --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000° MAX 0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000° MIN --0.05 0.17 8.70 6.90 8.70 6.90 0.40 0.45 0.00° MAX 1.60 0.15 0.27 9.30 7.10 9.30 7.10 0.60 0.75 7.00° ∝ * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS022 50 DS620F1 CS4384 11.ORDERING INFORMATION Product CS4384 CDB4384 Description Package 114 dB, 192 kHz 848-pin channel D/A Converter LQFP CS4384 Evaluation Board Pb-Free YES Grade Commercial Temp Range -40° to +85° C Container Tray Tape & Reel Order # CS4384-CQZ CS4384-CQZR CDB4384 12.REVISION HISTORY Release A1 Changes Initial Release Corrected DAC Pair Disable register description in “DAC Pair Disable (DACx_DIS)” on page 36 Added note to Digital Interface Format register description in “Digital Interface Format (DIF)” on page 36 Removed Automotive Grade Added PCM mode format changeable in reset only to “Mode Select” on page 21 Updated ambient operating temperature range for commercial grade Updated Full Scale Differential Output Voltage in “DAC Analog Characteristics” on page 9 Updated VD power supply current and package thermal resistance in Power and Thermal Characteristics Updated “Digital Characteristics” on page 13 Updated Legal Information under “IMPORTANT NOTICE” on page 51 F1 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. 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All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. Direct Stream Digital is a registered trademark of Sony Kabushiki Kaisha TA Sony Corporation. DSD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation. DS620F1 51 CS4384 52 DS620F1